Fix spelling

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index bd1611f864a5b67491bc21c4b427eb23e8b61673..c9f5d1435b72607a2f970624c258aef1ed50e2ff 100644 (file)
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -84,7 +84,7 @@ class TrapMainStage(PipeModBase):
 
         # addr to begin from on return
         comb += srr0_o.data.eq(return_addr)
-        comb += srro_o.ok.eq(1) # spelling
+        comb += srr0_o.ok.eq(1)
 
         # TODO: MSR (into srr1)