update comments

diff --git a/src/soc/bus/external_core.py b/src/soc/bus/external_core.py
index b90913d1ce704fa69aa65839c986bdea330295fa..102e66cffcdf0e35a07cd4985c41ab680acadef1 100644 (file)
--- a/src/soc/bus/external_core.py
+++ b/src/soc/bus/external_core.py
@@ -5,7 +5,9 @@
 # Sponsored by NLnet and NGI POINTER under EU Grants 871528 and 957073
 # Part of the Libre-SOC Project.
 #
-# this is a wrapper around the opencores verilog core16550 module
+# this is a wrapper around the external_core_top.v verilog module
+# which allows for faster development iteration (oh and microwatt or
+# other core to be dropped into a peripheral fabric)
 
 from nmigen import (Elaboratable, Cat, Module, Signal, ClockSignal, Instance,
                     ResetSignal, Const)