copy in cr0.data into cr0 temp, not whole of cr0 (including ok flag)

diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py
index 1faa1ee6015babb747829584fc00e7cbb63790e7..1b37a62529ec6700711cb9aeefc46adcaa37b542 100644 (file)
--- a/src/soc/fu/common_output_stage.py
+++ b/src/soc/fu/common_output_stage.py
@@ -55,7 +55,7 @@ class CommonOutputStage(PipeModBase):
         comb += is_negative.eq(~is_zero & msb_test)
 
         with m.If(is_cmpeqb):
-            comb += cr0.eq(self.i.cr0)
+            comb += cr0.eq(self.i.cr0.data)
         with m.Else():
             comb += cr0.eq(Cat(self.so, is_zero, is_positive, is_negative))