add bare wishbone option to TestIssuer, sort out ports

diff --git a/src/soc/config/ifetch.py b/src/soc/config/ifetch.py
index 8c56d904c2a85ee1db44f00f3be498d3b70400c1..a73a89bc6c5b2fe8962d0072a0b2939010ffd3fe 100644 (file)
--- a/src/soc/config/ifetch.py
+++ b/src/soc/config/ifetch.py
@@ -8,12 +8,14 @@ of unnecessarily-duplicated code
 """
 from soc.experiment.imem import TestMemFetchUnit
 from soc.bus.test.test_minerva import TestSRAMBareFetchUnit
+from soc.minerva.units.fetch import BareFetchUnit
 
 
 class ConfigFetchUnit:
     def __init__(self, pspec):
         fudict = {'testmem': TestMemFetchUnit,
                    'test_bare_wb': TestSRAMBareFetchUnit,
+                   'bare_wb': BareFetchUnit,
                    #'test_cache_wb': TestCacheFetchUnit
                   }
         fukls = fudict[pspec.imem_ifacetype]

diff --git a/src/soc/config/loadstore.py b/src/soc/config/loadstore.py
index f2361a67d94211b26f4bfb083c5cf81d6ab64b90..f280227d57d010fccd9fe7d08c335c7c024cecbf 100644 (file)
--- a/src/soc/config/loadstore.py
+++ b/src/soc/config/loadstore.py
@@ -10,11 +10,13 @@ from soc.experiment.lsmem import TestMemLoadStoreUnit
 from soc.bus.test.test_minerva import TestSRAMBareLoadStoreUnit
 from soc.experiment.pi2ls import Pi2LSUI
 from soc.experiment.pimem import TestMemoryPortInterface
+from soc.minerva.units.loadstore import BareLoadStoreUnit
 
 class ConfigLoadStoreUnit:
     def __init__(self, pspec):
         lsidict = {'testmem': TestMemLoadStoreUnit,
                    'test_bare_wb': TestSRAMBareLoadStoreUnit,
+                   'bare_wb': BareLoadStoreUnit,
                    #'test_cache_wb': TestCacheLoadStoreUnit
                   }
         lsikls = lsidict[pspec.ldst_ifacetype]
@@ -23,6 +25,7 @@ class ConfigLoadStoreUnit:
 
 class ConfigMemoryPortInterface:
     def __init__(self, pspec):
+        self.pspec = pspec
         if pspec.ldst_ifacetype == 'testpi':
             self.pi = TestMemoryPortInterface(addrwid=pspec.addr_wid, # adr bus
                                               regwid=pspec.reg_wid) # data bus
@@ -32,3 +35,8 @@ class ConfigMemoryPortInterface:
                           addr_wid=pspec.addr_wid, # address range
                           mask_wid=pspec.mask_wid, # cache line range
                           data_wid=pspec.reg_wid)  # data bus width
+
+    def ports(self):
+        if self.pspec.ldst_ifacetype == 'testpi':
+            return self.pi.ports()
+        return list(self.pi.ports()) + self.lsmem.lsi.ports()

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index aac034d79c990d18507d88c53d5f23b192d3e4ba..c622ef44996fd9bb533b47c6b3f163685360b62a 100644 (file)
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -281,8 +281,9 @@ class TstL0CacheBuffer(Elaboratable):
         return m
 
     def ports(self):
+        yield from self.cmpi.ports()
         yield from self.l0.ports()
-        yield from self.pimem
+        yield from self.pimem.ports()
 
 
 def wait_busy(port, no=False):

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index 102f1869f36e8a0e8629be6f315d0ce16ab477e7..cdc82e17ae20b0f3e6a41a6233604b861587bf35 100644 (file)
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -271,8 +271,7 @@ class PortInterfaceBase(Elaboratable):
         return m
 
     def ports(self):
-        for p in self.dports:
-            yield from p.ports()
+        yield from self.pi.ports()
 
 
 class TestMemoryPortInterface(PortInterfaceBase):

diff --git a/src/soc/minerva/units/fetch.py b/src/soc/minerva/units/fetch.py
index 98259a9bb24499832a9e5b4e8481bc51aa89368b..b7cdad11bf3528c848f2a10ce62918f6933fec5c 100644 (file)
--- a/src/soc/minerva/units/fetch.py
+++ b/src/soc/minerva/units/fetch.py
@@ -31,6 +31,23 @@ class FetchUnitInterface:
         self.f_fetch_err_o = Signal()
         self.f_badaddr_o = Signal(bad_wid)
 
+    def __iter__(self):
+        yield self.a_pc_i
+        yield self.a_stall_i
+        yield self.a_valid_i
+        yield self.f_stall_i
+        yield self.f_valid_i
+        yield self.a_busy_o
+        yield self.f_busy_o
+        yield self.f_instr_o
+        yield self.f_fetch_err_o
+        yield self.f_badaddr_o
+        for sig in self.ibus.fields.values():
+            yield sig
+
+    def ports(self):
+        return list(self)
+
 
 class BareFetchUnit(FetchUnitInterface, Elaboratable):
     def elaborate(self, platform):

diff --git a/src/soc/minerva/units/loadstore.py b/src/soc/minerva/units/loadstore.py
index 6cd7f889df1cd495460a3608611972bff9a89fda..f3ca09d7af248f5d1826e93529b783dd9ffc39cf 100644 (file)
--- a/src/soc/minerva/units/loadstore.py
+++ b/src/soc/minerva/units/loadstore.py
@@ -51,6 +51,29 @@ class LoadStoreUnitInterface:
         self.m_store_err_o = Signal()     # if there was an error when storing
         self.m_badaddr_o = Signal(badwid) # The address of the load/store error
 
+    def __iter__(self):
+        yield self.x_addr_i
+        yield self.x_mask_i
+        yield self.x_ld_i
+        yield self.x_st_i
+        yield self.x_st_data_i
+
+        yield self.x_stall_i
+        yield self.x_valid_i
+        yield self.m_stall_i
+        yield self.m_valid_i
+        yield self.x_busy_o
+        yield self.m_busy_o
+        yield self.m_ld_data_o
+        yield self.m_load_err_o
+        yield self.m_store_err_o
+        yield self.m_badaddr_o
+        for sig in self.dbus.fields.values():
+            yield sig
+
+    def ports(self):
+        return list(self)
+
 
 class BareLoadStoreUnit(LoadStoreUnitInterface, Elaboratable):
     def elaborate(self, platform):

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 5054643ce8358e3d068359cf298ea5445c666079..a158e19977b4096c885efd7ea72dcd65ab828513 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -305,6 +305,7 @@ class NonProductionCore(Elaboratable):
     def __iter__(self):
         yield from self.fus.ports()
         yield from self.pdecode2.ports()
+        yield from self.l0.ports()
         # TODO: regs
 
     def ports(self):

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 9ee19a4bd31dd313e1adf8270a043126962836f3..a610f60dccd689fcfcc9aab09d51ea404fd66de2 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -161,8 +161,8 @@ class TestIssuer(Elaboratable):
 
 
 if __name__ == '__main__':
-    pspec = TestMemPspec(ldst_ifacetype='testpi',
-                         imem_ifacetype='testmem',
+    pspec = TestMemPspec(ldst_ifacetype='bare_wb',
+                         imem_ifacetype='bare_wb',
                          addr_wid=48,
                          mask_wid=8,
                          reg_wid=64)