A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
A6XX_TEX_CONST_2_PITCH(tiling->tile0.extent.width * att->cpp);
dst[3] = 0;
- dst[4] = 0x100000 + att->gmem_offset;
+ dst[4] = cmd->device->physical_device->gmem_base + att->gmem_offset;
dst[5] = A6XX_TEX_CONST_5_DEPTH(1);
for (unsigned i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
dst[i] = 0;
goto fail;
}
+ if (tu_drm_get_gmem_base(device, &device->gmem_base)) {
+ if (instance->debug_flags & TU_DEBUG_STARTUP)
+ tu_logi("Could not query the GMEM size");
+ result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
+ "could not get GMEM size");
+ goto fail;
+ }
+
memset(device->name, 0, sizeof(device->name));
sprintf(device->name, "FD%d", device->gpu_id);
return 0;
}
+int
+tu_drm_get_gmem_base(const struct tu_physical_device *dev, uint64_t *base)
+{
+ return tu_drm_get_param(dev, MSM_PARAM_GMEM_BASE, base);
+}
+
int
tu_drm_submitqueue_new(const struct tu_device *dev,
int priority,
unsigned gpu_id;
uint32_t gmem_size;
+ uint64_t gmem_base;
uint32_t tile_align_w;
uint32_t tile_align_h;
int
tu_drm_get_gmem_size(const struct tu_physical_device *dev, uint32_t *size);
+int
+tu_drm_get_gmem_base(const struct tu_physical_device *dev, uint64_t *base);
+
int
tu_drm_submitqueue_new(const struct tu_device *dev,
int priority,