move obtaining simulator data into common function for logical pipe tests

diff --git a/src/soc/fu/compunits/test/test_logical_compunit.py b/src/soc/fu/compunits/test/test_logical_compunit.py
index 8745b0b1e7810ed2ea3d3e343b4b27e7da347144..2591bcd41820740c13ba476306e901d18370f3da 100644 (file)
--- a/src/soc/fu/compunits/test/test_logical_compunit.py
+++ b/src/soc/fu/compunits/test/test_logical_compunit.py
@@ -2,7 +2,7 @@ import unittest
 from soc.decoder.power_enums import (XER_bits, Function)
 
 # XXX bad practice: use of global variables
-from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
+from soc.fu.logical.test.test_pipe_caller import LogicalTestCase, get_cu_inputs
 from soc.fu.logical.test.test_pipe_caller import test_data
 
 from soc.fu.compunits.compunits import LogicalFunctionUnit
@@ -17,20 +17,7 @@ class LogicalTestRunner(TestRunner):
     def get_cu_inputs(self, dec2, sim):
         """naming (res) must conform to LogicalFunctionUnit input regspec
         """
-        res = {}
-
-        # RA (or RC)
-        reg1_ok = yield dec2.e.read_reg1.ok
-        if reg1_ok:
-            data1 = yield dec2.e.read_reg1.data
-            res['ra'] = sim.gpr(data1).value
-
-        # RB (or immediate)
-        reg2_ok = yield dec2.e.read_reg2.ok
-        if reg2_ok:
-            data2 = yield dec2.e.read_reg2.data
-            res['rb'] = sim.gpr(data2).value
-
+        res = yield from get_cu_inputs(dec2, sim)
         return res
 
     def check_cu_outputs(self, res, dec2, sim, code):

diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py
index c8f1ebc278002e348cd23782886b19799f61e530..480603ab3429d74f7f74739d9b97f286750b79b3 100644 (file)
--- a/src/soc/fu/logical/test/test_pipe_caller.py
+++ b/src/soc/fu/logical/test/test_pipe_caller.py
@@ -23,32 +23,45 @@ class TestCase:
         self.sprs = sprs
         self.name = name
 
+def get_cu_inputs(dec2, sim):
+    """naming (res) must conform to LogicalFunctionUnit input regspec
+    """
+    res = {}
 
-def set_alu_inputs(alu, dec2, sim):
-    # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
-    # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
-    # and place it into data_i.b
-
+    # RA (or RC)
     reg1_ok = yield dec2.e.read_reg1.ok
     if reg1_ok:
         data1 = yield dec2.e.read_reg1.data
-        data1 = sim.gpr(data1).value
-    else:
-        data1 = 0
+        res['ra'] = sim.gpr(data1).value
 
-    yield alu.p.data_i.a.eq(data1)
-
-    # If there's an immediate, set the B operand to that
+    # RB (or immediate)
     reg2_ok = yield dec2.e.read_reg2.ok
+    #imm_ok = yield dec2.e.imm_data.imm_ok
+    if reg2_ok:
+        data2 = yield dec2.e.read_reg2.data
+        data2 = sim.gpr(data2).value
+        res['rb'] = data2
+    #elif imm_ok:
+    #    data2 = yield dec2.e.imm_data.imm
+    #    res['rb'] = data2
+
+    return res
+
+
+def set_alu_inputs(alu, dec2, sim):
+    # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
+    # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
+    # and place it into data_i.b
+
+    inp = yield from get_cu_inputs(dec2, sim)
+    if 'ra' in inp:
+        yield alu.p.data_i.a.eq(inp['ra'])
+    if 'rb' in inp:
+        yield alu.p.data_i.b.eq(inp['rb'])
     imm_ok = yield dec2.e.imm_data.imm_ok
     if imm_ok:
         data2 = yield dec2.e.imm_data.imm
-    elif reg2_ok:
-        data2 = yield dec2.e.read_reg2.data
-        data2 = sim.gpr(data2).value
-    else:
-        data2 = 0
-    yield alu.p.data_i.b.eq(data2)
+        yield alu.p.data_i.b.eq(data2)
 
 
 # This test bench is a bit different than is usual. Initially when I