#endif
-#if 0
+#if 1
#if 1
// print out configuration parameters for QSPI
- volatile uint32_t *qspi_cfg = (uint32_t*)0xc0003000;
+ volatile uint32_t *qspi_cfg = (uint32_t*)SPI_FCTRL_BASE;
for (int k=0; k < 2; k++) {
tmp = readl((unsigned long)&(qspi_cfg[k]));
- //puts("cfg");
- //uart_writeuint32(k);
- //puts(" ");
- //uart_writeuint32(tmp);
- //puts("\n");
+ puts("cfg");
+ uart_writeuint32(k);
+ puts(" ");
+ uart_writeuint32(tmp);
+ puts("\n");
}
#endif
- volatile uint32_t *qspi = (uint32_t*)spi_mem;
- volatile uint8_t *qspi_bytes = (uint8_t*)spi_mem;
+ volatile uint32_t *qspi = (uint32_t*)spi_offs;
+ //volatile uint8_t *qspi_bytes = (uint8_t*)spi_offs;
// let's not, eh? writel(0xDEAF0123, (unsigned long)&(qspi[0]));
// tmp = readl((unsigned long)&(qspi[0]));
-for (i=0;i<1000;i++) {
- tmp = readl((unsigned long)&(qspi[i]));
- uart_writeuint32(tmp);
- puts(" ");
-}
-putchar(10);
-putchar(10);
-for (i=0;i<1000;i++) {
- tmp = readb((unsigned long)&(qspi_bytes[i]));
- uart_writeuint32(tmp);
- puts(" ");
-}
-#if 1
+ for (int i=0;i<256;i++) {
+ tmp = readl((unsigned long)&(qspi[i]));
+ uart_writeuint32(tmp);
+ puts(" ");
+ if ((i & 0x7) == 0x7) puts("\r\n");
+ }
+ puts("\r\n");
+ /*
+ for (i=0;i<256;i++) {
+ tmp = readb((unsigned long)&(qspi_bytes[i]));
+ uart_writeuint32(tmp);
+ puts(" ");
+ }
+ */
+#if 0
while (1) {
// quick read
tmp = readl((unsigned long)&(qspi[0x1000/4]));
uart_writeuint32(tmp);
putchar(10);
}
-#endif
while (1) {
unsigned char c = getchar();
putchar(c);
return 0;
#endif
+#endif
#if 0
volatile uint32_t *hyperram = (uint32_t*)0xa0000000;
writel(0xDEAF0123, (unsigned long)&(hyperram[0]));
dramcore_addr=0xc8000000, # DRAM_CTRL_BASE
ddr_addr=0x00000000, # DRAM_BASE
spi0_addr=0xf0000000, # SPI0_BASE
- spi0_cfg_addr=0xc0003000, # SPI0_CTRL_BASE
+ spi0_cfg_addr=0xc0006000, # SPI0_CTRL_BASE
eth0_cfg_addr=0xc0004000, # ETH0_CTRL_BASE (4k)
eth0_irqno=0, # ETH0_IRQ number
hyperram_addr=0xa0000000, # HYPERRAM_BASE