add example buffered pipe

diff --git a/src/add/example_buf_pipe.py b/src/add/example_buf_pipe.py
index 20e91e4e877948f72000b5ac789b053f82d21f4d..aedf8dceffa5e02d056ff18d5e18a9f00105eb9a 100644 (file)
--- a/src/add/example_buf_pipe.py
+++ b/src/add/example_buf_pipe.py
@@ -1,3 +1,6 @@
+""" nmigen implementation of buffered pipeline stage, based on zipcpu:
+    https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
+"""
 from nmigen import Signal, Cat, Const, Mux, Module
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil