wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_adr;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_addr_acked;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0" *)
(* generator = "nMigen" *)
-module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__data_len, oper_i_alu_alu0__insn, oper_i_alu_alu0__sv_pred_sz, oper_i_alu_alu0__sv_pred_dz, oper_i_alu_alu0__sv_saturate, oper_i_alu_alu0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, src4_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, xer_ca_ok, dest3_o, xer_ov_ok, dest4_o, xer_so_ok, dest5_o, coresync_clk);
+module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__data_len, oper_i_alu_alu0__insn, oper_i_alu_alu0__sv_pred_sz, oper_i_alu_alu0__sv_pred_dz, oper_i_alu_alu0__sv_saturate, oper_i_alu_alu0__sv_ldstmode, oper_i_alu_alu0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, src4_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, xer_ca_ok, dest3_o, xer_ov_ok, dest4_o, xer_so_ok, dest5_o, coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *)
wire \$101 ;
reg alu_alu0_alu_op__rc__rc = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_alu0_alu_op__rc__rc$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] alu_alu0_alu_op__sv_ldstmode = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \alu_alu0_alu_op__sv_ldstmode$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg alu_alu0_alu_op__sv_pred_dz = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output cr_a_ok;
input oper_i_alu_alu0__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_alu0__rc__rc;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] oper_i_alu_alu0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_alu0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
alu_alu0_alu_op__sv_pred_dz <= \alu_alu0_alu_op__sv_pred_dz$next ;
always @(posedge coresync_clk)
alu_alu0_alu_op__sv_saturate <= \alu_alu0_alu_op__sv_saturate$next ;
+ always @(posedge coresync_clk)
+ alu_alu0_alu_op__sv_ldstmode <= \alu_alu0_alu_op__sv_ldstmode$next ;
always @(posedge coresync_clk)
alu_alu0_alu_op__SV_Ptype <= \alu_alu0_alu_op__SV_Ptype$next ;
always @(posedge coresync_clk)
.alu_op__output_carry(alu_alu0_alu_op__output_carry),
.alu_op__rc__ok(alu_alu0_alu_op__rc__ok),
.alu_op__rc__rc(alu_alu0_alu_op__rc__rc),
+ .alu_op__sv_ldstmode(alu_alu0_alu_op__sv_ldstmode),
.alu_op__sv_pred_dz(alu_alu0_alu_op__sv_pred_dz),
.alu_op__sv_pred_sz(alu_alu0_alu_op__sv_pred_sz),
.alu_op__sv_saturate(alu_alu0_alu_op__sv_saturate),
\alu_alu0_alu_op__sv_pred_sz$next = alu_alu0_alu_op__sv_pred_sz;
\alu_alu0_alu_op__sv_pred_dz$next = alu_alu0_alu_op__sv_pred_dz;
\alu_alu0_alu_op__sv_saturate$next = alu_alu0_alu_op__sv_saturate;
+ \alu_alu0_alu_op__sv_ldstmode$next = alu_alu0_alu_op__sv_ldstmode;
\alu_alu0_alu_op__SV_Ptype$next = alu_alu0_alu_op__SV_Ptype;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *)
casez (cu_issue_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */
1'h1:
- { \alu_alu0_alu_op__SV_Ptype$next , \alu_alu0_alu_op__sv_saturate$next , \alu_alu0_alu_op__sv_pred_dz$next , \alu_alu0_alu_op__sv_pred_sz$next , \alu_alu0_alu_op__insn$next , \alu_alu0_alu_op__data_len$next , \alu_alu0_alu_op__is_signed$next , \alu_alu0_alu_op__is_32bit$next , \alu_alu0_alu_op__output_carry$next , \alu_alu0_alu_op__input_carry$next , \alu_alu0_alu_op__write_cr0$next , \alu_alu0_alu_op__invert_out$next , \alu_alu0_alu_op__zero_a$next , \alu_alu0_alu_op__invert_in$next , \alu_alu0_alu_op__oe__ok$next , \alu_alu0_alu_op__oe__oe$next , \alu_alu0_alu_op__rc__ok$next , \alu_alu0_alu_op__rc__rc$next , \alu_alu0_alu_op__imm_data__ok$next , \alu_alu0_alu_op__imm_data__data$next , \alu_alu0_alu_op__fn_unit$next , \alu_alu0_alu_op__insn_type$next } = { oper_i_alu_alu0__SV_Ptype, oper_i_alu_alu0__sv_saturate, oper_i_alu_alu0__sv_pred_dz, oper_i_alu_alu0__sv_pred_sz, oper_i_alu_alu0__insn, oper_i_alu_alu0__data_len, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__insn_type };
+ { \alu_alu0_alu_op__SV_Ptype$next , \alu_alu0_alu_op__sv_ldstmode$next , \alu_alu0_alu_op__sv_saturate$next , \alu_alu0_alu_op__sv_pred_dz$next , \alu_alu0_alu_op__sv_pred_sz$next , \alu_alu0_alu_op__insn$next , \alu_alu0_alu_op__data_len$next , \alu_alu0_alu_op__is_signed$next , \alu_alu0_alu_op__is_32bit$next , \alu_alu0_alu_op__output_carry$next , \alu_alu0_alu_op__input_carry$next , \alu_alu0_alu_op__write_cr0$next , \alu_alu0_alu_op__invert_out$next , \alu_alu0_alu_op__zero_a$next , \alu_alu0_alu_op__invert_in$next , \alu_alu0_alu_op__oe__ok$next , \alu_alu0_alu_op__oe__oe$next , \alu_alu0_alu_op__rc__ok$next , \alu_alu0_alu_op__rc__rc$next , \alu_alu0_alu_op__imm_data__ok$next , \alu_alu0_alu_op__imm_data__data$next , \alu_alu0_alu_op__fn_unit$next , \alu_alu0_alu_op__insn_type$next } = { oper_i_alu_alu0__SV_Ptype, oper_i_alu_alu0__sv_ldstmode, oper_i_alu_alu0__sv_saturate, oper_i_alu_alu0__sv_pred_dz, oper_i_alu_alu0__sv_pred_sz, oper_i_alu_alu0__insn, oper_i_alu_alu0__data_len, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__insn_type };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_alu0" *)
(* generator = "nMigen" *)
-module alu_alu0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, alu_op__sv_pred_sz, alu_op__sv_pred_dz, alu_op__sv_saturate, alu_op__SV_Ptype, o, cr_a, xer_ca, xer_ov, xer_so, ra, rb, \xer_so$1 , \xer_ca$2 , p_valid_i, p_ready_o, coresync_clk);
+module alu_alu0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, alu_op__sv_pred_sz, alu_op__sv_pred_dz, alu_op__sv_saturate, alu_op__sv_ldstmode, alu_op__SV_Ptype, o, cr_a, xer_ca, xer_ov, xer_so, ra, rb, \xer_so$1 , \xer_ca$2 , p_valid_i, p_ready_o, coresync_clk);
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \alu_op__SV_Ptype$83 ;
+ wire [1:0] \alu_op__SV_Ptype$86 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [3:0] alu_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [3:0] \alu_op__data_len$78 ;
+ wire [3:0] \alu_op__data_len$80 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \alu_op__fn_unit$63 ;
+ wire [14:0] \alu_op__fn_unit$65 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] alu_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \alu_op__imm_data__data$64 ;
+ wire [63:0] \alu_op__imm_data__data$66 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__imm_data__ok$65 ;
+ wire \alu_op__imm_data__ok$67 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \alu_op__input_carry$74 ;
+ wire [1:0] \alu_op__input_carry$76 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] alu_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \alu_op__insn$79 ;
+ wire [31:0] \alu_op__insn$81 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \alu_op__insn_type$62 ;
+ wire [6:0] \alu_op__insn_type$64 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__invert_in$70 ;
+ wire \alu_op__invert_in$72 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__invert_out;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__invert_out$72 ;
+ wire \alu_op__invert_out$74 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__is_32bit$76 ;
+ wire \alu_op__is_32bit$78 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__is_signed$77 ;
+ wire \alu_op__is_signed$79 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__oe__oe$68 ;
+ wire \alu_op__oe__oe$70 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__oe__ok$69 ;
+ wire \alu_op__oe__ok$71 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__output_carry;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__output_carry$75 ;
+ wire \alu_op__output_carry$77 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__rc__ok$67 ;
+ wire \alu_op__rc__ok$69 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__rc__rc$66 ;
+ wire \alu_op__rc__rc$68 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] alu_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \alu_op__sv_ldstmode$85 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__sv_pred_dz$81 ;
+ wire \alu_op__sv_pred_dz$83 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__sv_pred_sz$80 ;
+ wire \alu_op__sv_pred_sz$82 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \alu_op__sv_saturate$82 ;
+ wire [1:0] \alu_op__sv_saturate$84 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__write_cr0$73 ;
+ wire \alu_op__write_cr0$75 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__zero_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__zero_a$71 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ wire \alu_op__zero_a$73 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output [3:0] cr_a;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \muxid$61 ;
+ wire [1:0] \muxid$63 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
input n_ready_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \pipe1_alu_op__SV_Ptype$25 ;
+ wire [1:0] \pipe1_alu_op__SV_Ptype$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [3:0] pipe1_alu_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe1_alu_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire \pipe1_alu_op__rc__rc$8 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] pipe1_alu_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \pipe1_alu_op__sv_ldstmode$25 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe1_alu_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [1:0] pipe1_xer_ca;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [1:0] \pipe1_xer_ca$27 ;
+ wire [1:0] \pipe1_xer_ca$28 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe1_xer_ca_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe1_xer_so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire \pipe1_xer_so$26 ;
+ wire \pipe1_xer_so$27 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe1_xer_so_ok;
(* enum_base_type = "SVPtype" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \pipe2_alu_op__SV_Ptype$50 ;
+ wire [1:0] \pipe2_alu_op__SV_Ptype$52 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [3:0] pipe2_alu_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [3:0] \pipe2_alu_op__data_len$45 ;
+ wire [3:0] \pipe2_alu_op__data_len$46 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \pipe2_alu_op__fn_unit$30 ;
+ wire [14:0] \pipe2_alu_op__fn_unit$31 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] pipe2_alu_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \pipe2_alu_op__imm_data__data$31 ;
+ wire [63:0] \pipe2_alu_op__imm_data__data$32 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_alu_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_alu_op__imm_data__ok$32 ;
+ wire \pipe2_alu_op__imm_data__ok$33 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \pipe2_alu_op__input_carry$41 ;
+ wire [1:0] \pipe2_alu_op__input_carry$42 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] pipe2_alu_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \pipe2_alu_op__insn$46 ;
+ wire [31:0] \pipe2_alu_op__insn$47 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \pipe2_alu_op__insn_type$29 ;
+ wire [6:0] \pipe2_alu_op__insn_type$30 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_alu_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_alu_op__invert_in$37 ;
+ wire \pipe2_alu_op__invert_in$38 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_alu_op__invert_out;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_alu_op__invert_out$39 ;
+ wire \pipe2_alu_op__invert_out$40 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_alu_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_alu_op__is_32bit$43 ;
+ wire \pipe2_alu_op__is_32bit$44 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_alu_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_alu_op__is_signed$44 ;
+ wire \pipe2_alu_op__is_signed$45 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_alu_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_alu_op__oe__oe$35 ;
+ wire \pipe2_alu_op__oe__oe$36 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_alu_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_alu_op__oe__ok$36 ;
+ wire \pipe2_alu_op__oe__ok$37 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_alu_op__output_carry;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_alu_op__output_carry$42 ;
+ wire \pipe2_alu_op__output_carry$43 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_alu_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_alu_op__rc__ok$34 ;
+ wire \pipe2_alu_op__rc__ok$35 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_alu_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_alu_op__rc__rc$33 ;
+ wire \pipe2_alu_op__rc__rc$34 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] pipe2_alu_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \pipe2_alu_op__sv_ldstmode$51 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_alu_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_alu_op__sv_pred_dz$48 ;
+ wire \pipe2_alu_op__sv_pred_dz$49 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_alu_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_alu_op__sv_pred_sz$47 ;
+ wire \pipe2_alu_op__sv_pred_sz$48 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \pipe2_alu_op__sv_saturate$49 ;
+ wire [1:0] \pipe2_alu_op__sv_saturate$50 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_alu_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_alu_op__write_cr0$40 ;
+ wire \pipe2_alu_op__write_cr0$41 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_alu_op__zero_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_alu_op__zero_a$38 ;
+ wire \pipe2_alu_op__zero_a$39 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [3:0] pipe2_cr_a;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [3:0] \pipe2_cr_a$53 ;
+ wire [3:0] \pipe2_cr_a$55 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe2_cr_a_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \pipe2_cr_a_ok$54 ;
+ wire \pipe2_cr_a_ok$56 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] pipe2_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \pipe2_muxid$28 ;
+ wire [1:0] \pipe2_muxid$29 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
wire pipe2_n_ready_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [63:0] pipe2_o;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \pipe2_o$51 ;
+ wire [63:0] \pipe2_o$53 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe2_o_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \pipe2_o_ok$52 ;
+ wire \pipe2_o_ok$54 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
wire pipe2_p_ready_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [1:0] pipe2_xer_ca;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [1:0] \pipe2_xer_ca$55 ;
+ wire [1:0] \pipe2_xer_ca$57 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe2_xer_ca_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \pipe2_xer_ca_ok$56 ;
+ wire \pipe2_xer_ca_ok$58 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [1:0] pipe2_xer_ov;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [1:0] \pipe2_xer_ov$57 ;
+ wire [1:0] \pipe2_xer_ov$59 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe2_xer_ov_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \pipe2_xer_ov_ok$58 ;
+ wire \pipe2_xer_ov_ok$60 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe2_xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \pipe2_xer_so$59 ;
+ wire \pipe2_xer_so$61 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe2_xer_so_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \pipe2_xer_so_ok$60 ;
+ wire \pipe2_xer_so_ok$62 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] ra;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
);
pipe1 pipe1 (
.alu_op__SV_Ptype(pipe1_alu_op__SV_Ptype),
- .\alu_op__SV_Ptype$23 (\pipe1_alu_op__SV_Ptype$25 ),
+ .\alu_op__SV_Ptype$24 (\pipe1_alu_op__SV_Ptype$26 ),
.alu_op__data_len(pipe1_alu_op__data_len),
.\alu_op__data_len$18 (\pipe1_alu_op__data_len$20 ),
.alu_op__fn_unit(pipe1_alu_op__fn_unit),
.\alu_op__rc__ok$7 (\pipe1_alu_op__rc__ok$9 ),
.alu_op__rc__rc(pipe1_alu_op__rc__rc),
.\alu_op__rc__rc$6 (\pipe1_alu_op__rc__rc$8 ),
+ .alu_op__sv_ldstmode(pipe1_alu_op__sv_ldstmode),
+ .\alu_op__sv_ldstmode$23 (\pipe1_alu_op__sv_ldstmode$25 ),
.alu_op__sv_pred_dz(pipe1_alu_op__sv_pred_dz),
.\alu_op__sv_pred_dz$21 (\pipe1_alu_op__sv_pred_dz$23 ),
.alu_op__sv_pred_sz(pipe1_alu_op__sv_pred_sz),
.ra(pipe1_ra),
.rb(pipe1_rb),
.xer_ca(pipe1_xer_ca),
- .\xer_ca$25 (\pipe1_xer_ca$27 ),
+ .\xer_ca$26 (\pipe1_xer_ca$28 ),
.xer_ca_ok(pipe1_xer_ca_ok),
.xer_ov(pipe1_xer_ov),
.xer_ov_ok(pipe1_xer_ov_ok),
.xer_so(pipe1_xer_so),
- .\xer_so$24 (\pipe1_xer_so$26 ),
+ .\xer_so$25 (\pipe1_xer_so$27 ),
.xer_so_ok(pipe1_xer_so_ok)
);
pipe2 pipe2 (
.alu_op__SV_Ptype(pipe2_alu_op__SV_Ptype),
- .\alu_op__SV_Ptype$23 (\pipe2_alu_op__SV_Ptype$50 ),
+ .\alu_op__SV_Ptype$24 (\pipe2_alu_op__SV_Ptype$52 ),
.alu_op__data_len(pipe2_alu_op__data_len),
- .\alu_op__data_len$18 (\pipe2_alu_op__data_len$45 ),
+ .\alu_op__data_len$18 (\pipe2_alu_op__data_len$46 ),
.alu_op__fn_unit(pipe2_alu_op__fn_unit),
- .\alu_op__fn_unit$3 (\pipe2_alu_op__fn_unit$30 ),
+ .\alu_op__fn_unit$3 (\pipe2_alu_op__fn_unit$31 ),
.alu_op__imm_data__data(pipe2_alu_op__imm_data__data),
- .\alu_op__imm_data__data$4 (\pipe2_alu_op__imm_data__data$31 ),
+ .\alu_op__imm_data__data$4 (\pipe2_alu_op__imm_data__data$32 ),
.alu_op__imm_data__ok(pipe2_alu_op__imm_data__ok),
- .\alu_op__imm_data__ok$5 (\pipe2_alu_op__imm_data__ok$32 ),
+ .\alu_op__imm_data__ok$5 (\pipe2_alu_op__imm_data__ok$33 ),
.alu_op__input_carry(pipe2_alu_op__input_carry),
- .\alu_op__input_carry$14 (\pipe2_alu_op__input_carry$41 ),
+ .\alu_op__input_carry$14 (\pipe2_alu_op__input_carry$42 ),
.alu_op__insn(pipe2_alu_op__insn),
- .\alu_op__insn$19 (\pipe2_alu_op__insn$46 ),
+ .\alu_op__insn$19 (\pipe2_alu_op__insn$47 ),
.alu_op__insn_type(pipe2_alu_op__insn_type),
- .\alu_op__insn_type$2 (\pipe2_alu_op__insn_type$29 ),
+ .\alu_op__insn_type$2 (\pipe2_alu_op__insn_type$30 ),
.alu_op__invert_in(pipe2_alu_op__invert_in),
- .\alu_op__invert_in$10 (\pipe2_alu_op__invert_in$37 ),
+ .\alu_op__invert_in$10 (\pipe2_alu_op__invert_in$38 ),
.alu_op__invert_out(pipe2_alu_op__invert_out),
- .\alu_op__invert_out$12 (\pipe2_alu_op__invert_out$39 ),
+ .\alu_op__invert_out$12 (\pipe2_alu_op__invert_out$40 ),
.alu_op__is_32bit(pipe2_alu_op__is_32bit),
- .\alu_op__is_32bit$16 (\pipe2_alu_op__is_32bit$43 ),
+ .\alu_op__is_32bit$16 (\pipe2_alu_op__is_32bit$44 ),
.alu_op__is_signed(pipe2_alu_op__is_signed),
- .\alu_op__is_signed$17 (\pipe2_alu_op__is_signed$44 ),
+ .\alu_op__is_signed$17 (\pipe2_alu_op__is_signed$45 ),
.alu_op__oe__oe(pipe2_alu_op__oe__oe),
- .\alu_op__oe__oe$8 (\pipe2_alu_op__oe__oe$35 ),
+ .\alu_op__oe__oe$8 (\pipe2_alu_op__oe__oe$36 ),
.alu_op__oe__ok(pipe2_alu_op__oe__ok),
- .\alu_op__oe__ok$9 (\pipe2_alu_op__oe__ok$36 ),
+ .\alu_op__oe__ok$9 (\pipe2_alu_op__oe__ok$37 ),
.alu_op__output_carry(pipe2_alu_op__output_carry),
- .\alu_op__output_carry$15 (\pipe2_alu_op__output_carry$42 ),
+ .\alu_op__output_carry$15 (\pipe2_alu_op__output_carry$43 ),
.alu_op__rc__ok(pipe2_alu_op__rc__ok),
- .\alu_op__rc__ok$7 (\pipe2_alu_op__rc__ok$34 ),
+ .\alu_op__rc__ok$7 (\pipe2_alu_op__rc__ok$35 ),
.alu_op__rc__rc(pipe2_alu_op__rc__rc),
- .\alu_op__rc__rc$6 (\pipe2_alu_op__rc__rc$33 ),
+ .\alu_op__rc__rc$6 (\pipe2_alu_op__rc__rc$34 ),
+ .alu_op__sv_ldstmode(pipe2_alu_op__sv_ldstmode),
+ .\alu_op__sv_ldstmode$23 (\pipe2_alu_op__sv_ldstmode$51 ),
.alu_op__sv_pred_dz(pipe2_alu_op__sv_pred_dz),
- .\alu_op__sv_pred_dz$21 (\pipe2_alu_op__sv_pred_dz$48 ),
+ .\alu_op__sv_pred_dz$21 (\pipe2_alu_op__sv_pred_dz$49 ),
.alu_op__sv_pred_sz(pipe2_alu_op__sv_pred_sz),
- .\alu_op__sv_pred_sz$20 (\pipe2_alu_op__sv_pred_sz$47 ),
+ .\alu_op__sv_pred_sz$20 (\pipe2_alu_op__sv_pred_sz$48 ),
.alu_op__sv_saturate(pipe2_alu_op__sv_saturate),
- .\alu_op__sv_saturate$22 (\pipe2_alu_op__sv_saturate$49 ),
+ .\alu_op__sv_saturate$22 (\pipe2_alu_op__sv_saturate$50 ),
.alu_op__write_cr0(pipe2_alu_op__write_cr0),
- .\alu_op__write_cr0$13 (\pipe2_alu_op__write_cr0$40 ),
+ .\alu_op__write_cr0$13 (\pipe2_alu_op__write_cr0$41 ),
.alu_op__zero_a(pipe2_alu_op__zero_a),
- .\alu_op__zero_a$11 (\pipe2_alu_op__zero_a$38 ),
+ .\alu_op__zero_a$11 (\pipe2_alu_op__zero_a$39 ),
.coresync_clk(coresync_clk),
.coresync_rst(coresync_rst),
.cr_a(pipe2_cr_a),
- .\cr_a$26 (\pipe2_cr_a$53 ),
+ .\cr_a$27 (\pipe2_cr_a$55 ),
.cr_a_ok(pipe2_cr_a_ok),
- .\cr_a_ok$27 (\pipe2_cr_a_ok$54 ),
+ .\cr_a_ok$28 (\pipe2_cr_a_ok$56 ),
.muxid(pipe2_muxid),
- .\muxid$1 (\pipe2_muxid$28 ),
+ .\muxid$1 (\pipe2_muxid$29 ),
.n_ready_i(pipe2_n_ready_i),
.n_valid_o(pipe2_n_valid_o),
.o(pipe2_o),
- .\o$24 (\pipe2_o$51 ),
+ .\o$25 (\pipe2_o$53 ),
.o_ok(pipe2_o_ok),
- .\o_ok$25 (\pipe2_o_ok$52 ),
+ .\o_ok$26 (\pipe2_o_ok$54 ),
.p_ready_o(pipe2_p_ready_o),
.p_valid_i(pipe2_p_valid_i),
.xer_ca(pipe2_xer_ca),
- .\xer_ca$28 (\pipe2_xer_ca$55 ),
+ .\xer_ca$29 (\pipe2_xer_ca$57 ),
.xer_ca_ok(pipe2_xer_ca_ok),
- .\xer_ca_ok$29 (\pipe2_xer_ca_ok$56 ),
+ .\xer_ca_ok$30 (\pipe2_xer_ca_ok$58 ),
.xer_ov(pipe2_xer_ov),
- .\xer_ov$30 (\pipe2_xer_ov$57 ),
+ .\xer_ov$31 (\pipe2_xer_ov$59 ),
.xer_ov_ok(pipe2_xer_ov_ok),
- .\xer_ov_ok$31 (\pipe2_xer_ov_ok$58 ),
+ .\xer_ov_ok$32 (\pipe2_xer_ov_ok$60 ),
.xer_so(pipe2_xer_so),
- .\xer_so$32 (\pipe2_xer_so$59 ),
+ .\xer_so$33 (\pipe2_xer_so$61 ),
.xer_so_ok(pipe2_xer_so_ok),
- .\xer_so_ok$33 (\pipe2_xer_so_ok$60 )
+ .\xer_so_ok$34 (\pipe2_xer_so_ok$62 )
);
assign muxid = 2'h0;
- assign { xer_so_ok, xer_so } = { \pipe2_xer_so_ok$60 , \pipe2_xer_so$59 };
- assign { xer_ov_ok, xer_ov } = { \pipe2_xer_ov_ok$58 , \pipe2_xer_ov$57 };
- assign { xer_ca_ok, xer_ca } = { \pipe2_xer_ca_ok$56 , \pipe2_xer_ca$55 };
- assign { cr_a_ok, cr_a } = { \pipe2_cr_a_ok$54 , \pipe2_cr_a$53 };
- assign { o_ok, o } = { \pipe2_o_ok$52 , \pipe2_o$51 };
- assign { \alu_op__SV_Ptype$83 , \alu_op__sv_saturate$82 , \alu_op__sv_pred_dz$81 , \alu_op__sv_pred_sz$80 , \alu_op__insn$79 , \alu_op__data_len$78 , \alu_op__is_signed$77 , \alu_op__is_32bit$76 , \alu_op__output_carry$75 , \alu_op__input_carry$74 , \alu_op__write_cr0$73 , \alu_op__invert_out$72 , \alu_op__zero_a$71 , \alu_op__invert_in$70 , \alu_op__oe__ok$69 , \alu_op__oe__oe$68 , \alu_op__rc__ok$67 , \alu_op__rc__rc$66 , \alu_op__imm_data__ok$65 , \alu_op__imm_data__data$64 , \alu_op__fn_unit$63 , \alu_op__insn_type$62 } = { \pipe2_alu_op__SV_Ptype$50 , \pipe2_alu_op__sv_saturate$49 , \pipe2_alu_op__sv_pred_dz$48 , \pipe2_alu_op__sv_pred_sz$47 , \pipe2_alu_op__insn$46 , \pipe2_alu_op__data_len$45 , \pipe2_alu_op__is_signed$44 , \pipe2_alu_op__is_32bit$43 , \pipe2_alu_op__output_carry$42 , \pipe2_alu_op__input_carry$41 , \pipe2_alu_op__write_cr0$40 , \pipe2_alu_op__invert_out$39 , \pipe2_alu_op__zero_a$38 , \pipe2_alu_op__invert_in$37 , \pipe2_alu_op__oe__ok$36 , \pipe2_alu_op__oe__oe$35 , \pipe2_alu_op__rc__ok$34 , \pipe2_alu_op__rc__rc$33 , \pipe2_alu_op__imm_data__ok$32 , \pipe2_alu_op__imm_data__data$31 , \pipe2_alu_op__fn_unit$30 , \pipe2_alu_op__insn_type$29 };
- assign \muxid$61 = \pipe2_muxid$28 ;
+ assign { xer_so_ok, xer_so } = { \pipe2_xer_so_ok$62 , \pipe2_xer_so$61 };
+ assign { xer_ov_ok, xer_ov } = { \pipe2_xer_ov_ok$60 , \pipe2_xer_ov$59 };
+ assign { xer_ca_ok, xer_ca } = { \pipe2_xer_ca_ok$58 , \pipe2_xer_ca$57 };
+ assign { cr_a_ok, cr_a } = { \pipe2_cr_a_ok$56 , \pipe2_cr_a$55 };
+ assign { o_ok, o } = { \pipe2_o_ok$54 , \pipe2_o$53 };
+ assign { \alu_op__SV_Ptype$86 , \alu_op__sv_ldstmode$85 , \alu_op__sv_saturate$84 , \alu_op__sv_pred_dz$83 , \alu_op__sv_pred_sz$82 , \alu_op__insn$81 , \alu_op__data_len$80 , \alu_op__is_signed$79 , \alu_op__is_32bit$78 , \alu_op__output_carry$77 , \alu_op__input_carry$76 , \alu_op__write_cr0$75 , \alu_op__invert_out$74 , \alu_op__zero_a$73 , \alu_op__invert_in$72 , \alu_op__oe__ok$71 , \alu_op__oe__oe$70 , \alu_op__rc__ok$69 , \alu_op__rc__rc$68 , \alu_op__imm_data__ok$67 , \alu_op__imm_data__data$66 , \alu_op__fn_unit$65 , \alu_op__insn_type$64 } = { \pipe2_alu_op__SV_Ptype$52 , \pipe2_alu_op__sv_ldstmode$51 , \pipe2_alu_op__sv_saturate$50 , \pipe2_alu_op__sv_pred_dz$49 , \pipe2_alu_op__sv_pred_sz$48 , \pipe2_alu_op__insn$47 , \pipe2_alu_op__data_len$46 , \pipe2_alu_op__is_signed$45 , \pipe2_alu_op__is_32bit$44 , \pipe2_alu_op__output_carry$43 , \pipe2_alu_op__input_carry$42 , \pipe2_alu_op__write_cr0$41 , \pipe2_alu_op__invert_out$40 , \pipe2_alu_op__zero_a$39 , \pipe2_alu_op__invert_in$38 , \pipe2_alu_op__oe__ok$37 , \pipe2_alu_op__oe__oe$36 , \pipe2_alu_op__rc__ok$35 , \pipe2_alu_op__rc__rc$34 , \pipe2_alu_op__imm_data__ok$33 , \pipe2_alu_op__imm_data__data$32 , \pipe2_alu_op__fn_unit$31 , \pipe2_alu_op__insn_type$30 };
+ assign \muxid$63 = \pipe2_muxid$29 ;
assign pipe2_n_ready_i = n_ready_i;
assign n_valid_o = pipe2_n_valid_o;
- assign \pipe1_xer_ca$27 = \xer_ca$2 ;
- assign \pipe1_xer_so$26 = \xer_so$1 ;
+ assign \pipe1_xer_ca$28 = \xer_ca$2 ;
+ assign \pipe1_xer_so$27 = \xer_so$1 ;
assign pipe1_rb = rb;
assign pipe1_ra = ra;
- assign { \pipe1_alu_op__SV_Ptype$25 , \pipe1_alu_op__sv_saturate$24 , \pipe1_alu_op__sv_pred_dz$23 , \pipe1_alu_op__sv_pred_sz$22 , \pipe1_alu_op__insn$21 , \pipe1_alu_op__data_len$20 , \pipe1_alu_op__is_signed$19 , \pipe1_alu_op__is_32bit$18 , \pipe1_alu_op__output_carry$17 , \pipe1_alu_op__input_carry$16 , \pipe1_alu_op__write_cr0$15 , \pipe1_alu_op__invert_out$14 , \pipe1_alu_op__zero_a$13 , \pipe1_alu_op__invert_in$12 , \pipe1_alu_op__oe__ok$11 , \pipe1_alu_op__oe__oe$10 , \pipe1_alu_op__rc__ok$9 , \pipe1_alu_op__rc__rc$8 , \pipe1_alu_op__imm_data__ok$7 , \pipe1_alu_op__imm_data__data$6 , \pipe1_alu_op__fn_unit$5 , \pipe1_alu_op__insn_type$4 } = { alu_op__SV_Ptype, alu_op__sv_saturate, alu_op__sv_pred_dz, alu_op__sv_pred_sz, alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type };
+ assign { \pipe1_alu_op__SV_Ptype$26 , \pipe1_alu_op__sv_ldstmode$25 , \pipe1_alu_op__sv_saturate$24 , \pipe1_alu_op__sv_pred_dz$23 , \pipe1_alu_op__sv_pred_sz$22 , \pipe1_alu_op__insn$21 , \pipe1_alu_op__data_len$20 , \pipe1_alu_op__is_signed$19 , \pipe1_alu_op__is_32bit$18 , \pipe1_alu_op__output_carry$17 , \pipe1_alu_op__input_carry$16 , \pipe1_alu_op__write_cr0$15 , \pipe1_alu_op__invert_out$14 , \pipe1_alu_op__zero_a$13 , \pipe1_alu_op__invert_in$12 , \pipe1_alu_op__oe__ok$11 , \pipe1_alu_op__oe__oe$10 , \pipe1_alu_op__rc__ok$9 , \pipe1_alu_op__rc__rc$8 , \pipe1_alu_op__imm_data__ok$7 , \pipe1_alu_op__imm_data__data$6 , \pipe1_alu_op__fn_unit$5 , \pipe1_alu_op__insn_type$4 } = { alu_op__SV_Ptype, alu_op__sv_ldstmode, alu_op__sv_saturate, alu_op__sv_pred_dz, alu_op__sv_pred_sz, alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type };
assign \pipe1_muxid$3 = 2'h0;
assign p_ready_o = pipe1_p_ready_o;
assign pipe1_p_valid_i = p_valid_i;
assign { pipe2_xer_ca_ok, pipe2_xer_ca } = { pipe1_xer_ca_ok, pipe1_xer_ca };
assign { pipe2_cr_a_ok, pipe2_cr_a } = { pipe1_cr_a_ok, pipe1_cr_a };
assign { pipe2_o_ok, pipe2_o } = { pipe1_o_ok, pipe1_o };
- assign { pipe2_alu_op__SV_Ptype, pipe2_alu_op__sv_saturate, pipe2_alu_op__sv_pred_dz, pipe2_alu_op__sv_pred_sz, pipe2_alu_op__insn, pipe2_alu_op__data_len, pipe2_alu_op__is_signed, pipe2_alu_op__is_32bit, pipe2_alu_op__output_carry, pipe2_alu_op__input_carry, pipe2_alu_op__write_cr0, pipe2_alu_op__invert_out, pipe2_alu_op__zero_a, pipe2_alu_op__invert_in, pipe2_alu_op__oe__ok, pipe2_alu_op__oe__oe, pipe2_alu_op__rc__ok, pipe2_alu_op__rc__rc, pipe2_alu_op__imm_data__ok, pipe2_alu_op__imm_data__data, pipe2_alu_op__fn_unit, pipe2_alu_op__insn_type } = { pipe1_alu_op__SV_Ptype, pipe1_alu_op__sv_saturate, pipe1_alu_op__sv_pred_dz, pipe1_alu_op__sv_pred_sz, pipe1_alu_op__insn, pipe1_alu_op__data_len, pipe1_alu_op__is_signed, pipe1_alu_op__is_32bit, pipe1_alu_op__output_carry, pipe1_alu_op__input_carry, pipe1_alu_op__write_cr0, pipe1_alu_op__invert_out, pipe1_alu_op__zero_a, pipe1_alu_op__invert_in, pipe1_alu_op__oe__ok, pipe1_alu_op__oe__oe, pipe1_alu_op__rc__ok, pipe1_alu_op__rc__rc, pipe1_alu_op__imm_data__ok, pipe1_alu_op__imm_data__data, pipe1_alu_op__fn_unit, pipe1_alu_op__insn_type };
+ assign { pipe2_alu_op__SV_Ptype, pipe2_alu_op__sv_ldstmode, pipe2_alu_op__sv_saturate, pipe2_alu_op__sv_pred_dz, pipe2_alu_op__sv_pred_sz, pipe2_alu_op__insn, pipe2_alu_op__data_len, pipe2_alu_op__is_signed, pipe2_alu_op__is_32bit, pipe2_alu_op__output_carry, pipe2_alu_op__input_carry, pipe2_alu_op__write_cr0, pipe2_alu_op__invert_out, pipe2_alu_op__zero_a, pipe2_alu_op__invert_in, pipe2_alu_op__oe__ok, pipe2_alu_op__oe__oe, pipe2_alu_op__rc__ok, pipe2_alu_op__rc__rc, pipe2_alu_op__imm_data__ok, pipe2_alu_op__imm_data__data, pipe2_alu_op__fn_unit, pipe2_alu_op__insn_type } = { pipe1_alu_op__SV_Ptype, pipe1_alu_op__sv_ldstmode, pipe1_alu_op__sv_saturate, pipe1_alu_op__sv_pred_dz, pipe1_alu_op__sv_pred_sz, pipe1_alu_op__insn, pipe1_alu_op__data_len, pipe1_alu_op__is_signed, pipe1_alu_op__is_32bit, pipe1_alu_op__output_carry, pipe1_alu_op__input_carry, pipe1_alu_op__write_cr0, pipe1_alu_op__invert_out, pipe1_alu_op__zero_a, pipe1_alu_op__invert_in, pipe1_alu_op__oe__ok, pipe1_alu_op__oe__oe, pipe1_alu_op__rc__ok, pipe1_alu_op__rc__rc, pipe1_alu_op__imm_data__ok, pipe1_alu_op__imm_data__data, pipe1_alu_op__fn_unit, pipe1_alu_op__insn_type };
assign pipe2_muxid = pipe1_muxid;
assign pipe1_n_ready_i = pipe2_p_ready_o;
assign pipe2_p_valid_i = pipe1_n_valid_o;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.branch0.alu_branch0" *)
(* generator = "nMigen" *)
-module alu_branch0(coresync_rst, fast1_ok, fast2_ok, nia_ok, n_valid_o, n_ready_i, br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_op__imm_data__data, br_op__imm_data__ok, br_op__lk, br_op__is_32bit, br_op__sv_pred_sz, br_op__sv_pred_dz, br_op__sv_saturate, br_op__SV_Ptype, fast1, fast2, nia, \fast1$1 , \fast2$2 , cr_a, p_valid_i, p_ready_o, coresync_clk);
+module alu_branch0(coresync_rst, fast1_ok, fast2_ok, nia_ok, n_valid_o, n_ready_i, br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_op__imm_data__data, br_op__imm_data__ok, br_op__lk, br_op__is_32bit, br_op__sv_pred_sz, br_op__sv_pred_dz, br_op__sv_saturate, br_op__sv_ldstmode, br_op__SV_Ptype, fast1, fast2, nia, \fast1$1 , \fast2$2 , cr_a, p_valid_i, p_ready_o, coresync_clk);
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \br_op__SV_Ptype$30 ;
+ wire [1:0] \br_op__SV_Ptype$32 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] br_op__cia;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \br_op__cia$19 ;
+ wire [63:0] \br_op__cia$20 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \br_op__fn_unit$21 ;
+ wire [14:0] \br_op__fn_unit$22 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] br_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \br_op__imm_data__data$23 ;
+ wire [63:0] \br_op__imm_data__data$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input br_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \br_op__imm_data__ok$24 ;
+ wire \br_op__imm_data__ok$25 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] br_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \br_op__insn$22 ;
+ wire [31:0] \br_op__insn$23 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \br_op__insn_type$20 ;
+ wire [6:0] \br_op__insn_type$21 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input br_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \br_op__is_32bit$26 ;
+ wire \br_op__is_32bit$27 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input br_op__lk;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \br_op__lk$25 ;
+ wire \br_op__lk$26 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] br_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \br_op__sv_ldstmode$31 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input br_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \br_op__sv_pred_dz$28 ;
+ wire \br_op__sv_pred_dz$29 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input br_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \br_op__sv_pred_sz$27 ;
+ wire \br_op__sv_pred_sz$28 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \br_op__sv_saturate$29 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ wire [1:0] \br_op__sv_saturate$30 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [3:0] cr_a;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \muxid$18 ;
+ wire [1:0] \muxid$19 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
input n_ready_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \pipe_br_op__SV_Ptype$15 ;
+ wire [1:0] \pipe_br_op__SV_Ptype$16 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] pipe_br_op__cia;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_br_op__lk;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire \pipe_br_op__lk$10 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] pipe_br_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \pipe_br_op__sv_ldstmode$15 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_br_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] pipe_fast1;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \pipe_fast1$16 ;
+ wire [63:0] \pipe_fast1$17 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe_fast1_ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] pipe_fast2;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \pipe_fast2$17 ;
+ wire [63:0] \pipe_fast2$18 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe_fast2_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
);
\pipe$19 pipe (
.br_op__SV_Ptype(pipe_br_op__SV_Ptype),
- .\br_op__SV_Ptype$13 (\pipe_br_op__SV_Ptype$15 ),
+ .\br_op__SV_Ptype$14 (\pipe_br_op__SV_Ptype$16 ),
.br_op__cia(pipe_br_op__cia),
.\br_op__cia$2 (\pipe_br_op__cia$4 ),
.br_op__fn_unit(pipe_br_op__fn_unit),
.\br_op__is_32bit$9 (\pipe_br_op__is_32bit$11 ),
.br_op__lk(pipe_br_op__lk),
.\br_op__lk$8 (\pipe_br_op__lk$10 ),
+ .br_op__sv_ldstmode(pipe_br_op__sv_ldstmode),
+ .\br_op__sv_ldstmode$13 (\pipe_br_op__sv_ldstmode$15 ),
.br_op__sv_pred_dz(pipe_br_op__sv_pred_dz),
.\br_op__sv_pred_dz$11 (\pipe_br_op__sv_pred_dz$13 ),
.br_op__sv_pred_sz(pipe_br_op__sv_pred_sz),
.coresync_rst(coresync_rst),
.cr_a(pipe_cr_a),
.fast1(pipe_fast1),
- .\fast1$14 (\pipe_fast1$16 ),
+ .\fast1$15 (\pipe_fast1$17 ),
.fast1_ok(pipe_fast1_ok),
.fast2(pipe_fast2),
- .\fast2$15 (\pipe_fast2$17 ),
+ .\fast2$16 (\pipe_fast2$18 ),
.fast2_ok(pipe_fast2_ok),
.muxid(pipe_muxid),
.\muxid$1 (\pipe_muxid$3 ),
);
assign muxid = 2'h0;
assign { nia_ok, nia } = { pipe_nia_ok, pipe_nia };
- assign { fast2_ok, fast2 } = { pipe_fast2_ok, \pipe_fast2$17 };
- assign { fast1_ok, fast1 } = { pipe_fast1_ok, \pipe_fast1$16 };
- assign { \br_op__SV_Ptype$30 , \br_op__sv_saturate$29 , \br_op__sv_pred_dz$28 , \br_op__sv_pred_sz$27 , \br_op__is_32bit$26 , \br_op__lk$25 , \br_op__imm_data__ok$24 , \br_op__imm_data__data$23 , \br_op__insn$22 , \br_op__fn_unit$21 , \br_op__insn_type$20 , \br_op__cia$19 } = { \pipe_br_op__SV_Ptype$15 , \pipe_br_op__sv_saturate$14 , \pipe_br_op__sv_pred_dz$13 , \pipe_br_op__sv_pred_sz$12 , \pipe_br_op__is_32bit$11 , \pipe_br_op__lk$10 , \pipe_br_op__imm_data__ok$9 , \pipe_br_op__imm_data__data$8 , \pipe_br_op__insn$7 , \pipe_br_op__fn_unit$6 , \pipe_br_op__insn_type$5 , \pipe_br_op__cia$4 };
- assign \muxid$18 = \pipe_muxid$3 ;
+ assign { fast2_ok, fast2 } = { pipe_fast2_ok, \pipe_fast2$18 };
+ assign { fast1_ok, fast1 } = { pipe_fast1_ok, \pipe_fast1$17 };
+ assign { \br_op__SV_Ptype$32 , \br_op__sv_ldstmode$31 , \br_op__sv_saturate$30 , \br_op__sv_pred_dz$29 , \br_op__sv_pred_sz$28 , \br_op__is_32bit$27 , \br_op__lk$26 , \br_op__imm_data__ok$25 , \br_op__imm_data__data$24 , \br_op__insn$23 , \br_op__fn_unit$22 , \br_op__insn_type$21 , \br_op__cia$20 } = { \pipe_br_op__SV_Ptype$16 , \pipe_br_op__sv_ldstmode$15 , \pipe_br_op__sv_saturate$14 , \pipe_br_op__sv_pred_dz$13 , \pipe_br_op__sv_pred_sz$12 , \pipe_br_op__is_32bit$11 , \pipe_br_op__lk$10 , \pipe_br_op__imm_data__ok$9 , \pipe_br_op__imm_data__data$8 , \pipe_br_op__insn$7 , \pipe_br_op__fn_unit$6 , \pipe_br_op__insn_type$5 , \pipe_br_op__cia$4 };
+ assign \muxid$19 = \pipe_muxid$3 ;
assign pipe_n_ready_i = n_ready_i;
assign n_valid_o = pipe_n_valid_o;
assign pipe_cr_a = cr_a;
assign pipe_fast2 = \fast2$2 ;
assign pipe_fast1 = \fast1$1 ;
- assign { pipe_br_op__SV_Ptype, pipe_br_op__sv_saturate, pipe_br_op__sv_pred_dz, pipe_br_op__sv_pred_sz, pipe_br_op__is_32bit, pipe_br_op__lk, pipe_br_op__imm_data__ok, pipe_br_op__imm_data__data, pipe_br_op__insn, pipe_br_op__fn_unit, pipe_br_op__insn_type, pipe_br_op__cia } = { br_op__SV_Ptype, br_op__sv_saturate, br_op__sv_pred_dz, br_op__sv_pred_sz, br_op__is_32bit, br_op__lk, br_op__imm_data__ok, br_op__imm_data__data, br_op__insn, br_op__fn_unit, br_op__insn_type, br_op__cia };
+ assign { pipe_br_op__SV_Ptype, pipe_br_op__sv_ldstmode, pipe_br_op__sv_saturate, pipe_br_op__sv_pred_dz, pipe_br_op__sv_pred_sz, pipe_br_op__is_32bit, pipe_br_op__lk, pipe_br_op__imm_data__ok, pipe_br_op__imm_data__data, pipe_br_op__insn, pipe_br_op__fn_unit, pipe_br_op__insn_type, pipe_br_op__cia } = { br_op__SV_Ptype, br_op__sv_ldstmode, br_op__sv_saturate, br_op__sv_pred_dz, br_op__sv_pred_sz, br_op__is_32bit, br_op__lk, br_op__imm_data__ok, br_op__imm_data__data, br_op__insn, br_op__fn_unit, br_op__insn_type, br_op__cia };
assign pipe_muxid = 2'h0;
assign p_ready_o = pipe_p_ready_o;
assign pipe_p_valid_i = p_valid_i;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0.alu_cr0" *)
(* generator = "nMigen" *)
-module alu_cr0(coresync_rst, o_ok, full_cr_ok, cr_a_ok, n_valid_o, n_ready_i, cr_op__insn_type, cr_op__fn_unit, cr_op__insn, cr_op__sv_pred_sz, cr_op__sv_pred_dz, cr_op__sv_saturate, cr_op__SV_Ptype, o, full_cr, cr_a, ra, rb, \full_cr$1 , \cr_a$2 , cr_b, cr_c, p_valid_i, p_ready_o, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+module alu_cr0(coresync_rst, o_ok, full_cr_ok, cr_a_ok, n_valid_o, n_ready_i, cr_op__insn_type, cr_op__fn_unit, cr_op__insn, cr_op__sv_pred_sz, cr_op__sv_pred_dz, cr_op__sv_saturate, cr_op__sv_ldstmode, cr_op__SV_Ptype, o, full_cr, cr_a, ra, rb, \full_cr$1 , \cr_a$2 , cr_b, cr_c, p_valid_i, p_ready_o, coresync_clk);
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output [3:0] cr_a;
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \cr_op__SV_Ptype$20 ;
+ wire [1:0] \cr_op__SV_Ptype$22 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \cr_op__fn_unit$15 ;
+ wire [14:0] \cr_op__fn_unit$16 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] cr_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \cr_op__insn$16 ;
+ wire [31:0] \cr_op__insn$17 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \cr_op__insn_type$14 ;
+ wire [6:0] \cr_op__insn_type$15 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] cr_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \cr_op__sv_ldstmode$21 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input cr_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \cr_op__sv_pred_dz$18 ;
+ wire \cr_op__sv_pred_dz$19 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input cr_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \cr_op__sv_pred_sz$17 ;
+ wire \cr_op__sv_pred_sz$18 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \cr_op__sv_saturate$19 ;
+ wire [1:0] \cr_op__sv_saturate$20 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output [31:0] full_cr;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \muxid$13 ;
+ wire [1:0] \muxid$14 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
input n_ready_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [3:0] pipe_cr_a;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [3:0] \pipe_cr_a$12 ;
+ wire [3:0] \pipe_cr_a$13 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe_cr_a_ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \pipe_cr_op__SV_Ptype$10 ;
+ wire [1:0] \pipe_cr_op__SV_Ptype$11 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [6:0] \pipe_cr_op__insn_type$4 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] pipe_cr_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \pipe_cr_op__sv_ldstmode$10 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_cr_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [31:0] pipe_full_cr;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [31:0] \pipe_full_cr$11 ;
+ wire [31:0] \pipe_full_cr$12 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe_full_cr_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
.coresync_clk(coresync_clk),
.coresync_rst(coresync_rst),
.cr_a(pipe_cr_a),
- .\cr_a$10 (\pipe_cr_a$12 ),
+ .\cr_a$11 (\pipe_cr_a$13 ),
.cr_a_ok(pipe_cr_a_ok),
.cr_b(pipe_cr_b),
.cr_c(pipe_cr_c),
.cr_op__SV_Ptype(pipe_cr_op__SV_Ptype),
- .\cr_op__SV_Ptype$8 (\pipe_cr_op__SV_Ptype$10 ),
+ .\cr_op__SV_Ptype$9 (\pipe_cr_op__SV_Ptype$11 ),
.cr_op__fn_unit(pipe_cr_op__fn_unit),
.\cr_op__fn_unit$3 (\pipe_cr_op__fn_unit$5 ),
.cr_op__insn(pipe_cr_op__insn),
.\cr_op__insn$4 (\pipe_cr_op__insn$6 ),
.cr_op__insn_type(pipe_cr_op__insn_type),
.\cr_op__insn_type$2 (\pipe_cr_op__insn_type$4 ),
+ .cr_op__sv_ldstmode(pipe_cr_op__sv_ldstmode),
+ .\cr_op__sv_ldstmode$8 (\pipe_cr_op__sv_ldstmode$10 ),
.cr_op__sv_pred_dz(pipe_cr_op__sv_pred_dz),
.\cr_op__sv_pred_dz$6 (\pipe_cr_op__sv_pred_dz$8 ),
.cr_op__sv_pred_sz(pipe_cr_op__sv_pred_sz),
.cr_op__sv_saturate(pipe_cr_op__sv_saturate),
.\cr_op__sv_saturate$7 (\pipe_cr_op__sv_saturate$9 ),
.full_cr(pipe_full_cr),
- .\full_cr$9 (\pipe_full_cr$11 ),
+ .\full_cr$10 (\pipe_full_cr$12 ),
.full_cr_ok(pipe_full_cr_ok),
.muxid(pipe_muxid),
.\muxid$1 (\pipe_muxid$3 ),
.rb(pipe_rb)
);
assign muxid = 2'h0;
- assign { cr_a_ok, cr_a } = { pipe_cr_a_ok, \pipe_cr_a$12 };
- assign { full_cr_ok, full_cr } = { pipe_full_cr_ok, \pipe_full_cr$11 };
+ assign { cr_a_ok, cr_a } = { pipe_cr_a_ok, \pipe_cr_a$13 };
+ assign { full_cr_ok, full_cr } = { pipe_full_cr_ok, \pipe_full_cr$12 };
assign { o_ok, o } = { pipe_o_ok, pipe_o };
- assign { \cr_op__SV_Ptype$20 , \cr_op__sv_saturate$19 , \cr_op__sv_pred_dz$18 , \cr_op__sv_pred_sz$17 , \cr_op__insn$16 , \cr_op__fn_unit$15 , \cr_op__insn_type$14 } = { \pipe_cr_op__SV_Ptype$10 , \pipe_cr_op__sv_saturate$9 , \pipe_cr_op__sv_pred_dz$8 , \pipe_cr_op__sv_pred_sz$7 , \pipe_cr_op__insn$6 , \pipe_cr_op__fn_unit$5 , \pipe_cr_op__insn_type$4 };
- assign \muxid$13 = \pipe_muxid$3 ;
+ assign { \cr_op__SV_Ptype$22 , \cr_op__sv_ldstmode$21 , \cr_op__sv_saturate$20 , \cr_op__sv_pred_dz$19 , \cr_op__sv_pred_sz$18 , \cr_op__insn$17 , \cr_op__fn_unit$16 , \cr_op__insn_type$15 } = { \pipe_cr_op__SV_Ptype$11 , \pipe_cr_op__sv_ldstmode$10 , \pipe_cr_op__sv_saturate$9 , \pipe_cr_op__sv_pred_dz$8 , \pipe_cr_op__sv_pred_sz$7 , \pipe_cr_op__insn$6 , \pipe_cr_op__fn_unit$5 , \pipe_cr_op__insn_type$4 };
+ assign \muxid$14 = \pipe_muxid$3 ;
assign pipe_n_ready_i = n_ready_i;
assign n_valid_o = pipe_n_valid_o;
assign pipe_cr_c = cr_c;
assign pipe_full_cr = \full_cr$1 ;
assign pipe_rb = rb;
assign pipe_ra = ra;
- assign { pipe_cr_op__SV_Ptype, pipe_cr_op__sv_saturate, pipe_cr_op__sv_pred_dz, pipe_cr_op__sv_pred_sz, pipe_cr_op__insn, pipe_cr_op__fn_unit, pipe_cr_op__insn_type } = { cr_op__SV_Ptype, cr_op__sv_saturate, cr_op__sv_pred_dz, cr_op__sv_pred_sz, cr_op__insn, cr_op__fn_unit, cr_op__insn_type };
+ assign { pipe_cr_op__SV_Ptype, pipe_cr_op__sv_ldstmode, pipe_cr_op__sv_saturate, pipe_cr_op__sv_pred_dz, pipe_cr_op__sv_pred_sz, pipe_cr_op__insn, pipe_cr_op__fn_unit, pipe_cr_op__insn_type } = { cr_op__SV_Ptype, cr_op__sv_ldstmode, cr_op__sv_saturate, cr_op__sv_pred_dz, cr_op__sv_pred_sz, cr_op__insn, cr_op__fn_unit, cr_op__insn_type };
assign pipe_muxid = 2'h0;
assign p_ready_o = pipe_p_ready_o;
assign pipe_p_valid_i = p_valid_i;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0" *)
(* generator = "nMigen" *)
-module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, o, cr_a, xer_ov, xer_so, ra, rb, \xer_so$1 , p_valid_i, p_ready_o, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__sv_ldstmode, logical_op__SV_Ptype, o, cr_a, xer_ov, xer_so, ra, rb, \xer_so$1 , p_valid_i, p_ready_o, coresync_clk);
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output [3:0] cr_a;
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \logical_op__SV_Ptype$105 ;
+ wire [1:0] \logical_op__SV_Ptype$109 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [3:0] logical_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [3:0] \logical_op__data_len$100 ;
+ wire [3:0] \logical_op__data_len$103 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \logical_op__fn_unit$85 ;
+ wire [14:0] \logical_op__fn_unit$88 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] logical_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \logical_op__imm_data__data$86 ;
+ wire [63:0] \logical_op__imm_data__data$89 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__imm_data__ok$87 ;
+ wire \logical_op__imm_data__ok$90 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \logical_op__input_carry$94 ;
+ wire [1:0] \logical_op__input_carry$97 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] logical_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \logical_op__insn$101 ;
+ wire [31:0] \logical_op__insn$104 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \logical_op__insn_type$84 ;
+ wire [6:0] \logical_op__insn_type$87 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__invert_in$92 ;
+ wire \logical_op__invert_in$95 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__invert_out;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__invert_out$95 ;
+ wire \logical_op__invert_out$98 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__is_32bit$98 ;
+ wire \logical_op__is_32bit$101 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__is_signed$99 ;
+ wire \logical_op__is_signed$102 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__oe__oe$90 ;
+ wire \logical_op__oe__oe$93 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__oe__ok$91 ;
+ wire \logical_op__oe__ok$94 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__output_carry;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__output_carry$97 ;
+ wire \logical_op__output_carry$100 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__rc__ok$89 ;
+ wire \logical_op__rc__ok$92 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__rc__rc$88 ;
+ wire \logical_op__rc__rc$91 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] logical_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \logical_op__sv_ldstmode$108 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__sv_pred_dz$103 ;
+ wire \logical_op__sv_pred_dz$106 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__sv_pred_sz$102 ;
+ wire \logical_op__sv_pred_sz$105 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \logical_op__sv_saturate$104 ;
+ wire [1:0] \logical_op__sv_saturate$107 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__write_cr0$96 ;
+ wire \logical_op__write_cr0$99 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__zero_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__zero_a$93 ;
+ wire \logical_op__zero_a$96 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \muxid$83 ;
+ wire [1:0] \muxid$86 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
input n_ready_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \pipe_end_logical_op__SV_Ptype$81 ;
+ wire [1:0] \pipe_end_logical_op__SV_Ptype$84 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [3:0] pipe_end_logical_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [3:0] \pipe_end_logical_op__data_len$76 ;
+ wire [3:0] \pipe_end_logical_op__data_len$78 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \pipe_end_logical_op__fn_unit$61 ;
+ wire [14:0] \pipe_end_logical_op__fn_unit$63 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] pipe_end_logical_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \pipe_end_logical_op__imm_data__data$62 ;
+ wire [63:0] \pipe_end_logical_op__imm_data__data$64 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_end_logical_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_end_logical_op__imm_data__ok$63 ;
+ wire \pipe_end_logical_op__imm_data__ok$65 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \pipe_end_logical_op__input_carry$70 ;
+ wire [1:0] \pipe_end_logical_op__input_carry$72 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] pipe_end_logical_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \pipe_end_logical_op__insn$77 ;
+ wire [31:0] \pipe_end_logical_op__insn$79 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \pipe_end_logical_op__insn_type$60 ;
+ wire [6:0] \pipe_end_logical_op__insn_type$62 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_end_logical_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_end_logical_op__invert_in$68 ;
+ wire \pipe_end_logical_op__invert_in$70 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_end_logical_op__invert_out;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_end_logical_op__invert_out$71 ;
+ wire \pipe_end_logical_op__invert_out$73 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_end_logical_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_end_logical_op__is_32bit$74 ;
+ wire \pipe_end_logical_op__is_32bit$76 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_end_logical_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_end_logical_op__is_signed$75 ;
+ wire \pipe_end_logical_op__is_signed$77 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_end_logical_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_end_logical_op__oe__oe$66 ;
+ wire \pipe_end_logical_op__oe__oe$68 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_end_logical_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_end_logical_op__oe__ok$67 ;
+ wire \pipe_end_logical_op__oe__ok$69 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_end_logical_op__output_carry;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_end_logical_op__output_carry$73 ;
+ wire \pipe_end_logical_op__output_carry$75 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_end_logical_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_end_logical_op__rc__ok$65 ;
+ wire \pipe_end_logical_op__rc__ok$67 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_end_logical_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_end_logical_op__rc__rc$64 ;
+ wire \pipe_end_logical_op__rc__rc$66 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] pipe_end_logical_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \pipe_end_logical_op__sv_ldstmode$83 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_end_logical_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_end_logical_op__sv_pred_dz$79 ;
+ wire \pipe_end_logical_op__sv_pred_dz$81 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_end_logical_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_end_logical_op__sv_pred_sz$78 ;
+ wire \pipe_end_logical_op__sv_pred_sz$80 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \pipe_end_logical_op__sv_saturate$80 ;
+ wire [1:0] \pipe_end_logical_op__sv_saturate$82 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_end_logical_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_end_logical_op__write_cr0$72 ;
+ wire \pipe_end_logical_op__write_cr0$74 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_end_logical_op__zero_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_end_logical_op__zero_a$69 ;
+ wire \pipe_end_logical_op__zero_a$71 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] pipe_end_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \pipe_end_muxid$59 ;
+ wire [1:0] \pipe_end_muxid$61 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
wire pipe_end_n_ready_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire pipe_end_xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \pipe_end_xer_so$82 ;
+ wire \pipe_end_xer_so$85 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe_end_xer_so_ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
wire pipe_middle_0_div_by_zero;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
- wire \pipe_middle_0_div_by_zero$58 ;
+ wire \pipe_middle_0_div_by_zero$60 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
wire pipe_middle_0_dive_abs_ov32;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
- wire \pipe_middle_0_dive_abs_ov32$56 ;
+ wire \pipe_middle_0_dive_abs_ov32$58 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *)
wire pipe_middle_0_dive_abs_ov64;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *)
- wire \pipe_middle_0_dive_abs_ov64$57 ;
+ wire \pipe_middle_0_dive_abs_ov64$59 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *)
wire [127:0] pipe_middle_0_dividend;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *)
wire pipe_middle_0_dividend_neg;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *)
- wire \pipe_middle_0_dividend_neg$55 ;
+ wire \pipe_middle_0_dividend_neg$57 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *)
wire pipe_middle_0_divisor_neg;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *)
- wire \pipe_middle_0_divisor_neg$54 ;
+ wire \pipe_middle_0_divisor_neg$56 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *)
wire [63:0] pipe_middle_0_divisor_radicand;
(* enum_base_type = "SVPtype" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \pipe_middle_0_logical_op__SV_Ptype$50 ;
+ wire [1:0] \pipe_middle_0_logical_op__SV_Ptype$52 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [3:0] pipe_middle_0_logical_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [3:0] \pipe_middle_0_logical_op__data_len$45 ;
+ wire [3:0] \pipe_middle_0_logical_op__data_len$46 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \pipe_middle_0_logical_op__fn_unit$30 ;
+ wire [14:0] \pipe_middle_0_logical_op__fn_unit$31 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] pipe_middle_0_logical_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \pipe_middle_0_logical_op__imm_data__data$31 ;
+ wire [63:0] \pipe_middle_0_logical_op__imm_data__data$32 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_middle_0_logical_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_middle_0_logical_op__imm_data__ok$32 ;
+ wire \pipe_middle_0_logical_op__imm_data__ok$33 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \pipe_middle_0_logical_op__input_carry$39 ;
+ wire [1:0] \pipe_middle_0_logical_op__input_carry$40 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] pipe_middle_0_logical_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \pipe_middle_0_logical_op__insn$46 ;
+ wire [31:0] \pipe_middle_0_logical_op__insn$47 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \pipe_middle_0_logical_op__insn_type$29 ;
+ wire [6:0] \pipe_middle_0_logical_op__insn_type$30 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_middle_0_logical_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_middle_0_logical_op__invert_in$37 ;
+ wire \pipe_middle_0_logical_op__invert_in$38 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_middle_0_logical_op__invert_out;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_middle_0_logical_op__invert_out$40 ;
+ wire \pipe_middle_0_logical_op__invert_out$41 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_middle_0_logical_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_middle_0_logical_op__is_32bit$43 ;
+ wire \pipe_middle_0_logical_op__is_32bit$44 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_middle_0_logical_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_middle_0_logical_op__is_signed$44 ;
+ wire \pipe_middle_0_logical_op__is_signed$45 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_middle_0_logical_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_middle_0_logical_op__oe__oe$35 ;
+ wire \pipe_middle_0_logical_op__oe__oe$36 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_middle_0_logical_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_middle_0_logical_op__oe__ok$36 ;
+ wire \pipe_middle_0_logical_op__oe__ok$37 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_middle_0_logical_op__output_carry;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_middle_0_logical_op__output_carry$42 ;
+ wire \pipe_middle_0_logical_op__output_carry$43 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_middle_0_logical_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_middle_0_logical_op__rc__ok$34 ;
+ wire \pipe_middle_0_logical_op__rc__ok$35 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_middle_0_logical_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_middle_0_logical_op__rc__rc$33 ;
+ wire \pipe_middle_0_logical_op__rc__rc$34 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] pipe_middle_0_logical_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \pipe_middle_0_logical_op__sv_ldstmode$51 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_middle_0_logical_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_middle_0_logical_op__sv_pred_dz$48 ;
+ wire \pipe_middle_0_logical_op__sv_pred_dz$49 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_middle_0_logical_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_middle_0_logical_op__sv_pred_sz$47 ;
+ wire \pipe_middle_0_logical_op__sv_pred_sz$48 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \pipe_middle_0_logical_op__sv_saturate$49 ;
+ wire [1:0] \pipe_middle_0_logical_op__sv_saturate$50 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_middle_0_logical_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_middle_0_logical_op__write_cr0$41 ;
+ wire \pipe_middle_0_logical_op__write_cr0$42 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_middle_0_logical_op__zero_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe_middle_0_logical_op__zero_a$38 ;
+ wire \pipe_middle_0_logical_op__zero_a$39 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] pipe_middle_0_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \pipe_middle_0_muxid$28 ;
+ wire [1:0] \pipe_middle_0_muxid$29 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
wire pipe_middle_0_n_ready_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] pipe_middle_0_ra;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \pipe_middle_0_ra$51 ;
+ wire [63:0] \pipe_middle_0_ra$53 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] pipe_middle_0_rb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \pipe_middle_0_rb$52 ;
+ wire [63:0] \pipe_middle_0_rb$54 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" *)
wire [191:0] pipe_middle_0_remainder;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire pipe_middle_0_xer_so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire \pipe_middle_0_xer_so$53 ;
+ wire \pipe_middle_0_xer_so$55 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
wire pipe_start_div_by_zero;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \pipe_start_logical_op__SV_Ptype$24 ;
+ wire [1:0] \pipe_start_logical_op__SV_Ptype$25 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [3:0] pipe_start_logical_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_start_logical_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire \pipe_start_logical_op__rc__rc$7 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] pipe_start_logical_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \pipe_start_logical_op__sv_ldstmode$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_start_logical_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] pipe_start_ra;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \pipe_start_ra$25 ;
+ wire [63:0] \pipe_start_ra$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] pipe_start_rb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \pipe_start_rb$26 ;
+ wire [63:0] \pipe_start_rb$27 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire pipe_start_xer_so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire \pipe_start_xer_so$27 ;
+ wire \pipe_start_xer_so$28 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] ra;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
.dividend_neg(pipe_end_dividend_neg),
.divisor_neg(pipe_end_divisor_neg),
.logical_op__SV_Ptype(pipe_end_logical_op__SV_Ptype),
- .\logical_op__SV_Ptype$23 (\pipe_end_logical_op__SV_Ptype$81 ),
+ .\logical_op__SV_Ptype$24 (\pipe_end_logical_op__SV_Ptype$84 ),
.logical_op__data_len(pipe_end_logical_op__data_len),
- .\logical_op__data_len$18 (\pipe_end_logical_op__data_len$76 ),
+ .\logical_op__data_len$18 (\pipe_end_logical_op__data_len$78 ),
.logical_op__fn_unit(pipe_end_logical_op__fn_unit),
- .\logical_op__fn_unit$3 (\pipe_end_logical_op__fn_unit$61 ),
+ .\logical_op__fn_unit$3 (\pipe_end_logical_op__fn_unit$63 ),
.logical_op__imm_data__data(pipe_end_logical_op__imm_data__data),
- .\logical_op__imm_data__data$4 (\pipe_end_logical_op__imm_data__data$62 ),
+ .\logical_op__imm_data__data$4 (\pipe_end_logical_op__imm_data__data$64 ),
.logical_op__imm_data__ok(pipe_end_logical_op__imm_data__ok),
- .\logical_op__imm_data__ok$5 (\pipe_end_logical_op__imm_data__ok$63 ),
+ .\logical_op__imm_data__ok$5 (\pipe_end_logical_op__imm_data__ok$65 ),
.logical_op__input_carry(pipe_end_logical_op__input_carry),
- .\logical_op__input_carry$12 (\pipe_end_logical_op__input_carry$70 ),
+ .\logical_op__input_carry$12 (\pipe_end_logical_op__input_carry$72 ),
.logical_op__insn(pipe_end_logical_op__insn),
- .\logical_op__insn$19 (\pipe_end_logical_op__insn$77 ),
+ .\logical_op__insn$19 (\pipe_end_logical_op__insn$79 ),
.logical_op__insn_type(pipe_end_logical_op__insn_type),
- .\logical_op__insn_type$2 (\pipe_end_logical_op__insn_type$60 ),
+ .\logical_op__insn_type$2 (\pipe_end_logical_op__insn_type$62 ),
.logical_op__invert_in(pipe_end_logical_op__invert_in),
- .\logical_op__invert_in$10 (\pipe_end_logical_op__invert_in$68 ),
+ .\logical_op__invert_in$10 (\pipe_end_logical_op__invert_in$70 ),
.logical_op__invert_out(pipe_end_logical_op__invert_out),
- .\logical_op__invert_out$13 (\pipe_end_logical_op__invert_out$71 ),
+ .\logical_op__invert_out$13 (\pipe_end_logical_op__invert_out$73 ),
.logical_op__is_32bit(pipe_end_logical_op__is_32bit),
- .\logical_op__is_32bit$16 (\pipe_end_logical_op__is_32bit$74 ),
+ .\logical_op__is_32bit$16 (\pipe_end_logical_op__is_32bit$76 ),
.logical_op__is_signed(pipe_end_logical_op__is_signed),
- .\logical_op__is_signed$17 (\pipe_end_logical_op__is_signed$75 ),
+ .\logical_op__is_signed$17 (\pipe_end_logical_op__is_signed$77 ),
.logical_op__oe__oe(pipe_end_logical_op__oe__oe),
- .\logical_op__oe__oe$8 (\pipe_end_logical_op__oe__oe$66 ),
+ .\logical_op__oe__oe$8 (\pipe_end_logical_op__oe__oe$68 ),
.logical_op__oe__ok(pipe_end_logical_op__oe__ok),
- .\logical_op__oe__ok$9 (\pipe_end_logical_op__oe__ok$67 ),
+ .\logical_op__oe__ok$9 (\pipe_end_logical_op__oe__ok$69 ),
.logical_op__output_carry(pipe_end_logical_op__output_carry),
- .\logical_op__output_carry$15 (\pipe_end_logical_op__output_carry$73 ),
+ .\logical_op__output_carry$15 (\pipe_end_logical_op__output_carry$75 ),
.logical_op__rc__ok(pipe_end_logical_op__rc__ok),
- .\logical_op__rc__ok$7 (\pipe_end_logical_op__rc__ok$65 ),
+ .\logical_op__rc__ok$7 (\pipe_end_logical_op__rc__ok$67 ),
.logical_op__rc__rc(pipe_end_logical_op__rc__rc),
- .\logical_op__rc__rc$6 (\pipe_end_logical_op__rc__rc$64 ),
+ .\logical_op__rc__rc$6 (\pipe_end_logical_op__rc__rc$66 ),
+ .logical_op__sv_ldstmode(pipe_end_logical_op__sv_ldstmode),
+ .\logical_op__sv_ldstmode$23 (\pipe_end_logical_op__sv_ldstmode$83 ),
.logical_op__sv_pred_dz(pipe_end_logical_op__sv_pred_dz),
- .\logical_op__sv_pred_dz$21 (\pipe_end_logical_op__sv_pred_dz$79 ),
+ .\logical_op__sv_pred_dz$21 (\pipe_end_logical_op__sv_pred_dz$81 ),
.logical_op__sv_pred_sz(pipe_end_logical_op__sv_pred_sz),
- .\logical_op__sv_pred_sz$20 (\pipe_end_logical_op__sv_pred_sz$78 ),
+ .\logical_op__sv_pred_sz$20 (\pipe_end_logical_op__sv_pred_sz$80 ),
.logical_op__sv_saturate(pipe_end_logical_op__sv_saturate),
- .\logical_op__sv_saturate$22 (\pipe_end_logical_op__sv_saturate$80 ),
+ .\logical_op__sv_saturate$22 (\pipe_end_logical_op__sv_saturate$82 ),
.logical_op__write_cr0(pipe_end_logical_op__write_cr0),
- .\logical_op__write_cr0$14 (\pipe_end_logical_op__write_cr0$72 ),
+ .\logical_op__write_cr0$14 (\pipe_end_logical_op__write_cr0$74 ),
.logical_op__zero_a(pipe_end_logical_op__zero_a),
- .\logical_op__zero_a$11 (\pipe_end_logical_op__zero_a$69 ),
+ .\logical_op__zero_a$11 (\pipe_end_logical_op__zero_a$71 ),
.muxid(pipe_end_muxid),
- .\muxid$1 (\pipe_end_muxid$59 ),
+ .\muxid$1 (\pipe_end_muxid$61 ),
.n_ready_i(pipe_end_n_ready_i),
.n_valid_o(pipe_end_n_valid_o),
.o(pipe_end_o),
.xer_ov(pipe_end_xer_ov),
.xer_ov_ok(pipe_end_xer_ov_ok),
.xer_so(pipe_end_xer_so),
- .\xer_so$24 (\pipe_end_xer_so$82 ),
+ .\xer_so$25 (\pipe_end_xer_so$85 ),
.xer_so_ok(pipe_end_xer_so_ok)
);
pipe_middle_0 pipe_middle_0 (
.coresync_clk(coresync_clk),
.coresync_rst(coresync_rst),
.div_by_zero(pipe_middle_0_div_by_zero),
- .\div_by_zero$31 (\pipe_middle_0_div_by_zero$58 ),
+ .\div_by_zero$32 (\pipe_middle_0_div_by_zero$60 ),
.dive_abs_ov32(pipe_middle_0_dive_abs_ov32),
- .\dive_abs_ov32$29 (\pipe_middle_0_dive_abs_ov32$56 ),
+ .\dive_abs_ov32$30 (\pipe_middle_0_dive_abs_ov32$58 ),
.dive_abs_ov64(pipe_middle_0_dive_abs_ov64),
- .\dive_abs_ov64$30 (\pipe_middle_0_dive_abs_ov64$57 ),
+ .\dive_abs_ov64$31 (\pipe_middle_0_dive_abs_ov64$59 ),
.dividend(pipe_middle_0_dividend),
.dividend_neg(pipe_middle_0_dividend_neg),
- .\dividend_neg$28 (\pipe_middle_0_dividend_neg$55 ),
+ .\dividend_neg$29 (\pipe_middle_0_dividend_neg$57 ),
.divisor_neg(pipe_middle_0_divisor_neg),
- .\divisor_neg$27 (\pipe_middle_0_divisor_neg$54 ),
+ .\divisor_neg$28 (\pipe_middle_0_divisor_neg$56 ),
.divisor_radicand(pipe_middle_0_divisor_radicand),
.logical_op__SV_Ptype(pipe_middle_0_logical_op__SV_Ptype),
- .\logical_op__SV_Ptype$23 (\pipe_middle_0_logical_op__SV_Ptype$50 ),
+ .\logical_op__SV_Ptype$24 (\pipe_middle_0_logical_op__SV_Ptype$52 ),
.logical_op__data_len(pipe_middle_0_logical_op__data_len),
- .\logical_op__data_len$18 (\pipe_middle_0_logical_op__data_len$45 ),
+ .\logical_op__data_len$18 (\pipe_middle_0_logical_op__data_len$46 ),
.logical_op__fn_unit(pipe_middle_0_logical_op__fn_unit),
- .\logical_op__fn_unit$3 (\pipe_middle_0_logical_op__fn_unit$30 ),
+ .\logical_op__fn_unit$3 (\pipe_middle_0_logical_op__fn_unit$31 ),
.logical_op__imm_data__data(pipe_middle_0_logical_op__imm_data__data),
- .\logical_op__imm_data__data$4 (\pipe_middle_0_logical_op__imm_data__data$31 ),
+ .\logical_op__imm_data__data$4 (\pipe_middle_0_logical_op__imm_data__data$32 ),
.logical_op__imm_data__ok(pipe_middle_0_logical_op__imm_data__ok),
- .\logical_op__imm_data__ok$5 (\pipe_middle_0_logical_op__imm_data__ok$32 ),
+ .\logical_op__imm_data__ok$5 (\pipe_middle_0_logical_op__imm_data__ok$33 ),
.logical_op__input_carry(pipe_middle_0_logical_op__input_carry),
- .\logical_op__input_carry$12 (\pipe_middle_0_logical_op__input_carry$39 ),
+ .\logical_op__input_carry$12 (\pipe_middle_0_logical_op__input_carry$40 ),
.logical_op__insn(pipe_middle_0_logical_op__insn),
- .\logical_op__insn$19 (\pipe_middle_0_logical_op__insn$46 ),
+ .\logical_op__insn$19 (\pipe_middle_0_logical_op__insn$47 ),
.logical_op__insn_type(pipe_middle_0_logical_op__insn_type),
- .\logical_op__insn_type$2 (\pipe_middle_0_logical_op__insn_type$29 ),
+ .\logical_op__insn_type$2 (\pipe_middle_0_logical_op__insn_type$30 ),
.logical_op__invert_in(pipe_middle_0_logical_op__invert_in),
- .\logical_op__invert_in$10 (\pipe_middle_0_logical_op__invert_in$37 ),
+ .\logical_op__invert_in$10 (\pipe_middle_0_logical_op__invert_in$38 ),
.logical_op__invert_out(pipe_middle_0_logical_op__invert_out),
- .\logical_op__invert_out$13 (\pipe_middle_0_logical_op__invert_out$40 ),
+ .\logical_op__invert_out$13 (\pipe_middle_0_logical_op__invert_out$41 ),
.logical_op__is_32bit(pipe_middle_0_logical_op__is_32bit),
- .\logical_op__is_32bit$16 (\pipe_middle_0_logical_op__is_32bit$43 ),
+ .\logical_op__is_32bit$16 (\pipe_middle_0_logical_op__is_32bit$44 ),
.logical_op__is_signed(pipe_middle_0_logical_op__is_signed),
- .\logical_op__is_signed$17 (\pipe_middle_0_logical_op__is_signed$44 ),
+ .\logical_op__is_signed$17 (\pipe_middle_0_logical_op__is_signed$45 ),
.logical_op__oe__oe(pipe_middle_0_logical_op__oe__oe),
- .\logical_op__oe__oe$8 (\pipe_middle_0_logical_op__oe__oe$35 ),
+ .\logical_op__oe__oe$8 (\pipe_middle_0_logical_op__oe__oe$36 ),
.logical_op__oe__ok(pipe_middle_0_logical_op__oe__ok),
- .\logical_op__oe__ok$9 (\pipe_middle_0_logical_op__oe__ok$36 ),
+ .\logical_op__oe__ok$9 (\pipe_middle_0_logical_op__oe__ok$37 ),
.logical_op__output_carry(pipe_middle_0_logical_op__output_carry),
- .\logical_op__output_carry$15 (\pipe_middle_0_logical_op__output_carry$42 ),
+ .\logical_op__output_carry$15 (\pipe_middle_0_logical_op__output_carry$43 ),
.logical_op__rc__ok(pipe_middle_0_logical_op__rc__ok),
- .\logical_op__rc__ok$7 (\pipe_middle_0_logical_op__rc__ok$34 ),
+ .\logical_op__rc__ok$7 (\pipe_middle_0_logical_op__rc__ok$35 ),
.logical_op__rc__rc(pipe_middle_0_logical_op__rc__rc),
- .\logical_op__rc__rc$6 (\pipe_middle_0_logical_op__rc__rc$33 ),
+ .\logical_op__rc__rc$6 (\pipe_middle_0_logical_op__rc__rc$34 ),
+ .logical_op__sv_ldstmode(pipe_middle_0_logical_op__sv_ldstmode),
+ .\logical_op__sv_ldstmode$23 (\pipe_middle_0_logical_op__sv_ldstmode$51 ),
.logical_op__sv_pred_dz(pipe_middle_0_logical_op__sv_pred_dz),
- .\logical_op__sv_pred_dz$21 (\pipe_middle_0_logical_op__sv_pred_dz$48 ),
+ .\logical_op__sv_pred_dz$21 (\pipe_middle_0_logical_op__sv_pred_dz$49 ),
.logical_op__sv_pred_sz(pipe_middle_0_logical_op__sv_pred_sz),
- .\logical_op__sv_pred_sz$20 (\pipe_middle_0_logical_op__sv_pred_sz$47 ),
+ .\logical_op__sv_pred_sz$20 (\pipe_middle_0_logical_op__sv_pred_sz$48 ),
.logical_op__sv_saturate(pipe_middle_0_logical_op__sv_saturate),
- .\logical_op__sv_saturate$22 (\pipe_middle_0_logical_op__sv_saturate$49 ),
+ .\logical_op__sv_saturate$22 (\pipe_middle_0_logical_op__sv_saturate$50 ),
.logical_op__write_cr0(pipe_middle_0_logical_op__write_cr0),
- .\logical_op__write_cr0$14 (\pipe_middle_0_logical_op__write_cr0$41 ),
+ .\logical_op__write_cr0$14 (\pipe_middle_0_logical_op__write_cr0$42 ),
.logical_op__zero_a(pipe_middle_0_logical_op__zero_a),
- .\logical_op__zero_a$11 (\pipe_middle_0_logical_op__zero_a$38 ),
+ .\logical_op__zero_a$11 (\pipe_middle_0_logical_op__zero_a$39 ),
.muxid(pipe_middle_0_muxid),
- .\muxid$1 (\pipe_middle_0_muxid$28 ),
+ .\muxid$1 (\pipe_middle_0_muxid$29 ),
.n_ready_i(pipe_middle_0_n_ready_i),
.n_valid_o(pipe_middle_0_n_valid_o),
.operation(pipe_middle_0_operation),
.p_valid_i(pipe_middle_0_p_valid_i),
.quotient_root(pipe_middle_0_quotient_root),
.ra(pipe_middle_0_ra),
- .\ra$24 (\pipe_middle_0_ra$51 ),
+ .\ra$25 (\pipe_middle_0_ra$53 ),
.rb(pipe_middle_0_rb),
- .\rb$25 (\pipe_middle_0_rb$52 ),
+ .\rb$26 (\pipe_middle_0_rb$54 ),
.remainder(pipe_middle_0_remainder),
.xer_so(pipe_middle_0_xer_so),
- .\xer_so$26 (\pipe_middle_0_xer_so$53 )
+ .\xer_so$27 (\pipe_middle_0_xer_so$55 )
);
pipe_start pipe_start (
.coresync_clk(coresync_clk),
.divisor_neg(pipe_start_divisor_neg),
.divisor_radicand(pipe_start_divisor_radicand),
.logical_op__SV_Ptype(pipe_start_logical_op__SV_Ptype),
- .\logical_op__SV_Ptype$23 (\pipe_start_logical_op__SV_Ptype$24 ),
+ .\logical_op__SV_Ptype$24 (\pipe_start_logical_op__SV_Ptype$25 ),
.logical_op__data_len(pipe_start_logical_op__data_len),
.\logical_op__data_len$18 (\pipe_start_logical_op__data_len$19 ),
.logical_op__fn_unit(pipe_start_logical_op__fn_unit),
.\logical_op__rc__ok$7 (\pipe_start_logical_op__rc__ok$8 ),
.logical_op__rc__rc(pipe_start_logical_op__rc__rc),
.\logical_op__rc__rc$6 (\pipe_start_logical_op__rc__rc$7 ),
+ .logical_op__sv_ldstmode(pipe_start_logical_op__sv_ldstmode),
+ .\logical_op__sv_ldstmode$23 (\pipe_start_logical_op__sv_ldstmode$24 ),
.logical_op__sv_pred_dz(pipe_start_logical_op__sv_pred_dz),
.\logical_op__sv_pred_dz$21 (\pipe_start_logical_op__sv_pred_dz$22 ),
.logical_op__sv_pred_sz(pipe_start_logical_op__sv_pred_sz),
.p_ready_o(pipe_start_p_ready_o),
.p_valid_i(pipe_start_p_valid_i),
.ra(pipe_start_ra),
- .\ra$24 (\pipe_start_ra$25 ),
+ .\ra$25 (\pipe_start_ra$26 ),
.rb(pipe_start_rb),
- .\rb$25 (\pipe_start_rb$26 ),
+ .\rb$26 (\pipe_start_rb$27 ),
.xer_so(pipe_start_xer_so),
- .\xer_so$26 (\pipe_start_xer_so$27 )
+ .\xer_so$27 (\pipe_start_xer_so$28 )
);
assign muxid = 2'h0;
- assign { xer_so_ok, xer_so } = { pipe_end_xer_so_ok, \pipe_end_xer_so$82 };
+ assign { xer_so_ok, xer_so } = { pipe_end_xer_so_ok, \pipe_end_xer_so$85 };
assign { xer_ov_ok, xer_ov } = { pipe_end_xer_ov_ok, pipe_end_xer_ov };
assign { cr_a_ok, cr_a } = { pipe_end_cr_a_ok, pipe_end_cr_a };
assign { o_ok, o } = { pipe_end_o_ok, pipe_end_o };
- assign { \logical_op__SV_Ptype$105 , \logical_op__sv_saturate$104 , \logical_op__sv_pred_dz$103 , \logical_op__sv_pred_sz$102 , \logical_op__insn$101 , \logical_op__data_len$100 , \logical_op__is_signed$99 , \logical_op__is_32bit$98 , \logical_op__output_carry$97 , \logical_op__write_cr0$96 , \logical_op__invert_out$95 , \logical_op__input_carry$94 , \logical_op__zero_a$93 , \logical_op__invert_in$92 , \logical_op__oe__ok$91 , \logical_op__oe__oe$90 , \logical_op__rc__ok$89 , \logical_op__rc__rc$88 , \logical_op__imm_data__ok$87 , \logical_op__imm_data__data$86 , \logical_op__fn_unit$85 , \logical_op__insn_type$84 } = { \pipe_end_logical_op__SV_Ptype$81 , \pipe_end_logical_op__sv_saturate$80 , \pipe_end_logical_op__sv_pred_dz$79 , \pipe_end_logical_op__sv_pred_sz$78 , \pipe_end_logical_op__insn$77 , \pipe_end_logical_op__data_len$76 , \pipe_end_logical_op__is_signed$75 , \pipe_end_logical_op__is_32bit$74 , \pipe_end_logical_op__output_carry$73 , \pipe_end_logical_op__write_cr0$72 , \pipe_end_logical_op__invert_out$71 , \pipe_end_logical_op__input_carry$70 , \pipe_end_logical_op__zero_a$69 , \pipe_end_logical_op__invert_in$68 , \pipe_end_logical_op__oe__ok$67 , \pipe_end_logical_op__oe__oe$66 , \pipe_end_logical_op__rc__ok$65 , \pipe_end_logical_op__rc__rc$64 , \pipe_end_logical_op__imm_data__ok$63 , \pipe_end_logical_op__imm_data__data$62 , \pipe_end_logical_op__fn_unit$61 , \pipe_end_logical_op__insn_type$60 };
- assign \muxid$83 = \pipe_end_muxid$59 ;
+ assign { \logical_op__SV_Ptype$109 , \logical_op__sv_ldstmode$108 , \logical_op__sv_saturate$107 , \logical_op__sv_pred_dz$106 , \logical_op__sv_pred_sz$105 , \logical_op__insn$104 , \logical_op__data_len$103 , \logical_op__is_signed$102 , \logical_op__is_32bit$101 , \logical_op__output_carry$100 , \logical_op__write_cr0$99 , \logical_op__invert_out$98 , \logical_op__input_carry$97 , \logical_op__zero_a$96 , \logical_op__invert_in$95 , \logical_op__oe__ok$94 , \logical_op__oe__oe$93 , \logical_op__rc__ok$92 , \logical_op__rc__rc$91 , \logical_op__imm_data__ok$90 , \logical_op__imm_data__data$89 , \logical_op__fn_unit$88 , \logical_op__insn_type$87 } = { \pipe_end_logical_op__SV_Ptype$84 , \pipe_end_logical_op__sv_ldstmode$83 , \pipe_end_logical_op__sv_saturate$82 , \pipe_end_logical_op__sv_pred_dz$81 , \pipe_end_logical_op__sv_pred_sz$80 , \pipe_end_logical_op__insn$79 , \pipe_end_logical_op__data_len$78 , \pipe_end_logical_op__is_signed$77 , \pipe_end_logical_op__is_32bit$76 , \pipe_end_logical_op__output_carry$75 , \pipe_end_logical_op__write_cr0$74 , \pipe_end_logical_op__invert_out$73 , \pipe_end_logical_op__input_carry$72 , \pipe_end_logical_op__zero_a$71 , \pipe_end_logical_op__invert_in$70 , \pipe_end_logical_op__oe__ok$69 , \pipe_end_logical_op__oe__oe$68 , \pipe_end_logical_op__rc__ok$67 , \pipe_end_logical_op__rc__rc$66 , \pipe_end_logical_op__imm_data__ok$65 , \pipe_end_logical_op__imm_data__data$64 , \pipe_end_logical_op__fn_unit$63 , \pipe_end_logical_op__insn_type$62 };
+ assign \muxid$86 = \pipe_end_muxid$61 ;
assign pipe_end_n_ready_i = n_ready_i;
assign n_valid_o = pipe_end_n_valid_o;
- assign \pipe_start_xer_so$27 = \xer_so$1 ;
- assign \pipe_start_rb$26 = rb;
- assign \pipe_start_ra$25 = ra;
- assign { \pipe_start_logical_op__SV_Ptype$24 , \pipe_start_logical_op__sv_saturate$23 , \pipe_start_logical_op__sv_pred_dz$22 , \pipe_start_logical_op__sv_pred_sz$21 , \pipe_start_logical_op__insn$20 , \pipe_start_logical_op__data_len$19 , \pipe_start_logical_op__is_signed$18 , \pipe_start_logical_op__is_32bit$17 , \pipe_start_logical_op__output_carry$16 , \pipe_start_logical_op__write_cr0$15 , \pipe_start_logical_op__invert_out$14 , \pipe_start_logical_op__input_carry$13 , \pipe_start_logical_op__zero_a$12 , \pipe_start_logical_op__invert_in$11 , \pipe_start_logical_op__oe__ok$10 , \pipe_start_logical_op__oe__oe$9 , \pipe_start_logical_op__rc__ok$8 , \pipe_start_logical_op__rc__rc$7 , \pipe_start_logical_op__imm_data__ok$6 , \pipe_start_logical_op__imm_data__data$5 , \pipe_start_logical_op__fn_unit$4 , \pipe_start_logical_op__insn_type$3 } = { logical_op__SV_Ptype, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
+ assign \pipe_start_xer_so$28 = \xer_so$1 ;
+ assign \pipe_start_rb$27 = rb;
+ assign \pipe_start_ra$26 = ra;
+ assign { \pipe_start_logical_op__SV_Ptype$25 , \pipe_start_logical_op__sv_ldstmode$24 , \pipe_start_logical_op__sv_saturate$23 , \pipe_start_logical_op__sv_pred_dz$22 , \pipe_start_logical_op__sv_pred_sz$21 , \pipe_start_logical_op__insn$20 , \pipe_start_logical_op__data_len$19 , \pipe_start_logical_op__is_signed$18 , \pipe_start_logical_op__is_32bit$17 , \pipe_start_logical_op__output_carry$16 , \pipe_start_logical_op__write_cr0$15 , \pipe_start_logical_op__invert_out$14 , \pipe_start_logical_op__input_carry$13 , \pipe_start_logical_op__zero_a$12 , \pipe_start_logical_op__invert_in$11 , \pipe_start_logical_op__oe__ok$10 , \pipe_start_logical_op__oe__oe$9 , \pipe_start_logical_op__rc__ok$8 , \pipe_start_logical_op__rc__rc$7 , \pipe_start_logical_op__imm_data__ok$6 , \pipe_start_logical_op__imm_data__data$5 , \pipe_start_logical_op__fn_unit$4 , \pipe_start_logical_op__insn_type$3 } = { logical_op__SV_Ptype, logical_op__sv_ldstmode, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
assign \pipe_start_muxid$2 = 2'h0;
assign p_ready_o = pipe_start_p_ready_o;
assign pipe_start_p_valid_i = p_valid_i;
assign pipe_end_remainder = pipe_middle_0_remainder;
assign pipe_end_quotient_root = pipe_middle_0_quotient_root;
- assign pipe_end_div_by_zero = \pipe_middle_0_div_by_zero$58 ;
- assign pipe_end_dive_abs_ov64 = \pipe_middle_0_dive_abs_ov64$57 ;
- assign pipe_end_dive_abs_ov32 = \pipe_middle_0_dive_abs_ov32$56 ;
- assign pipe_end_dividend_neg = \pipe_middle_0_dividend_neg$55 ;
- assign pipe_end_divisor_neg = \pipe_middle_0_divisor_neg$54 ;
- assign pipe_end_xer_so = \pipe_middle_0_xer_so$53 ;
- assign pipe_end_rb = \pipe_middle_0_rb$52 ;
- assign pipe_end_ra = \pipe_middle_0_ra$51 ;
- assign { pipe_end_logical_op__SV_Ptype, pipe_end_logical_op__sv_saturate, pipe_end_logical_op__sv_pred_dz, pipe_end_logical_op__sv_pred_sz, pipe_end_logical_op__insn, pipe_end_logical_op__data_len, pipe_end_logical_op__is_signed, pipe_end_logical_op__is_32bit, pipe_end_logical_op__output_carry, pipe_end_logical_op__write_cr0, pipe_end_logical_op__invert_out, pipe_end_logical_op__input_carry, pipe_end_logical_op__zero_a, pipe_end_logical_op__invert_in, pipe_end_logical_op__oe__ok, pipe_end_logical_op__oe__oe, pipe_end_logical_op__rc__ok, pipe_end_logical_op__rc__rc, pipe_end_logical_op__imm_data__ok, pipe_end_logical_op__imm_data__data, pipe_end_logical_op__fn_unit, pipe_end_logical_op__insn_type } = { \pipe_middle_0_logical_op__SV_Ptype$50 , \pipe_middle_0_logical_op__sv_saturate$49 , \pipe_middle_0_logical_op__sv_pred_dz$48 , \pipe_middle_0_logical_op__sv_pred_sz$47 , \pipe_middle_0_logical_op__insn$46 , \pipe_middle_0_logical_op__data_len$45 , \pipe_middle_0_logical_op__is_signed$44 , \pipe_middle_0_logical_op__is_32bit$43 , \pipe_middle_0_logical_op__output_carry$42 , \pipe_middle_0_logical_op__write_cr0$41 , \pipe_middle_0_logical_op__invert_out$40 , \pipe_middle_0_logical_op__input_carry$39 , \pipe_middle_0_logical_op__zero_a$38 , \pipe_middle_0_logical_op__invert_in$37 , \pipe_middle_0_logical_op__oe__ok$36 , \pipe_middle_0_logical_op__oe__oe$35 , \pipe_middle_0_logical_op__rc__ok$34 , \pipe_middle_0_logical_op__rc__rc$33 , \pipe_middle_0_logical_op__imm_data__ok$32 , \pipe_middle_0_logical_op__imm_data__data$31 , \pipe_middle_0_logical_op__fn_unit$30 , \pipe_middle_0_logical_op__insn_type$29 };
- assign pipe_end_muxid = \pipe_middle_0_muxid$28 ;
+ assign pipe_end_div_by_zero = \pipe_middle_0_div_by_zero$60 ;
+ assign pipe_end_dive_abs_ov64 = \pipe_middle_0_dive_abs_ov64$59 ;
+ assign pipe_end_dive_abs_ov32 = \pipe_middle_0_dive_abs_ov32$58 ;
+ assign pipe_end_dividend_neg = \pipe_middle_0_dividend_neg$57 ;
+ assign pipe_end_divisor_neg = \pipe_middle_0_divisor_neg$56 ;
+ assign pipe_end_xer_so = \pipe_middle_0_xer_so$55 ;
+ assign pipe_end_rb = \pipe_middle_0_rb$54 ;
+ assign pipe_end_ra = \pipe_middle_0_ra$53 ;
+ assign { pipe_end_logical_op__SV_Ptype, pipe_end_logical_op__sv_ldstmode, pipe_end_logical_op__sv_saturate, pipe_end_logical_op__sv_pred_dz, pipe_end_logical_op__sv_pred_sz, pipe_end_logical_op__insn, pipe_end_logical_op__data_len, pipe_end_logical_op__is_signed, pipe_end_logical_op__is_32bit, pipe_end_logical_op__output_carry, pipe_end_logical_op__write_cr0, pipe_end_logical_op__invert_out, pipe_end_logical_op__input_carry, pipe_end_logical_op__zero_a, pipe_end_logical_op__invert_in, pipe_end_logical_op__oe__ok, pipe_end_logical_op__oe__oe, pipe_end_logical_op__rc__ok, pipe_end_logical_op__rc__rc, pipe_end_logical_op__imm_data__ok, pipe_end_logical_op__imm_data__data, pipe_end_logical_op__fn_unit, pipe_end_logical_op__insn_type } = { \pipe_middle_0_logical_op__SV_Ptype$52 , \pipe_middle_0_logical_op__sv_ldstmode$51 , \pipe_middle_0_logical_op__sv_saturate$50 , \pipe_middle_0_logical_op__sv_pred_dz$49 , \pipe_middle_0_logical_op__sv_pred_sz$48 , \pipe_middle_0_logical_op__insn$47 , \pipe_middle_0_logical_op__data_len$46 , \pipe_middle_0_logical_op__is_signed$45 , \pipe_middle_0_logical_op__is_32bit$44 , \pipe_middle_0_logical_op__output_carry$43 , \pipe_middle_0_logical_op__write_cr0$42 , \pipe_middle_0_logical_op__invert_out$41 , \pipe_middle_0_logical_op__input_carry$40 , \pipe_middle_0_logical_op__zero_a$39 , \pipe_middle_0_logical_op__invert_in$38 , \pipe_middle_0_logical_op__oe__ok$37 , \pipe_middle_0_logical_op__oe__oe$36 , \pipe_middle_0_logical_op__rc__ok$35 , \pipe_middle_0_logical_op__rc__rc$34 , \pipe_middle_0_logical_op__imm_data__ok$33 , \pipe_middle_0_logical_op__imm_data__data$32 , \pipe_middle_0_logical_op__fn_unit$31 , \pipe_middle_0_logical_op__insn_type$30 };
+ assign pipe_end_muxid = \pipe_middle_0_muxid$29 ;
assign pipe_middle_0_n_ready_i = pipe_end_p_ready_o;
assign pipe_end_p_valid_i = pipe_middle_0_n_valid_o;
assign pipe_middle_0_operation = pipe_start_operation;
assign pipe_middle_0_xer_so = pipe_start_xer_so;
assign pipe_middle_0_rb = pipe_start_rb;
assign pipe_middle_0_ra = pipe_start_ra;
- assign { pipe_middle_0_logical_op__SV_Ptype, pipe_middle_0_logical_op__sv_saturate, pipe_middle_0_logical_op__sv_pred_dz, pipe_middle_0_logical_op__sv_pred_sz, pipe_middle_0_logical_op__insn, pipe_middle_0_logical_op__data_len, pipe_middle_0_logical_op__is_signed, pipe_middle_0_logical_op__is_32bit, pipe_middle_0_logical_op__output_carry, pipe_middle_0_logical_op__write_cr0, pipe_middle_0_logical_op__invert_out, pipe_middle_0_logical_op__input_carry, pipe_middle_0_logical_op__zero_a, pipe_middle_0_logical_op__invert_in, pipe_middle_0_logical_op__oe__ok, pipe_middle_0_logical_op__oe__oe, pipe_middle_0_logical_op__rc__ok, pipe_middle_0_logical_op__rc__rc, pipe_middle_0_logical_op__imm_data__ok, pipe_middle_0_logical_op__imm_data__data, pipe_middle_0_logical_op__fn_unit, pipe_middle_0_logical_op__insn_type } = { pipe_start_logical_op__SV_Ptype, pipe_start_logical_op__sv_saturate, pipe_start_logical_op__sv_pred_dz, pipe_start_logical_op__sv_pred_sz, pipe_start_logical_op__insn, pipe_start_logical_op__data_len, pipe_start_logical_op__is_signed, pipe_start_logical_op__is_32bit, pipe_start_logical_op__output_carry, pipe_start_logical_op__write_cr0, pipe_start_logical_op__invert_out, pipe_start_logical_op__input_carry, pipe_start_logical_op__zero_a, pipe_start_logical_op__invert_in, pipe_start_logical_op__oe__ok, pipe_start_logical_op__oe__oe, pipe_start_logical_op__rc__ok, pipe_start_logical_op__rc__rc, pipe_start_logical_op__imm_data__ok, pipe_start_logical_op__imm_data__data, pipe_start_logical_op__fn_unit, pipe_start_logical_op__insn_type };
+ assign { pipe_middle_0_logical_op__SV_Ptype, pipe_middle_0_logical_op__sv_ldstmode, pipe_middle_0_logical_op__sv_saturate, pipe_middle_0_logical_op__sv_pred_dz, pipe_middle_0_logical_op__sv_pred_sz, pipe_middle_0_logical_op__insn, pipe_middle_0_logical_op__data_len, pipe_middle_0_logical_op__is_signed, pipe_middle_0_logical_op__is_32bit, pipe_middle_0_logical_op__output_carry, pipe_middle_0_logical_op__write_cr0, pipe_middle_0_logical_op__invert_out, pipe_middle_0_logical_op__input_carry, pipe_middle_0_logical_op__zero_a, pipe_middle_0_logical_op__invert_in, pipe_middle_0_logical_op__oe__ok, pipe_middle_0_logical_op__oe__oe, pipe_middle_0_logical_op__rc__ok, pipe_middle_0_logical_op__rc__rc, pipe_middle_0_logical_op__imm_data__ok, pipe_middle_0_logical_op__imm_data__data, pipe_middle_0_logical_op__fn_unit, pipe_middle_0_logical_op__insn_type } = { pipe_start_logical_op__SV_Ptype, pipe_start_logical_op__sv_ldstmode, pipe_start_logical_op__sv_saturate, pipe_start_logical_op__sv_pred_dz, pipe_start_logical_op__sv_pred_sz, pipe_start_logical_op__insn, pipe_start_logical_op__data_len, pipe_start_logical_op__is_signed, pipe_start_logical_op__is_32bit, pipe_start_logical_op__output_carry, pipe_start_logical_op__write_cr0, pipe_start_logical_op__invert_out, pipe_start_logical_op__input_carry, pipe_start_logical_op__zero_a, pipe_start_logical_op__invert_in, pipe_start_logical_op__oe__ok, pipe_start_logical_op__oe__oe, pipe_start_logical_op__rc__ok, pipe_start_logical_op__rc__rc, pipe_start_logical_op__imm_data__ok, pipe_start_logical_op__imm_data__data, pipe_start_logical_op__fn_unit, pipe_start_logical_op__insn_type };
assign pipe_middle_0_muxid = pipe_start_muxid;
assign pipe_start_n_ready_i = pipe_middle_0_p_ready_o;
assign pipe_middle_0_p_valid_i = pipe_start_n_valid_o;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0" *)
(* generator = "nMigen" *)
-module alu_logical0(coresync_rst, o_ok, cr_a_ok, n_valid_o, n_ready_i, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, o, cr_a, ra, rb, xer_so, p_valid_i, p_ready_o, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+module alu_logical0(coresync_rst, o_ok, cr_a_ok, n_valid_o, n_ready_i, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__sv_ldstmode, logical_op__SV_Ptype, o, cr_a, ra, rb, xer_so, p_valid_i, p_ready_o, coresync_clk);
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output [3:0] cr_a;
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \logical_op__SV_Ptype$74 ;
+ wire [1:0] \logical_op__SV_Ptype$77 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [3:0] logical_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [3:0] \logical_op__data_len$69 ;
+ wire [3:0] \logical_op__data_len$71 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \logical_op__fn_unit$54 ;
+ wire [14:0] \logical_op__fn_unit$56 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] logical_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \logical_op__imm_data__data$55 ;
+ wire [63:0] \logical_op__imm_data__data$57 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__imm_data__ok$56 ;
+ wire \logical_op__imm_data__ok$58 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \logical_op__input_carry$63 ;
+ wire [1:0] \logical_op__input_carry$65 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] logical_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \logical_op__insn$70 ;
+ wire [31:0] \logical_op__insn$72 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \logical_op__insn_type$53 ;
+ wire [6:0] \logical_op__insn_type$55 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__invert_in$61 ;
+ wire \logical_op__invert_in$63 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__invert_out;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__invert_out$64 ;
+ wire \logical_op__invert_out$66 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__is_32bit$67 ;
+ wire \logical_op__is_32bit$69 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__is_signed$68 ;
+ wire \logical_op__is_signed$70 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__oe__oe$59 ;
+ wire \logical_op__oe__oe$61 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__oe__ok$60 ;
+ wire \logical_op__oe__ok$62 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__output_carry;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__output_carry$66 ;
+ wire \logical_op__output_carry$68 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__rc__ok$58 ;
+ wire \logical_op__rc__ok$60 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__rc__rc$57 ;
+ wire \logical_op__rc__rc$59 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] logical_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \logical_op__sv_ldstmode$76 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__sv_pred_dz$72 ;
+ wire \logical_op__sv_pred_dz$74 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__sv_pred_sz$71 ;
+ wire \logical_op__sv_pred_sz$73 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \logical_op__sv_saturate$73 ;
+ wire [1:0] \logical_op__sv_saturate$75 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__write_cr0$65 ;
+ wire \logical_op__write_cr0$67 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__zero_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__zero_a$62 ;
+ wire \logical_op__zero_a$64 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [3:0] logical_pipe1_cr_a;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \logical_pipe1_logical_op__SV_Ptype$23 ;
+ wire [1:0] \logical_pipe1_logical_op__SV_Ptype$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [3:0] logical_pipe1_logical_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire logical_pipe1_logical_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire \logical_pipe1_logical_op__rc__rc$6 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] logical_pipe1_logical_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \logical_pipe1_logical_op__sv_ldstmode$23 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire logical_pipe1_logical_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire logical_pipe1_xer_so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire \logical_pipe1_xer_so$24 ;
+ wire \logical_pipe1_xer_so$25 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire logical_pipe1_xer_so_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [3:0] logical_pipe2_cr_a;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [3:0] \logical_pipe2_cr_a$50 ;
+ wire [3:0] \logical_pipe2_cr_a$52 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire logical_pipe2_cr_a_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \logical_pipe2_cr_a_ok$51 ;
+ wire \logical_pipe2_cr_a_ok$53 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \logical_pipe2_logical_op__SV_Ptype$47 ;
+ wire [1:0] \logical_pipe2_logical_op__SV_Ptype$49 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [3:0] logical_pipe2_logical_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [3:0] \logical_pipe2_logical_op__data_len$42 ;
+ wire [3:0] \logical_pipe2_logical_op__data_len$43 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \logical_pipe2_logical_op__fn_unit$27 ;
+ wire [14:0] \logical_pipe2_logical_op__fn_unit$28 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] logical_pipe2_logical_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \logical_pipe2_logical_op__imm_data__data$28 ;
+ wire [63:0] \logical_pipe2_logical_op__imm_data__data$29 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire logical_pipe2_logical_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_pipe2_logical_op__imm_data__ok$29 ;
+ wire \logical_pipe2_logical_op__imm_data__ok$30 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \logical_pipe2_logical_op__input_carry$36 ;
+ wire [1:0] \logical_pipe2_logical_op__input_carry$37 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] logical_pipe2_logical_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \logical_pipe2_logical_op__insn$43 ;
+ wire [31:0] \logical_pipe2_logical_op__insn$44 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \logical_pipe2_logical_op__insn_type$26 ;
+ wire [6:0] \logical_pipe2_logical_op__insn_type$27 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire logical_pipe2_logical_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_pipe2_logical_op__invert_in$34 ;
+ wire \logical_pipe2_logical_op__invert_in$35 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire logical_pipe2_logical_op__invert_out;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_pipe2_logical_op__invert_out$37 ;
+ wire \logical_pipe2_logical_op__invert_out$38 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire logical_pipe2_logical_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_pipe2_logical_op__is_32bit$40 ;
+ wire \logical_pipe2_logical_op__is_32bit$41 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire logical_pipe2_logical_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_pipe2_logical_op__is_signed$41 ;
+ wire \logical_pipe2_logical_op__is_signed$42 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire logical_pipe2_logical_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_pipe2_logical_op__oe__oe$32 ;
+ wire \logical_pipe2_logical_op__oe__oe$33 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire logical_pipe2_logical_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_pipe2_logical_op__oe__ok$33 ;
+ wire \logical_pipe2_logical_op__oe__ok$34 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire logical_pipe2_logical_op__output_carry;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_pipe2_logical_op__output_carry$39 ;
+ wire \logical_pipe2_logical_op__output_carry$40 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire logical_pipe2_logical_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_pipe2_logical_op__rc__ok$31 ;
+ wire \logical_pipe2_logical_op__rc__ok$32 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire logical_pipe2_logical_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_pipe2_logical_op__rc__rc$30 ;
+ wire \logical_pipe2_logical_op__rc__rc$31 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] logical_pipe2_logical_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \logical_pipe2_logical_op__sv_ldstmode$48 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire logical_pipe2_logical_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_pipe2_logical_op__sv_pred_dz$45 ;
+ wire \logical_pipe2_logical_op__sv_pred_dz$46 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire logical_pipe2_logical_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_pipe2_logical_op__sv_pred_sz$44 ;
+ wire \logical_pipe2_logical_op__sv_pred_sz$45 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \logical_pipe2_logical_op__sv_saturate$46 ;
+ wire [1:0] \logical_pipe2_logical_op__sv_saturate$47 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire logical_pipe2_logical_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_pipe2_logical_op__write_cr0$38 ;
+ wire \logical_pipe2_logical_op__write_cr0$39 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire logical_pipe2_logical_op__zero_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_pipe2_logical_op__zero_a$35 ;
+ wire \logical_pipe2_logical_op__zero_a$36 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] logical_pipe2_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \logical_pipe2_muxid$25 ;
+ wire [1:0] \logical_pipe2_muxid$26 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
wire logical_pipe2_n_ready_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [63:0] logical_pipe2_o;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \logical_pipe2_o$48 ;
+ wire [63:0] \logical_pipe2_o$50 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire logical_pipe2_o_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \logical_pipe2_o_ok$49 ;
+ wire \logical_pipe2_o_ok$51 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
wire logical_pipe2_p_ready_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \muxid$52 ;
+ wire [1:0] \muxid$54 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
input n_ready_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
.cr_a(logical_pipe1_cr_a),
.cr_a_ok(logical_pipe1_cr_a_ok),
.logical_op__SV_Ptype(logical_pipe1_logical_op__SV_Ptype),
- .\logical_op__SV_Ptype$23 (\logical_pipe1_logical_op__SV_Ptype$23 ),
+ .\logical_op__SV_Ptype$24 (\logical_pipe1_logical_op__SV_Ptype$24 ),
.logical_op__data_len(logical_pipe1_logical_op__data_len),
.\logical_op__data_len$18 (\logical_pipe1_logical_op__data_len$18 ),
.logical_op__fn_unit(logical_pipe1_logical_op__fn_unit),
.\logical_op__rc__ok$7 (\logical_pipe1_logical_op__rc__ok$7 ),
.logical_op__rc__rc(logical_pipe1_logical_op__rc__rc),
.\logical_op__rc__rc$6 (\logical_pipe1_logical_op__rc__rc$6 ),
+ .logical_op__sv_ldstmode(logical_pipe1_logical_op__sv_ldstmode),
+ .\logical_op__sv_ldstmode$23 (\logical_pipe1_logical_op__sv_ldstmode$23 ),
.logical_op__sv_pred_dz(logical_pipe1_logical_op__sv_pred_dz),
.\logical_op__sv_pred_dz$21 (\logical_pipe1_logical_op__sv_pred_dz$21 ),
.logical_op__sv_pred_sz(logical_pipe1_logical_op__sv_pred_sz),
.ra(logical_pipe1_ra),
.rb(logical_pipe1_rb),
.xer_so(logical_pipe1_xer_so),
- .\xer_so$24 (\logical_pipe1_xer_so$24 ),
+ .\xer_so$25 (\logical_pipe1_xer_so$25 ),
.xer_so_ok(logical_pipe1_xer_so_ok)
);
logical_pipe2 logical_pipe2 (
.coresync_clk(coresync_clk),
.coresync_rst(coresync_rst),
.cr_a(logical_pipe2_cr_a),
- .\cr_a$26 (\logical_pipe2_cr_a$50 ),
+ .\cr_a$27 (\logical_pipe2_cr_a$52 ),
.cr_a_ok(logical_pipe2_cr_a_ok),
- .\cr_a_ok$27 (\logical_pipe2_cr_a_ok$51 ),
+ .\cr_a_ok$28 (\logical_pipe2_cr_a_ok$53 ),
.logical_op__SV_Ptype(logical_pipe2_logical_op__SV_Ptype),
- .\logical_op__SV_Ptype$23 (\logical_pipe2_logical_op__SV_Ptype$47 ),
+ .\logical_op__SV_Ptype$24 (\logical_pipe2_logical_op__SV_Ptype$49 ),
.logical_op__data_len(logical_pipe2_logical_op__data_len),
- .\logical_op__data_len$18 (\logical_pipe2_logical_op__data_len$42 ),
+ .\logical_op__data_len$18 (\logical_pipe2_logical_op__data_len$43 ),
.logical_op__fn_unit(logical_pipe2_logical_op__fn_unit),
- .\logical_op__fn_unit$3 (\logical_pipe2_logical_op__fn_unit$27 ),
+ .\logical_op__fn_unit$3 (\logical_pipe2_logical_op__fn_unit$28 ),
.logical_op__imm_data__data(logical_pipe2_logical_op__imm_data__data),
- .\logical_op__imm_data__data$4 (\logical_pipe2_logical_op__imm_data__data$28 ),
+ .\logical_op__imm_data__data$4 (\logical_pipe2_logical_op__imm_data__data$29 ),
.logical_op__imm_data__ok(logical_pipe2_logical_op__imm_data__ok),
- .\logical_op__imm_data__ok$5 (\logical_pipe2_logical_op__imm_data__ok$29 ),
+ .\logical_op__imm_data__ok$5 (\logical_pipe2_logical_op__imm_data__ok$30 ),
.logical_op__input_carry(logical_pipe2_logical_op__input_carry),
- .\logical_op__input_carry$12 (\logical_pipe2_logical_op__input_carry$36 ),
+ .\logical_op__input_carry$12 (\logical_pipe2_logical_op__input_carry$37 ),
.logical_op__insn(logical_pipe2_logical_op__insn),
- .\logical_op__insn$19 (\logical_pipe2_logical_op__insn$43 ),
+ .\logical_op__insn$19 (\logical_pipe2_logical_op__insn$44 ),
.logical_op__insn_type(logical_pipe2_logical_op__insn_type),
- .\logical_op__insn_type$2 (\logical_pipe2_logical_op__insn_type$26 ),
+ .\logical_op__insn_type$2 (\logical_pipe2_logical_op__insn_type$27 ),
.logical_op__invert_in(logical_pipe2_logical_op__invert_in),
- .\logical_op__invert_in$10 (\logical_pipe2_logical_op__invert_in$34 ),
+ .\logical_op__invert_in$10 (\logical_pipe2_logical_op__invert_in$35 ),
.logical_op__invert_out(logical_pipe2_logical_op__invert_out),
- .\logical_op__invert_out$13 (\logical_pipe2_logical_op__invert_out$37 ),
+ .\logical_op__invert_out$13 (\logical_pipe2_logical_op__invert_out$38 ),
.logical_op__is_32bit(logical_pipe2_logical_op__is_32bit),
- .\logical_op__is_32bit$16 (\logical_pipe2_logical_op__is_32bit$40 ),
+ .\logical_op__is_32bit$16 (\logical_pipe2_logical_op__is_32bit$41 ),
.logical_op__is_signed(logical_pipe2_logical_op__is_signed),
- .\logical_op__is_signed$17 (\logical_pipe2_logical_op__is_signed$41 ),
+ .\logical_op__is_signed$17 (\logical_pipe2_logical_op__is_signed$42 ),
.logical_op__oe__oe(logical_pipe2_logical_op__oe__oe),
- .\logical_op__oe__oe$8 (\logical_pipe2_logical_op__oe__oe$32 ),
+ .\logical_op__oe__oe$8 (\logical_pipe2_logical_op__oe__oe$33 ),
.logical_op__oe__ok(logical_pipe2_logical_op__oe__ok),
- .\logical_op__oe__ok$9 (\logical_pipe2_logical_op__oe__ok$33 ),
+ .\logical_op__oe__ok$9 (\logical_pipe2_logical_op__oe__ok$34 ),
.logical_op__output_carry(logical_pipe2_logical_op__output_carry),
- .\logical_op__output_carry$15 (\logical_pipe2_logical_op__output_carry$39 ),
+ .\logical_op__output_carry$15 (\logical_pipe2_logical_op__output_carry$40 ),
.logical_op__rc__ok(logical_pipe2_logical_op__rc__ok),
- .\logical_op__rc__ok$7 (\logical_pipe2_logical_op__rc__ok$31 ),
+ .\logical_op__rc__ok$7 (\logical_pipe2_logical_op__rc__ok$32 ),
.logical_op__rc__rc(logical_pipe2_logical_op__rc__rc),
- .\logical_op__rc__rc$6 (\logical_pipe2_logical_op__rc__rc$30 ),
+ .\logical_op__rc__rc$6 (\logical_pipe2_logical_op__rc__rc$31 ),
+ .logical_op__sv_ldstmode(logical_pipe2_logical_op__sv_ldstmode),
+ .\logical_op__sv_ldstmode$23 (\logical_pipe2_logical_op__sv_ldstmode$48 ),
.logical_op__sv_pred_dz(logical_pipe2_logical_op__sv_pred_dz),
- .\logical_op__sv_pred_dz$21 (\logical_pipe2_logical_op__sv_pred_dz$45 ),
+ .\logical_op__sv_pred_dz$21 (\logical_pipe2_logical_op__sv_pred_dz$46 ),
.logical_op__sv_pred_sz(logical_pipe2_logical_op__sv_pred_sz),
- .\logical_op__sv_pred_sz$20 (\logical_pipe2_logical_op__sv_pred_sz$44 ),
+ .\logical_op__sv_pred_sz$20 (\logical_pipe2_logical_op__sv_pred_sz$45 ),
.logical_op__sv_saturate(logical_pipe2_logical_op__sv_saturate),
- .\logical_op__sv_saturate$22 (\logical_pipe2_logical_op__sv_saturate$46 ),
+ .\logical_op__sv_saturate$22 (\logical_pipe2_logical_op__sv_saturate$47 ),
.logical_op__write_cr0(logical_pipe2_logical_op__write_cr0),
- .\logical_op__write_cr0$14 (\logical_pipe2_logical_op__write_cr0$38 ),
+ .\logical_op__write_cr0$14 (\logical_pipe2_logical_op__write_cr0$39 ),
.logical_op__zero_a(logical_pipe2_logical_op__zero_a),
- .\logical_op__zero_a$11 (\logical_pipe2_logical_op__zero_a$35 ),
+ .\logical_op__zero_a$11 (\logical_pipe2_logical_op__zero_a$36 ),
.muxid(logical_pipe2_muxid),
- .\muxid$1 (\logical_pipe2_muxid$25 ),
+ .\muxid$1 (\logical_pipe2_muxid$26 ),
.n_ready_i(logical_pipe2_n_ready_i),
.n_valid_o(logical_pipe2_n_valid_o),
.o(logical_pipe2_o),
- .\o$24 (\logical_pipe2_o$48 ),
+ .\o$25 (\logical_pipe2_o$50 ),
.o_ok(logical_pipe2_o_ok),
- .\o_ok$25 (\logical_pipe2_o_ok$49 ),
+ .\o_ok$26 (\logical_pipe2_o_ok$51 ),
.p_ready_o(logical_pipe2_p_ready_o),
.p_valid_i(logical_pipe2_p_valid_i),
.xer_so(logical_pipe2_xer_so),
.p_valid_i(p_valid_i)
);
assign muxid = 2'h0;
- assign { cr_a_ok, cr_a } = { \logical_pipe2_cr_a_ok$51 , \logical_pipe2_cr_a$50 };
- assign { o_ok, o } = { \logical_pipe2_o_ok$49 , \logical_pipe2_o$48 };
- assign { \logical_op__SV_Ptype$74 , \logical_op__sv_saturate$73 , \logical_op__sv_pred_dz$72 , \logical_op__sv_pred_sz$71 , \logical_op__insn$70 , \logical_op__data_len$69 , \logical_op__is_signed$68 , \logical_op__is_32bit$67 , \logical_op__output_carry$66 , \logical_op__write_cr0$65 , \logical_op__invert_out$64 , \logical_op__input_carry$63 , \logical_op__zero_a$62 , \logical_op__invert_in$61 , \logical_op__oe__ok$60 , \logical_op__oe__oe$59 , \logical_op__rc__ok$58 , \logical_op__rc__rc$57 , \logical_op__imm_data__ok$56 , \logical_op__imm_data__data$55 , \logical_op__fn_unit$54 , \logical_op__insn_type$53 } = { \logical_pipe2_logical_op__SV_Ptype$47 , \logical_pipe2_logical_op__sv_saturate$46 , \logical_pipe2_logical_op__sv_pred_dz$45 , \logical_pipe2_logical_op__sv_pred_sz$44 , \logical_pipe2_logical_op__insn$43 , \logical_pipe2_logical_op__data_len$42 , \logical_pipe2_logical_op__is_signed$41 , \logical_pipe2_logical_op__is_32bit$40 , \logical_pipe2_logical_op__output_carry$39 , \logical_pipe2_logical_op__write_cr0$38 , \logical_pipe2_logical_op__invert_out$37 , \logical_pipe2_logical_op__input_carry$36 , \logical_pipe2_logical_op__zero_a$35 , \logical_pipe2_logical_op__invert_in$34 , \logical_pipe2_logical_op__oe__ok$33 , \logical_pipe2_logical_op__oe__oe$32 , \logical_pipe2_logical_op__rc__ok$31 , \logical_pipe2_logical_op__rc__rc$30 , \logical_pipe2_logical_op__imm_data__ok$29 , \logical_pipe2_logical_op__imm_data__data$28 , \logical_pipe2_logical_op__fn_unit$27 , \logical_pipe2_logical_op__insn_type$26 };
- assign \muxid$52 = \logical_pipe2_muxid$25 ;
+ assign { cr_a_ok, cr_a } = { \logical_pipe2_cr_a_ok$53 , \logical_pipe2_cr_a$52 };
+ assign { o_ok, o } = { \logical_pipe2_o_ok$51 , \logical_pipe2_o$50 };
+ assign { \logical_op__SV_Ptype$77 , \logical_op__sv_ldstmode$76 , \logical_op__sv_saturate$75 , \logical_op__sv_pred_dz$74 , \logical_op__sv_pred_sz$73 , \logical_op__insn$72 , \logical_op__data_len$71 , \logical_op__is_signed$70 , \logical_op__is_32bit$69 , \logical_op__output_carry$68 , \logical_op__write_cr0$67 , \logical_op__invert_out$66 , \logical_op__input_carry$65 , \logical_op__zero_a$64 , \logical_op__invert_in$63 , \logical_op__oe__ok$62 , \logical_op__oe__oe$61 , \logical_op__rc__ok$60 , \logical_op__rc__rc$59 , \logical_op__imm_data__ok$58 , \logical_op__imm_data__data$57 , \logical_op__fn_unit$56 , \logical_op__insn_type$55 } = { \logical_pipe2_logical_op__SV_Ptype$49 , \logical_pipe2_logical_op__sv_ldstmode$48 , \logical_pipe2_logical_op__sv_saturate$47 , \logical_pipe2_logical_op__sv_pred_dz$46 , \logical_pipe2_logical_op__sv_pred_sz$45 , \logical_pipe2_logical_op__insn$44 , \logical_pipe2_logical_op__data_len$43 , \logical_pipe2_logical_op__is_signed$42 , \logical_pipe2_logical_op__is_32bit$41 , \logical_pipe2_logical_op__output_carry$40 , \logical_pipe2_logical_op__write_cr0$39 , \logical_pipe2_logical_op__invert_out$38 , \logical_pipe2_logical_op__input_carry$37 , \logical_pipe2_logical_op__zero_a$36 , \logical_pipe2_logical_op__invert_in$35 , \logical_pipe2_logical_op__oe__ok$34 , \logical_pipe2_logical_op__oe__oe$33 , \logical_pipe2_logical_op__rc__ok$32 , \logical_pipe2_logical_op__rc__rc$31 , \logical_pipe2_logical_op__imm_data__ok$30 , \logical_pipe2_logical_op__imm_data__data$29 , \logical_pipe2_logical_op__fn_unit$28 , \logical_pipe2_logical_op__insn_type$27 };
+ assign \muxid$54 = \logical_pipe2_muxid$26 ;
assign logical_pipe2_n_ready_i = n_ready_i;
assign n_valid_o = logical_pipe2_n_valid_o;
- assign \logical_pipe1_xer_so$24 = xer_so;
+ assign \logical_pipe1_xer_so$25 = xer_so;
assign logical_pipe1_rb = rb;
assign logical_pipe1_ra = ra;
- assign { \logical_pipe1_logical_op__SV_Ptype$23 , \logical_pipe1_logical_op__sv_saturate$22 , \logical_pipe1_logical_op__sv_pred_dz$21 , \logical_pipe1_logical_op__sv_pred_sz$20 , \logical_pipe1_logical_op__insn$19 , \logical_pipe1_logical_op__data_len$18 , \logical_pipe1_logical_op__is_signed$17 , \logical_pipe1_logical_op__is_32bit$16 , \logical_pipe1_logical_op__output_carry$15 , \logical_pipe1_logical_op__write_cr0$14 , \logical_pipe1_logical_op__invert_out$13 , \logical_pipe1_logical_op__input_carry$12 , \logical_pipe1_logical_op__zero_a$11 , \logical_pipe1_logical_op__invert_in$10 , \logical_pipe1_logical_op__oe__ok$9 , \logical_pipe1_logical_op__oe__oe$8 , \logical_pipe1_logical_op__rc__ok$7 , \logical_pipe1_logical_op__rc__rc$6 , \logical_pipe1_logical_op__imm_data__ok$5 , \logical_pipe1_logical_op__imm_data__data$4 , \logical_pipe1_logical_op__fn_unit$3 , \logical_pipe1_logical_op__insn_type$2 } = { logical_op__SV_Ptype, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
+ assign { \logical_pipe1_logical_op__SV_Ptype$24 , \logical_pipe1_logical_op__sv_ldstmode$23 , \logical_pipe1_logical_op__sv_saturate$22 , \logical_pipe1_logical_op__sv_pred_dz$21 , \logical_pipe1_logical_op__sv_pred_sz$20 , \logical_pipe1_logical_op__insn$19 , \logical_pipe1_logical_op__data_len$18 , \logical_pipe1_logical_op__is_signed$17 , \logical_pipe1_logical_op__is_32bit$16 , \logical_pipe1_logical_op__output_carry$15 , \logical_pipe1_logical_op__write_cr0$14 , \logical_pipe1_logical_op__invert_out$13 , \logical_pipe1_logical_op__input_carry$12 , \logical_pipe1_logical_op__zero_a$11 , \logical_pipe1_logical_op__invert_in$10 , \logical_pipe1_logical_op__oe__ok$9 , \logical_pipe1_logical_op__oe__oe$8 , \logical_pipe1_logical_op__rc__ok$7 , \logical_pipe1_logical_op__rc__rc$6 , \logical_pipe1_logical_op__imm_data__ok$5 , \logical_pipe1_logical_op__imm_data__data$4 , \logical_pipe1_logical_op__fn_unit$3 , \logical_pipe1_logical_op__insn_type$2 } = { logical_op__SV_Ptype, logical_op__sv_ldstmode, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
assign \logical_pipe1_muxid$1 = 2'h0;
assign p_ready_o = logical_pipe1_p_ready_o;
assign logical_pipe1_p_valid_i = p_valid_i;
assign { logical_pipe2_xer_so_ok, logical_pipe2_xer_so } = { logical_pipe1_xer_so_ok, logical_pipe1_xer_so };
assign { logical_pipe2_cr_a_ok, logical_pipe2_cr_a } = { logical_pipe1_cr_a_ok, logical_pipe1_cr_a };
assign { logical_pipe2_o_ok, logical_pipe2_o } = { logical_pipe1_o_ok, logical_pipe1_o };
- assign { logical_pipe2_logical_op__SV_Ptype, logical_pipe2_logical_op__sv_saturate, logical_pipe2_logical_op__sv_pred_dz, logical_pipe2_logical_op__sv_pred_sz, logical_pipe2_logical_op__insn, logical_pipe2_logical_op__data_len, logical_pipe2_logical_op__is_signed, logical_pipe2_logical_op__is_32bit, logical_pipe2_logical_op__output_carry, logical_pipe2_logical_op__write_cr0, logical_pipe2_logical_op__invert_out, logical_pipe2_logical_op__input_carry, logical_pipe2_logical_op__zero_a, logical_pipe2_logical_op__invert_in, logical_pipe2_logical_op__oe__ok, logical_pipe2_logical_op__oe__oe, logical_pipe2_logical_op__rc__ok, logical_pipe2_logical_op__rc__rc, logical_pipe2_logical_op__imm_data__ok, logical_pipe2_logical_op__imm_data__data, logical_pipe2_logical_op__fn_unit, logical_pipe2_logical_op__insn_type } = { logical_pipe1_logical_op__SV_Ptype, logical_pipe1_logical_op__sv_saturate, logical_pipe1_logical_op__sv_pred_dz, logical_pipe1_logical_op__sv_pred_sz, logical_pipe1_logical_op__insn, logical_pipe1_logical_op__data_len, logical_pipe1_logical_op__is_signed, logical_pipe1_logical_op__is_32bit, logical_pipe1_logical_op__output_carry, logical_pipe1_logical_op__write_cr0, logical_pipe1_logical_op__invert_out, logical_pipe1_logical_op__input_carry, logical_pipe1_logical_op__zero_a, logical_pipe1_logical_op__invert_in, logical_pipe1_logical_op__oe__ok, logical_pipe1_logical_op__oe__oe, logical_pipe1_logical_op__rc__ok, logical_pipe1_logical_op__rc__rc, logical_pipe1_logical_op__imm_data__ok, logical_pipe1_logical_op__imm_data__data, logical_pipe1_logical_op__fn_unit, logical_pipe1_logical_op__insn_type };
+ assign { logical_pipe2_logical_op__SV_Ptype, logical_pipe2_logical_op__sv_ldstmode, logical_pipe2_logical_op__sv_saturate, logical_pipe2_logical_op__sv_pred_dz, logical_pipe2_logical_op__sv_pred_sz, logical_pipe2_logical_op__insn, logical_pipe2_logical_op__data_len, logical_pipe2_logical_op__is_signed, logical_pipe2_logical_op__is_32bit, logical_pipe2_logical_op__output_carry, logical_pipe2_logical_op__write_cr0, logical_pipe2_logical_op__invert_out, logical_pipe2_logical_op__input_carry, logical_pipe2_logical_op__zero_a, logical_pipe2_logical_op__invert_in, logical_pipe2_logical_op__oe__ok, logical_pipe2_logical_op__oe__oe, logical_pipe2_logical_op__rc__ok, logical_pipe2_logical_op__rc__rc, logical_pipe2_logical_op__imm_data__ok, logical_pipe2_logical_op__imm_data__data, logical_pipe2_logical_op__fn_unit, logical_pipe2_logical_op__insn_type } = { logical_pipe1_logical_op__SV_Ptype, logical_pipe1_logical_op__sv_ldstmode, logical_pipe1_logical_op__sv_saturate, logical_pipe1_logical_op__sv_pred_dz, logical_pipe1_logical_op__sv_pred_sz, logical_pipe1_logical_op__insn, logical_pipe1_logical_op__data_len, logical_pipe1_logical_op__is_signed, logical_pipe1_logical_op__is_32bit, logical_pipe1_logical_op__output_carry, logical_pipe1_logical_op__write_cr0, logical_pipe1_logical_op__invert_out, logical_pipe1_logical_op__input_carry, logical_pipe1_logical_op__zero_a, logical_pipe1_logical_op__invert_in, logical_pipe1_logical_op__oe__ok, logical_pipe1_logical_op__oe__oe, logical_pipe1_logical_op__rc__ok, logical_pipe1_logical_op__rc__rc, logical_pipe1_logical_op__imm_data__ok, logical_pipe1_logical_op__imm_data__data, logical_pipe1_logical_op__fn_unit, logical_pipe1_logical_op__insn_type };
assign logical_pipe2_muxid = logical_pipe1_muxid;
assign logical_pipe1_n_ready_i = logical_pipe2_p_ready_o;
assign logical_pipe2_p_valid_i = logical_pipe1_n_valid_o;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0" *)
(* generator = "nMigen" *)
-module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__SV_Ptype, o, cr_a, xer_ov, xer_so, ra, rb, \xer_so$1 , p_valid_i, p_ready_o, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__sv_ldstmode, mul_op__SV_Ptype, o, cr_a, xer_ov, xer_so, ra, rb, \xer_so$1 , p_valid_i, p_ready_o, coresync_clk);
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output [3:0] cr_a;
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \mul_op__SV_Ptype$77 ;
+ wire [1:0] \mul_op__SV_Ptype$81 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \mul_op__fn_unit$63 ;
+ wire [14:0] \mul_op__fn_unit$66 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] mul_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \mul_op__imm_data__data$64 ;
+ wire [63:0] \mul_op__imm_data__data$67 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__imm_data__ok$65 ;
+ wire \mul_op__imm_data__ok$68 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] mul_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \mul_op__insn$73 ;
+ wire [31:0] \mul_op__insn$76 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \mul_op__insn_type$62 ;
+ wire [6:0] \mul_op__insn_type$65 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__is_32bit$71 ;
+ wire \mul_op__is_32bit$74 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__is_signed$72 ;
+ wire \mul_op__is_signed$75 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__oe__oe$68 ;
+ wire \mul_op__oe__oe$71 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__oe__ok$69 ;
+ wire \mul_op__oe__ok$72 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__rc__ok$67 ;
+ wire \mul_op__rc__ok$70 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__rc__rc$66 ;
+ wire \mul_op__rc__rc$69 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] mul_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \mul_op__sv_ldstmode$80 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__sv_pred_dz$75 ;
+ wire \mul_op__sv_pred_dz$78 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__sv_pred_sz$74 ;
+ wire \mul_op__sv_pred_sz$77 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \mul_op__sv_saturate$76 ;
+ wire [1:0] \mul_op__sv_saturate$79 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__write_cr0$70 ;
+ wire \mul_op__write_cr0$73 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \mul_pipe1_mul_op__SV_Ptype$18 ;
+ wire [1:0] \mul_pipe1_mul_op__SV_Ptype$19 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
wire mul_pipe1_mul_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire \mul_pipe1_mul_op__rc__rc$7 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] mul_pipe1_mul_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \mul_pipe1_mul_op__sv_ldstmode$18 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul_pipe1_mul_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] mul_pipe1_ra;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \mul_pipe1_ra$19 ;
+ wire [63:0] \mul_pipe1_ra$20 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] mul_pipe1_rb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \mul_pipe1_rb$20 ;
+ wire [63:0] \mul_pipe1_rb$21 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire mul_pipe1_xer_so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire \mul_pipe1_xer_so$21 ;
+ wire \mul_pipe1_xer_so$22 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \mul_pipe2_mul_op__SV_Ptype$38 ;
+ wire [1:0] \mul_pipe2_mul_op__SV_Ptype$40 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \mul_pipe2_mul_op__fn_unit$24 ;
+ wire [14:0] \mul_pipe2_mul_op__fn_unit$25 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] mul_pipe2_mul_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \mul_pipe2_mul_op__imm_data__data$25 ;
+ wire [63:0] \mul_pipe2_mul_op__imm_data__data$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul_pipe2_mul_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_pipe2_mul_op__imm_data__ok$26 ;
+ wire \mul_pipe2_mul_op__imm_data__ok$27 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] mul_pipe2_mul_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \mul_pipe2_mul_op__insn$34 ;
+ wire [31:0] \mul_pipe2_mul_op__insn$35 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \mul_pipe2_mul_op__insn_type$23 ;
+ wire [6:0] \mul_pipe2_mul_op__insn_type$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul_pipe2_mul_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_pipe2_mul_op__is_32bit$32 ;
+ wire \mul_pipe2_mul_op__is_32bit$33 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul_pipe2_mul_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_pipe2_mul_op__is_signed$33 ;
+ wire \mul_pipe2_mul_op__is_signed$34 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul_pipe2_mul_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_pipe2_mul_op__oe__oe$29 ;
+ wire \mul_pipe2_mul_op__oe__oe$30 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul_pipe2_mul_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_pipe2_mul_op__oe__ok$30 ;
+ wire \mul_pipe2_mul_op__oe__ok$31 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul_pipe2_mul_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_pipe2_mul_op__rc__ok$28 ;
+ wire \mul_pipe2_mul_op__rc__ok$29 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul_pipe2_mul_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_pipe2_mul_op__rc__rc$27 ;
+ wire \mul_pipe2_mul_op__rc__rc$28 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] mul_pipe2_mul_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \mul_pipe2_mul_op__sv_ldstmode$39 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul_pipe2_mul_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_pipe2_mul_op__sv_pred_dz$36 ;
+ wire \mul_pipe2_mul_op__sv_pred_dz$37 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul_pipe2_mul_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_pipe2_mul_op__sv_pred_sz$35 ;
+ wire \mul_pipe2_mul_op__sv_pred_sz$36 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \mul_pipe2_mul_op__sv_saturate$37 ;
+ wire [1:0] \mul_pipe2_mul_op__sv_saturate$38 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul_pipe2_mul_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_pipe2_mul_op__write_cr0$31 ;
+ wire \mul_pipe2_mul_op__write_cr0$32 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] mul_pipe2_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \mul_pipe2_muxid$22 ;
+ wire [1:0] \mul_pipe2_muxid$23 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
wire mul_pipe2_n_ready_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *)
wire mul_pipe2_neg_res;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *)
- wire \mul_pipe2_neg_res$40 ;
+ wire \mul_pipe2_neg_res$42 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *)
wire mul_pipe2_neg_res32;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *)
- wire \mul_pipe2_neg_res32$41 ;
+ wire \mul_pipe2_neg_res32$43 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [128:0] mul_pipe2_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire mul_pipe2_xer_so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire \mul_pipe2_xer_so$39 ;
+ wire \mul_pipe2_xer_so$41 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [3:0] mul_pipe3_cr_a;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \mul_pipe3_mul_op__SV_Ptype$58 ;
+ wire [1:0] \mul_pipe3_mul_op__SV_Ptype$61 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \mul_pipe3_mul_op__fn_unit$44 ;
+ wire [14:0] \mul_pipe3_mul_op__fn_unit$46 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] mul_pipe3_mul_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \mul_pipe3_mul_op__imm_data__data$45 ;
+ wire [63:0] \mul_pipe3_mul_op__imm_data__data$47 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul_pipe3_mul_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_pipe3_mul_op__imm_data__ok$46 ;
+ wire \mul_pipe3_mul_op__imm_data__ok$48 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] mul_pipe3_mul_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \mul_pipe3_mul_op__insn$54 ;
+ wire [31:0] \mul_pipe3_mul_op__insn$56 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \mul_pipe3_mul_op__insn_type$43 ;
+ wire [6:0] \mul_pipe3_mul_op__insn_type$45 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul_pipe3_mul_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_pipe3_mul_op__is_32bit$52 ;
+ wire \mul_pipe3_mul_op__is_32bit$54 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul_pipe3_mul_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_pipe3_mul_op__is_signed$53 ;
+ wire \mul_pipe3_mul_op__is_signed$55 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul_pipe3_mul_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_pipe3_mul_op__oe__oe$49 ;
+ wire \mul_pipe3_mul_op__oe__oe$51 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul_pipe3_mul_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_pipe3_mul_op__oe__ok$50 ;
+ wire \mul_pipe3_mul_op__oe__ok$52 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul_pipe3_mul_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_pipe3_mul_op__rc__ok$48 ;
+ wire \mul_pipe3_mul_op__rc__ok$50 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul_pipe3_mul_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_pipe3_mul_op__rc__rc$47 ;
+ wire \mul_pipe3_mul_op__rc__rc$49 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] mul_pipe3_mul_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \mul_pipe3_mul_op__sv_ldstmode$60 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul_pipe3_mul_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_pipe3_mul_op__sv_pred_dz$56 ;
+ wire \mul_pipe3_mul_op__sv_pred_dz$58 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul_pipe3_mul_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_pipe3_mul_op__sv_pred_sz$55 ;
+ wire \mul_pipe3_mul_op__sv_pred_sz$57 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \mul_pipe3_mul_op__sv_saturate$57 ;
+ wire [1:0] \mul_pipe3_mul_op__sv_saturate$59 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul_pipe3_mul_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_pipe3_mul_op__write_cr0$51 ;
+ wire \mul_pipe3_mul_op__write_cr0$53 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] mul_pipe3_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \mul_pipe3_muxid$42 ;
+ wire [1:0] \mul_pipe3_muxid$44 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
wire mul_pipe3_n_ready_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [128:0] mul_pipe3_o;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \mul_pipe3_o$59 ;
+ wire [63:0] \mul_pipe3_o$62 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire mul_pipe3_o_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire mul_pipe3_xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \mul_pipe3_xer_so$60 ;
+ wire \mul_pipe3_xer_so$63 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire mul_pipe3_xer_so_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \muxid$61 ;
+ wire [1:0] \muxid$64 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
input n_ready_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
.coresync_clk(coresync_clk),
.coresync_rst(coresync_rst),
.mul_op__SV_Ptype(mul_pipe1_mul_op__SV_Ptype),
- .\mul_op__SV_Ptype$17 (\mul_pipe1_mul_op__SV_Ptype$18 ),
+ .\mul_op__SV_Ptype$18 (\mul_pipe1_mul_op__SV_Ptype$19 ),
.mul_op__fn_unit(mul_pipe1_mul_op__fn_unit),
.\mul_op__fn_unit$3 (\mul_pipe1_mul_op__fn_unit$4 ),
.mul_op__imm_data__data(mul_pipe1_mul_op__imm_data__data),
.\mul_op__rc__ok$7 (\mul_pipe1_mul_op__rc__ok$8 ),
.mul_op__rc__rc(mul_pipe1_mul_op__rc__rc),
.\mul_op__rc__rc$6 (\mul_pipe1_mul_op__rc__rc$7 ),
+ .mul_op__sv_ldstmode(mul_pipe1_mul_op__sv_ldstmode),
+ .\mul_op__sv_ldstmode$17 (\mul_pipe1_mul_op__sv_ldstmode$18 ),
.mul_op__sv_pred_dz(mul_pipe1_mul_op__sv_pred_dz),
.\mul_op__sv_pred_dz$15 (\mul_pipe1_mul_op__sv_pred_dz$16 ),
.mul_op__sv_pred_sz(mul_pipe1_mul_op__sv_pred_sz),
.p_ready_o(mul_pipe1_p_ready_o),
.p_valid_i(mul_pipe1_p_valid_i),
.ra(mul_pipe1_ra),
- .\ra$18 (\mul_pipe1_ra$19 ),
+ .\ra$19 (\mul_pipe1_ra$20 ),
.rb(mul_pipe1_rb),
- .\rb$19 (\mul_pipe1_rb$20 ),
+ .\rb$20 (\mul_pipe1_rb$21 ),
.xer_so(mul_pipe1_xer_so),
- .\xer_so$20 (\mul_pipe1_xer_so$21 )
+ .\xer_so$21 (\mul_pipe1_xer_so$22 )
);
mul_pipe2 mul_pipe2 (
.coresync_clk(coresync_clk),
.coresync_rst(coresync_rst),
.mul_op__SV_Ptype(mul_pipe2_mul_op__SV_Ptype),
- .\mul_op__SV_Ptype$17 (\mul_pipe2_mul_op__SV_Ptype$38 ),
+ .\mul_op__SV_Ptype$18 (\mul_pipe2_mul_op__SV_Ptype$40 ),
.mul_op__fn_unit(mul_pipe2_mul_op__fn_unit),
- .\mul_op__fn_unit$3 (\mul_pipe2_mul_op__fn_unit$24 ),
+ .\mul_op__fn_unit$3 (\mul_pipe2_mul_op__fn_unit$25 ),
.mul_op__imm_data__data(mul_pipe2_mul_op__imm_data__data),
- .\mul_op__imm_data__data$4 (\mul_pipe2_mul_op__imm_data__data$25 ),
+ .\mul_op__imm_data__data$4 (\mul_pipe2_mul_op__imm_data__data$26 ),
.mul_op__imm_data__ok(mul_pipe2_mul_op__imm_data__ok),
- .\mul_op__imm_data__ok$5 (\mul_pipe2_mul_op__imm_data__ok$26 ),
+ .\mul_op__imm_data__ok$5 (\mul_pipe2_mul_op__imm_data__ok$27 ),
.mul_op__insn(mul_pipe2_mul_op__insn),
- .\mul_op__insn$13 (\mul_pipe2_mul_op__insn$34 ),
+ .\mul_op__insn$13 (\mul_pipe2_mul_op__insn$35 ),
.mul_op__insn_type(mul_pipe2_mul_op__insn_type),
- .\mul_op__insn_type$2 (\mul_pipe2_mul_op__insn_type$23 ),
+ .\mul_op__insn_type$2 (\mul_pipe2_mul_op__insn_type$24 ),
.mul_op__is_32bit(mul_pipe2_mul_op__is_32bit),
- .\mul_op__is_32bit$11 (\mul_pipe2_mul_op__is_32bit$32 ),
+ .\mul_op__is_32bit$11 (\mul_pipe2_mul_op__is_32bit$33 ),
.mul_op__is_signed(mul_pipe2_mul_op__is_signed),
- .\mul_op__is_signed$12 (\mul_pipe2_mul_op__is_signed$33 ),
+ .\mul_op__is_signed$12 (\mul_pipe2_mul_op__is_signed$34 ),
.mul_op__oe__oe(mul_pipe2_mul_op__oe__oe),
- .\mul_op__oe__oe$8 (\mul_pipe2_mul_op__oe__oe$29 ),
+ .\mul_op__oe__oe$8 (\mul_pipe2_mul_op__oe__oe$30 ),
.mul_op__oe__ok(mul_pipe2_mul_op__oe__ok),
- .\mul_op__oe__ok$9 (\mul_pipe2_mul_op__oe__ok$30 ),
+ .\mul_op__oe__ok$9 (\mul_pipe2_mul_op__oe__ok$31 ),
.mul_op__rc__ok(mul_pipe2_mul_op__rc__ok),
- .\mul_op__rc__ok$7 (\mul_pipe2_mul_op__rc__ok$28 ),
+ .\mul_op__rc__ok$7 (\mul_pipe2_mul_op__rc__ok$29 ),
.mul_op__rc__rc(mul_pipe2_mul_op__rc__rc),
- .\mul_op__rc__rc$6 (\mul_pipe2_mul_op__rc__rc$27 ),
+ .\mul_op__rc__rc$6 (\mul_pipe2_mul_op__rc__rc$28 ),
+ .mul_op__sv_ldstmode(mul_pipe2_mul_op__sv_ldstmode),
+ .\mul_op__sv_ldstmode$17 (\mul_pipe2_mul_op__sv_ldstmode$39 ),
.mul_op__sv_pred_dz(mul_pipe2_mul_op__sv_pred_dz),
- .\mul_op__sv_pred_dz$15 (\mul_pipe2_mul_op__sv_pred_dz$36 ),
+ .\mul_op__sv_pred_dz$15 (\mul_pipe2_mul_op__sv_pred_dz$37 ),
.mul_op__sv_pred_sz(mul_pipe2_mul_op__sv_pred_sz),
- .\mul_op__sv_pred_sz$14 (\mul_pipe2_mul_op__sv_pred_sz$35 ),
+ .\mul_op__sv_pred_sz$14 (\mul_pipe2_mul_op__sv_pred_sz$36 ),
.mul_op__sv_saturate(mul_pipe2_mul_op__sv_saturate),
- .\mul_op__sv_saturate$16 (\mul_pipe2_mul_op__sv_saturate$37 ),
+ .\mul_op__sv_saturate$16 (\mul_pipe2_mul_op__sv_saturate$38 ),
.mul_op__write_cr0(mul_pipe2_mul_op__write_cr0),
- .\mul_op__write_cr0$10 (\mul_pipe2_mul_op__write_cr0$31 ),
+ .\mul_op__write_cr0$10 (\mul_pipe2_mul_op__write_cr0$32 ),
.muxid(mul_pipe2_muxid),
- .\muxid$1 (\mul_pipe2_muxid$22 ),
+ .\muxid$1 (\mul_pipe2_muxid$23 ),
.n_ready_i(mul_pipe2_n_ready_i),
.n_valid_o(mul_pipe2_n_valid_o),
.neg_res(mul_pipe2_neg_res),
- .\neg_res$19 (\mul_pipe2_neg_res$40 ),
+ .\neg_res$20 (\mul_pipe2_neg_res$42 ),
.neg_res32(mul_pipe2_neg_res32),
- .\neg_res32$20 (\mul_pipe2_neg_res32$41 ),
+ .\neg_res32$21 (\mul_pipe2_neg_res32$43 ),
.o(mul_pipe2_o),
.p_ready_o(mul_pipe2_p_ready_o),
.p_valid_i(mul_pipe2_p_valid_i),
.ra(mul_pipe2_ra),
.rb(mul_pipe2_rb),
.xer_so(mul_pipe2_xer_so),
- .\xer_so$18 (\mul_pipe2_xer_so$39 )
+ .\xer_so$19 (\mul_pipe2_xer_so$41 )
);
mul_pipe3 mul_pipe3 (
.coresync_clk(coresync_clk),
.cr_a(mul_pipe3_cr_a),
.cr_a_ok(mul_pipe3_cr_a_ok),
.mul_op__SV_Ptype(mul_pipe3_mul_op__SV_Ptype),
- .\mul_op__SV_Ptype$17 (\mul_pipe3_mul_op__SV_Ptype$58 ),
+ .\mul_op__SV_Ptype$18 (\mul_pipe3_mul_op__SV_Ptype$61 ),
.mul_op__fn_unit(mul_pipe3_mul_op__fn_unit),
- .\mul_op__fn_unit$3 (\mul_pipe3_mul_op__fn_unit$44 ),
+ .\mul_op__fn_unit$3 (\mul_pipe3_mul_op__fn_unit$46 ),
.mul_op__imm_data__data(mul_pipe3_mul_op__imm_data__data),
- .\mul_op__imm_data__data$4 (\mul_pipe3_mul_op__imm_data__data$45 ),
+ .\mul_op__imm_data__data$4 (\mul_pipe3_mul_op__imm_data__data$47 ),
.mul_op__imm_data__ok(mul_pipe3_mul_op__imm_data__ok),
- .\mul_op__imm_data__ok$5 (\mul_pipe3_mul_op__imm_data__ok$46 ),
+ .\mul_op__imm_data__ok$5 (\mul_pipe3_mul_op__imm_data__ok$48 ),
.mul_op__insn(mul_pipe3_mul_op__insn),
- .\mul_op__insn$13 (\mul_pipe3_mul_op__insn$54 ),
+ .\mul_op__insn$13 (\mul_pipe3_mul_op__insn$56 ),
.mul_op__insn_type(mul_pipe3_mul_op__insn_type),
- .\mul_op__insn_type$2 (\mul_pipe3_mul_op__insn_type$43 ),
+ .\mul_op__insn_type$2 (\mul_pipe3_mul_op__insn_type$45 ),
.mul_op__is_32bit(mul_pipe3_mul_op__is_32bit),
- .\mul_op__is_32bit$11 (\mul_pipe3_mul_op__is_32bit$52 ),
+ .\mul_op__is_32bit$11 (\mul_pipe3_mul_op__is_32bit$54 ),
.mul_op__is_signed(mul_pipe3_mul_op__is_signed),
- .\mul_op__is_signed$12 (\mul_pipe3_mul_op__is_signed$53 ),
+ .\mul_op__is_signed$12 (\mul_pipe3_mul_op__is_signed$55 ),
.mul_op__oe__oe(mul_pipe3_mul_op__oe__oe),
- .\mul_op__oe__oe$8 (\mul_pipe3_mul_op__oe__oe$49 ),
+ .\mul_op__oe__oe$8 (\mul_pipe3_mul_op__oe__oe$51 ),
.mul_op__oe__ok(mul_pipe3_mul_op__oe__ok),
- .\mul_op__oe__ok$9 (\mul_pipe3_mul_op__oe__ok$50 ),
+ .\mul_op__oe__ok$9 (\mul_pipe3_mul_op__oe__ok$52 ),
.mul_op__rc__ok(mul_pipe3_mul_op__rc__ok),
- .\mul_op__rc__ok$7 (\mul_pipe3_mul_op__rc__ok$48 ),
+ .\mul_op__rc__ok$7 (\mul_pipe3_mul_op__rc__ok$50 ),
.mul_op__rc__rc(mul_pipe3_mul_op__rc__rc),
- .\mul_op__rc__rc$6 (\mul_pipe3_mul_op__rc__rc$47 ),
+ .\mul_op__rc__rc$6 (\mul_pipe3_mul_op__rc__rc$49 ),
+ .mul_op__sv_ldstmode(mul_pipe3_mul_op__sv_ldstmode),
+ .\mul_op__sv_ldstmode$17 (\mul_pipe3_mul_op__sv_ldstmode$60 ),
.mul_op__sv_pred_dz(mul_pipe3_mul_op__sv_pred_dz),
- .\mul_op__sv_pred_dz$15 (\mul_pipe3_mul_op__sv_pred_dz$56 ),
+ .\mul_op__sv_pred_dz$15 (\mul_pipe3_mul_op__sv_pred_dz$58 ),
.mul_op__sv_pred_sz(mul_pipe3_mul_op__sv_pred_sz),
- .\mul_op__sv_pred_sz$14 (\mul_pipe3_mul_op__sv_pred_sz$55 ),
+ .\mul_op__sv_pred_sz$14 (\mul_pipe3_mul_op__sv_pred_sz$57 ),
.mul_op__sv_saturate(mul_pipe3_mul_op__sv_saturate),
- .\mul_op__sv_saturate$16 (\mul_pipe3_mul_op__sv_saturate$57 ),
+ .\mul_op__sv_saturate$16 (\mul_pipe3_mul_op__sv_saturate$59 ),
.mul_op__write_cr0(mul_pipe3_mul_op__write_cr0),
- .\mul_op__write_cr0$10 (\mul_pipe3_mul_op__write_cr0$51 ),
+ .\mul_op__write_cr0$10 (\mul_pipe3_mul_op__write_cr0$53 ),
.muxid(mul_pipe3_muxid),
- .\muxid$1 (\mul_pipe3_muxid$42 ),
+ .\muxid$1 (\mul_pipe3_muxid$44 ),
.n_ready_i(mul_pipe3_n_ready_i),
.n_valid_o(mul_pipe3_n_valid_o),
.neg_res(mul_pipe3_neg_res),
.neg_res32(mul_pipe3_neg_res32),
.o(mul_pipe3_o),
- .\o$18 (\mul_pipe3_o$59 ),
+ .\o$19 (\mul_pipe3_o$62 ),
.o_ok(mul_pipe3_o_ok),
.p_ready_o(mul_pipe3_p_ready_o),
.p_valid_i(mul_pipe3_p_valid_i),
.xer_ov(mul_pipe3_xer_ov),
.xer_ov_ok(mul_pipe3_xer_ov_ok),
.xer_so(mul_pipe3_xer_so),
- .\xer_so$19 (\mul_pipe3_xer_so$60 ),
+ .\xer_so$20 (\mul_pipe3_xer_so$63 ),
.xer_so_ok(mul_pipe3_xer_so_ok)
);
\n$92 n (
.p_valid_i(p_valid_i)
);
assign muxid = 2'h0;
- assign { xer_so_ok, xer_so } = { mul_pipe3_xer_so_ok, \mul_pipe3_xer_so$60 };
+ assign { xer_so_ok, xer_so } = { mul_pipe3_xer_so_ok, \mul_pipe3_xer_so$63 };
assign { xer_ov_ok, xer_ov } = { mul_pipe3_xer_ov_ok, mul_pipe3_xer_ov };
assign { cr_a_ok, cr_a } = { mul_pipe3_cr_a_ok, mul_pipe3_cr_a };
- assign { o_ok, o } = { mul_pipe3_o_ok, \mul_pipe3_o$59 };
- assign { \mul_op__SV_Ptype$77 , \mul_op__sv_saturate$76 , \mul_op__sv_pred_dz$75 , \mul_op__sv_pred_sz$74 , \mul_op__insn$73 , \mul_op__is_signed$72 , \mul_op__is_32bit$71 , \mul_op__write_cr0$70 , \mul_op__oe__ok$69 , \mul_op__oe__oe$68 , \mul_op__rc__ok$67 , \mul_op__rc__rc$66 , \mul_op__imm_data__ok$65 , \mul_op__imm_data__data$64 , \mul_op__fn_unit$63 , \mul_op__insn_type$62 } = { \mul_pipe3_mul_op__SV_Ptype$58 , \mul_pipe3_mul_op__sv_saturate$57 , \mul_pipe3_mul_op__sv_pred_dz$56 , \mul_pipe3_mul_op__sv_pred_sz$55 , \mul_pipe3_mul_op__insn$54 , \mul_pipe3_mul_op__is_signed$53 , \mul_pipe3_mul_op__is_32bit$52 , \mul_pipe3_mul_op__write_cr0$51 , \mul_pipe3_mul_op__oe__ok$50 , \mul_pipe3_mul_op__oe__oe$49 , \mul_pipe3_mul_op__rc__ok$48 , \mul_pipe3_mul_op__rc__rc$47 , \mul_pipe3_mul_op__imm_data__ok$46 , \mul_pipe3_mul_op__imm_data__data$45 , \mul_pipe3_mul_op__fn_unit$44 , \mul_pipe3_mul_op__insn_type$43 };
- assign \muxid$61 = \mul_pipe3_muxid$42 ;
+ assign { o_ok, o } = { mul_pipe3_o_ok, \mul_pipe3_o$62 };
+ assign { \mul_op__SV_Ptype$81 , \mul_op__sv_ldstmode$80 , \mul_op__sv_saturate$79 , \mul_op__sv_pred_dz$78 , \mul_op__sv_pred_sz$77 , \mul_op__insn$76 , \mul_op__is_signed$75 , \mul_op__is_32bit$74 , \mul_op__write_cr0$73 , \mul_op__oe__ok$72 , \mul_op__oe__oe$71 , \mul_op__rc__ok$70 , \mul_op__rc__rc$69 , \mul_op__imm_data__ok$68 , \mul_op__imm_data__data$67 , \mul_op__fn_unit$66 , \mul_op__insn_type$65 } = { \mul_pipe3_mul_op__SV_Ptype$61 , \mul_pipe3_mul_op__sv_ldstmode$60 , \mul_pipe3_mul_op__sv_saturate$59 , \mul_pipe3_mul_op__sv_pred_dz$58 , \mul_pipe3_mul_op__sv_pred_sz$57 , \mul_pipe3_mul_op__insn$56 , \mul_pipe3_mul_op__is_signed$55 , \mul_pipe3_mul_op__is_32bit$54 , \mul_pipe3_mul_op__write_cr0$53 , \mul_pipe3_mul_op__oe__ok$52 , \mul_pipe3_mul_op__oe__oe$51 , \mul_pipe3_mul_op__rc__ok$50 , \mul_pipe3_mul_op__rc__rc$49 , \mul_pipe3_mul_op__imm_data__ok$48 , \mul_pipe3_mul_op__imm_data__data$47 , \mul_pipe3_mul_op__fn_unit$46 , \mul_pipe3_mul_op__insn_type$45 };
+ assign \muxid$64 = \mul_pipe3_muxid$44 ;
assign mul_pipe3_n_ready_i = n_ready_i;
assign n_valid_o = mul_pipe3_n_valid_o;
- assign \mul_pipe1_xer_so$21 = \xer_so$1 ;
- assign \mul_pipe1_rb$20 = rb;
- assign \mul_pipe1_ra$19 = ra;
- assign { \mul_pipe1_mul_op__SV_Ptype$18 , \mul_pipe1_mul_op__sv_saturate$17 , \mul_pipe1_mul_op__sv_pred_dz$16 , \mul_pipe1_mul_op__sv_pred_sz$15 , \mul_pipe1_mul_op__insn$14 , \mul_pipe1_mul_op__is_signed$13 , \mul_pipe1_mul_op__is_32bit$12 , \mul_pipe1_mul_op__write_cr0$11 , \mul_pipe1_mul_op__oe__ok$10 , \mul_pipe1_mul_op__oe__oe$9 , \mul_pipe1_mul_op__rc__ok$8 , \mul_pipe1_mul_op__rc__rc$7 , \mul_pipe1_mul_op__imm_data__ok$6 , \mul_pipe1_mul_op__imm_data__data$5 , \mul_pipe1_mul_op__fn_unit$4 , \mul_pipe1_mul_op__insn_type$3 } = { mul_op__SV_Ptype, mul_op__sv_saturate, mul_op__sv_pred_dz, mul_op__sv_pred_sz, mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type };
+ assign \mul_pipe1_xer_so$22 = \xer_so$1 ;
+ assign \mul_pipe1_rb$21 = rb;
+ assign \mul_pipe1_ra$20 = ra;
+ assign { \mul_pipe1_mul_op__SV_Ptype$19 , \mul_pipe1_mul_op__sv_ldstmode$18 , \mul_pipe1_mul_op__sv_saturate$17 , \mul_pipe1_mul_op__sv_pred_dz$16 , \mul_pipe1_mul_op__sv_pred_sz$15 , \mul_pipe1_mul_op__insn$14 , \mul_pipe1_mul_op__is_signed$13 , \mul_pipe1_mul_op__is_32bit$12 , \mul_pipe1_mul_op__write_cr0$11 , \mul_pipe1_mul_op__oe__ok$10 , \mul_pipe1_mul_op__oe__oe$9 , \mul_pipe1_mul_op__rc__ok$8 , \mul_pipe1_mul_op__rc__rc$7 , \mul_pipe1_mul_op__imm_data__ok$6 , \mul_pipe1_mul_op__imm_data__data$5 , \mul_pipe1_mul_op__fn_unit$4 , \mul_pipe1_mul_op__insn_type$3 } = { mul_op__SV_Ptype, mul_op__sv_ldstmode, mul_op__sv_saturate, mul_op__sv_pred_dz, mul_op__sv_pred_sz, mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type };
assign \mul_pipe1_muxid$2 = 2'h0;
assign p_ready_o = mul_pipe1_p_ready_o;
assign mul_pipe1_p_valid_i = p_valid_i;
- assign mul_pipe3_neg_res32 = \mul_pipe2_neg_res32$41 ;
- assign mul_pipe3_neg_res = \mul_pipe2_neg_res$40 ;
- assign mul_pipe3_xer_so = \mul_pipe2_xer_so$39 ;
+ assign mul_pipe3_neg_res32 = \mul_pipe2_neg_res32$43 ;
+ assign mul_pipe3_neg_res = \mul_pipe2_neg_res$42 ;
+ assign mul_pipe3_xer_so = \mul_pipe2_xer_so$41 ;
assign mul_pipe3_o = mul_pipe2_o;
- assign { mul_pipe3_mul_op__SV_Ptype, mul_pipe3_mul_op__sv_saturate, mul_pipe3_mul_op__sv_pred_dz, mul_pipe3_mul_op__sv_pred_sz, mul_pipe3_mul_op__insn, mul_pipe3_mul_op__is_signed, mul_pipe3_mul_op__is_32bit, mul_pipe3_mul_op__write_cr0, mul_pipe3_mul_op__oe__ok, mul_pipe3_mul_op__oe__oe, mul_pipe3_mul_op__rc__ok, mul_pipe3_mul_op__rc__rc, mul_pipe3_mul_op__imm_data__ok, mul_pipe3_mul_op__imm_data__data, mul_pipe3_mul_op__fn_unit, mul_pipe3_mul_op__insn_type } = { \mul_pipe2_mul_op__SV_Ptype$38 , \mul_pipe2_mul_op__sv_saturate$37 , \mul_pipe2_mul_op__sv_pred_dz$36 , \mul_pipe2_mul_op__sv_pred_sz$35 , \mul_pipe2_mul_op__insn$34 , \mul_pipe2_mul_op__is_signed$33 , \mul_pipe2_mul_op__is_32bit$32 , \mul_pipe2_mul_op__write_cr0$31 , \mul_pipe2_mul_op__oe__ok$30 , \mul_pipe2_mul_op__oe__oe$29 , \mul_pipe2_mul_op__rc__ok$28 , \mul_pipe2_mul_op__rc__rc$27 , \mul_pipe2_mul_op__imm_data__ok$26 , \mul_pipe2_mul_op__imm_data__data$25 , \mul_pipe2_mul_op__fn_unit$24 , \mul_pipe2_mul_op__insn_type$23 };
- assign mul_pipe3_muxid = \mul_pipe2_muxid$22 ;
+ assign { mul_pipe3_mul_op__SV_Ptype, mul_pipe3_mul_op__sv_ldstmode, mul_pipe3_mul_op__sv_saturate, mul_pipe3_mul_op__sv_pred_dz, mul_pipe3_mul_op__sv_pred_sz, mul_pipe3_mul_op__insn, mul_pipe3_mul_op__is_signed, mul_pipe3_mul_op__is_32bit, mul_pipe3_mul_op__write_cr0, mul_pipe3_mul_op__oe__ok, mul_pipe3_mul_op__oe__oe, mul_pipe3_mul_op__rc__ok, mul_pipe3_mul_op__rc__rc, mul_pipe3_mul_op__imm_data__ok, mul_pipe3_mul_op__imm_data__data, mul_pipe3_mul_op__fn_unit, mul_pipe3_mul_op__insn_type } = { \mul_pipe2_mul_op__SV_Ptype$40 , \mul_pipe2_mul_op__sv_ldstmode$39 , \mul_pipe2_mul_op__sv_saturate$38 , \mul_pipe2_mul_op__sv_pred_dz$37 , \mul_pipe2_mul_op__sv_pred_sz$36 , \mul_pipe2_mul_op__insn$35 , \mul_pipe2_mul_op__is_signed$34 , \mul_pipe2_mul_op__is_32bit$33 , \mul_pipe2_mul_op__write_cr0$32 , \mul_pipe2_mul_op__oe__ok$31 , \mul_pipe2_mul_op__oe__oe$30 , \mul_pipe2_mul_op__rc__ok$29 , \mul_pipe2_mul_op__rc__rc$28 , \mul_pipe2_mul_op__imm_data__ok$27 , \mul_pipe2_mul_op__imm_data__data$26 , \mul_pipe2_mul_op__fn_unit$25 , \mul_pipe2_mul_op__insn_type$24 };
+ assign mul_pipe3_muxid = \mul_pipe2_muxid$23 ;
assign mul_pipe2_n_ready_i = mul_pipe3_p_ready_o;
assign mul_pipe3_p_valid_i = mul_pipe2_n_valid_o;
assign mul_pipe2_neg_res32 = mul_pipe1_neg_res32;
assign mul_pipe2_xer_so = mul_pipe1_xer_so;
assign mul_pipe2_rb = mul_pipe1_rb;
assign mul_pipe2_ra = mul_pipe1_ra;
- assign { mul_pipe2_mul_op__SV_Ptype, mul_pipe2_mul_op__sv_saturate, mul_pipe2_mul_op__sv_pred_dz, mul_pipe2_mul_op__sv_pred_sz, mul_pipe2_mul_op__insn, mul_pipe2_mul_op__is_signed, mul_pipe2_mul_op__is_32bit, mul_pipe2_mul_op__write_cr0, mul_pipe2_mul_op__oe__ok, mul_pipe2_mul_op__oe__oe, mul_pipe2_mul_op__rc__ok, mul_pipe2_mul_op__rc__rc, mul_pipe2_mul_op__imm_data__ok, mul_pipe2_mul_op__imm_data__data, mul_pipe2_mul_op__fn_unit, mul_pipe2_mul_op__insn_type } = { mul_pipe1_mul_op__SV_Ptype, mul_pipe1_mul_op__sv_saturate, mul_pipe1_mul_op__sv_pred_dz, mul_pipe1_mul_op__sv_pred_sz, mul_pipe1_mul_op__insn, mul_pipe1_mul_op__is_signed, mul_pipe1_mul_op__is_32bit, mul_pipe1_mul_op__write_cr0, mul_pipe1_mul_op__oe__ok, mul_pipe1_mul_op__oe__oe, mul_pipe1_mul_op__rc__ok, mul_pipe1_mul_op__rc__rc, mul_pipe1_mul_op__imm_data__ok, mul_pipe1_mul_op__imm_data__data, mul_pipe1_mul_op__fn_unit, mul_pipe1_mul_op__insn_type };
+ assign { mul_pipe2_mul_op__SV_Ptype, mul_pipe2_mul_op__sv_ldstmode, mul_pipe2_mul_op__sv_saturate, mul_pipe2_mul_op__sv_pred_dz, mul_pipe2_mul_op__sv_pred_sz, mul_pipe2_mul_op__insn, mul_pipe2_mul_op__is_signed, mul_pipe2_mul_op__is_32bit, mul_pipe2_mul_op__write_cr0, mul_pipe2_mul_op__oe__ok, mul_pipe2_mul_op__oe__oe, mul_pipe2_mul_op__rc__ok, mul_pipe2_mul_op__rc__rc, mul_pipe2_mul_op__imm_data__ok, mul_pipe2_mul_op__imm_data__data, mul_pipe2_mul_op__fn_unit, mul_pipe2_mul_op__insn_type } = { mul_pipe1_mul_op__SV_Ptype, mul_pipe1_mul_op__sv_ldstmode, mul_pipe1_mul_op__sv_saturate, mul_pipe1_mul_op__sv_pred_dz, mul_pipe1_mul_op__sv_pred_sz, mul_pipe1_mul_op__insn, mul_pipe1_mul_op__is_signed, mul_pipe1_mul_op__is_32bit, mul_pipe1_mul_op__write_cr0, mul_pipe1_mul_op__oe__ok, mul_pipe1_mul_op__oe__oe, mul_pipe1_mul_op__rc__ok, mul_pipe1_mul_op__rc__rc, mul_pipe1_mul_op__imm_data__ok, mul_pipe1_mul_op__imm_data__data, mul_pipe1_mul_op__fn_unit, mul_pipe1_mul_op__insn_type };
assign mul_pipe2_muxid = mul_pipe1_muxid;
assign mul_pipe1_n_ready_i = mul_pipe2_p_ready_o;
assign mul_pipe2_p_valid_i = mul_pipe1_n_valid_o;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0" *)
(* generator = "nMigen" *)
-module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready_i, sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, sr_op__sv_pred_sz, sr_op__sv_pred_dz, sr_op__sv_saturate, sr_op__SV_Ptype, o, cr_a, xer_ca, ra, rb, rc, xer_so, \xer_ca$1 , p_valid_i, p_ready_o, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready_i, sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, sr_op__sv_pred_sz, sr_op__sv_pred_dz, sr_op__sv_saturate, sr_op__sv_ldstmode, sr_op__SV_Ptype, o, cr_a, xer_ca, ra, rb, rc, xer_so, \xer_ca$1 , p_valid_i, p_ready_o, coresync_clk);
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output [3:0] cr_a;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \muxid$54 ;
+ wire [1:0] \muxid$56 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
input n_ready_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \pipe1_sr_op__SV_Ptype$23 ;
+ wire [1:0] \pipe1_sr_op__SV_Ptype$24 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
wire pipe1_sr_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire \pipe1_sr_op__rc__rc$7 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] pipe1_sr_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \pipe1_sr_op__sv_ldstmode$23 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe1_sr_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [1:0] pipe1_xer_ca;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [1:0] \pipe1_xer_ca$25 ;
+ wire [1:0] \pipe1_xer_ca$26 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe1_xer_ca_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe1_xer_so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire \pipe1_xer_so$24 ;
+ wire \pipe1_xer_so$25 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe1_xer_so_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [3:0] pipe2_cr_a;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [3:0] \pipe2_cr_a$50 ;
+ wire [3:0] \pipe2_cr_a$52 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe2_cr_a_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \pipe2_cr_a_ok$51 ;
+ wire \pipe2_cr_a_ok$53 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] pipe2_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \pipe2_muxid$26 ;
+ wire [1:0] \pipe2_muxid$27 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
wire pipe2_n_ready_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [63:0] pipe2_o;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \pipe2_o$48 ;
+ wire [63:0] \pipe2_o$50 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe2_o_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \pipe2_o_ok$49 ;
+ wire \pipe2_o_ok$51 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
wire pipe2_p_ready_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \pipe2_sr_op__SV_Ptype$47 ;
+ wire [1:0] \pipe2_sr_op__SV_Ptype$49 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \pipe2_sr_op__fn_unit$28 ;
+ wire [14:0] \pipe2_sr_op__fn_unit$29 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] pipe2_sr_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \pipe2_sr_op__imm_data__data$29 ;
+ wire [63:0] \pipe2_sr_op__imm_data__data$30 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_sr_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_sr_op__imm_data__ok$30 ;
+ wire \pipe2_sr_op__imm_data__ok$31 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \pipe2_sr_op__input_carry$37 ;
+ wire [1:0] \pipe2_sr_op__input_carry$38 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_sr_op__input_cr;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_sr_op__input_cr$39 ;
+ wire \pipe2_sr_op__input_cr$40 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] pipe2_sr_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \pipe2_sr_op__insn$43 ;
+ wire [31:0] \pipe2_sr_op__insn$44 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \pipe2_sr_op__insn_type$27 ;
+ wire [6:0] \pipe2_sr_op__insn_type$28 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_sr_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_sr_op__invert_in$36 ;
+ wire \pipe2_sr_op__invert_in$37 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_sr_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_sr_op__is_32bit$41 ;
+ wire \pipe2_sr_op__is_32bit$42 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_sr_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_sr_op__is_signed$42 ;
+ wire \pipe2_sr_op__is_signed$43 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_sr_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_sr_op__oe__oe$33 ;
+ wire \pipe2_sr_op__oe__oe$34 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_sr_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_sr_op__oe__ok$34 ;
+ wire \pipe2_sr_op__oe__ok$35 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_sr_op__output_carry;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_sr_op__output_carry$38 ;
+ wire \pipe2_sr_op__output_carry$39 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_sr_op__output_cr;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_sr_op__output_cr$40 ;
+ wire \pipe2_sr_op__output_cr$41 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_sr_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_sr_op__rc__ok$32 ;
+ wire \pipe2_sr_op__rc__ok$33 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_sr_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_sr_op__rc__rc$31 ;
+ wire \pipe2_sr_op__rc__rc$32 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] pipe2_sr_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \pipe2_sr_op__sv_ldstmode$48 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_sr_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_sr_op__sv_pred_dz$45 ;
+ wire \pipe2_sr_op__sv_pred_dz$46 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_sr_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_sr_op__sv_pred_sz$44 ;
+ wire \pipe2_sr_op__sv_pred_sz$45 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \pipe2_sr_op__sv_saturate$46 ;
+ wire [1:0] \pipe2_sr_op__sv_saturate$47 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_sr_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_sr_op__write_cr0$35 ;
+ wire \pipe2_sr_op__write_cr0$36 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [1:0] pipe2_xer_ca;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [1:0] \pipe2_xer_ca$52 ;
+ wire [1:0] \pipe2_xer_ca$54 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe2_xer_ca_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \pipe2_xer_ca_ok$53 ;
+ wire \pipe2_xer_ca_ok$55 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe2_xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \sr_op__SV_Ptype$75 ;
+ wire [1:0] \sr_op__SV_Ptype$78 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \sr_op__fn_unit$56 ;
+ wire [14:0] \sr_op__fn_unit$58 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] sr_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \sr_op__imm_data__data$57 ;
+ wire [63:0] \sr_op__imm_data__data$59 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__imm_data__ok$58 ;
+ wire \sr_op__imm_data__ok$60 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \sr_op__input_carry$65 ;
+ wire [1:0] \sr_op__input_carry$67 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__input_cr;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__input_cr$67 ;
+ wire \sr_op__input_cr$69 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] sr_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \sr_op__insn$71 ;
+ wire [31:0] \sr_op__insn$73 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \sr_op__insn_type$55 ;
+ wire [6:0] \sr_op__insn_type$57 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__invert_in$64 ;
+ wire \sr_op__invert_in$66 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__is_32bit$69 ;
+ wire \sr_op__is_32bit$71 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__is_signed$70 ;
+ wire \sr_op__is_signed$72 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__oe__oe$61 ;
+ wire \sr_op__oe__oe$63 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__oe__ok$62 ;
+ wire \sr_op__oe__ok$64 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__output_carry;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__output_carry$66 ;
+ wire \sr_op__output_carry$68 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__output_cr;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__output_cr$68 ;
+ wire \sr_op__output_cr$70 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__rc__ok$60 ;
+ wire \sr_op__rc__ok$62 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__rc__rc$59 ;
+ wire \sr_op__rc__rc$61 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] sr_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \sr_op__sv_ldstmode$77 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__sv_pred_dz$73 ;
+ wire \sr_op__sv_pred_dz$75 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__sv_pred_sz$72 ;
+ wire \sr_op__sv_pred_sz$74 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \sr_op__sv_saturate$74 ;
+ wire [1:0] \sr_op__sv_saturate$76 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__write_cr0$63 ;
+ wire \sr_op__write_cr0$65 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output [1:0] xer_ca;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
.rb(pipe1_rb),
.rc(pipe1_rc),
.sr_op__SV_Ptype(pipe1_sr_op__SV_Ptype),
- .\sr_op__SV_Ptype$22 (\pipe1_sr_op__SV_Ptype$23 ),
+ .\sr_op__SV_Ptype$23 (\pipe1_sr_op__SV_Ptype$24 ),
.sr_op__fn_unit(pipe1_sr_op__fn_unit),
.\sr_op__fn_unit$3 (\pipe1_sr_op__fn_unit$4 ),
.sr_op__imm_data__data(pipe1_sr_op__imm_data__data),
.\sr_op__rc__ok$7 (\pipe1_sr_op__rc__ok$8 ),
.sr_op__rc__rc(pipe1_sr_op__rc__rc),
.\sr_op__rc__rc$6 (\pipe1_sr_op__rc__rc$7 ),
+ .sr_op__sv_ldstmode(pipe1_sr_op__sv_ldstmode),
+ .\sr_op__sv_ldstmode$22 (\pipe1_sr_op__sv_ldstmode$23 ),
.sr_op__sv_pred_dz(pipe1_sr_op__sv_pred_dz),
.\sr_op__sv_pred_dz$20 (\pipe1_sr_op__sv_pred_dz$21 ),
.sr_op__sv_pred_sz(pipe1_sr_op__sv_pred_sz),
.sr_op__write_cr0(pipe1_sr_op__write_cr0),
.\sr_op__write_cr0$10 (\pipe1_sr_op__write_cr0$11 ),
.xer_ca(pipe1_xer_ca),
- .\xer_ca$24 (\pipe1_xer_ca$25 ),
+ .\xer_ca$25 (\pipe1_xer_ca$26 ),
.xer_ca_ok(pipe1_xer_ca_ok),
.xer_so(pipe1_xer_so),
- .\xer_so$23 (\pipe1_xer_so$24 ),
+ .\xer_so$24 (\pipe1_xer_so$25 ),
.xer_so_ok(pipe1_xer_so_ok)
);
\pipe2$115 pipe2 (
.coresync_clk(coresync_clk),
.coresync_rst(coresync_rst),
.cr_a(pipe2_cr_a),
- .\cr_a$25 (\pipe2_cr_a$50 ),
+ .\cr_a$26 (\pipe2_cr_a$52 ),
.cr_a_ok(pipe2_cr_a_ok),
- .\cr_a_ok$26 (\pipe2_cr_a_ok$51 ),
+ .\cr_a_ok$27 (\pipe2_cr_a_ok$53 ),
.muxid(pipe2_muxid),
- .\muxid$1 (\pipe2_muxid$26 ),
+ .\muxid$1 (\pipe2_muxid$27 ),
.n_ready_i(pipe2_n_ready_i),
.n_valid_o(pipe2_n_valid_o),
.o(pipe2_o),
- .\o$23 (\pipe2_o$48 ),
+ .\o$24 (\pipe2_o$50 ),
.o_ok(pipe2_o_ok),
- .\o_ok$24 (\pipe2_o_ok$49 ),
+ .\o_ok$25 (\pipe2_o_ok$51 ),
.p_ready_o(pipe2_p_ready_o),
.p_valid_i(pipe2_p_valid_i),
.sr_op__SV_Ptype(pipe2_sr_op__SV_Ptype),
- .\sr_op__SV_Ptype$22 (\pipe2_sr_op__SV_Ptype$47 ),
+ .\sr_op__SV_Ptype$23 (\pipe2_sr_op__SV_Ptype$49 ),
.sr_op__fn_unit(pipe2_sr_op__fn_unit),
- .\sr_op__fn_unit$3 (\pipe2_sr_op__fn_unit$28 ),
+ .\sr_op__fn_unit$3 (\pipe2_sr_op__fn_unit$29 ),
.sr_op__imm_data__data(pipe2_sr_op__imm_data__data),
- .\sr_op__imm_data__data$4 (\pipe2_sr_op__imm_data__data$29 ),
+ .\sr_op__imm_data__data$4 (\pipe2_sr_op__imm_data__data$30 ),
.sr_op__imm_data__ok(pipe2_sr_op__imm_data__ok),
- .\sr_op__imm_data__ok$5 (\pipe2_sr_op__imm_data__ok$30 ),
+ .\sr_op__imm_data__ok$5 (\pipe2_sr_op__imm_data__ok$31 ),
.sr_op__input_carry(pipe2_sr_op__input_carry),
- .\sr_op__input_carry$12 (\pipe2_sr_op__input_carry$37 ),
+ .\sr_op__input_carry$12 (\pipe2_sr_op__input_carry$38 ),
.sr_op__input_cr(pipe2_sr_op__input_cr),
- .\sr_op__input_cr$14 (\pipe2_sr_op__input_cr$39 ),
+ .\sr_op__input_cr$14 (\pipe2_sr_op__input_cr$40 ),
.sr_op__insn(pipe2_sr_op__insn),
- .\sr_op__insn$18 (\pipe2_sr_op__insn$43 ),
+ .\sr_op__insn$18 (\pipe2_sr_op__insn$44 ),
.sr_op__insn_type(pipe2_sr_op__insn_type),
- .\sr_op__insn_type$2 (\pipe2_sr_op__insn_type$27 ),
+ .\sr_op__insn_type$2 (\pipe2_sr_op__insn_type$28 ),
.sr_op__invert_in(pipe2_sr_op__invert_in),
- .\sr_op__invert_in$11 (\pipe2_sr_op__invert_in$36 ),
+ .\sr_op__invert_in$11 (\pipe2_sr_op__invert_in$37 ),
.sr_op__is_32bit(pipe2_sr_op__is_32bit),
- .\sr_op__is_32bit$16 (\pipe2_sr_op__is_32bit$41 ),
+ .\sr_op__is_32bit$16 (\pipe2_sr_op__is_32bit$42 ),
.sr_op__is_signed(pipe2_sr_op__is_signed),
- .\sr_op__is_signed$17 (\pipe2_sr_op__is_signed$42 ),
+ .\sr_op__is_signed$17 (\pipe2_sr_op__is_signed$43 ),
.sr_op__oe__oe(pipe2_sr_op__oe__oe),
- .\sr_op__oe__oe$8 (\pipe2_sr_op__oe__oe$33 ),
+ .\sr_op__oe__oe$8 (\pipe2_sr_op__oe__oe$34 ),
.sr_op__oe__ok(pipe2_sr_op__oe__ok),
- .\sr_op__oe__ok$9 (\pipe2_sr_op__oe__ok$34 ),
+ .\sr_op__oe__ok$9 (\pipe2_sr_op__oe__ok$35 ),
.sr_op__output_carry(pipe2_sr_op__output_carry),
- .\sr_op__output_carry$13 (\pipe2_sr_op__output_carry$38 ),
+ .\sr_op__output_carry$13 (\pipe2_sr_op__output_carry$39 ),
.sr_op__output_cr(pipe2_sr_op__output_cr),
- .\sr_op__output_cr$15 (\pipe2_sr_op__output_cr$40 ),
+ .\sr_op__output_cr$15 (\pipe2_sr_op__output_cr$41 ),
.sr_op__rc__ok(pipe2_sr_op__rc__ok),
- .\sr_op__rc__ok$7 (\pipe2_sr_op__rc__ok$32 ),
+ .\sr_op__rc__ok$7 (\pipe2_sr_op__rc__ok$33 ),
.sr_op__rc__rc(pipe2_sr_op__rc__rc),
- .\sr_op__rc__rc$6 (\pipe2_sr_op__rc__rc$31 ),
+ .\sr_op__rc__rc$6 (\pipe2_sr_op__rc__rc$32 ),
+ .sr_op__sv_ldstmode(pipe2_sr_op__sv_ldstmode),
+ .\sr_op__sv_ldstmode$22 (\pipe2_sr_op__sv_ldstmode$48 ),
.sr_op__sv_pred_dz(pipe2_sr_op__sv_pred_dz),
- .\sr_op__sv_pred_dz$20 (\pipe2_sr_op__sv_pred_dz$45 ),
+ .\sr_op__sv_pred_dz$20 (\pipe2_sr_op__sv_pred_dz$46 ),
.sr_op__sv_pred_sz(pipe2_sr_op__sv_pred_sz),
- .\sr_op__sv_pred_sz$19 (\pipe2_sr_op__sv_pred_sz$44 ),
+ .\sr_op__sv_pred_sz$19 (\pipe2_sr_op__sv_pred_sz$45 ),
.sr_op__sv_saturate(pipe2_sr_op__sv_saturate),
- .\sr_op__sv_saturate$21 (\pipe2_sr_op__sv_saturate$46 ),
+ .\sr_op__sv_saturate$21 (\pipe2_sr_op__sv_saturate$47 ),
.sr_op__write_cr0(pipe2_sr_op__write_cr0),
- .\sr_op__write_cr0$10 (\pipe2_sr_op__write_cr0$35 ),
+ .\sr_op__write_cr0$10 (\pipe2_sr_op__write_cr0$36 ),
.xer_ca(pipe2_xer_ca),
- .\xer_ca$27 (\pipe2_xer_ca$52 ),
+ .\xer_ca$28 (\pipe2_xer_ca$54 ),
.xer_ca_ok(pipe2_xer_ca_ok),
- .\xer_ca_ok$28 (\pipe2_xer_ca_ok$53 ),
+ .\xer_ca_ok$29 (\pipe2_xer_ca_ok$55 ),
.xer_so(pipe2_xer_so),
.xer_so_ok(pipe2_xer_so_ok)
);
assign muxid = 2'h0;
- assign { xer_ca_ok, xer_ca } = { \pipe2_xer_ca_ok$53 , \pipe2_xer_ca$52 };
- assign { cr_a_ok, cr_a } = { \pipe2_cr_a_ok$51 , \pipe2_cr_a$50 };
- assign { o_ok, o } = { \pipe2_o_ok$49 , \pipe2_o$48 };
- assign { \sr_op__SV_Ptype$75 , \sr_op__sv_saturate$74 , \sr_op__sv_pred_dz$73 , \sr_op__sv_pred_sz$72 , \sr_op__insn$71 , \sr_op__is_signed$70 , \sr_op__is_32bit$69 , \sr_op__output_cr$68 , \sr_op__input_cr$67 , \sr_op__output_carry$66 , \sr_op__input_carry$65 , \sr_op__invert_in$64 , \sr_op__write_cr0$63 , \sr_op__oe__ok$62 , \sr_op__oe__oe$61 , \sr_op__rc__ok$60 , \sr_op__rc__rc$59 , \sr_op__imm_data__ok$58 , \sr_op__imm_data__data$57 , \sr_op__fn_unit$56 , \sr_op__insn_type$55 } = { \pipe2_sr_op__SV_Ptype$47 , \pipe2_sr_op__sv_saturate$46 , \pipe2_sr_op__sv_pred_dz$45 , \pipe2_sr_op__sv_pred_sz$44 , \pipe2_sr_op__insn$43 , \pipe2_sr_op__is_signed$42 , \pipe2_sr_op__is_32bit$41 , \pipe2_sr_op__output_cr$40 , \pipe2_sr_op__input_cr$39 , \pipe2_sr_op__output_carry$38 , \pipe2_sr_op__input_carry$37 , \pipe2_sr_op__invert_in$36 , \pipe2_sr_op__write_cr0$35 , \pipe2_sr_op__oe__ok$34 , \pipe2_sr_op__oe__oe$33 , \pipe2_sr_op__rc__ok$32 , \pipe2_sr_op__rc__rc$31 , \pipe2_sr_op__imm_data__ok$30 , \pipe2_sr_op__imm_data__data$29 , \pipe2_sr_op__fn_unit$28 , \pipe2_sr_op__insn_type$27 };
- assign \muxid$54 = \pipe2_muxid$26 ;
+ assign { xer_ca_ok, xer_ca } = { \pipe2_xer_ca_ok$55 , \pipe2_xer_ca$54 };
+ assign { cr_a_ok, cr_a } = { \pipe2_cr_a_ok$53 , \pipe2_cr_a$52 };
+ assign { o_ok, o } = { \pipe2_o_ok$51 , \pipe2_o$50 };
+ assign { \sr_op__SV_Ptype$78 , \sr_op__sv_ldstmode$77 , \sr_op__sv_saturate$76 , \sr_op__sv_pred_dz$75 , \sr_op__sv_pred_sz$74 , \sr_op__insn$73 , \sr_op__is_signed$72 , \sr_op__is_32bit$71 , \sr_op__output_cr$70 , \sr_op__input_cr$69 , \sr_op__output_carry$68 , \sr_op__input_carry$67 , \sr_op__invert_in$66 , \sr_op__write_cr0$65 , \sr_op__oe__ok$64 , \sr_op__oe__oe$63 , \sr_op__rc__ok$62 , \sr_op__rc__rc$61 , \sr_op__imm_data__ok$60 , \sr_op__imm_data__data$59 , \sr_op__fn_unit$58 , \sr_op__insn_type$57 } = { \pipe2_sr_op__SV_Ptype$49 , \pipe2_sr_op__sv_ldstmode$48 , \pipe2_sr_op__sv_saturate$47 , \pipe2_sr_op__sv_pred_dz$46 , \pipe2_sr_op__sv_pred_sz$45 , \pipe2_sr_op__insn$44 , \pipe2_sr_op__is_signed$43 , \pipe2_sr_op__is_32bit$42 , \pipe2_sr_op__output_cr$41 , \pipe2_sr_op__input_cr$40 , \pipe2_sr_op__output_carry$39 , \pipe2_sr_op__input_carry$38 , \pipe2_sr_op__invert_in$37 , \pipe2_sr_op__write_cr0$36 , \pipe2_sr_op__oe__ok$35 , \pipe2_sr_op__oe__oe$34 , \pipe2_sr_op__rc__ok$33 , \pipe2_sr_op__rc__rc$32 , \pipe2_sr_op__imm_data__ok$31 , \pipe2_sr_op__imm_data__data$30 , \pipe2_sr_op__fn_unit$29 , \pipe2_sr_op__insn_type$28 };
+ assign \muxid$56 = \pipe2_muxid$27 ;
assign pipe2_n_ready_i = n_ready_i;
assign n_valid_o = pipe2_n_valid_o;
- assign \pipe1_xer_ca$25 = \xer_ca$1 ;
- assign \pipe1_xer_so$24 = xer_so;
+ assign \pipe1_xer_ca$26 = \xer_ca$1 ;
+ assign \pipe1_xer_so$25 = xer_so;
assign pipe1_rc = rc;
assign pipe1_rb = rb;
assign pipe1_ra = ra;
- assign { \pipe1_sr_op__SV_Ptype$23 , \pipe1_sr_op__sv_saturate$22 , \pipe1_sr_op__sv_pred_dz$21 , \pipe1_sr_op__sv_pred_sz$20 , \pipe1_sr_op__insn$19 , \pipe1_sr_op__is_signed$18 , \pipe1_sr_op__is_32bit$17 , \pipe1_sr_op__output_cr$16 , \pipe1_sr_op__input_cr$15 , \pipe1_sr_op__output_carry$14 , \pipe1_sr_op__input_carry$13 , \pipe1_sr_op__invert_in$12 , \pipe1_sr_op__write_cr0$11 , \pipe1_sr_op__oe__ok$10 , \pipe1_sr_op__oe__oe$9 , \pipe1_sr_op__rc__ok$8 , \pipe1_sr_op__rc__rc$7 , \pipe1_sr_op__imm_data__ok$6 , \pipe1_sr_op__imm_data__data$5 , \pipe1_sr_op__fn_unit$4 , \pipe1_sr_op__insn_type$3 } = { sr_op__SV_Ptype, sr_op__sv_saturate, sr_op__sv_pred_dz, sr_op__sv_pred_sz, sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type };
+ assign { \pipe1_sr_op__SV_Ptype$24 , \pipe1_sr_op__sv_ldstmode$23 , \pipe1_sr_op__sv_saturate$22 , \pipe1_sr_op__sv_pred_dz$21 , \pipe1_sr_op__sv_pred_sz$20 , \pipe1_sr_op__insn$19 , \pipe1_sr_op__is_signed$18 , \pipe1_sr_op__is_32bit$17 , \pipe1_sr_op__output_cr$16 , \pipe1_sr_op__input_cr$15 , \pipe1_sr_op__output_carry$14 , \pipe1_sr_op__input_carry$13 , \pipe1_sr_op__invert_in$12 , \pipe1_sr_op__write_cr0$11 , \pipe1_sr_op__oe__ok$10 , \pipe1_sr_op__oe__oe$9 , \pipe1_sr_op__rc__ok$8 , \pipe1_sr_op__rc__rc$7 , \pipe1_sr_op__imm_data__ok$6 , \pipe1_sr_op__imm_data__data$5 , \pipe1_sr_op__fn_unit$4 , \pipe1_sr_op__insn_type$3 } = { sr_op__SV_Ptype, sr_op__sv_ldstmode, sr_op__sv_saturate, sr_op__sv_pred_dz, sr_op__sv_pred_sz, sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type };
assign \pipe1_muxid$2 = 2'h0;
assign p_ready_o = pipe1_p_ready_o;
assign pipe1_p_valid_i = p_valid_i;
assign { pipe2_xer_so_ok, pipe2_xer_so } = { pipe1_xer_so_ok, pipe1_xer_so };
assign { pipe2_cr_a_ok, pipe2_cr_a } = { pipe1_cr_a_ok, pipe1_cr_a };
assign { pipe2_o_ok, pipe2_o } = { pipe1_o_ok, pipe1_o };
- assign { pipe2_sr_op__SV_Ptype, pipe2_sr_op__sv_saturate, pipe2_sr_op__sv_pred_dz, pipe2_sr_op__sv_pred_sz, pipe2_sr_op__insn, pipe2_sr_op__is_signed, pipe2_sr_op__is_32bit, pipe2_sr_op__output_cr, pipe2_sr_op__input_cr, pipe2_sr_op__output_carry, pipe2_sr_op__input_carry, pipe2_sr_op__invert_in, pipe2_sr_op__write_cr0, pipe2_sr_op__oe__ok, pipe2_sr_op__oe__oe, pipe2_sr_op__rc__ok, pipe2_sr_op__rc__rc, pipe2_sr_op__imm_data__ok, pipe2_sr_op__imm_data__data, pipe2_sr_op__fn_unit, pipe2_sr_op__insn_type } = { pipe1_sr_op__SV_Ptype, pipe1_sr_op__sv_saturate, pipe1_sr_op__sv_pred_dz, pipe1_sr_op__sv_pred_sz, pipe1_sr_op__insn, pipe1_sr_op__is_signed, pipe1_sr_op__is_32bit, pipe1_sr_op__output_cr, pipe1_sr_op__input_cr, pipe1_sr_op__output_carry, pipe1_sr_op__input_carry, pipe1_sr_op__invert_in, pipe1_sr_op__write_cr0, pipe1_sr_op__oe__ok, pipe1_sr_op__oe__oe, pipe1_sr_op__rc__ok, pipe1_sr_op__rc__rc, pipe1_sr_op__imm_data__ok, pipe1_sr_op__imm_data__data, pipe1_sr_op__fn_unit, pipe1_sr_op__insn_type };
+ assign { pipe2_sr_op__SV_Ptype, pipe2_sr_op__sv_ldstmode, pipe2_sr_op__sv_saturate, pipe2_sr_op__sv_pred_dz, pipe2_sr_op__sv_pred_sz, pipe2_sr_op__insn, pipe2_sr_op__is_signed, pipe2_sr_op__is_32bit, pipe2_sr_op__output_cr, pipe2_sr_op__input_cr, pipe2_sr_op__output_carry, pipe2_sr_op__input_carry, pipe2_sr_op__invert_in, pipe2_sr_op__write_cr0, pipe2_sr_op__oe__ok, pipe2_sr_op__oe__oe, pipe2_sr_op__rc__ok, pipe2_sr_op__rc__rc, pipe2_sr_op__imm_data__ok, pipe2_sr_op__imm_data__data, pipe2_sr_op__fn_unit, pipe2_sr_op__insn_type } = { pipe1_sr_op__SV_Ptype, pipe1_sr_op__sv_ldstmode, pipe1_sr_op__sv_saturate, pipe1_sr_op__sv_pred_dz, pipe1_sr_op__sv_pred_sz, pipe1_sr_op__insn, pipe1_sr_op__is_signed, pipe1_sr_op__is_32bit, pipe1_sr_op__output_cr, pipe1_sr_op__input_cr, pipe1_sr_op__output_carry, pipe1_sr_op__input_carry, pipe1_sr_op__invert_in, pipe1_sr_op__write_cr0, pipe1_sr_op__oe__ok, pipe1_sr_op__oe__oe, pipe1_sr_op__rc__ok, pipe1_sr_op__rc__rc, pipe1_sr_op__imm_data__ok, pipe1_sr_op__imm_data__data, pipe1_sr_op__fn_unit, pipe1_sr_op__insn_type };
assign pipe2_muxid = pipe1_muxid;
assign pipe1_n_ready_i = pipe2_p_ready_o;
assign pipe2_p_valid_i = pipe1_n_valid_o;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0.alu_spr0" *)
(* generator = "nMigen" *)
-module alu_spr0(coresync_rst, o_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, fast1_ok, spr1_ok, n_valid_o, n_ready_i, spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32bit, spr_op__sv_pred_sz, spr_op__sv_pred_dz, spr_op__sv_saturate, spr_op__SV_Ptype, o, spr1, fast1, xer_so, xer_ov, xer_ca, ra, \spr1$1 , \fast1$2 , \xer_so$3 , \xer_ov$4 , \xer_ca$5 , p_valid_i, p_ready_o, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+module alu_spr0(coresync_rst, o_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, fast1_ok, spr1_ok, n_valid_o, n_ready_i, spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32bit, spr_op__sv_pred_sz, spr_op__sv_pred_dz, spr_op__sv_saturate, spr_op__sv_ldstmode, spr_op__SV_Ptype, o, spr1, fast1, xer_so, xer_ov, xer_ca, ra, \spr1$1 , \fast1$2 , \xer_so$3 , \xer_ov$4 , \xer_ca$5 , p_valid_i, p_ready_o, coresync_clk);
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output [63:0] fast1;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \muxid$20 ;
+ wire [1:0] \muxid$21 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
input n_ready_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] pipe_fast1;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \pipe_fast1$16 ;
+ wire [63:0] \pipe_fast1$17 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe_fast1_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] pipe_spr1;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \pipe_spr1$15 ;
+ wire [63:0] \pipe_spr1$16 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe_spr1_ok;
(* enum_base_type = "SVPtype" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \pipe_spr_op__SV_Ptype$14 ;
+ wire [1:0] \pipe_spr_op__SV_Ptype$15 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
wire pipe_spr_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire \pipe_spr_op__is_32bit$10 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] pipe_spr_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \pipe_spr_op__sv_ldstmode$14 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe_spr_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [1:0] pipe_xer_ca;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [1:0] \pipe_xer_ca$19 ;
+ wire [1:0] \pipe_xer_ca$20 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe_xer_ca_ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [1:0] pipe_xer_ov;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [1:0] \pipe_xer_ov$18 ;
+ wire [1:0] \pipe_xer_ov$19 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe_xer_ov_ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire pipe_xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \pipe_xer_so$17 ;
+ wire \pipe_xer_so$18 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe_xer_so_ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \spr_op__SV_Ptype$28 ;
+ wire [1:0] \spr_op__SV_Ptype$30 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \spr_op__fn_unit$22 ;
+ wire [14:0] \spr_op__fn_unit$23 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] spr_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \spr_op__insn$23 ;
+ wire [31:0] \spr_op__insn$24 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \spr_op__insn_type$21 ;
+ wire [6:0] \spr_op__insn_type$22 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input spr_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \spr_op__is_32bit$24 ;
+ wire \spr_op__is_32bit$25 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] spr_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \spr_op__sv_ldstmode$29 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input spr_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \spr_op__sv_pred_dz$26 ;
+ wire \spr_op__sv_pred_dz$27 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input spr_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \spr_op__sv_pred_sz$25 ;
+ wire \spr_op__sv_pred_sz$26 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \spr_op__sv_saturate$27 ;
+ wire [1:0] \spr_op__sv_saturate$28 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output [1:0] xer_ca;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
.coresync_clk(coresync_clk),
.coresync_rst(coresync_rst),
.fast1(pipe_fast1),
- .\fast1$11 (\pipe_fast1$16 ),
+ .\fast1$12 (\pipe_fast1$17 ),
.fast1_ok(pipe_fast1_ok),
.muxid(pipe_muxid),
.\muxid$1 (\pipe_muxid$6 ),
.p_valid_i(pipe_p_valid_i),
.ra(pipe_ra),
.spr1(pipe_spr1),
- .\spr1$10 (\pipe_spr1$15 ),
+ .\spr1$11 (\pipe_spr1$16 ),
.spr1_ok(pipe_spr1_ok),
.spr_op__SV_Ptype(pipe_spr_op__SV_Ptype),
- .\spr_op__SV_Ptype$9 (\pipe_spr_op__SV_Ptype$14 ),
+ .\spr_op__SV_Ptype$10 (\pipe_spr_op__SV_Ptype$15 ),
.spr_op__fn_unit(pipe_spr_op__fn_unit),
.\spr_op__fn_unit$3 (\pipe_spr_op__fn_unit$8 ),
.spr_op__insn(pipe_spr_op__insn),
.\spr_op__insn_type$2 (\pipe_spr_op__insn_type$7 ),
.spr_op__is_32bit(pipe_spr_op__is_32bit),
.\spr_op__is_32bit$5 (\pipe_spr_op__is_32bit$10 ),
+ .spr_op__sv_ldstmode(pipe_spr_op__sv_ldstmode),
+ .\spr_op__sv_ldstmode$9 (\pipe_spr_op__sv_ldstmode$14 ),
.spr_op__sv_pred_dz(pipe_spr_op__sv_pred_dz),
.\spr_op__sv_pred_dz$7 (\pipe_spr_op__sv_pred_dz$12 ),
.spr_op__sv_pred_sz(pipe_spr_op__sv_pred_sz),
.spr_op__sv_saturate(pipe_spr_op__sv_saturate),
.\spr_op__sv_saturate$8 (\pipe_spr_op__sv_saturate$13 ),
.xer_ca(pipe_xer_ca),
- .\xer_ca$14 (\pipe_xer_ca$19 ),
+ .\xer_ca$15 (\pipe_xer_ca$20 ),
.xer_ca_ok(pipe_xer_ca_ok),
.xer_ov(pipe_xer_ov),
- .\xer_ov$13 (\pipe_xer_ov$18 ),
+ .\xer_ov$14 (\pipe_xer_ov$19 ),
.xer_ov_ok(pipe_xer_ov_ok),
.xer_so(pipe_xer_so),
- .\xer_so$12 (\pipe_xer_so$17 ),
+ .\xer_so$13 (\pipe_xer_so$18 ),
.xer_so_ok(pipe_xer_so_ok)
);
assign muxid = 2'h0;
- assign { xer_ca_ok, xer_ca } = { pipe_xer_ca_ok, \pipe_xer_ca$19 };
- assign { xer_ov_ok, xer_ov } = { pipe_xer_ov_ok, \pipe_xer_ov$18 };
- assign { xer_so_ok, xer_so } = { pipe_xer_so_ok, \pipe_xer_so$17 };
- assign { fast1_ok, fast1 } = { pipe_fast1_ok, \pipe_fast1$16 };
- assign { spr1_ok, spr1 } = { pipe_spr1_ok, \pipe_spr1$15 };
+ assign { xer_ca_ok, xer_ca } = { pipe_xer_ca_ok, \pipe_xer_ca$20 };
+ assign { xer_ov_ok, xer_ov } = { pipe_xer_ov_ok, \pipe_xer_ov$19 };
+ assign { xer_so_ok, xer_so } = { pipe_xer_so_ok, \pipe_xer_so$18 };
+ assign { fast1_ok, fast1 } = { pipe_fast1_ok, \pipe_fast1$17 };
+ assign { spr1_ok, spr1 } = { pipe_spr1_ok, \pipe_spr1$16 };
assign { o_ok, o } = { pipe_o_ok, pipe_o };
- assign { \spr_op__SV_Ptype$28 , \spr_op__sv_saturate$27 , \spr_op__sv_pred_dz$26 , \spr_op__sv_pred_sz$25 , \spr_op__is_32bit$24 , \spr_op__insn$23 , \spr_op__fn_unit$22 , \spr_op__insn_type$21 } = { \pipe_spr_op__SV_Ptype$14 , \pipe_spr_op__sv_saturate$13 , \pipe_spr_op__sv_pred_dz$12 , \pipe_spr_op__sv_pred_sz$11 , \pipe_spr_op__is_32bit$10 , \pipe_spr_op__insn$9 , \pipe_spr_op__fn_unit$8 , \pipe_spr_op__insn_type$7 };
- assign \muxid$20 = \pipe_muxid$6 ;
+ assign { \spr_op__SV_Ptype$30 , \spr_op__sv_ldstmode$29 , \spr_op__sv_saturate$28 , \spr_op__sv_pred_dz$27 , \spr_op__sv_pred_sz$26 , \spr_op__is_32bit$25 , \spr_op__insn$24 , \spr_op__fn_unit$23 , \spr_op__insn_type$22 } = { \pipe_spr_op__SV_Ptype$15 , \pipe_spr_op__sv_ldstmode$14 , \pipe_spr_op__sv_saturate$13 , \pipe_spr_op__sv_pred_dz$12 , \pipe_spr_op__sv_pred_sz$11 , \pipe_spr_op__is_32bit$10 , \pipe_spr_op__insn$9 , \pipe_spr_op__fn_unit$8 , \pipe_spr_op__insn_type$7 };
+ assign \muxid$21 = \pipe_muxid$6 ;
assign pipe_n_ready_i = n_ready_i;
assign n_valid_o = pipe_n_valid_o;
assign pipe_xer_ca = \xer_ca$5 ;
assign pipe_fast1 = \fast1$2 ;
assign pipe_spr1 = \spr1$1 ;
assign pipe_ra = ra;
- assign { pipe_spr_op__SV_Ptype, pipe_spr_op__sv_saturate, pipe_spr_op__sv_pred_dz, pipe_spr_op__sv_pred_sz, pipe_spr_op__is_32bit, pipe_spr_op__insn, pipe_spr_op__fn_unit, pipe_spr_op__insn_type } = { spr_op__SV_Ptype, spr_op__sv_saturate, spr_op__sv_pred_dz, spr_op__sv_pred_sz, spr_op__is_32bit, spr_op__insn, spr_op__fn_unit, spr_op__insn_type };
+ assign { pipe_spr_op__SV_Ptype, pipe_spr_op__sv_ldstmode, pipe_spr_op__sv_saturate, pipe_spr_op__sv_pred_dz, pipe_spr_op__sv_pred_sz, pipe_spr_op__is_32bit, pipe_spr_op__insn, pipe_spr_op__fn_unit, pipe_spr_op__insn_type } = { spr_op__SV_Ptype, spr_op__sv_ldstmode, spr_op__sv_saturate, spr_op__sv_pred_dz, spr_op__sv_pred_sz, spr_op__is_32bit, spr_op__insn, spr_op__fn_unit, spr_op__insn_type };
assign pipe_muxid = 2'h0;
assign p_ready_o = pipe_p_ready_o;
assign pipe_p_valid_i = p_valid_i;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_trap0" *)
(* generator = "nMigen" *)
-module alu_trap0(coresync_rst, o_ok, fast1_ok, fast2_ok, fast3_ok, nia_ok, msr_ok, svstate_ok, n_valid_o, n_ready_i, trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__svstate, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, trap_op__sv_pred_sz, trap_op__sv_pred_dz, trap_op__sv_saturate, trap_op__SV_Ptype, o, fast1, fast2, fast3, nia, msr, svstate, ra, rb, \fast1$1 , \fast2$2 , \fast3$3 , p_valid_i, p_ready_o, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+module alu_trap0(coresync_rst, o_ok, fast1_ok, fast2_ok, fast3_ok, nia_ok, msr_ok, svstate_ok, n_valid_o, n_ready_i, trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__svstate, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, trap_op__sv_pred_sz, trap_op__sv_pred_dz, trap_op__sv_saturate, trap_op__sv_ldstmode, trap_op__SV_Ptype, o, fast1, fast2, fast3, nia, msr, svstate, ra, rb, \fast1$1 , \fast2$2 , \fast3$3 , p_valid_i, p_ready_o, coresync_clk);
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output [63:0] fast1;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \muxid$42 ;
+ wire [1:0] \muxid$44 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
input n_ready_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] pipe1_fast1;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \pipe1_fast1$21 ;
+ wire [63:0] \pipe1_fast1$22 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] pipe1_fast2;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \pipe1_fast2$22 ;
+ wire [63:0] \pipe1_fast2$23 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] pipe1_fast3;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \pipe1_fast3$23 ;
+ wire [63:0] \pipe1_fast3$24 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] pipe1_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] pipe1_ra;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \pipe1_ra$19 ;
+ wire [63:0] \pipe1_ra$20 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] pipe1_rb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \pipe1_rb$20 ;
+ wire [63:0] \pipe1_rb$21 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \pipe1_trap_op__SV_Ptype$18 ;
+ wire [1:0] \pipe1_trap_op__SV_Ptype$19 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] pipe1_trap_op__cia;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] pipe1_trap_op__msr;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] \pipe1_trap_op__msr$8 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] pipe1_trap_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \pipe1_trap_op__sv_ldstmode$18 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe1_trap_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] pipe2_fast1;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \pipe2_fast1$39 ;
+ wire [63:0] \pipe2_fast1$41 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe2_fast1_ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] pipe2_fast2;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \pipe2_fast2$40 ;
+ wire [63:0] \pipe2_fast2$42 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe2_fast2_ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] pipe2_fast3;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \pipe2_fast3$41 ;
+ wire [63:0] \pipe2_fast3$43 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire pipe2_fast3_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] pipe2_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \pipe2_muxid$24 ;
+ wire [1:0] \pipe2_muxid$25 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
wire pipe2_n_ready_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \pipe2_trap_op__SV_Ptype$38 ;
+ wire [1:0] \pipe2_trap_op__SV_Ptype$40 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] pipe2_trap_op__cia;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \pipe2_trap_op__cia$29 ;
+ wire [63:0] \pipe2_trap_op__cia$30 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \pipe2_trap_op__fn_unit$26 ;
+ wire [14:0] \pipe2_trap_op__fn_unit$27 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] pipe2_trap_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \pipe2_trap_op__insn$27 ;
+ wire [31:0] \pipe2_trap_op__insn$28 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \pipe2_trap_op__insn_type$25 ;
+ wire [6:0] \pipe2_trap_op__insn_type$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_trap_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_trap_op__is_32bit$31 ;
+ wire \pipe2_trap_op__is_32bit$32 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [7:0] pipe2_trap_op__ldst_exc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [7:0] \pipe2_trap_op__ldst_exc$34 ;
+ wire [7:0] \pipe2_trap_op__ldst_exc$35 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] pipe2_trap_op__msr;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \pipe2_trap_op__msr$28 ;
+ wire [63:0] \pipe2_trap_op__msr$29 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] pipe2_trap_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \pipe2_trap_op__sv_ldstmode$39 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_trap_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_trap_op__sv_pred_dz$36 ;
+ wire \pipe2_trap_op__sv_pred_dz$37 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire pipe2_trap_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \pipe2_trap_op__sv_pred_sz$35 ;
+ wire \pipe2_trap_op__sv_pred_sz$36 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \pipe2_trap_op__sv_saturate$37 ;
+ wire [1:0] \pipe2_trap_op__sv_saturate$38 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] pipe2_trap_op__svstate;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \pipe2_trap_op__svstate$30 ;
+ wire [31:0] \pipe2_trap_op__svstate$31 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [12:0] pipe2_trap_op__trapaddr;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [12:0] \pipe2_trap_op__trapaddr$33 ;
+ wire [12:0] \pipe2_trap_op__trapaddr$34 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [7:0] pipe2_trap_op__traptype;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [7:0] \pipe2_trap_op__traptype$32 ;
+ wire [7:0] \pipe2_trap_op__traptype$33 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] ra;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \trap_op__SV_Ptype$56 ;
+ wire [1:0] \trap_op__SV_Ptype$59 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] trap_op__cia;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \trap_op__cia$47 ;
+ wire [63:0] \trap_op__cia$49 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \trap_op__fn_unit$44 ;
+ wire [14:0] \trap_op__fn_unit$46 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] trap_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \trap_op__insn$45 ;
+ wire [31:0] \trap_op__insn$47 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \trap_op__insn_type$43 ;
+ wire [6:0] \trap_op__insn_type$45 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input trap_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \trap_op__is_32bit$49 ;
+ wire \trap_op__is_32bit$51 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [7:0] trap_op__ldst_exc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [7:0] \trap_op__ldst_exc$52 ;
+ wire [7:0] \trap_op__ldst_exc$54 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] trap_op__msr;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \trap_op__msr$46 ;
+ wire [63:0] \trap_op__msr$48 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] trap_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \trap_op__sv_ldstmode$58 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input trap_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \trap_op__sv_pred_dz$54 ;
+ wire \trap_op__sv_pred_dz$56 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input trap_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \trap_op__sv_pred_sz$53 ;
+ wire \trap_op__sv_pred_sz$55 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \trap_op__sv_saturate$55 ;
+ wire [1:0] \trap_op__sv_saturate$57 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] trap_op__svstate;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \trap_op__svstate$48 ;
+ wire [31:0] \trap_op__svstate$50 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [12:0] trap_op__trapaddr;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [12:0] \trap_op__trapaddr$51 ;
+ wire [12:0] \trap_op__trapaddr$53 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [7:0] trap_op__traptype;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [7:0] \trap_op__traptype$50 ;
+ wire [7:0] \trap_op__traptype$52 ;
\n$31 n (
.n_ready_i(n_ready_i),
.n_valid_o(n_valid_o)
.coresync_clk(coresync_clk),
.coresync_rst(coresync_rst),
.fast1(pipe1_fast1),
- .\fast1$18 (\pipe1_fast1$21 ),
+ .\fast1$19 (\pipe1_fast1$22 ),
.fast2(pipe1_fast2),
- .\fast2$19 (\pipe1_fast2$22 ),
+ .\fast2$20 (\pipe1_fast2$23 ),
.fast3(pipe1_fast3),
- .\fast3$20 (\pipe1_fast3$23 ),
+ .\fast3$21 (\pipe1_fast3$24 ),
.muxid(pipe1_muxid),
.\muxid$1 (\pipe1_muxid$4 ),
.n_ready_i(pipe1_n_ready_i),
.p_ready_o(pipe1_p_ready_o),
.p_valid_i(pipe1_p_valid_i),
.ra(pipe1_ra),
- .\ra$16 (\pipe1_ra$19 ),
+ .\ra$17 (\pipe1_ra$20 ),
.rb(pipe1_rb),
- .\rb$17 (\pipe1_rb$20 ),
+ .\rb$18 (\pipe1_rb$21 ),
.trap_op__SV_Ptype(pipe1_trap_op__SV_Ptype),
- .\trap_op__SV_Ptype$15 (\pipe1_trap_op__SV_Ptype$18 ),
+ .\trap_op__SV_Ptype$16 (\pipe1_trap_op__SV_Ptype$19 ),
.trap_op__cia(pipe1_trap_op__cia),
.\trap_op__cia$6 (\pipe1_trap_op__cia$9 ),
.trap_op__fn_unit(pipe1_trap_op__fn_unit),
.\trap_op__ldst_exc$11 (\pipe1_trap_op__ldst_exc$14 ),
.trap_op__msr(pipe1_trap_op__msr),
.\trap_op__msr$5 (\pipe1_trap_op__msr$8 ),
+ .trap_op__sv_ldstmode(pipe1_trap_op__sv_ldstmode),
+ .\trap_op__sv_ldstmode$15 (\pipe1_trap_op__sv_ldstmode$18 ),
.trap_op__sv_pred_dz(pipe1_trap_op__sv_pred_dz),
.\trap_op__sv_pred_dz$13 (\pipe1_trap_op__sv_pred_dz$16 ),
.trap_op__sv_pred_sz(pipe1_trap_op__sv_pred_sz),
.coresync_clk(coresync_clk),
.coresync_rst(coresync_rst),
.fast1(pipe2_fast1),
- .\fast1$16 (\pipe2_fast1$39 ),
+ .\fast1$17 (\pipe2_fast1$41 ),
.fast1_ok(pipe2_fast1_ok),
.fast2(pipe2_fast2),
- .\fast2$17 (\pipe2_fast2$40 ),
+ .\fast2$18 (\pipe2_fast2$42 ),
.fast2_ok(pipe2_fast2_ok),
.fast3(pipe2_fast3),
- .\fast3$18 (\pipe2_fast3$41 ),
+ .\fast3$19 (\pipe2_fast3$43 ),
.fast3_ok(pipe2_fast3_ok),
.msr(pipe2_msr),
.msr_ok(pipe2_msr_ok),
.muxid(pipe2_muxid),
- .\muxid$1 (\pipe2_muxid$24 ),
+ .\muxid$1 (\pipe2_muxid$25 ),
.n_ready_i(pipe2_n_ready_i),
.n_valid_o(pipe2_n_valid_o),
.nia(pipe2_nia),
.svstate(pipe2_svstate),
.svstate_ok(pipe2_svstate_ok),
.trap_op__SV_Ptype(pipe2_trap_op__SV_Ptype),
- .\trap_op__SV_Ptype$15 (\pipe2_trap_op__SV_Ptype$38 ),
+ .\trap_op__SV_Ptype$16 (\pipe2_trap_op__SV_Ptype$40 ),
.trap_op__cia(pipe2_trap_op__cia),
- .\trap_op__cia$6 (\pipe2_trap_op__cia$29 ),
+ .\trap_op__cia$6 (\pipe2_trap_op__cia$30 ),
.trap_op__fn_unit(pipe2_trap_op__fn_unit),
- .\trap_op__fn_unit$3 (\pipe2_trap_op__fn_unit$26 ),
+ .\trap_op__fn_unit$3 (\pipe2_trap_op__fn_unit$27 ),
.trap_op__insn(pipe2_trap_op__insn),
- .\trap_op__insn$4 (\pipe2_trap_op__insn$27 ),
+ .\trap_op__insn$4 (\pipe2_trap_op__insn$28 ),
.trap_op__insn_type(pipe2_trap_op__insn_type),
- .\trap_op__insn_type$2 (\pipe2_trap_op__insn_type$25 ),
+ .\trap_op__insn_type$2 (\pipe2_trap_op__insn_type$26 ),
.trap_op__is_32bit(pipe2_trap_op__is_32bit),
- .\trap_op__is_32bit$8 (\pipe2_trap_op__is_32bit$31 ),
+ .\trap_op__is_32bit$8 (\pipe2_trap_op__is_32bit$32 ),
.trap_op__ldst_exc(pipe2_trap_op__ldst_exc),
- .\trap_op__ldst_exc$11 (\pipe2_trap_op__ldst_exc$34 ),
+ .\trap_op__ldst_exc$11 (\pipe2_trap_op__ldst_exc$35 ),
.trap_op__msr(pipe2_trap_op__msr),
- .\trap_op__msr$5 (\pipe2_trap_op__msr$28 ),
+ .\trap_op__msr$5 (\pipe2_trap_op__msr$29 ),
+ .trap_op__sv_ldstmode(pipe2_trap_op__sv_ldstmode),
+ .\trap_op__sv_ldstmode$15 (\pipe2_trap_op__sv_ldstmode$39 ),
.trap_op__sv_pred_dz(pipe2_trap_op__sv_pred_dz),
- .\trap_op__sv_pred_dz$13 (\pipe2_trap_op__sv_pred_dz$36 ),
+ .\trap_op__sv_pred_dz$13 (\pipe2_trap_op__sv_pred_dz$37 ),
.trap_op__sv_pred_sz(pipe2_trap_op__sv_pred_sz),
- .\trap_op__sv_pred_sz$12 (\pipe2_trap_op__sv_pred_sz$35 ),
+ .\trap_op__sv_pred_sz$12 (\pipe2_trap_op__sv_pred_sz$36 ),
.trap_op__sv_saturate(pipe2_trap_op__sv_saturate),
- .\trap_op__sv_saturate$14 (\pipe2_trap_op__sv_saturate$37 ),
+ .\trap_op__sv_saturate$14 (\pipe2_trap_op__sv_saturate$38 ),
.trap_op__svstate(pipe2_trap_op__svstate),
- .\trap_op__svstate$7 (\pipe2_trap_op__svstate$30 ),
+ .\trap_op__svstate$7 (\pipe2_trap_op__svstate$31 ),
.trap_op__trapaddr(pipe2_trap_op__trapaddr),
- .\trap_op__trapaddr$10 (\pipe2_trap_op__trapaddr$33 ),
+ .\trap_op__trapaddr$10 (\pipe2_trap_op__trapaddr$34 ),
.trap_op__traptype(pipe2_trap_op__traptype),
- .\trap_op__traptype$9 (\pipe2_trap_op__traptype$32 )
+ .\trap_op__traptype$9 (\pipe2_trap_op__traptype$33 )
);
assign muxid = 2'h0;
assign { svstate_ok, svstate } = { pipe2_svstate_ok, pipe2_svstate };
assign { msr_ok, msr } = { pipe2_msr_ok, pipe2_msr };
assign { nia_ok, nia } = { pipe2_nia_ok, pipe2_nia };
- assign { fast3_ok, fast3 } = { pipe2_fast3_ok, \pipe2_fast3$41 };
- assign { fast2_ok, fast2 } = { pipe2_fast2_ok, \pipe2_fast2$40 };
- assign { fast1_ok, fast1 } = { pipe2_fast1_ok, \pipe2_fast1$39 };
+ assign { fast3_ok, fast3 } = { pipe2_fast3_ok, \pipe2_fast3$43 };
+ assign { fast2_ok, fast2 } = { pipe2_fast2_ok, \pipe2_fast2$42 };
+ assign { fast1_ok, fast1 } = { pipe2_fast1_ok, \pipe2_fast1$41 };
assign { o_ok, o } = { pipe2_o_ok, pipe2_o };
- assign { \trap_op__SV_Ptype$56 , \trap_op__sv_saturate$55 , \trap_op__sv_pred_dz$54 , \trap_op__sv_pred_sz$53 , \trap_op__ldst_exc$52 , \trap_op__trapaddr$51 , \trap_op__traptype$50 , \trap_op__is_32bit$49 , \trap_op__svstate$48 , \trap_op__cia$47 , \trap_op__msr$46 , \trap_op__insn$45 , \trap_op__fn_unit$44 , \trap_op__insn_type$43 } = { \pipe2_trap_op__SV_Ptype$38 , \pipe2_trap_op__sv_saturate$37 , \pipe2_trap_op__sv_pred_dz$36 , \pipe2_trap_op__sv_pred_sz$35 , \pipe2_trap_op__ldst_exc$34 , \pipe2_trap_op__trapaddr$33 , \pipe2_trap_op__traptype$32 , \pipe2_trap_op__is_32bit$31 , \pipe2_trap_op__svstate$30 , \pipe2_trap_op__cia$29 , \pipe2_trap_op__msr$28 , \pipe2_trap_op__insn$27 , \pipe2_trap_op__fn_unit$26 , \pipe2_trap_op__insn_type$25 };
- assign \muxid$42 = \pipe2_muxid$24 ;
+ assign { \trap_op__SV_Ptype$59 , \trap_op__sv_ldstmode$58 , \trap_op__sv_saturate$57 , \trap_op__sv_pred_dz$56 , \trap_op__sv_pred_sz$55 , \trap_op__ldst_exc$54 , \trap_op__trapaddr$53 , \trap_op__traptype$52 , \trap_op__is_32bit$51 , \trap_op__svstate$50 , \trap_op__cia$49 , \trap_op__msr$48 , \trap_op__insn$47 , \trap_op__fn_unit$46 , \trap_op__insn_type$45 } = { \pipe2_trap_op__SV_Ptype$40 , \pipe2_trap_op__sv_ldstmode$39 , \pipe2_trap_op__sv_saturate$38 , \pipe2_trap_op__sv_pred_dz$37 , \pipe2_trap_op__sv_pred_sz$36 , \pipe2_trap_op__ldst_exc$35 , \pipe2_trap_op__trapaddr$34 , \pipe2_trap_op__traptype$33 , \pipe2_trap_op__is_32bit$32 , \pipe2_trap_op__svstate$31 , \pipe2_trap_op__cia$30 , \pipe2_trap_op__msr$29 , \pipe2_trap_op__insn$28 , \pipe2_trap_op__fn_unit$27 , \pipe2_trap_op__insn_type$26 };
+ assign \muxid$44 = \pipe2_muxid$25 ;
assign pipe2_n_ready_i = n_ready_i;
assign n_valid_o = pipe2_n_valid_o;
- assign \pipe1_fast3$23 = \fast3$3 ;
- assign \pipe1_fast2$22 = \fast2$2 ;
- assign \pipe1_fast1$21 = \fast1$1 ;
- assign \pipe1_rb$20 = rb;
- assign \pipe1_ra$19 = ra;
- assign { \pipe1_trap_op__SV_Ptype$18 , \pipe1_trap_op__sv_saturate$17 , \pipe1_trap_op__sv_pred_dz$16 , \pipe1_trap_op__sv_pred_sz$15 , \pipe1_trap_op__ldst_exc$14 , \pipe1_trap_op__trapaddr$13 , \pipe1_trap_op__traptype$12 , \pipe1_trap_op__is_32bit$11 , \pipe1_trap_op__svstate$10 , \pipe1_trap_op__cia$9 , \pipe1_trap_op__msr$8 , \pipe1_trap_op__insn$7 , \pipe1_trap_op__fn_unit$6 , \pipe1_trap_op__insn_type$5 } = { trap_op__SV_Ptype, trap_op__sv_saturate, trap_op__sv_pred_dz, trap_op__sv_pred_sz, trap_op__ldst_exc, trap_op__trapaddr, trap_op__traptype, trap_op__is_32bit, trap_op__svstate, trap_op__cia, trap_op__msr, trap_op__insn, trap_op__fn_unit, trap_op__insn_type };
+ assign \pipe1_fast3$24 = \fast3$3 ;
+ assign \pipe1_fast2$23 = \fast2$2 ;
+ assign \pipe1_fast1$22 = \fast1$1 ;
+ assign \pipe1_rb$21 = rb;
+ assign \pipe1_ra$20 = ra;
+ assign { \pipe1_trap_op__SV_Ptype$19 , \pipe1_trap_op__sv_ldstmode$18 , \pipe1_trap_op__sv_saturate$17 , \pipe1_trap_op__sv_pred_dz$16 , \pipe1_trap_op__sv_pred_sz$15 , \pipe1_trap_op__ldst_exc$14 , \pipe1_trap_op__trapaddr$13 , \pipe1_trap_op__traptype$12 , \pipe1_trap_op__is_32bit$11 , \pipe1_trap_op__svstate$10 , \pipe1_trap_op__cia$9 , \pipe1_trap_op__msr$8 , \pipe1_trap_op__insn$7 , \pipe1_trap_op__fn_unit$6 , \pipe1_trap_op__insn_type$5 } = { trap_op__SV_Ptype, trap_op__sv_ldstmode, trap_op__sv_saturate, trap_op__sv_pred_dz, trap_op__sv_pred_sz, trap_op__ldst_exc, trap_op__trapaddr, trap_op__traptype, trap_op__is_32bit, trap_op__svstate, trap_op__cia, trap_op__msr, trap_op__insn, trap_op__fn_unit, trap_op__insn_type };
assign \pipe1_muxid$4 = 2'h0;
assign p_ready_o = pipe1_p_ready_o;
assign pipe1_p_valid_i = p_valid_i;
assign pipe2_fast1 = pipe1_fast1;
assign pipe2_rb = pipe1_rb;
assign pipe2_ra = pipe1_ra;
- assign { pipe2_trap_op__SV_Ptype, pipe2_trap_op__sv_saturate, pipe2_trap_op__sv_pred_dz, pipe2_trap_op__sv_pred_sz, pipe2_trap_op__ldst_exc, pipe2_trap_op__trapaddr, pipe2_trap_op__traptype, pipe2_trap_op__is_32bit, pipe2_trap_op__svstate, pipe2_trap_op__cia, pipe2_trap_op__msr, pipe2_trap_op__insn, pipe2_trap_op__fn_unit, pipe2_trap_op__insn_type } = { pipe1_trap_op__SV_Ptype, pipe1_trap_op__sv_saturate, pipe1_trap_op__sv_pred_dz, pipe1_trap_op__sv_pred_sz, pipe1_trap_op__ldst_exc, pipe1_trap_op__trapaddr, pipe1_trap_op__traptype, pipe1_trap_op__is_32bit, pipe1_trap_op__svstate, pipe1_trap_op__cia, pipe1_trap_op__msr, pipe1_trap_op__insn, pipe1_trap_op__fn_unit, pipe1_trap_op__insn_type };
+ assign { pipe2_trap_op__SV_Ptype, pipe2_trap_op__sv_ldstmode, pipe2_trap_op__sv_saturate, pipe2_trap_op__sv_pred_dz, pipe2_trap_op__sv_pred_sz, pipe2_trap_op__ldst_exc, pipe2_trap_op__trapaddr, pipe2_trap_op__traptype, pipe2_trap_op__is_32bit, pipe2_trap_op__svstate, pipe2_trap_op__cia, pipe2_trap_op__msr, pipe2_trap_op__insn, pipe2_trap_op__fn_unit, pipe2_trap_op__insn_type } = { pipe1_trap_op__SV_Ptype, pipe1_trap_op__sv_ldstmode, pipe1_trap_op__sv_saturate, pipe1_trap_op__sv_pred_dz, pipe1_trap_op__sv_pred_sz, pipe1_trap_op__ldst_exc, pipe1_trap_op__trapaddr, pipe1_trap_op__traptype, pipe1_trap_op__is_32bit, pipe1_trap_op__svstate, pipe1_trap_op__cia, pipe1_trap_op__msr, pipe1_trap_op__insn, pipe1_trap_op__fn_unit, pipe1_trap_op__insn_type };
assign pipe2_muxid = pipe1_muxid;
assign pipe1_n_ready_i = pipe2_p_ready_o;
assign pipe2_p_valid_i = pipe1_n_valid_o;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.branch0" *)
(* generator = "nMigen" *)
-module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__lk, oper_i_alu_branch0__is_32bit, oper_i_alu_branch0__sv_pred_sz, oper_i_alu_branch0__sv_pred_dz, oper_i_alu_branch0__sv_saturate, oper_i_alu_branch0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src3_i, src1_i, src2_i, fast1_ok, cu_wr__rel_o, cu_wr__go_i, fast2_ok, dest1_o, dest2_o, nia_ok, dest3_o, coresync_clk);
+module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__lk, oper_i_alu_branch0__is_32bit, oper_i_alu_branch0__sv_pred_sz, oper_i_alu_branch0__sv_pred_dz, oper_i_alu_branch0__sv_saturate, oper_i_alu_branch0__sv_ldstmode, oper_i_alu_branch0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src3_i, src1_i, src2_i, fast1_ok, cu_wr__rel_o, cu_wr__go_i, fast2_ok, dest1_o, dest2_o, nia_ok, dest3_o, coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
wire \$101 ;
reg alu_branch0_br_op__lk = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_branch0_br_op__lk$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] alu_branch0_br_op__sv_ldstmode = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \alu_branch0_br_op__sv_ldstmode$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg alu_branch0_br_op__sv_pred_dz = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
output cu_busy_o;
input oper_i_alu_branch0__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_branch0__lk;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] oper_i_alu_branch0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_branch0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
alu_branch0_br_op__sv_pred_dz <= \alu_branch0_br_op__sv_pred_dz$next ;
always @(posedge coresync_clk)
alu_branch0_br_op__sv_saturate <= \alu_branch0_br_op__sv_saturate$next ;
+ always @(posedge coresync_clk)
+ alu_branch0_br_op__sv_ldstmode <= \alu_branch0_br_op__sv_ldstmode$next ;
always @(posedge coresync_clk)
alu_branch0_br_op__SV_Ptype <= \alu_branch0_br_op__SV_Ptype$next ;
always @(posedge coresync_clk)
.br_op__insn_type(alu_branch0_br_op__insn_type),
.br_op__is_32bit(alu_branch0_br_op__is_32bit),
.br_op__lk(alu_branch0_br_op__lk),
+ .br_op__sv_ldstmode(alu_branch0_br_op__sv_ldstmode),
.br_op__sv_pred_dz(alu_branch0_br_op__sv_pred_dz),
.br_op__sv_pred_sz(alu_branch0_br_op__sv_pred_sz),
.br_op__sv_saturate(alu_branch0_br_op__sv_saturate),
\alu_branch0_br_op__sv_pred_sz$next = alu_branch0_br_op__sv_pred_sz;
\alu_branch0_br_op__sv_pred_dz$next = alu_branch0_br_op__sv_pred_dz;
\alu_branch0_br_op__sv_saturate$next = alu_branch0_br_op__sv_saturate;
+ \alu_branch0_br_op__sv_ldstmode$next = alu_branch0_br_op__sv_ldstmode;
\alu_branch0_br_op__SV_Ptype$next = alu_branch0_br_op__SV_Ptype;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *)
casez (cu_issue_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */
1'h1:
- { \alu_branch0_br_op__SV_Ptype$next , \alu_branch0_br_op__sv_saturate$next , \alu_branch0_br_op__sv_pred_dz$next , \alu_branch0_br_op__sv_pred_sz$next , \alu_branch0_br_op__is_32bit$next , \alu_branch0_br_op__lk$next , \alu_branch0_br_op__imm_data__ok$next , \alu_branch0_br_op__imm_data__data$next , \alu_branch0_br_op__insn$next , \alu_branch0_br_op__fn_unit$next , \alu_branch0_br_op__insn_type$next , \alu_branch0_br_op__cia$next } = { oper_i_alu_branch0__SV_Ptype, oper_i_alu_branch0__sv_saturate, oper_i_alu_branch0__sv_pred_dz, oper_i_alu_branch0__sv_pred_sz, oper_i_alu_branch0__is_32bit, oper_i_alu_branch0__lk, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__insn, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__cia };
+ { \alu_branch0_br_op__SV_Ptype$next , \alu_branch0_br_op__sv_ldstmode$next , \alu_branch0_br_op__sv_saturate$next , \alu_branch0_br_op__sv_pred_dz$next , \alu_branch0_br_op__sv_pred_sz$next , \alu_branch0_br_op__is_32bit$next , \alu_branch0_br_op__lk$next , \alu_branch0_br_op__imm_data__ok$next , \alu_branch0_br_op__imm_data__data$next , \alu_branch0_br_op__insn$next , \alu_branch0_br_op__fn_unit$next , \alu_branch0_br_op__insn_type$next , \alu_branch0_br_op__cia$next } = { oper_i_alu_branch0__SV_Ptype, oper_i_alu_branch0__sv_ldstmode, oper_i_alu_branch0__sv_saturate, oper_i_alu_branch0__sv_pred_dz, oper_i_alu_branch0__sv_pred_sz, oper_i_alu_branch0__is_32bit, oper_i_alu_branch0__lk, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__insn, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__cia };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_busy;
(* \nmigen.hierarchy = "test_issuer.ti.core" *)
(* generator = "nMigen" *)
-module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data_i, msr__ren, core_terminate_o, msr__data_o, exc_o_happened, core_rego, core_ea, core_reg1, core_reg1_ok, core_reg2, core_reg2_ok, core_reg3, core_reg3_ok, core_spro, core_spr1, core_spr1_ok, core_xer_in, core_fast1, core_fast1_ok, core_fast2, core_fast2_ok, core_fast3, core_fast3_ok, core_fasto1, core_fasto2, core_fasto3, core_cr_in1, core_cr_in1_ok, core_cr_in2, core_cr_in2_ok, \core_cr_in2$1 , \core_cr_in2_ok$2 , core_cr_out, core_core__sv_pred_sz, core_core__sv_pred_dz, core_core__sv_saturate, core_core__SV_Ptype, core_core_msr, core_core_cia, core_core_svstate, core_core_insn, core_core_insn_type, core_core_fn_unit, core_core_rc, core_core_rc_ok, core_core_oe, core_core_oe_ok, core_core_input_carry, core_core_traptype, core_core_exc_alignment, core_core_exc_instr_fault, core_core_exc_invalid, core_core_exc_badtree, core_core_exc_perm_error, core_core_exc_rc_error, core_core_exc_segment_fault, core_core_exc_happened, core_core_trapaddr, core_core_cr_rd, core_core_cr_rd_ok, core_core_cr_wr, core_core_is_32bit, core_pc, core_msr, raw_insn_i, bigendian_i, \wen$3 , \data_i$4 , ivalid_i, issue_i, state_nia_wen, dmi__addr, dmi__ren, dmi__data_o, full_rd2__ren, full_rd2__data_o, full_rd__ren, full_rd__data_o, issue__addr, issue__ren, issue__data_o, \issue__addr$5 , issue__wen, issue__data_i, wb_dcache_en, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, coresync_clk);
+module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data_i, msr__ren, core_terminate_o, msr__data_o, exc_o_happened, core_rego, core_ea, core_reg1, core_reg1_ok, core_reg2, core_reg2_ok, core_reg3, core_reg3_ok, core_spro, core_spr1, core_spr1_ok, core_xer_in, core_fast1, core_fast1_ok, core_fast2, core_fast2_ok, core_fast3, core_fast3_ok, core_fasto1, core_fasto2, core_fasto3, core_cr_in1, core_cr_in1_ok, core_cr_in2, core_cr_in2_ok, \core_cr_in2$1 , \core_cr_in2_ok$2 , core_cr_out, core_core__sv_pred_sz, core_core__sv_pred_dz, core_core__sv_saturate, core_core__sv_ldstmode, core_core__SV_Ptype, core_core_msr, core_core_cia, core_core_svstate, core_core_insn, core_core_insn_type, core_core_fn_unit, core_core_rc, core_core_rc_ok, core_core_oe, core_core_oe_ok, core_core_input_carry, core_core_traptype, core_core_exc_alignment, core_core_exc_instr_fault, core_core_exc_invalid, core_core_exc_badtree, core_core_exc_perm_error, core_core_exc_rc_error, core_core_exc_segment_fault, core_core_exc_happened, core_core_trapaddr, core_core_cr_rd, core_core_cr_rd_ok, core_core_cr_wr, core_core_is_32bit, core_pc, core_msr, raw_insn_i, bigendian_i, \wen$3 , \data_i$4 , ivalid_i, issue_i, state_nia_wen, dmi__addr, dmi__ren, dmi__data_o, full_rd2__ren, full_rd2__data_o, full_rd__ren, full_rd__data_o, issue__addr, issue__ren, issue__data_o, \issue__addr$5 , issue__wen, issue__data_i, wb_dcache_en, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *)
wire \$1004 ;
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [1:0] ALU__SV_Ptype;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] ALU__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire ALU__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [1:0] BRANCH__SV_Ptype;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] BRANCH__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire BRANCH__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [1:0] CR__SV_Ptype;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] CR__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire CR__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [1:0] DIV__SV_Ptype;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] DIV__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire DIV__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [1:0] LDST__SV_Ptype;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] LDST__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire LDST__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [1:0] LOGICAL__SV_Ptype;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] LOGICAL__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire LOGICAL__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [1:0] MUL__SV_Ptype;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] MUL__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire MUL__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [1:0] SHIFT_ROT__SV_Ptype;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] SHIFT_ROT__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire SHIFT_ROT__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [1:0] SPR__SV_Ptype;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] SPR__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire SPR__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [1:0] core_core__SV_Ptype;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
+ input [1:0] core_core__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input core_core__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:120" *)
output corebusy_o;
reg corebusy_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" *)
reg [1:0] counter = 2'h0;
reg fus_oper_i_alu_alu0__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg fus_oper_i_alu_alu0__rc__rc;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] fus_oper_i_alu_alu0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg fus_oper_i_alu_alu0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg fus_oper_i_alu_branch0__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg fus_oper_i_alu_branch0__lk;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] fus_oper_i_alu_branch0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg fus_oper_i_alu_branch0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [6:0] fus_oper_i_alu_cr0__insn_type;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] fus_oper_i_alu_cr0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg fus_oper_i_alu_cr0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg fus_oper_i_alu_div0__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg fus_oper_i_alu_div0__rc__rc;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] fus_oper_i_alu_div0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg fus_oper_i_alu_div0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg fus_oper_i_alu_logical0__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg fus_oper_i_alu_logical0__rc__rc;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] fus_oper_i_alu_logical0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg fus_oper_i_alu_logical0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg fus_oper_i_alu_mul0__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg fus_oper_i_alu_mul0__rc__rc;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] fus_oper_i_alu_mul0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg fus_oper_i_alu_mul0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg fus_oper_i_alu_shift_rot0__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg fus_oper_i_alu_shift_rot0__rc__rc;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] fus_oper_i_alu_shift_rot0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg fus_oper_i_alu_shift_rot0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [6:0] fus_oper_i_alu_spr0__insn_type;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg fus_oper_i_alu_spr0__is_32bit;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] fus_oper_i_alu_spr0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg fus_oper_i_alu_spr0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [7:0] fus_oper_i_alu_trap0__ldst_exc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [63:0] fus_oper_i_alu_trap0__msr;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] fus_oper_i_alu_trap0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg fus_oper_i_alu_trap0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg fus_oper_i_ldst_ldst0__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg fus_oper_i_ldst_ldst0__sign_extend;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] fus_oper_i_ldst_ldst0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg fus_oper_i_ldst_ldst0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire \sv_a_nz$169 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:747" *)
wire \sv_a_nz$170 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:99" *)
input wb_dcache_en;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [2:0] wen;
.oper_i_alu_alu0__output_carry(fus_oper_i_alu_alu0__output_carry),
.oper_i_alu_alu0__rc__ok(fus_oper_i_alu_alu0__rc__ok),
.oper_i_alu_alu0__rc__rc(fus_oper_i_alu_alu0__rc__rc),
+ .oper_i_alu_alu0__sv_ldstmode(fus_oper_i_alu_alu0__sv_ldstmode),
.oper_i_alu_alu0__sv_pred_dz(fus_oper_i_alu_alu0__sv_pred_dz),
.oper_i_alu_alu0__sv_pred_sz(fus_oper_i_alu_alu0__sv_pred_sz),
.oper_i_alu_alu0__sv_saturate(fus_oper_i_alu_alu0__sv_saturate),
.oper_i_alu_branch0__insn_type(fus_oper_i_alu_branch0__insn_type),
.oper_i_alu_branch0__is_32bit(fus_oper_i_alu_branch0__is_32bit),
.oper_i_alu_branch0__lk(fus_oper_i_alu_branch0__lk),
+ .oper_i_alu_branch0__sv_ldstmode(fus_oper_i_alu_branch0__sv_ldstmode),
.oper_i_alu_branch0__sv_pred_dz(fus_oper_i_alu_branch0__sv_pred_dz),
.oper_i_alu_branch0__sv_pred_sz(fus_oper_i_alu_branch0__sv_pred_sz),
.oper_i_alu_branch0__sv_saturate(fus_oper_i_alu_branch0__sv_saturate),
.oper_i_alu_cr0__fn_unit(fus_oper_i_alu_cr0__fn_unit),
.oper_i_alu_cr0__insn(fus_oper_i_alu_cr0__insn),
.oper_i_alu_cr0__insn_type(fus_oper_i_alu_cr0__insn_type),
+ .oper_i_alu_cr0__sv_ldstmode(fus_oper_i_alu_cr0__sv_ldstmode),
.oper_i_alu_cr0__sv_pred_dz(fus_oper_i_alu_cr0__sv_pred_dz),
.oper_i_alu_cr0__sv_pred_sz(fus_oper_i_alu_cr0__sv_pred_sz),
.oper_i_alu_cr0__sv_saturate(fus_oper_i_alu_cr0__sv_saturate),
.oper_i_alu_div0__output_carry(fus_oper_i_alu_div0__output_carry),
.oper_i_alu_div0__rc__ok(fus_oper_i_alu_div0__rc__ok),
.oper_i_alu_div0__rc__rc(fus_oper_i_alu_div0__rc__rc),
+ .oper_i_alu_div0__sv_ldstmode(fus_oper_i_alu_div0__sv_ldstmode),
.oper_i_alu_div0__sv_pred_dz(fus_oper_i_alu_div0__sv_pred_dz),
.oper_i_alu_div0__sv_pred_sz(fus_oper_i_alu_div0__sv_pred_sz),
.oper_i_alu_div0__sv_saturate(fus_oper_i_alu_div0__sv_saturate),
.oper_i_alu_logical0__output_carry(fus_oper_i_alu_logical0__output_carry),
.oper_i_alu_logical0__rc__ok(fus_oper_i_alu_logical0__rc__ok),
.oper_i_alu_logical0__rc__rc(fus_oper_i_alu_logical0__rc__rc),
+ .oper_i_alu_logical0__sv_ldstmode(fus_oper_i_alu_logical0__sv_ldstmode),
.oper_i_alu_logical0__sv_pred_dz(fus_oper_i_alu_logical0__sv_pred_dz),
.oper_i_alu_logical0__sv_pred_sz(fus_oper_i_alu_logical0__sv_pred_sz),
.oper_i_alu_logical0__sv_saturate(fus_oper_i_alu_logical0__sv_saturate),
.oper_i_alu_mul0__oe__ok(fus_oper_i_alu_mul0__oe__ok),
.oper_i_alu_mul0__rc__ok(fus_oper_i_alu_mul0__rc__ok),
.oper_i_alu_mul0__rc__rc(fus_oper_i_alu_mul0__rc__rc),
+ .oper_i_alu_mul0__sv_ldstmode(fus_oper_i_alu_mul0__sv_ldstmode),
.oper_i_alu_mul0__sv_pred_dz(fus_oper_i_alu_mul0__sv_pred_dz),
.oper_i_alu_mul0__sv_pred_sz(fus_oper_i_alu_mul0__sv_pred_sz),
.oper_i_alu_mul0__sv_saturate(fus_oper_i_alu_mul0__sv_saturate),
.oper_i_alu_shift_rot0__output_cr(fus_oper_i_alu_shift_rot0__output_cr),
.oper_i_alu_shift_rot0__rc__ok(fus_oper_i_alu_shift_rot0__rc__ok),
.oper_i_alu_shift_rot0__rc__rc(fus_oper_i_alu_shift_rot0__rc__rc),
+ .oper_i_alu_shift_rot0__sv_ldstmode(fus_oper_i_alu_shift_rot0__sv_ldstmode),
.oper_i_alu_shift_rot0__sv_pred_dz(fus_oper_i_alu_shift_rot0__sv_pred_dz),
.oper_i_alu_shift_rot0__sv_pred_sz(fus_oper_i_alu_shift_rot0__sv_pred_sz),
.oper_i_alu_shift_rot0__sv_saturate(fus_oper_i_alu_shift_rot0__sv_saturate),
.oper_i_alu_spr0__insn(fus_oper_i_alu_spr0__insn),
.oper_i_alu_spr0__insn_type(fus_oper_i_alu_spr0__insn_type),
.oper_i_alu_spr0__is_32bit(fus_oper_i_alu_spr0__is_32bit),
+ .oper_i_alu_spr0__sv_ldstmode(fus_oper_i_alu_spr0__sv_ldstmode),
.oper_i_alu_spr0__sv_pred_dz(fus_oper_i_alu_spr0__sv_pred_dz),
.oper_i_alu_spr0__sv_pred_sz(fus_oper_i_alu_spr0__sv_pred_sz),
.oper_i_alu_spr0__sv_saturate(fus_oper_i_alu_spr0__sv_saturate),
.oper_i_alu_trap0__is_32bit(fus_oper_i_alu_trap0__is_32bit),
.oper_i_alu_trap0__ldst_exc(fus_oper_i_alu_trap0__ldst_exc),
.oper_i_alu_trap0__msr(fus_oper_i_alu_trap0__msr),
+ .oper_i_alu_trap0__sv_ldstmode(fus_oper_i_alu_trap0__sv_ldstmode),
.oper_i_alu_trap0__sv_pred_dz(fus_oper_i_alu_trap0__sv_pred_dz),
.oper_i_alu_trap0__sv_pred_sz(fus_oper_i_alu_trap0__sv_pred_sz),
.oper_i_alu_trap0__sv_saturate(fus_oper_i_alu_trap0__sv_saturate),
.oper_i_ldst_ldst0__rc__ok(fus_oper_i_ldst_ldst0__rc__ok),
.oper_i_ldst_ldst0__rc__rc(fus_oper_i_ldst_ldst0__rc__rc),
.oper_i_ldst_ldst0__sign_extend(fus_oper_i_ldst_ldst0__sign_extend),
+ .oper_i_ldst_ldst0__sv_ldstmode(fus_oper_i_ldst_ldst0__sv_ldstmode),
.oper_i_ldst_ldst0__sv_pred_dz(fus_oper_i_ldst_ldst0__sv_pred_dz),
.oper_i_ldst_ldst0__sv_pred_sz(fus_oper_i_ldst_ldst0__sv_pred_sz),
.oper_i_ldst_ldst0__sv_saturate(fus_oper_i_ldst_ldst0__sv_saturate),
.\wen$2 (\xer_wen$159 ),
.\wen$4 (\xer_wen$161 )
);
+ always @* begin
+ if (\initial ) begin end
+ fus_oper_i_alu_trap0__ldst_exc = 8'h00;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
+ casez (ivalid_i)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
+ 1'h1:
+ (* full_case = 32'd1 *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ casez (core_core_insn_type)
+ /* \nmigen.decoding = "OP_ATTN/5" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */
+ 7'h05:
+ /* empty */;
+ /* \nmigen.decoding = "OP_NOP/1" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */
+ 7'h01:
+ /* empty */;
+ /* \nmigen.decoding = {0{1'b0}} */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */
+ default:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *)
+ casez (fu_enable[3])
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
+ 1'h1:
+ fus_oper_i_alu_trap0__ldst_exc = { core_core_exc_happened, core_core_exc_segment_fault, core_core_exc_rc_error, core_core_exc_perm_error, core_core_exc_badtree, core_core_exc_invalid, core_core_exc_instr_fault, core_core_exc_alignment };
+ endcase
+ endcase
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ fus_oper_i_alu_trap0__sv_pred_sz = 1'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
+ casez (ivalid_i)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
+ 1'h1:
+ (* full_case = 32'd1 *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ casez (core_core_insn_type)
+ /* \nmigen.decoding = "OP_ATTN/5" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */
+ 7'h05:
+ /* empty */;
+ /* \nmigen.decoding = "OP_NOP/1" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */
+ 7'h01:
+ /* empty */;
+ /* \nmigen.decoding = {0{1'b0}} */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */
+ default:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *)
+ casez (fu_enable[3])
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
+ 1'h1:
+ fus_oper_i_alu_trap0__sv_pred_sz = core_core__sv_pred_sz;
+ endcase
+ endcase
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ fus_oper_i_alu_trap0__sv_pred_dz = 1'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
+ casez (ivalid_i)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
+ 1'h1:
+ (* full_case = 32'd1 *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ casez (core_core_insn_type)
+ /* \nmigen.decoding = "OP_ATTN/5" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */
+ 7'h05:
+ /* empty */;
+ /* \nmigen.decoding = "OP_NOP/1" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */
+ 7'h01:
+ /* empty */;
+ /* \nmigen.decoding = {0{1'b0}} */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */
+ default:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *)
+ casez (fu_enable[3])
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
+ 1'h1:
+ fus_oper_i_alu_trap0__sv_pred_dz = core_core__sv_pred_dz;
+ endcase
+ endcase
+ endcase
+ end
always @* begin
if (\initial ) begin end
fus_oper_i_alu_trap0__sv_saturate = 2'h0;
endcase
endcase
end
+ always @* begin
+ if (\initial ) begin end
+ fus_oper_i_alu_trap0__sv_ldstmode = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
+ casez (ivalid_i)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
+ 1'h1:
+ (* full_case = 32'd1 *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ casez (core_core_insn_type)
+ /* \nmigen.decoding = "OP_ATTN/5" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */
+ 7'h05:
+ /* empty */;
+ /* \nmigen.decoding = "OP_NOP/1" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */
+ 7'h01:
+ /* empty */;
+ /* \nmigen.decoding = {0{1'b0}} */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */
+ default:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *)
+ casez (fu_enable[3])
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
+ 1'h1:
+ fus_oper_i_alu_trap0__sv_ldstmode = core_core__sv_ldstmode;
+ endcase
+ endcase
+ endcase
+ end
always @* begin
if (\initial ) begin end
fus_oper_i_alu_trap0__SV_Ptype = 2'h0;
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_logical0__SV_Ptype = 2'h0;
+ fus_oper_i_alu_logical0__sv_ldstmode = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[4])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_logical0__SV_Ptype = LOGICAL__SV_Ptype;
+ fus_oper_i_alu_logical0__sv_ldstmode = LOGICAL__sv_ldstmode;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- \fus_cu_issue_i$15 = 1'h0;
+ fus_oper_i_alu_logical0__SV_Ptype = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[4])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- \fus_cu_issue_i$15 = issue_i;
+ fus_oper_i_alu_logical0__SV_Ptype = LOGICAL__SV_Ptype;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- \fus_cu_rdmaskn_i$17 = 3'h0;
+ \fus_cu_issue_i$15 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[4])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- \fus_cu_rdmaskn_i$17 = \$246 ;
+ \fus_cu_issue_i$15 = issue_i;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_spr0__insn_type = 7'h00;
+ \fus_cu_rdmaskn_i$17 = 3'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */
default:
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *)
- casez (fu_enable[5])
+ casez (fu_enable[4])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_spr0__insn_type = dec_SPR_SPR__insn_type;
+ \fus_cu_rdmaskn_i$17 = \$246 ;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_spr0__fn_unit = 15'h0000;
+ fus_oper_i_alu_spr0__insn_type = 7'h00;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[5])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_spr0__fn_unit = dec_SPR_SPR__fn_unit;
+ fus_oper_i_alu_spr0__insn_type = dec_SPR_SPR__insn_type;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_spr0__insn = 32'd0;
+ fus_oper_i_alu_spr0__fn_unit = 15'h0000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[5])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_spr0__insn = dec_SPR_SPR__insn;
+ fus_oper_i_alu_spr0__fn_unit = dec_SPR_SPR__fn_unit;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_spr0__is_32bit = 1'h0;
+ fus_oper_i_alu_spr0__insn = 32'd0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[5])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_spr0__is_32bit = dec_SPR_SPR__is_32bit;
+ fus_oper_i_alu_spr0__insn = dec_SPR_SPR__insn;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_spr0__sv_pred_sz = 1'h0;
+ fus_oper_i_alu_spr0__is_32bit = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[5])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_spr0__sv_pred_sz = SPR__sv_pred_sz;
+ fus_oper_i_alu_spr0__is_32bit = dec_SPR_SPR__is_32bit;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_spr0__sv_pred_dz = 1'h0;
+ fus_oper_i_alu_spr0__sv_pred_sz = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[5])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_spr0__sv_pred_dz = SPR__sv_pred_dz;
+ fus_oper_i_alu_spr0__sv_pred_sz = SPR__sv_pred_sz;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_spr0__sv_saturate = 2'h0;
+ fus_oper_i_alu_spr0__sv_pred_dz = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[5])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_spr0__sv_saturate = SPR__sv_saturate;
+ fus_oper_i_alu_spr0__sv_pred_dz = SPR__sv_pred_dz;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_spr0__SV_Ptype = 2'h0;
+ fus_oper_i_alu_spr0__sv_saturate = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[5])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_spr0__SV_Ptype = SPR__SV_Ptype;
+ fus_oper_i_alu_spr0__sv_saturate = SPR__sv_saturate;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- \fus_cu_issue_i$18 = 1'h0;
+ fus_oper_i_alu_spr0__sv_ldstmode = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[5])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- \fus_cu_issue_i$18 = issue_i;
+ fus_oper_i_alu_spr0__sv_ldstmode = SPR__sv_ldstmode;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- \fus_cu_rdmaskn_i$20 = 6'h00;
+ fus_oper_i_alu_spr0__SV_Ptype = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[5])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- \fus_cu_rdmaskn_i$20 = \$260 ;
+ fus_oper_i_alu_spr0__SV_Ptype = SPR__SV_Ptype;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_div0__insn_type = 7'h00;
+ \fus_cu_issue_i$18 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */
default:
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *)
- casez (fu_enable[6])
+ casez (fu_enable[5])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_div0__insn_type = dec_DIV_DIV__insn_type;
+ \fus_cu_issue_i$18 = issue_i;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_div0__fn_unit = 15'h0000;
+ \fus_cu_rdmaskn_i$20 = 6'h00;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */
default:
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *)
- casez (fu_enable[6])
+ casez (fu_enable[5])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_div0__fn_unit = dec_DIV_DIV__fn_unit;
+ \fus_cu_rdmaskn_i$20 = \$260 ;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_div0__imm_data__data = 64'h0000000000000000;
- fus_oper_i_alu_div0__imm_data__ok = 1'h0;
+ fus_oper_i_alu_div0__insn_type = 7'h00;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[6])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- { fus_oper_i_alu_div0__imm_data__ok, fus_oper_i_alu_div0__imm_data__data } = { dec_DIV_DIV__imm_data__ok, dec_DIV_DIV__imm_data__data };
+ fus_oper_i_alu_div0__insn_type = dec_DIV_DIV__insn_type;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_div0__rc__rc = 1'h0;
- fus_oper_i_alu_div0__rc__ok = 1'h0;
+ fus_oper_i_alu_div0__fn_unit = 15'h0000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[6])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- { fus_oper_i_alu_div0__rc__ok, fus_oper_i_alu_div0__rc__rc } = { dec_DIV_DIV__rc__ok, dec_DIV_DIV__rc__rc };
+ fus_oper_i_alu_div0__fn_unit = dec_DIV_DIV__fn_unit;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_div0__oe__oe = 1'h0;
- fus_oper_i_alu_div0__oe__ok = 1'h0;
+ fus_oper_i_alu_div0__imm_data__data = 64'h0000000000000000;
+ fus_oper_i_alu_div0__imm_data__ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[6])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- { fus_oper_i_alu_div0__oe__ok, fus_oper_i_alu_div0__oe__oe } = { dec_DIV_DIV__oe__ok, dec_DIV_DIV__oe__oe };
+ { fus_oper_i_alu_div0__imm_data__ok, fus_oper_i_alu_div0__imm_data__data } = { dec_DIV_DIV__imm_data__ok, dec_DIV_DIV__imm_data__data };
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_div0__invert_in = 1'h0;
+ fus_oper_i_alu_div0__rc__rc = 1'h0;
+ fus_oper_i_alu_div0__rc__ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[6])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_div0__invert_in = dec_DIV_DIV__invert_in;
+ { fus_oper_i_alu_div0__rc__ok, fus_oper_i_alu_div0__rc__rc } = { dec_DIV_DIV__rc__ok, dec_DIV_DIV__rc__rc };
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_div0__zero_a = 1'h0;
+ fus_oper_i_alu_div0__oe__oe = 1'h0;
+ fus_oper_i_alu_div0__oe__ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[6])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_div0__zero_a = dec_DIV_DIV__zero_a;
+ { fus_oper_i_alu_div0__oe__ok, fus_oper_i_alu_div0__oe__oe } = { dec_DIV_DIV__oe__ok, dec_DIV_DIV__oe__oe };
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_div0__input_carry = 2'h0;
+ fus_oper_i_alu_div0__invert_in = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[6])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_div0__input_carry = dec_DIV_DIV__input_carry;
+ fus_oper_i_alu_div0__invert_in = dec_DIV_DIV__invert_in;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_div0__invert_out = 1'h0;
+ fus_oper_i_alu_div0__zero_a = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[6])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_div0__invert_out = dec_DIV_DIV__invert_out;
+ fus_oper_i_alu_div0__zero_a = dec_DIV_DIV__zero_a;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_div0__write_cr0 = 1'h0;
+ fus_oper_i_alu_div0__input_carry = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[6])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_div0__write_cr0 = dec_DIV_DIV__write_cr0;
+ fus_oper_i_alu_div0__input_carry = dec_DIV_DIV__input_carry;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_div0__output_carry = 1'h0;
+ fus_oper_i_alu_div0__invert_out = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[6])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_div0__output_carry = dec_DIV_DIV__output_carry;
+ fus_oper_i_alu_div0__invert_out = dec_DIV_DIV__invert_out;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_div0__is_32bit = 1'h0;
+ fus_oper_i_alu_div0__write_cr0 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[6])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_div0__is_32bit = dec_DIV_DIV__is_32bit;
+ fus_oper_i_alu_div0__write_cr0 = dec_DIV_DIV__write_cr0;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_div0__is_signed = 1'h0;
+ fus_oper_i_alu_div0__output_carry = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[6])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_div0__is_signed = dec_DIV_DIV__is_signed;
+ fus_oper_i_alu_div0__output_carry = dec_DIV_DIV__output_carry;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_div0__data_len = 4'h0;
+ fus_oper_i_alu_div0__is_32bit = 1'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
+ casez (ivalid_i)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
+ 1'h1:
+ (* full_case = 32'd1 *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ casez (core_core_insn_type)
+ /* \nmigen.decoding = "OP_ATTN/5" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */
+ 7'h05:
+ /* empty */;
+ /* \nmigen.decoding = "OP_NOP/1" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */
+ 7'h01:
+ /* empty */;
+ /* \nmigen.decoding = {0{1'b0}} */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */
+ default:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *)
+ casez (fu_enable[6])
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
+ 1'h1:
+ fus_oper_i_alu_div0__is_32bit = dec_DIV_DIV__is_32bit;
+ endcase
+ endcase
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ fus_oper_i_alu_div0__is_signed = 1'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
+ casez (ivalid_i)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
+ 1'h1:
+ (* full_case = 32'd1 *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ casez (core_core_insn_type)
+ /* \nmigen.decoding = "OP_ATTN/5" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */
+ 7'h05:
+ /* empty */;
+ /* \nmigen.decoding = "OP_NOP/1" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */
+ 7'h01:
+ /* empty */;
+ /* \nmigen.decoding = {0{1'b0}} */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */
+ default:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *)
+ casez (fu_enable[6])
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
+ 1'h1:
+ fus_oper_i_alu_div0__is_signed = dec_DIV_DIV__is_signed;
+ endcase
+ endcase
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ fus_oper_i_alu_div0__data_len = 4'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
endcase
endcase
end
+ always @* begin
+ if (\initial ) begin end
+ fus_oper_i_alu_div0__sv_ldstmode = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
+ casez (ivalid_i)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
+ 1'h1:
+ (* full_case = 32'd1 *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ casez (core_core_insn_type)
+ /* \nmigen.decoding = "OP_ATTN/5" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */
+ 7'h05:
+ /* empty */;
+ /* \nmigen.decoding = "OP_NOP/1" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */
+ 7'h01:
+ /* empty */;
+ /* \nmigen.decoding = {0{1'b0}} */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */
+ default:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *)
+ casez (fu_enable[6])
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
+ 1'h1:
+ fus_oper_i_alu_div0__sv_ldstmode = DIV__sv_ldstmode;
+ endcase
+ endcase
+ endcase
+ end
always @* begin
if (\initial ) begin end
fus_oper_i_alu_div0__SV_Ptype = 2'h0;
endcase
endcase
end
+ always @* begin
+ if (\initial ) begin end
+ fus_oper_i_alu_mul0__sv_ldstmode = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
+ casez (ivalid_i)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
+ 1'h1:
+ (* full_case = 32'd1 *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ casez (core_core_insn_type)
+ /* \nmigen.decoding = "OP_ATTN/5" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */
+ 7'h05:
+ /* empty */;
+ /* \nmigen.decoding = "OP_NOP/1" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */
+ 7'h01:
+ /* empty */;
+ /* \nmigen.decoding = {0{1'b0}} */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */
+ default:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *)
+ casez (fu_enable[7])
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
+ 1'h1:
+ fus_oper_i_alu_mul0__sv_ldstmode = MUL__sv_ldstmode;
+ endcase
+ endcase
+ endcase
+ end
always @* begin
if (\initial ) begin end
fus_oper_i_alu_mul0__SV_Ptype = 2'h0;
endcase
endcase
end
+ always @* begin
+ if (\initial ) begin end
+ fus_oper_i_alu_shift_rot0__sv_ldstmode = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
+ casez (ivalid_i)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
+ 1'h1:
+ (* full_case = 32'd1 *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ casez (core_core_insn_type)
+ /* \nmigen.decoding = "OP_ATTN/5" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */
+ 7'h05:
+ /* empty */;
+ /* \nmigen.decoding = "OP_NOP/1" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */
+ 7'h01:
+ /* empty */;
+ /* \nmigen.decoding = {0{1'b0}} */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */
+ default:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *)
+ casez (fu_enable[8])
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
+ 1'h1:
+ fus_oper_i_alu_shift_rot0__sv_ldstmode = SHIFT_ROT__sv_ldstmode;
+ endcase
+ endcase
+ endcase
+ end
always @* begin
if (\initial ) begin end
fus_oper_i_alu_shift_rot0__SV_Ptype = 2'h0;
endcase
endcase
end
+ always @* begin
+ if (\initial ) begin end
+ fus_oper_i_ldst_ldst0__sv_ldstmode = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
+ casez (ivalid_i)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
+ 1'h1:
+ (* full_case = 32'd1 *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ casez (core_core_insn_type)
+ /* \nmigen.decoding = "OP_ATTN/5" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */
+ 7'h05:
+ /* empty */;
+ /* \nmigen.decoding = "OP_NOP/1" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */
+ 7'h01:
+ /* empty */;
+ /* \nmigen.decoding = {0{1'b0}} */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */
+ default:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *)
+ casez (fu_enable[9])
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
+ 1'h1:
+ fus_oper_i_ldst_ldst0__sv_ldstmode = LDST__sv_ldstmode;
+ endcase
+ endcase
+ endcase
+ end
always @* begin
if (\initial ) begin end
fus_oper_i_ldst_ldst0__SV_Ptype = 2'h0;
\fus_src4_i$69 = xer_src1__data_o[0];
endcase
end
- always @* begin
- if (\initial ) begin end
- \dp_XER_xer_ca_alu0_0$next = rp_XER_xer_ca_alu0_0;
- (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (coresync_rst)
- 1'h1:
- \dp_XER_xer_ca_alu0_0$next = 1'h0;
- endcase
- end
- always @* begin
- if (\initial ) begin end
- \fus_src4_i$70 = 2'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
- casez (dp_XER_xer_ca_alu0_0)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
- 1'h1:
- \fus_src4_i$70 = xer_src2__data_o;
- endcase
- end
- always @* begin
- if (\initial ) begin end
- \dp_XER_xer_ca_spr0_1$next = rp_XER_xer_ca_spr0_1;
- (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (coresync_rst)
- 1'h1:
- \dp_XER_xer_ca_spr0_1$next = 1'h0;
- endcase
- end
always @* begin
if (\initial ) begin end
\counter$next = counter;
end
always @* begin
if (\initial ) begin end
- fus_src6_i = 2'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
- casez (dp_XER_xer_ca_spr0_1)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
+ \dp_XER_xer_ca_alu0_0$next = rp_XER_xer_ca_alu0_0;
+ (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
+ casez (coresync_rst)
1'h1:
- fus_src6_i = xer_src2__data_o;
+ \dp_XER_xer_ca_alu0_0$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
- \dp_XER_xer_ca_shiftrot0_2$next = rp_XER_xer_ca_shiftrot0_2;
- (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (coresync_rst)
+ \fus_src4_i$70 = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
+ casez (dp_XER_xer_ca_alu0_0)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
1'h1:
- \dp_XER_xer_ca_shiftrot0_2$next = 1'h0;
+ \fus_src4_i$70 = xer_src2__data_o;
endcase
end
always @* begin
if (\initial ) begin end
- fus_src5_i = 2'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
- casez (dp_XER_xer_ca_shiftrot0_2)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
+ \dp_XER_xer_ca_spr0_1$next = rp_XER_xer_ca_spr0_1;
+ (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
+ casez (coresync_rst)
1'h1:
- fus_src5_i = xer_src2__data_o;
+ \dp_XER_xer_ca_spr0_1$next = 1'h0;
endcase
end
always @* begin
end
always @* begin
if (\initial ) begin end
- \dp_XER_xer_ov_spr0_0$next = rp_XER_xer_ov_spr0_0;
- (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (coresync_rst)
+ fus_src6_i = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
+ casez (dp_XER_xer_ca_spr0_1)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
1'h1:
- \dp_XER_xer_ov_spr0_0$next = 1'h0;
+ fus_src6_i = xer_src2__data_o;
endcase
end
always @* begin
if (\initial ) begin end
- \fus_src5_i$71 = 2'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
- casez (dp_XER_xer_ov_spr0_0)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
+ \dp_XER_xer_ca_shiftrot0_2$next = rp_XER_xer_ca_shiftrot0_2;
+ (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
+ casez (coresync_rst)
1'h1:
- \fus_src5_i$71 = xer_src3__data_o;
+ \dp_XER_xer_ca_shiftrot0_2$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
- \dp_CR_full_cr_cr0_0$next = rp_CR_full_cr_cr0_0;
- (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (coresync_rst)
+ fus_src5_i = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
+ casez (dp_XER_xer_ca_shiftrot0_2)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
1'h1:
- \dp_CR_full_cr_cr0_0$next = 1'h0;
+ fus_src5_i = xer_src2__data_o;
endcase
end
always @* begin
end
always @* begin
if (\initial ) begin end
- \fus_src3_i$72 = 32'd0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
- casez (dp_CR_full_cr_cr0_0)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
+ \dp_XER_xer_ov_spr0_0$next = rp_XER_xer_ov_spr0_0;
+ (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
+ casez (coresync_rst)
1'h1:
- \fus_src3_i$72 = cr_full_rd__data_o;
+ \dp_XER_xer_ov_spr0_0$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
- \dp_CR_cr_a_cr0_0$next = rp_CR_cr_a_cr0_0;
- (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (coresync_rst)
+ \fus_src5_i$71 = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
+ casez (dp_XER_xer_ov_spr0_0)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
1'h1:
- \dp_CR_cr_a_cr0_0$next = 1'h0;
+ \fus_src5_i$71 = xer_src3__data_o;
endcase
end
always @* begin
if (\initial ) begin end
- \fus_src4_i$73 = 4'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
- casez (dp_CR_cr_a_cr0_0)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
+ \dp_CR_full_cr_cr0_0$next = rp_CR_full_cr_cr0_0;
+ (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
+ casez (coresync_rst)
1'h1:
- \fus_src4_i$73 = cr_src1__data_o;
+ \dp_CR_full_cr_cr0_0$next = 1'h0;
endcase
end
always @* begin
end
always @* begin
if (\initial ) begin end
- \dp_CR_cr_a_branch0_1$next = rp_CR_cr_a_branch0_1;
+ \fus_src3_i$72 = 32'd0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
+ casez (dp_CR_full_cr_cr0_0)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
+ 1'h1:
+ \fus_src3_i$72 = cr_full_rd__data_o;
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ \dp_CR_cr_a_cr0_0$next = rp_CR_cr_a_cr0_0;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
1'h1:
- \dp_CR_cr_a_branch0_1$next = 1'h0;
+ \dp_CR_cr_a_cr0_0$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
- \fus_src3_i$76 = 4'h0;
+ \fus_src4_i$73 = 4'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
- casez (dp_CR_cr_a_branch0_1)
+ casez (dp_CR_cr_a_cr0_0)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
1'h1:
- \fus_src3_i$76 = cr_src1__data_o;
+ \fus_src4_i$73 = cr_src1__data_o;
endcase
end
always @* begin
end
always @* begin
if (\initial ) begin end
- \dp_CR_cr_b_cr0_0$next = rp_CR_cr_b_cr0_0;
+ \dp_CR_cr_a_branch0_1$next = rp_CR_cr_a_branch0_1;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
1'h1:
- \dp_CR_cr_b_cr0_0$next = 1'h0;
+ \dp_CR_cr_a_branch0_1$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
- \fus_src5_i$77 = 4'h0;
+ \fus_src3_i$76 = 4'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
- casez (dp_CR_cr_b_cr0_0)
+ casez (dp_CR_cr_a_branch0_1)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
1'h1:
- \fus_src5_i$77 = cr_src2__data_o;
- endcase
- end
- always @* begin
- if (\initial ) begin end
- \dp_CR_cr_c_cr0_0$next = rp_CR_cr_c_cr0_0;
- (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (coresync_rst)
- 1'h1:
- \dp_CR_cr_c_cr0_0$next = 1'h0;
+ \fus_src3_i$76 = cr_src1__data_o;
endcase
end
always @* begin
end
always @* begin
if (\initial ) begin end
- \fus_src6_i$78 = 4'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
- casez (dp_CR_cr_c_cr0_0)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
- 1'h1:
- \fus_src6_i$78 = cr_src3__data_o;
- endcase
- end
- always @* begin
- if (\initial ) begin end
- \dp_FAST_fast1_branch0_0$next = rp_FAST_fast1_branch0_0;
+ \dp_CR_cr_b_cr0_0$next = rp_CR_cr_b_cr0_0;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
1'h1:
- \dp_FAST_fast1_branch0_0$next = 1'h0;
+ \dp_CR_cr_b_cr0_0$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
- \fus_src1_i$79 = 64'h0000000000000000;
+ \fus_src5_i$77 = 4'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
- casez (dp_FAST_fast1_branch0_0)
+ casez (dp_CR_cr_b_cr0_0)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
1'h1:
- \fus_src1_i$79 = fast_src1__data_o;
+ \fus_src5_i$77 = cr_src2__data_o;
endcase
end
always @* begin
if (\initial ) begin end
- \dp_FAST_fast1_trap0_1$next = rp_FAST_fast1_trap0_1;
+ \dp_CR_cr_c_cr0_0$next = rp_CR_cr_c_cr0_0;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
1'h1:
- \dp_FAST_fast1_trap0_1$next = 1'h0;
+ \dp_CR_cr_c_cr0_0$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
- \fus_src3_i$80 = 64'h0000000000000000;
+ \fus_src6_i$78 = 4'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
- casez (dp_FAST_fast1_trap0_1)
+ casez (dp_CR_cr_c_cr0_0)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
1'h1:
- \fus_src3_i$80 = fast_src1__data_o;
+ \fus_src6_i$78 = cr_src3__data_o;
endcase
end
always @* begin
if (\initial ) begin end
- \dp_FAST_fast1_spr0_2$next = rp_FAST_fast1_spr0_2;
+ \dp_FAST_fast1_branch0_0$next = rp_FAST_fast1_branch0_0;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
1'h1:
- \dp_FAST_fast1_spr0_2$next = 1'h0;
+ \dp_FAST_fast1_branch0_0$next = 1'h0;
endcase
end
always @* begin
end
always @* begin
if (\initial ) begin end
- \fus_src3_i$81 = 64'h0000000000000000;
+ \fus_src1_i$79 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
- casez (dp_FAST_fast1_spr0_2)
+ casez (dp_FAST_fast1_branch0_0)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
1'h1:
- \fus_src3_i$81 = fast_src1__data_o;
+ \fus_src1_i$79 = fast_src1__data_o;
endcase
end
always @* begin
if (\initial ) begin end
- \dp_FAST_fast1_branch0_3$next = rp_FAST_fast1_branch0_3;
+ \dp_FAST_fast1_trap0_1$next = rp_FAST_fast1_trap0_1;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
1'h1:
- \dp_FAST_fast1_branch0_3$next = 1'h0;
+ \dp_FAST_fast1_trap0_1$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
- \fus_src2_i$82 = 64'h0000000000000000;
+ \fus_src3_i$80 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
- casez (dp_FAST_fast1_branch0_3)
+ casez (dp_FAST_fast1_trap0_1)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
1'h1:
- \fus_src2_i$82 = fast_src1__data_o;
+ \fus_src3_i$80 = fast_src1__data_o;
endcase
end
always @* begin
if (\initial ) begin end
- \dp_FAST_fast1_trap0_4$next = rp_FAST_fast1_trap0_4;
+ \dp_FAST_fast1_spr0_2$next = rp_FAST_fast1_spr0_2;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
1'h1:
- \dp_FAST_fast1_trap0_4$next = 1'h0;
+ \dp_FAST_fast1_spr0_2$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
- \fus_src4_i$83 = 64'h0000000000000000;
+ \fus_src3_i$81 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
- casez (dp_FAST_fast1_trap0_4)
+ casez (dp_FAST_fast1_spr0_2)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
1'h1:
- \fus_src4_i$83 = fast_src1__data_o;
+ \fus_src3_i$81 = fast_src1__data_o;
endcase
end
always @* begin
if (\initial ) begin end
- \dp_FAST_fast1_trap0_5$next = rp_FAST_fast1_trap0_5;
+ \dp_FAST_fast1_branch0_3$next = rp_FAST_fast1_branch0_3;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
1'h1:
- \dp_FAST_fast1_trap0_5$next = 1'h0;
+ \dp_FAST_fast1_branch0_3$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
- \fus_src5_i$84 = 64'h0000000000000000;
+ \fus_src2_i$82 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
- casez (dp_FAST_fast1_trap0_5)
+ casez (dp_FAST_fast1_branch0_3)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
1'h1:
- \fus_src5_i$84 = fast_src1__data_o;
+ \fus_src2_i$82 = fast_src1__data_o;
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ \dp_FAST_fast1_trap0_4$next = rp_FAST_fast1_trap0_4;
+ (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
+ casez (coresync_rst)
+ 1'h1:
+ \dp_FAST_fast1_trap0_4$next = 1'h0;
endcase
end
always @* begin
endcase
endcase
end
+ always @* begin
+ if (\initial ) begin end
+ \fus_src4_i$83 = 64'h0000000000000000;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
+ casez (dp_FAST_fast1_trap0_4)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
+ 1'h1:
+ \fus_src4_i$83 = fast_src1__data_o;
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ \dp_FAST_fast1_trap0_5$next = rp_FAST_fast1_trap0_5;
+ (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
+ casez (coresync_rst)
+ 1'h1:
+ \dp_FAST_fast1_trap0_5$next = 1'h0;
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ \fus_src5_i$84 = 64'h0000000000000000;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *)
+ casez (dp_FAST_fast1_trap0_5)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */
+ 1'h1:
+ \fus_src5_i$84 = fast_src1__data_o;
+ endcase
+ end
always @* begin
if (\initial ) begin end
\dp_SPR_spr1_spr0_0$next = rp_SPR_spr1_spr0_0;
\fus_src2_i$85 = spr_spr1__data_o;
endcase
end
+ always @* begin
+ if (\initial ) begin end
+ fus_oper_i_alu_alu0__invert_in = 1'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
+ casez (ivalid_i)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
+ 1'h1:
+ (* full_case = 32'd1 *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ casez (core_core_insn_type)
+ /* \nmigen.decoding = "OP_ATTN/5" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */
+ 7'h05:
+ /* empty */;
+ /* \nmigen.decoding = "OP_NOP/1" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */
+ 7'h01:
+ /* empty */;
+ /* \nmigen.decoding = {0{1'b0}} */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */
+ default:
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *)
+ casez (fu_enable[0])
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
+ 1'h1:
+ fus_oper_i_alu_alu0__invert_in = dec_ALU_ALU__invert_in;
+ endcase
+ endcase
+ endcase
+ end
always @* begin
if (\initial ) begin end
\wr_pick_dly$next = wr_pick;
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_alu0__invert_in = 1'h0;
+ fus_oper_i_alu_alu0__zero_a = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[0])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_alu0__invert_in = dec_ALU_ALU__invert_in;
+ fus_oper_i_alu_alu0__zero_a = dec_ALU_ALU__zero_a;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_alu0__zero_a = 1'h0;
+ fus_oper_i_alu_alu0__invert_out = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[0])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_alu0__zero_a = dec_ALU_ALU__zero_a;
+ fus_oper_i_alu_alu0__invert_out = dec_ALU_ALU__invert_out;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_alu0__invert_out = 1'h0;
+ fus_oper_i_alu_alu0__write_cr0 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[0])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_alu0__invert_out = dec_ALU_ALU__invert_out;
+ fus_oper_i_alu_alu0__write_cr0 = dec_ALU_ALU__write_cr0;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_alu0__write_cr0 = 1'h0;
+ fus_oper_i_alu_alu0__input_carry = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[0])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_alu0__write_cr0 = dec_ALU_ALU__write_cr0;
+ fus_oper_i_alu_alu0__input_carry = dec_ALU_ALU__input_carry;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_alu0__input_carry = 2'h0;
+ fus_oper_i_alu_alu0__output_carry = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[0])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_alu0__input_carry = dec_ALU_ALU__input_carry;
+ fus_oper_i_alu_alu0__output_carry = dec_ALU_ALU__output_carry;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_alu0__output_carry = 1'h0;
+ fus_oper_i_alu_alu0__is_32bit = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[0])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_alu0__output_carry = dec_ALU_ALU__output_carry;
+ fus_oper_i_alu_alu0__is_32bit = dec_ALU_ALU__is_32bit;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_alu0__is_32bit = 1'h0;
+ fus_oper_i_alu_alu0__is_signed = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[0])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_alu0__is_32bit = dec_ALU_ALU__is_32bit;
+ fus_oper_i_alu_alu0__is_signed = dec_ALU_ALU__is_signed;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_alu0__is_signed = 1'h0;
+ fus_oper_i_alu_alu0__data_len = 4'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[0])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_alu0__is_signed = dec_ALU_ALU__is_signed;
+ fus_oper_i_alu_alu0__data_len = dec_ALU_ALU__data_len;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_alu0__data_len = 4'h0;
+ fus_oper_i_alu_alu0__insn = 32'd0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[0])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_alu0__data_len = dec_ALU_ALU__data_len;
+ fus_oper_i_alu_alu0__insn = dec_ALU_ALU__insn;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_alu0__insn = 32'd0;
+ fus_oper_i_alu_alu0__sv_pred_sz = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[0])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_alu0__insn = dec_ALU_ALU__insn;
+ fus_oper_i_alu_alu0__sv_pred_sz = ALU__sv_pred_sz;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_alu0__sv_pred_sz = 1'h0;
+ fus_oper_i_alu_alu0__sv_pred_dz = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[0])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_alu0__sv_pred_sz = ALU__sv_pred_sz;
+ fus_oper_i_alu_alu0__sv_pred_dz = ALU__sv_pred_dz;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_alu0__sv_pred_dz = 1'h0;
+ fus_oper_i_alu_alu0__sv_saturate = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[0])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_alu0__sv_pred_dz = ALU__sv_pred_dz;
+ fus_oper_i_alu_alu0__sv_saturate = ALU__sv_saturate;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_alu0__sv_saturate = 2'h0;
+ fus_oper_i_alu_alu0__sv_ldstmode = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[0])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_alu0__sv_saturate = ALU__sv_saturate;
+ fus_oper_i_alu_alu0__sv_ldstmode = ALU__sv_ldstmode;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_cr0__SV_Ptype = 2'h0;
+ fus_oper_i_alu_cr0__sv_ldstmode = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[1])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_cr0__SV_Ptype = CR__SV_Ptype;
+ fus_oper_i_alu_cr0__sv_ldstmode = CR__sv_ldstmode;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- \fus_cu_issue_i$6 = 1'h0;
+ fus_oper_i_alu_cr0__SV_Ptype = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[1])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- \fus_cu_issue_i$6 = issue_i;
+ fus_oper_i_alu_cr0__SV_Ptype = CR__SV_Ptype;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- \fus_cu_rdmaskn_i$8 = 6'h00;
+ \fus_cu_issue_i$6 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[1])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- \fus_cu_rdmaskn_i$8 = \$240 ;
+ \fus_cu_issue_i$6 = issue_i;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_branch0__cia = 64'h0000000000000000;
+ \fus_cu_rdmaskn_i$8 = 6'h00;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */
default:
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *)
- casez (fu_enable[2])
+ casez (fu_enable[1])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_branch0__cia = dec_BRANCH_BRANCH__cia;
+ \fus_cu_rdmaskn_i$8 = \$240 ;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_branch0__insn_type = 7'h00;
+ fus_oper_i_alu_branch0__cia = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[2])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_branch0__insn_type = dec_BRANCH_BRANCH__insn_type;
+ fus_oper_i_alu_branch0__cia = dec_BRANCH_BRANCH__cia;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_branch0__fn_unit = 15'h0000;
+ fus_oper_i_alu_branch0__insn_type = 7'h00;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[2])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_branch0__fn_unit = dec_BRANCH_BRANCH__fn_unit;
+ fus_oper_i_alu_branch0__insn_type = dec_BRANCH_BRANCH__insn_type;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_branch0__insn = 32'd0;
+ fus_oper_i_alu_branch0__fn_unit = 15'h0000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[2])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_branch0__insn = dec_BRANCH_BRANCH__insn;
+ fus_oper_i_alu_branch0__fn_unit = dec_BRANCH_BRANCH__fn_unit;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_branch0__imm_data__data = 64'h0000000000000000;
- fus_oper_i_alu_branch0__imm_data__ok = 1'h0;
+ fus_oper_i_alu_branch0__insn = 32'd0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[2])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- { fus_oper_i_alu_branch0__imm_data__ok, fus_oper_i_alu_branch0__imm_data__data } = { dec_BRANCH_BRANCH__imm_data__ok, dec_BRANCH_BRANCH__imm_data__data };
+ fus_oper_i_alu_branch0__insn = dec_BRANCH_BRANCH__insn;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_branch0__lk = 1'h0;
+ fus_oper_i_alu_branch0__imm_data__data = 64'h0000000000000000;
+ fus_oper_i_alu_branch0__imm_data__ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[2])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_branch0__lk = dec_BRANCH_BRANCH__lk;
+ { fus_oper_i_alu_branch0__imm_data__ok, fus_oper_i_alu_branch0__imm_data__data } = { dec_BRANCH_BRANCH__imm_data__ok, dec_BRANCH_BRANCH__imm_data__data };
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_branch0__is_32bit = 1'h0;
+ fus_oper_i_alu_branch0__lk = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[2])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_branch0__is_32bit = dec_BRANCH_BRANCH__is_32bit;
+ fus_oper_i_alu_branch0__lk = dec_BRANCH_BRANCH__lk;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_branch0__sv_pred_sz = 1'h0;
+ fus_oper_i_alu_branch0__is_32bit = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[2])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_branch0__sv_pred_sz = BRANCH__sv_pred_sz;
+ fus_oper_i_alu_branch0__is_32bit = dec_BRANCH_BRANCH__is_32bit;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_branch0__sv_pred_dz = 1'h0;
+ fus_oper_i_alu_branch0__sv_pred_sz = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[2])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_branch0__sv_pred_dz = BRANCH__sv_pred_dz;
+ fus_oper_i_alu_branch0__sv_pred_sz = BRANCH__sv_pred_sz;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_branch0__sv_saturate = 2'h0;
+ fus_oper_i_alu_branch0__sv_pred_dz = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[2])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_branch0__sv_saturate = BRANCH__sv_saturate;
+ fus_oper_i_alu_branch0__sv_pred_dz = BRANCH__sv_pred_dz;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_branch0__SV_Ptype = 2'h0;
+ fus_oper_i_alu_branch0__sv_saturate = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[2])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_branch0__SV_Ptype = BRANCH__SV_Ptype;
+ fus_oper_i_alu_branch0__sv_saturate = BRANCH__sv_saturate;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- \fus_cu_issue_i$9 = 1'h0;
+ fus_oper_i_alu_branch0__sv_ldstmode = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[2])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- \fus_cu_issue_i$9 = issue_i;
+ fus_oper_i_alu_branch0__sv_ldstmode = BRANCH__sv_ldstmode;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- \fus_cu_rdmaskn_i$11 = 3'h0;
+ fus_oper_i_alu_branch0__SV_Ptype = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[2])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- \fus_cu_rdmaskn_i$11 = \$242 ;
- endcase
- endcase
- endcase
- end
- always @* begin
- if (\initial ) begin end
- fus_oper_i_alu_trap0__insn_type = 7'h00;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
- casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
- 1'h1:
- (* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
- casez (core_core_insn_type)
- /* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */
- 7'h05:
- /* empty */;
- /* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */
- 7'h01:
- /* empty */;
- /* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */
- default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *)
- casez (fu_enable[3])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
- 1'h1:
- fus_oper_i_alu_trap0__insn_type = core_core_insn_type;
+ fus_oper_i_alu_branch0__SV_Ptype = BRANCH__SV_Ptype;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_trap0__fn_unit = 15'h0000;
+ \fus_cu_issue_i$9 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */
default:
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *)
- casez (fu_enable[3])
+ casez (fu_enable[2])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_trap0__fn_unit = core_core_fn_unit;
+ \fus_cu_issue_i$9 = issue_i;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_trap0__insn = 32'd0;
+ \fus_cu_rdmaskn_i$11 = 3'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */
default:
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *)
- casez (fu_enable[3])
+ casez (fu_enable[2])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_trap0__insn = core_core_insn;
+ \fus_cu_rdmaskn_i$11 = \$242 ;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_trap0__msr = 64'h0000000000000000;
+ fus_oper_i_alu_trap0__insn_type = 7'h00;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[3])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_trap0__msr = core_core_msr;
+ fus_oper_i_alu_trap0__insn_type = core_core_insn_type;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_trap0__cia = 64'h0000000000000000;
+ fus_oper_i_alu_trap0__fn_unit = 15'h0000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[3])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_trap0__cia = core_core_cia;
+ fus_oper_i_alu_trap0__fn_unit = core_core_fn_unit;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_trap0__svstate = 32'd0;
+ fus_oper_i_alu_trap0__insn = 32'd0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[3])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_trap0__svstate = core_core_svstate;
+ fus_oper_i_alu_trap0__insn = core_core_insn;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_trap0__is_32bit = 1'h0;
+ fus_oper_i_alu_trap0__msr = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[3])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_trap0__is_32bit = core_core_is_32bit;
+ fus_oper_i_alu_trap0__msr = core_core_msr;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_trap0__traptype = 8'h00;
+ fus_oper_i_alu_trap0__cia = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[3])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_trap0__traptype = core_core_traptype;
+ fus_oper_i_alu_trap0__cia = core_core_cia;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_trap0__trapaddr = 13'h0000;
+ fus_oper_i_alu_trap0__svstate = 32'd0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[3])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_trap0__trapaddr = core_core_trapaddr;
+ fus_oper_i_alu_trap0__svstate = core_core_svstate;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_trap0__ldst_exc = 8'h00;
+ fus_oper_i_alu_trap0__is_32bit = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[3])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_trap0__ldst_exc = { core_core_exc_happened, core_core_exc_segment_fault, core_core_exc_rc_error, core_core_exc_perm_error, core_core_exc_badtree, core_core_exc_invalid, core_core_exc_instr_fault, core_core_exc_alignment };
+ fus_oper_i_alu_trap0__is_32bit = core_core_is_32bit;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_trap0__sv_pred_sz = 1'h0;
+ fus_oper_i_alu_trap0__traptype = 8'h00;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[3])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_trap0__sv_pred_sz = core_core__sv_pred_sz;
+ fus_oper_i_alu_trap0__traptype = core_core_traptype;
endcase
endcase
endcase
end
always @* begin
if (\initial ) begin end
- fus_oper_i_alu_trap0__sv_pred_dz = 1'h0;
+ fus_oper_i_alu_trap0__trapaddr = 13'h0000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (ivalid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
casez (fu_enable[3])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */
1'h1:
- fus_oper_i_alu_trap0__sv_pred_dz = core_core__sv_pred_dz;
+ fus_oper_i_alu_trap0__trapaddr = core_core_trapaddr;
endcase
endcase
endcase
assign ALU__sv_pred_sz = 1'h0;
assign ALU__sv_pred_dz = 1'h0;
assign ALU__sv_saturate = 2'h0;
+ assign ALU__sv_ldstmode = 2'h0;
assign ALU__SV_Ptype = 2'h0;
assign CR__sv_pred_sz = 1'h0;
assign CR__sv_pred_dz = 1'h0;
assign CR__sv_saturate = 2'h0;
+ assign CR__sv_ldstmode = 2'h0;
assign CR__SV_Ptype = 2'h0;
assign BRANCH__sv_pred_sz = 1'h0;
assign BRANCH__sv_pred_dz = 1'h0;
assign BRANCH__sv_saturate = 2'h0;
+ assign BRANCH__sv_ldstmode = 2'h0;
assign BRANCH__SV_Ptype = 2'h0;
assign LOGICAL__sv_pred_sz = 1'h0;
assign LOGICAL__sv_pred_dz = 1'h0;
assign LOGICAL__sv_saturate = 2'h0;
+ assign LOGICAL__sv_ldstmode = 2'h0;
assign LOGICAL__SV_Ptype = 2'h0;
assign SPR__sv_pred_sz = 1'h0;
assign SPR__sv_pred_dz = 1'h0;
assign SPR__sv_saturate = 2'h0;
+ assign SPR__sv_ldstmode = 2'h0;
assign SPR__SV_Ptype = 2'h0;
assign DIV__sv_pred_sz = 1'h0;
assign DIV__sv_pred_dz = 1'h0;
assign DIV__sv_saturate = 2'h0;
+ assign DIV__sv_ldstmode = 2'h0;
assign DIV__SV_Ptype = 2'h0;
assign MUL__sv_pred_sz = 1'h0;
assign MUL__sv_pred_dz = 1'h0;
assign MUL__sv_saturate = 2'h0;
+ assign MUL__sv_ldstmode = 2'h0;
assign MUL__SV_Ptype = 2'h0;
assign SHIFT_ROT__sv_pred_sz = 1'h0;
assign SHIFT_ROT__sv_pred_dz = 1'h0;
assign SHIFT_ROT__sv_saturate = 2'h0;
+ assign SHIFT_ROT__sv_ldstmode = 2'h0;
assign SHIFT_ROT__SV_Ptype = 2'h0;
assign LDST__sv_pred_sz = 1'h0;
assign LDST__sv_pred_dz = 1'h0;
assign LDST__sv_saturate = 2'h0;
+ assign LDST__sv_ldstmode = 2'h0;
assign LDST__SV_Ptype = 2'h0;
assign o_ok = 1'h0;
assign ea_ok = 1'h0;
wire [3:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
wire [3:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] data_i;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0" *)
(* generator = "nMigen" *)
-module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, oper_i_alu_cr0__insn, oper_i_alu_cr0__sv_pred_sz, oper_i_alu_cr0__sv_pred_dz, oper_i_alu_cr0__sv_saturate, oper_i_alu_cr0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, src4_i, src5_i, src6_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, full_cr_ok, dest2_o, cr_a_ok, dest3_o, coresync_clk);
+module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, oper_i_alu_cr0__insn, oper_i_alu_cr0__sv_pred_sz, oper_i_alu_cr0__sv_pred_dz, oper_i_alu_cr0__sv_saturate, oper_i_alu_cr0__sv_ldstmode, oper_i_alu_cr0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, src4_i, src5_i, src6_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, full_cr_ok, dest2_o, cr_a_ok, dest3_o, coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
wire \$101 ;
reg [6:0] alu_cr0_cr_op__insn_type = 7'h00;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [6:0] \alu_cr0_cr_op__insn_type$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] alu_cr0_cr_op__sv_ldstmode = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \alu_cr0_cr_op__sv_ldstmode$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg alu_cr0_cr_op__sv_pred_dz = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output cr_a_ok;
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [6:0] oper_i_alu_cr0__insn_type;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] oper_i_alu_cr0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_cr0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
alu_cr0_cr_op__sv_pred_dz <= \alu_cr0_cr_op__sv_pred_dz$next ;
always @(posedge coresync_clk)
alu_cr0_cr_op__sv_saturate <= \alu_cr0_cr_op__sv_saturate$next ;
+ always @(posedge coresync_clk)
+ alu_cr0_cr_op__sv_ldstmode <= \alu_cr0_cr_op__sv_ldstmode$next ;
always @(posedge coresync_clk)
alu_cr0_cr_op__SV_Ptype <= \alu_cr0_cr_op__SV_Ptype$next ;
always @(posedge coresync_clk)
.cr_op__fn_unit(alu_cr0_cr_op__fn_unit),
.cr_op__insn(alu_cr0_cr_op__insn),
.cr_op__insn_type(alu_cr0_cr_op__insn_type),
+ .cr_op__sv_ldstmode(alu_cr0_cr_op__sv_ldstmode),
.cr_op__sv_pred_dz(alu_cr0_cr_op__sv_pred_dz),
.cr_op__sv_pred_sz(alu_cr0_cr_op__sv_pred_sz),
.cr_op__sv_saturate(alu_cr0_cr_op__sv_saturate),
\alu_cr0_cr_op__sv_pred_sz$next = alu_cr0_cr_op__sv_pred_sz;
\alu_cr0_cr_op__sv_pred_dz$next = alu_cr0_cr_op__sv_pred_dz;
\alu_cr0_cr_op__sv_saturate$next = alu_cr0_cr_op__sv_saturate;
+ \alu_cr0_cr_op__sv_ldstmode$next = alu_cr0_cr_op__sv_ldstmode;
\alu_cr0_cr_op__SV_Ptype$next = alu_cr0_cr_op__SV_Ptype;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *)
casez (cu_issue_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */
1'h1:
- { \alu_cr0_cr_op__SV_Ptype$next , \alu_cr0_cr_op__sv_saturate$next , \alu_cr0_cr_op__sv_pred_dz$next , \alu_cr0_cr_op__sv_pred_sz$next , \alu_cr0_cr_op__insn$next , \alu_cr0_cr_op__fn_unit$next , \alu_cr0_cr_op__insn_type$next } = { oper_i_alu_cr0__SV_Ptype, oper_i_alu_cr0__sv_saturate, oper_i_alu_cr0__sv_pred_dz, oper_i_alu_cr0__sv_pred_sz, oper_i_alu_cr0__insn, oper_i_alu_cr0__fn_unit, oper_i_alu_cr0__insn_type };
+ { \alu_cr0_cr_op__SV_Ptype$next , \alu_cr0_cr_op__sv_ldstmode$next , \alu_cr0_cr_op__sv_saturate$next , \alu_cr0_cr_op__sv_pred_dz$next , \alu_cr0_cr_op__sv_pred_sz$next , \alu_cr0_cr_op__insn$next , \alu_cr0_cr_op__fn_unit$next , \alu_cr0_cr_op__insn_type$next } = { oper_i_alu_cr0__SV_Ptype, oper_i_alu_cr0__sv_ldstmode, oper_i_alu_cr0__sv_saturate, oper_i_alu_cr0__sv_pred_dz, oper_i_alu_cr0__sv_pred_sz, oper_i_alu_cr0__insn, oper_i_alu_cr0__fn_unit, oper_i_alu_cr0__insn_type };
endcase
end
always @* begin
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_cyc;
wire \$97 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *)
wire \$99 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *)
input clk;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:28" *)
input [6:0] core_dbg_core_dbg_dststep;
wire [63:0] log_dmi_data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120" *)
wire [31:0] log_write_addr_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *)
input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135" *)
wire [63:0] stat_reg;
(* \nmigen.hierarchy = "test_issuer.ti.dec2" *)
(* generator = "nMigen" *)
-module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl, cur_cur_dststep, cur_cur_srcstep, cur_cur_vl, cur_cur_maxvl, raw_opcode_in, asmcode, rego, rego_ok, ea, ea_ok, reg1, reg1_ok, reg2, reg2_ok, reg3, reg3_ok, spro, spro_ok, spr1, spr1_ok, xer_in, xer_out, fast1, fast1_ok, fast2, fast2_ok, fast3, fast3_ok, fasto1, fasto1_ok, fasto2, fasto2_ok, fasto3, fasto3_ok, cr_in1, cr_in1_ok, cr_in2, cr_in2_ok, \cr_in2$1 , \cr_in2_ok$2 , cr_out, cr_out_ok, sv_pred_sz, sv_pred_dz, sv_saturate, SV_Ptype, msr, cia, svstate, insn, insn_type, fn_unit, lk, rc, rc_ok, oe, oe_ok, input_carry, traptype, exc_alignment, exc_instr_fault, exc_invalid, exc_badtree, exc_perm_error, exc_rc_error, exc_segment_fault, exc_happened, trapaddr, cr_rd, cr_rd_ok, cr_wr, cr_wr_ok, is_32bit, cur_eint);
+module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl, cur_cur_dststep, cur_cur_srcstep, cur_cur_vl, cur_cur_maxvl, raw_opcode_in, asmcode, rego, rego_ok, ea, ea_ok, reg1, reg1_ok, reg2, reg2_ok, reg3, reg3_ok, spro, spro_ok, spr1, spr1_ok, xer_in, xer_out, fast1, fast1_ok, fast2, fast2_ok, fast3, fast3_ok, fasto1, fasto1_ok, fasto2, fasto2_ok, fasto3, fasto3_ok, cr_in1, cr_in1_ok, cr_in2, cr_in2_ok, \cr_in2$1 , \cr_in2_ok$2 , cr_out, cr_out_ok, sv_pred_sz, sv_pred_dz, sv_saturate, sv_ldstmode, SV_Ptype, msr, cia, svstate, insn, insn_type, fn_unit, lk, rc, rc_ok, oe, oe_ok, input_carry, traptype, exc_alignment, exc_instr_fault, exc_invalid, exc_badtree, exc_perm_error, exc_rc_error, exc_segment_fault, exc_happened, trapaddr, cr_rd, cr_rd_ok, cr_wr, cr_wr_ok, is_32bit, cur_eint);
reg \initial = 0;
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1357" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1364" *)
wire \$11 ;
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1369" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1376" *)
wire \$13 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *)
wire \$16 ;
wire \$62 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [6:0] \$69 ;
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1356" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1363" *)
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [6:0] \$71 ;
wire [6:0] \$81 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [6:0] \$83 ;
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1274" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1281" *)
wire \$85 ;
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1276" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1283" *)
wire \$87 ;
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1278" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1285" *)
wire \$89 ;
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1357" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1364" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1282" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1289" *)
wire \$91 ;
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1305" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1312" *)
wire \$93 ;
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1306" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1313" *)
wire \$95 ;
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1307" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1314" *)
wire \$97 ;
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1308" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1315" *)
wire \$99 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:191" *)
wire [6:0] dec_internal_op;
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1300" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1307" *)
wire dec_irq_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:200" *)
wire dec_is_32b;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
output exc_segment_fault;
reg exc_segment_fault;
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1299" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1306" *)
wire ext_irq_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output [2:0] fast1;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:53" *)
output [14:0] fn_unit;
reg [14:0] fn_unit;
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1302" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1309" *)
wire illeg_ok;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output oe_ok;
reg oe_ok;
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1301" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1308" *)
wire priv_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:480" *)
input [31:0] raw_opcode_in;
reg spro_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:747" *)
wire sv_a_nz;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
+ output [1:0] sv_ldstmode;
+ reg [1:0] sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
output sv_pred_dz;
reg sv_pred_dz;
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
wire [1:0] tmp_tmp__SV_Ptype;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
+ wire [1:0] tmp_tmp__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
wire tmp_tmp__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:116" *)
output xer_out;
reg xer_out;
- assign \$9 = insn_type == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1357" *) 7'h49;
- assign \$99 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1308" *) 7'h00;
- assign \$11 = \$7 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1357" *) \$9 ;
- assign \$13 = insn_type == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1369" *) 7'h46;
+ assign \$9 = insn_type == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1364" *) 7'h49;
+ assign \$99 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1315" *) 7'h00;
+ assign \$11 = \$7 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1364" *) \$9 ;
+ assign \$13 = insn_type == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1376" *) 7'h46;
assign \$16 = dec_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) 15'h0400;
assign \$18 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) \$16 ;
assign \$20 = \$18 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) is_mmu_spr;
assign \$73 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *) dec_o_reg_o;
assign \$75 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *) dec_o2_reg_o2;
assign \$77 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *) dec_cr_in_cr_bitfield;
- assign \$7 = insn_type == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1356" *) 7'h3f;
+ assign \$7 = insn_type == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1363" *) 7'h3f;
assign \$79 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *) dec_cr_in_cr_bitfield_b;
assign \$81 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *) dec_cr_in_cr_bitfield_o;
assign \$83 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *) dec_cr_out_cr_bitfield;
- assign \$85 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1274" *) 7'h2e;
- assign \$87 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1276" *) 7'h0a;
- assign \$89 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1278" *) 7'h31;
- assign \$91 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1282" *) 7'h3f;
- assign \$93 = cur_eint & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1305" *) cur_msr[15];
- assign \$95 = cur_dec[63] & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1306" *) cur_msr[15];
- assign \$97 = is_priv_insn & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1307" *) cur_msr[14];
+ assign \$85 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1281" *) 7'h2e;
+ assign \$87 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1283" *) 7'h0a;
+ assign \$89 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1285" *) 7'h31;
+ assign \$91 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1289" *) 7'h3f;
+ assign \$93 = cur_eint & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1312" *) cur_msr[15];
+ assign \$95 = cur_dec[63] & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1313" *) cur_msr[15];
+ assign \$97 = is_priv_insn & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1314" *) cur_msr[14];
\dec$171 dec (
.BA(dec_BA),
.BB(dec_BB),
always @* begin
if (\initial ) begin end
tmp_tmp_lk = 1'h0;
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:948" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:951" *)
casez (dec_lk)
- /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:948" */
+ /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:951" */
1'h1:
tmp_tmp_lk = dec_LK;
endcase
always @* begin
if (\initial ) begin end
tmp_xer_in = 3'h0;
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1274" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1281" *)
casez (\$85 )
- /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1274" */
+ /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1281" */
1'h1:
tmp_xer_in = 3'h7;
endcase
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1276" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1283" *)
casez (\$87 )
- /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1276" */
+ /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1283" */
1'h1:
tmp_xer_in = 3'h1;
endcase
always @* begin
if (\initial ) begin end
tmp_xer_out = 1'h0;
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1278" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1285" *)
casez (\$89 )
- /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1278" */
+ /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1285" */
1'h1:
tmp_xer_out = 1'h1;
endcase
always @* begin
if (\initial ) begin end
tmp_tmp_trapaddr = 13'h0000;
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1282" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1289" *)
casez (\$91 )
- /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1282" */
+ /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1289" */
1'h1:
tmp_tmp_trapaddr = 13'h0070;
endcase
always @* begin
if (\initial ) begin end
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1312" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1319" *)
casez ({ illeg_ok, priv_ok, ext_irq_ok, dec_irq_ok, dec2_exc_happened })
- /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1312" */
+ /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1319" */
5'b????1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1313" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1320" *)
casez ({ dec2_exc_instr_fault, dec2_exc_alignment })
- /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1313" */
+ /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1320" */
2'b?1:
begin
- { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_ldstmode, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 407'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
insn = dec_opcode_in;
insn_type = 7'h3f;
fn_unit = 15'h0080;
cia = cur_pc;
svstate = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep };
end
- /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1315" */
+ /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1322" */
2'b1?:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1316" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1323" *)
casez (dec2_exc_segment_fault)
- /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1316" */
+ /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1323" */
1'h1:
begin
- { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_ldstmode, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 407'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
insn = dec_opcode_in;
insn_type = 7'h3f;
fn_unit = 15'h0080;
cia = cur_pc;
svstate = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep };
end
- /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1318" */
+ /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1325" */
default:
begin
- { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_ldstmode, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 407'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
insn = dec_opcode_in;
insn_type = 7'h3f;
fn_unit = 15'h0080;
svstate = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep };
end
endcase
- /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1321" */
+ /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1328" */
default:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1322" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1329" *)
casez (dec2_exc_segment_fault)
- /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1322" */
+ /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1329" */
1'h1:
begin
- { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_ldstmode, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 407'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
insn = dec_opcode_in;
insn_type = 7'h3f;
fn_unit = 15'h0080;
cia = cur_pc;
svstate = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep };
end
- /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1324" */
+ /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1331" */
default:
begin
- { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_ldstmode, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 407'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
insn = dec_opcode_in;
insn_type = 7'h3f;
fn_unit = 15'h0080;
end
endcase
endcase
- /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1328" */
+ /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1335" */
5'b???1?:
begin
- { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_ldstmode, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 407'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
insn = dec_opcode_in;
insn_type = 7'h3f;
fn_unit = 15'h0080;
cia = cur_pc;
svstate = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep };
end
- /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1332" */
+ /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1339" */
5'b??1??:
begin
- { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_ldstmode, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 407'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
insn = dec_opcode_in;
insn_type = 7'h3f;
fn_unit = 15'h0080;
cia = cur_pc;
svstate = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep };
end
- /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1336" */
+ /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1343" */
5'b?1???:
begin
- { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_ldstmode, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 407'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
insn = dec_opcode_in;
insn_type = 7'h3f;
fn_unit = 15'h0080;
cia = cur_pc;
svstate = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep };
end
- /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1343" */
+ /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1350" */
5'h1?:
begin
- { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_ldstmode, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 407'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
insn = dec_opcode_in;
insn_type = 7'h3f;
fn_unit = 15'h0080;
cia = cur_pc;
svstate = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep };
end
- /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1348" */
+ /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1355" */
default:
- { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = { tmp_tmp_is_32bit, tmp_tmp_cr_wr_ok, tmp_tmp_cr_wr, tmp_tmp_cr_rd_ok, tmp_tmp_cr_rd, tmp_tmp_trapaddr, tmp_tmp_exc_happened, tmp_tmp_exc_segment_fault, tmp_tmp_exc_rc_error, tmp_tmp_exc_perm_error, tmp_tmp_exc_badtree, tmp_tmp_exc_invalid, tmp_tmp_exc_instr_fault, tmp_tmp_exc_alignment, tmp_tmp_traptype, tmp_tmp_input_carry, tmp_tmp_oe_ok, tmp_tmp_oe, tmp_tmp_rc_ok, tmp_tmp_rc, tmp_tmp_lk, tmp_tmp_fn_unit, tmp_tmp_insn_type, tmp_tmp_insn, tmp_tmp_svstate, tmp_tmp_cia, tmp_tmp_msr, tmp_tmp__SV_Ptype, tmp_tmp__sv_saturate, tmp_tmp__sv_pred_dz, tmp_tmp__sv_pred_sz, tmp_cr_out_ok, tmp_cr_out, \tmp_cr_in2_ok$6 , \tmp_cr_in2$5 , tmp_cr_in2_ok, tmp_cr_in2, tmp_cr_in1_ok, tmp_cr_in1, tmp_fasto3_ok, tmp_fasto3, tmp_fasto2_ok, tmp_fasto2, tmp_fasto1_ok, tmp_fasto1, tmp_fast3_ok, tmp_fast3, tmp_fast2_ok, tmp_fast2, tmp_fast1_ok, tmp_fast1, tmp_xer_out, tmp_xer_in, tmp_spr1_ok, tmp_spr1, tmp_spro_ok, tmp_spro, tmp_reg3_ok, tmp_reg3, tmp_reg2_ok, tmp_reg2, tmp_reg1_ok, tmp_reg1, tmp_ea_ok, tmp_ea, tmp_rego_ok, tmp_rego, tmp_asmcode };
+ { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, exc_happened, exc_segment_fault, exc_rc_error, exc_perm_error, exc_badtree, exc_invalid, exc_instr_fault, exc_alignment, traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_ldstmode, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = { tmp_tmp_is_32bit, tmp_tmp_cr_wr_ok, tmp_tmp_cr_wr, tmp_tmp_cr_rd_ok, tmp_tmp_cr_rd, tmp_tmp_trapaddr, tmp_tmp_exc_happened, tmp_tmp_exc_segment_fault, tmp_tmp_exc_rc_error, tmp_tmp_exc_perm_error, tmp_tmp_exc_badtree, tmp_tmp_exc_invalid, tmp_tmp_exc_instr_fault, tmp_tmp_exc_alignment, tmp_tmp_traptype, tmp_tmp_input_carry, tmp_tmp_oe_ok, tmp_tmp_oe, tmp_tmp_rc_ok, tmp_tmp_rc, tmp_tmp_lk, tmp_tmp_fn_unit, tmp_tmp_insn_type, tmp_tmp_insn, tmp_tmp_svstate, tmp_tmp_cia, tmp_tmp_msr, tmp_tmp__SV_Ptype, tmp_tmp__sv_ldstmode, tmp_tmp__sv_saturate, tmp_tmp__sv_pred_dz, tmp_tmp__sv_pred_sz, tmp_cr_out_ok, tmp_cr_out, \tmp_cr_in2_ok$6 , \tmp_cr_in2$5 , tmp_cr_in2_ok, tmp_cr_in2, tmp_cr_in1_ok, tmp_cr_in1, tmp_fasto3_ok, tmp_fasto3, tmp_fasto2_ok, tmp_fasto2, tmp_fasto1_ok, tmp_fasto1, tmp_fast3_ok, tmp_fast3, tmp_fast2_ok, tmp_fast2, tmp_fast1_ok, tmp_fast1, tmp_xer_out, tmp_xer_in, tmp_spr1_ok, tmp_spr1, tmp_spro_ok, tmp_spro, tmp_reg3_ok, tmp_reg3, tmp_reg2_ok, tmp_reg2, tmp_reg1_ok, tmp_reg1, tmp_ea_ok, tmp_ea, tmp_rego_ok, tmp_rego, tmp_asmcode };
endcase
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1357" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1364" *)
casez (\$11 )
- /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1357" */
+ /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1364" */
1'h1:
begin
fasto1 = 3'h3;
fasto3_ok = 1'h1;
end
endcase
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1369" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1376" *)
casez (\$13 )
- /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1369" */
+ /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1376" */
1'h1:
begin
fast1 = 3'h3;
assign tmp_tmp__sv_pred_sz = 1'h0;
assign tmp_tmp__sv_pred_dz = 1'h0;
assign tmp_tmp__sv_saturate = 2'h0;
+ assign tmp_tmp__sv_ldstmode = 2'h0;
assign tmp_tmp__SV_Ptype = 2'h0;
assign tmp_tmp_traptype = 8'h00;
assign tmp_tmp_exc_alignment = 1'h0;
always @* begin
if (\initial ) begin end
BRANCH__lk = 1'h0;
- (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:948" *)
+ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:951" *)
casez (dec_BRANCH_lk)
- /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:948" */
+ /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:951" */
1'h1:
BRANCH__lk = dec_BRANCH_LK;
endcase
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0" *)
(* generator = "nMigen" *)
-module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__rc__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__oe__ok, oper_i_alu_div0__invert_in, oper_i_alu_div0__zero_a, oper_i_alu_div0__input_carry, oper_i_alu_div0__invert_out, oper_i_alu_div0__write_cr0, oper_i_alu_div0__output_carry, oper_i_alu_div0__is_32bit, oper_i_alu_div0__is_signed, oper_i_alu_div0__data_len, oper_i_alu_div0__insn, oper_i_alu_div0__sv_pred_sz, oper_i_alu_div0__sv_pred_dz, oper_i_alu_div0__sv_saturate, oper_i_alu_div0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, xer_ov_ok, dest3_o, xer_so_ok, dest4_o, coresync_clk);
+module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__rc__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__oe__ok, oper_i_alu_div0__invert_in, oper_i_alu_div0__zero_a, oper_i_alu_div0__input_carry, oper_i_alu_div0__invert_out, oper_i_alu_div0__write_cr0, oper_i_alu_div0__output_carry, oper_i_alu_div0__is_32bit, oper_i_alu_div0__is_signed, oper_i_alu_div0__data_len, oper_i_alu_div0__insn, oper_i_alu_div0__sv_pred_sz, oper_i_alu_div0__sv_pred_dz, oper_i_alu_div0__sv_saturate, oper_i_alu_div0__sv_ldstmode, oper_i_alu_div0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, xer_ov_ok, dest3_o, xer_so_ok, dest4_o, coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
wire \$10 ;
reg alu_div0_logical_op__rc__rc = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_div0_logical_op__rc__rc$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] alu_div0_logical_op__sv_ldstmode = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \alu_div0_logical_op__sv_ldstmode$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg alu_div0_logical_op__sv_pred_dz = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output cr_a_ok;
input oper_i_alu_div0__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_div0__rc__rc;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] oper_i_alu_div0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_div0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
alu_div0_logical_op__sv_pred_dz <= \alu_div0_logical_op__sv_pred_dz$next ;
always @(posedge coresync_clk)
alu_div0_logical_op__sv_saturate <= \alu_div0_logical_op__sv_saturate$next ;
+ always @(posedge coresync_clk)
+ alu_div0_logical_op__sv_ldstmode <= \alu_div0_logical_op__sv_ldstmode$next ;
always @(posedge coresync_clk)
alu_div0_logical_op__SV_Ptype <= \alu_div0_logical_op__SV_Ptype$next ;
always @(posedge coresync_clk)
.logical_op__output_carry(alu_div0_logical_op__output_carry),
.logical_op__rc__ok(alu_div0_logical_op__rc__ok),
.logical_op__rc__rc(alu_div0_logical_op__rc__rc),
+ .logical_op__sv_ldstmode(alu_div0_logical_op__sv_ldstmode),
.logical_op__sv_pred_dz(alu_div0_logical_op__sv_pred_dz),
.logical_op__sv_pred_sz(alu_div0_logical_op__sv_pred_sz),
.logical_op__sv_saturate(alu_div0_logical_op__sv_saturate),
\alu_div0_logical_op__sv_pred_sz$next = alu_div0_logical_op__sv_pred_sz;
\alu_div0_logical_op__sv_pred_dz$next = alu_div0_logical_op__sv_pred_dz;
\alu_div0_logical_op__sv_saturate$next = alu_div0_logical_op__sv_saturate;
+ \alu_div0_logical_op__sv_ldstmode$next = alu_div0_logical_op__sv_ldstmode;
\alu_div0_logical_op__SV_Ptype$next = alu_div0_logical_op__SV_Ptype;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *)
casez (cu_issue_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */
1'h1:
- { \alu_div0_logical_op__SV_Ptype$next , \alu_div0_logical_op__sv_saturate$next , \alu_div0_logical_op__sv_pred_dz$next , \alu_div0_logical_op__sv_pred_sz$next , \alu_div0_logical_op__insn$next , \alu_div0_logical_op__data_len$next , \alu_div0_logical_op__is_signed$next , \alu_div0_logical_op__is_32bit$next , \alu_div0_logical_op__output_carry$next , \alu_div0_logical_op__write_cr0$next , \alu_div0_logical_op__invert_out$next , \alu_div0_logical_op__input_carry$next , \alu_div0_logical_op__zero_a$next , \alu_div0_logical_op__invert_in$next , \alu_div0_logical_op__oe__ok$next , \alu_div0_logical_op__oe__oe$next , \alu_div0_logical_op__rc__ok$next , \alu_div0_logical_op__rc__rc$next , \alu_div0_logical_op__imm_data__ok$next , \alu_div0_logical_op__imm_data__data$next , \alu_div0_logical_op__fn_unit$next , \alu_div0_logical_op__insn_type$next } = { oper_i_alu_div0__SV_Ptype, oper_i_alu_div0__sv_saturate, oper_i_alu_div0__sv_pred_dz, oper_i_alu_div0__sv_pred_sz, oper_i_alu_div0__insn, oper_i_alu_div0__data_len, oper_i_alu_div0__is_signed, oper_i_alu_div0__is_32bit, oper_i_alu_div0__output_carry, oper_i_alu_div0__write_cr0, oper_i_alu_div0__invert_out, oper_i_alu_div0__input_carry, oper_i_alu_div0__zero_a, oper_i_alu_div0__invert_in, oper_i_alu_div0__oe__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__rc__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__fn_unit, oper_i_alu_div0__insn_type };
+ { \alu_div0_logical_op__SV_Ptype$next , \alu_div0_logical_op__sv_ldstmode$next , \alu_div0_logical_op__sv_saturate$next , \alu_div0_logical_op__sv_pred_dz$next , \alu_div0_logical_op__sv_pred_sz$next , \alu_div0_logical_op__insn$next , \alu_div0_logical_op__data_len$next , \alu_div0_logical_op__is_signed$next , \alu_div0_logical_op__is_32bit$next , \alu_div0_logical_op__output_carry$next , \alu_div0_logical_op__write_cr0$next , \alu_div0_logical_op__invert_out$next , \alu_div0_logical_op__input_carry$next , \alu_div0_logical_op__zero_a$next , \alu_div0_logical_op__invert_in$next , \alu_div0_logical_op__oe__ok$next , \alu_div0_logical_op__oe__oe$next , \alu_div0_logical_op__rc__ok$next , \alu_div0_logical_op__rc__rc$next , \alu_div0_logical_op__imm_data__ok$next , \alu_div0_logical_op__imm_data__data$next , \alu_div0_logical_op__fn_unit$next , \alu_div0_logical_op__insn_type$next } = { oper_i_alu_div0__SV_Ptype, oper_i_alu_div0__sv_ldstmode, oper_i_alu_div0__sv_saturate, oper_i_alu_div0__sv_pred_dz, oper_i_alu_div0__sv_pred_sz, oper_i_alu_div0__insn, oper_i_alu_div0__data_len, oper_i_alu_div0__is_signed, oper_i_alu_div0__is_32bit, oper_i_alu_div0__output_carry, oper_i_alu_div0__write_cr0, oper_i_alu_div0__invert_out, oper_i_alu_div0__input_carry, oper_i_alu_div0__zero_a, oper_i_alu_div0__invert_in, oper_i_alu_div0__oe__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__rc__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__fn_unit, oper_i_alu_div0__insn_type };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.dummy" *)
(* generator = "nMigen" *)
-module dummy(trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__svstate, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, trap_op__sv_pred_sz, trap_op__sv_pred_dz, trap_op__sv_saturate, trap_op__SV_Ptype, ra, rb, fast1, fast2, fast3, \muxid$1 , \trap_op__insn_type$2 , \trap_op__fn_unit$3 , \trap_op__insn$4 , \trap_op__msr$5 , \trap_op__cia$6 , \trap_op__svstate$7 , \trap_op__is_32bit$8 , \trap_op__traptype$9 , \trap_op__trapaddr$10 , \trap_op__ldst_exc$11 , \trap_op__sv_pred_sz$12 , \trap_op__sv_pred_dz$13 , \trap_op__sv_saturate$14 , \trap_op__SV_Ptype$15 , \ra$16 , \rb$17 , \fast1$18 , \fast2$19 , \fast3$20 , muxid);
+module dummy(trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__svstate, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, trap_op__sv_pred_sz, trap_op__sv_pred_dz, trap_op__sv_saturate, trap_op__sv_ldstmode, trap_op__SV_Ptype, ra, rb, fast1, fast2, fast3, \muxid$1 , \trap_op__insn_type$2 , \trap_op__fn_unit$3 , \trap_op__insn$4 , \trap_op__msr$5 , \trap_op__cia$6 , \trap_op__svstate$7 , \trap_op__is_32bit$8 , \trap_op__traptype$9 , \trap_op__trapaddr$10 , \trap_op__ldst_exc$11 , \trap_op__sv_pred_sz$12 , \trap_op__sv_pred_dz$13 , \trap_op__sv_saturate$14 , \trap_op__sv_ldstmode$15 , \trap_op__SV_Ptype$16 , \ra$17 , \rb$18 , \fast1$19 , \fast2$20 , \fast3$21 , muxid);
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] fast1;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output [63:0] \fast1$18 ;
+ output [63:0] \fast1$19 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] fast2;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output [63:0] \fast2$19 ;
+ output [63:0] \fast2$20 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] fast3;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output [63:0] \fast3$20 ;
+ output [63:0] \fast3$21 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
input [1:0] muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] ra;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output [63:0] \ra$16 ;
+ output [63:0] \ra$17 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] rb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output [63:0] \rb$17 ;
+ output [63:0] \rb$18 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \trap_op__SV_Ptype$15 ;
+ output [1:0] \trap_op__SV_Ptype$16 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] trap_op__cia;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] trap_op__msr;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output [63:0] \trap_op__msr$5 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] trap_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \trap_op__sv_ldstmode$15 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input trap_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [7:0] trap_op__traptype;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output [7:0] \trap_op__traptype$9 ;
- assign \fast3$20 = fast3;
- assign \fast2$19 = fast2;
- assign \fast1$18 = fast1;
- assign \rb$17 = rb;
- assign \ra$16 = ra;
- assign { \trap_op__SV_Ptype$15 , \trap_op__sv_saturate$14 , \trap_op__sv_pred_dz$13 , \trap_op__sv_pred_sz$12 , \trap_op__ldst_exc$11 , \trap_op__trapaddr$10 , \trap_op__traptype$9 , \trap_op__is_32bit$8 , \trap_op__svstate$7 , \trap_op__cia$6 , \trap_op__msr$5 , \trap_op__insn$4 , \trap_op__fn_unit$3 , \trap_op__insn_type$2 } = { trap_op__SV_Ptype, trap_op__sv_saturate, trap_op__sv_pred_dz, trap_op__sv_pred_sz, trap_op__ldst_exc, trap_op__trapaddr, trap_op__traptype, trap_op__is_32bit, trap_op__svstate, trap_op__cia, trap_op__msr, trap_op__insn, trap_op__fn_unit, trap_op__insn_type };
+ assign \fast3$21 = fast3;
+ assign \fast2$20 = fast2;
+ assign \fast1$19 = fast1;
+ assign \rb$18 = rb;
+ assign \ra$17 = ra;
+ assign { \trap_op__SV_Ptype$16 , \trap_op__sv_ldstmode$15 , \trap_op__sv_saturate$14 , \trap_op__sv_pred_dz$13 , \trap_op__sv_pred_sz$12 , \trap_op__ldst_exc$11 , \trap_op__trapaddr$10 , \trap_op__traptype$9 , \trap_op__is_32bit$8 , \trap_op__svstate$7 , \trap_op__cia$6 , \trap_op__msr$5 , \trap_op__insn$4 , \trap_op__fn_unit$3 , \trap_op__insn_type$2 } = { trap_op__SV_Ptype, trap_op__sv_ldstmode, trap_op__sv_saturate, trap_op__sv_pred_dz, trap_op__sv_pred_sz, trap_op__ldst_exc, trap_op__trapaddr, trap_op__traptype, trap_op__is_32bit, trap_op__svstate, trap_op__cia, trap_op__msr, trap_op__insn, trap_op__fn_unit, trap_op__insn_type };
assign \muxid$1 = muxid;
endmodule
(* generator = "nMigen" *)
module fast(coresync_rst, issue__addr, issue__ren, issue__data_o, \issue__addr$1 , issue__wen, issue__data_i, src1__data_o, src1__addr, src1__ren, dest1__data_i, dest1__addr, dest1__wen, coresync_clk);
reg \initial = 0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] dest1__addr;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:68" *)
input TAP_bus__tck;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:68" *)
input TAP_bus__tms;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" *)
output capture;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus" *)
(* generator = "nMigen" *)
-module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, exc_o_happened, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__data_len, oper_i_alu_alu0__insn, oper_i_alu_alu0__sv_pred_sz, oper_i_alu_alu0__sv_pred_dz, oper_i_alu_alu0__sv_saturate, oper_i_alu_alu0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, oper_i_alu_cr0__insn, oper_i_alu_cr0__sv_pred_sz, oper_i_alu_cr0__sv_pred_dz, oper_i_alu_cr0__sv_saturate, oper_i_alu_cr0__SV_Ptype, \cu_issue_i$1 , \cu_busy_o$2 , \cu_rdmaskn_i$3 , oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__lk, oper_i_alu_branch0__is_32bit, oper_i_alu_branch0__sv_pred_sz, oper_i_alu_branch0__sv_pred_dz, oper_i_alu_branch0__sv_saturate, oper_i_alu_branch0__SV_Ptype, \cu_issue_i$4 , \cu_busy_o$5 , \cu_rdmaskn_i$6 , oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_unit, oper_i_alu_trap0__insn, oper_i_alu_trap0__msr, oper_i_alu_trap0__cia, oper_i_alu_trap0__svstate, oper_i_alu_trap0__is_32bit, oper_i_alu_trap0__traptype, oper_i_alu_trap0__trapaddr, oper_i_alu_trap0__ldst_exc, oper_i_alu_trap0__sv_pred_sz, oper_i_alu_trap0__sv_pred_dz, oper_i_alu_trap0__sv_saturate, oper_i_alu_trap0__SV_Ptype, \cu_issue_i$7 , \cu_busy_o$8 , \cu_rdmaskn_i$9 , oper_i_alu_logical0__insn_type, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__data_len, oper_i_alu_logical0__insn, oper_i_alu_logical0__sv_pred_sz, oper_i_alu_logical0__sv_pred_dz, oper_i_alu_logical0__sv_saturate, oper_i_alu_logical0__SV_Ptype, \cu_issue_i$10 , \cu_busy_o$11 , \cu_rdmaskn_i$12 , oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, oper_i_alu_spr0__insn, oper_i_alu_spr0__is_32bit, oper_i_alu_spr0__sv_pred_sz, oper_i_alu_spr0__sv_pred_dz, oper_i_alu_spr0__sv_saturate, oper_i_alu_spr0__SV_Ptype, \cu_issue_i$13 , \cu_busy_o$14 , \cu_rdmaskn_i$15 , oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__rc__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__oe__ok, oper_i_alu_div0__invert_in, oper_i_alu_div0__zero_a, oper_i_alu_div0__input_carry, oper_i_alu_div0__invert_out, oper_i_alu_div0__write_cr0, oper_i_alu_div0__output_carry, oper_i_alu_div0__is_32bit, oper_i_alu_div0__is_signed, oper_i_alu_div0__data_len, oper_i_alu_div0__insn, oper_i_alu_div0__sv_pred_sz, oper_i_alu_div0__sv_pred_dz, oper_i_alu_div0__sv_saturate, oper_i_alu_div0__SV_Ptype, \cu_issue_i$16 , \cu_busy_o$17 , \cu_rdmaskn_i$18 , oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__insn, oper_i_alu_mul0__sv_pred_sz, oper_i_alu_mul0__sv_pred_dz, oper_i_alu_mul0__sv_saturate, oper_i_alu_mul0__SV_Ptype, \cu_issue_i$19 , \cu_busy_o$20 , \cu_rdmaskn_i$21 , oper_i_alu_shift_rot0__insn_type, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__insn, oper_i_alu_shift_rot0__sv_pred_sz, oper_i_alu_shift_rot0__sv_pred_dz, oper_i_alu_shift_rot0__sv_saturate, oper_i_alu_shift_rot0__SV_Ptype, \cu_issue_i$22 , \cu_busy_o$23 , \cu_rdmaskn_i$24 , oper_i_ldst_ldst0__insn_type, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__msr, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__insn, oper_i_ldst_ldst0__sv_pred_sz, oper_i_ldst_ldst0__sv_pred_dz, oper_i_ldst_ldst0__sv_saturate, oper_i_ldst_ldst0__SV_Ptype, \cu_issue_i$25 , \cu_busy_o$26 , \cu_rdmaskn_i$27 , cu_rd__rel_o, cu_rd__go_i, src2_i, \cu_rd__rel_o$28 , \cu_rd__go_i$29 , \src2_i$30 , \cu_rd__rel_o$31 , \cu_rd__go_i$32 , \src2_i$33 , \cu_rd__rel_o$34 , \cu_rd__go_i$35 , \src2_i$36 , \cu_rd__rel_o$37 , \cu_rd__go_i$38 , \src2_i$39 , \cu_rd__rel_o$40 , \cu_rd__go_i$41 , \src2_i$42 , \cu_rd__rel_o$43 , \cu_rd__go_i$44 , \src2_i$45 , \cu_rd__rel_o$46 , \cu_rd__go_i$47 , \src2_i$48 , src3_i, \src3_i$49 , src1_i, \src1_i$50 , \src1_i$51 , \src1_i$52 , \cu_rd__rel_o$53 , \cu_rd__go_i$54 , \src1_i$55 , \src1_i$56 , \src1_i$57 , \src1_i$58 , \src1_i$59 , \src3_i$60 , \src3_i$61 , src4_i, \src3_i$62 , \src3_i$63 , \src4_i$64 , \src4_i$65 , src6_i, src5_i, \src5_i$66 , \src3_i$67 , \src4_i$68 , \cu_rd__rel_o$69 , \cu_rd__go_i$70 , \src3_i$71 , \src5_i$72 , \src6_i$73 , \src1_i$74 , \src3_i$75 , \src3_i$76 , \src2_i$77 , \src4_i$78 , \src5_i$79 , \src2_i$80 , o_ok, cu_wr__rel_o, cu_wr__go_i, \o_ok$81 , \cu_wr__rel_o$82 , \cu_wr__go_i$83 , \o_ok$84 , \cu_wr__rel_o$85 , \cu_wr__go_i$86 , \o_ok$87 , \cu_wr__rel_o$88 , \cu_wr__go_i$89 , \o_ok$90 , \cu_wr__rel_o$91 , \cu_wr__go_i$92 , \o_ok$93 , \cu_wr__rel_o$94 , \cu_wr__go_i$95 , \o_ok$96 , \cu_wr__rel_o$97 , \cu_wr__go_i$98 , \o_ok$99 , \cu_wr__rel_o$100 , \cu_wr__go_i$101 , \cu_wr__rel_o$102 , \cu_wr__go_i$103 , dest1_o, \dest1_o$104 , \dest1_o$105 , \dest1_o$106 , \dest1_o$107 , \dest1_o$108 , \dest1_o$109 , \dest1_o$110 , o, ea, full_cr_ok, dest2_o, cr_a_ok, \cr_a_ok$111 , \cr_a_ok$112 , \cr_a_ok$113 , \cr_a_ok$114 , \cr_a_ok$115 , \dest2_o$116 , dest3_o, \dest2_o$117 , \dest2_o$118 , \dest2_o$119 , \dest2_o$120 , xer_ca_ok, \xer_ca_ok$121 , \xer_ca_ok$122 , \dest3_o$123 , dest6_o, \dest3_o$124 , xer_ov_ok, \xer_ov_ok$125 , \xer_ov_ok$126 , \xer_ov_ok$127 , dest4_o, dest5_o, \dest3_o$128 , \dest3_o$129 , xer_so_ok, \xer_so_ok$130 , \xer_so_ok$131 , \xer_so_ok$132 , \dest5_o$133 , \dest4_o$134 , \dest4_o$135 , \dest4_o$136 , fast1_ok, \cu_wr__rel_o$137 , \cu_wr__go_i$138 , \fast1_ok$139 , \fast1_ok$140 , fast2_ok, \fast2_ok$141 , fast3_ok, \dest1_o$142 , \dest2_o$143 , \dest3_o$144 , \dest2_o$145 , \dest3_o$146 , \dest4_o$147 , nia_ok, \nia_ok$148 , \dest3_o$149 , \dest5_o$150 , msr_ok, \dest6_o$151 , svstate_ok, dest7_o, spr1_ok, \dest2_o$152 , ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, ldst_port0_exc_alignment, ldst_port0_exc_instr_fault, ldst_port0_exc_invalid, ldst_port0_exc_badtree, ldst_port0_exc_perm_error, ldst_port0_exc_rc_error, ldst_port0_exc_segment_fault, ldst_port0_exc_happened, ldst_port0_addr_ok_o, ldst_port0_msr_pr, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, exc_o_happened, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__data_len, oper_i_alu_alu0__insn, oper_i_alu_alu0__sv_pred_sz, oper_i_alu_alu0__sv_pred_dz, oper_i_alu_alu0__sv_saturate, oper_i_alu_alu0__sv_ldstmode, oper_i_alu_alu0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, oper_i_alu_cr0__insn, oper_i_alu_cr0__sv_pred_sz, oper_i_alu_cr0__sv_pred_dz, oper_i_alu_cr0__sv_saturate, oper_i_alu_cr0__sv_ldstmode, oper_i_alu_cr0__SV_Ptype, \cu_issue_i$1 , \cu_busy_o$2 , \cu_rdmaskn_i$3 , oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__lk, oper_i_alu_branch0__is_32bit, oper_i_alu_branch0__sv_pred_sz, oper_i_alu_branch0__sv_pred_dz, oper_i_alu_branch0__sv_saturate, oper_i_alu_branch0__sv_ldstmode, oper_i_alu_branch0__SV_Ptype, \cu_issue_i$4 , \cu_busy_o$5 , \cu_rdmaskn_i$6 , oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_unit, oper_i_alu_trap0__insn, oper_i_alu_trap0__msr, oper_i_alu_trap0__cia, oper_i_alu_trap0__svstate, oper_i_alu_trap0__is_32bit, oper_i_alu_trap0__traptype, oper_i_alu_trap0__trapaddr, oper_i_alu_trap0__ldst_exc, oper_i_alu_trap0__sv_pred_sz, oper_i_alu_trap0__sv_pred_dz, oper_i_alu_trap0__sv_saturate, oper_i_alu_trap0__sv_ldstmode, oper_i_alu_trap0__SV_Ptype, \cu_issue_i$7 , \cu_busy_o$8 , \cu_rdmaskn_i$9 , oper_i_alu_logical0__insn_type, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__data_len, oper_i_alu_logical0__insn, oper_i_alu_logical0__sv_pred_sz, oper_i_alu_logical0__sv_pred_dz, oper_i_alu_logical0__sv_saturate, oper_i_alu_logical0__sv_ldstmode, oper_i_alu_logical0__SV_Ptype, \cu_issue_i$10 , \cu_busy_o$11 , \cu_rdmaskn_i$12 , oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, oper_i_alu_spr0__insn, oper_i_alu_spr0__is_32bit, oper_i_alu_spr0__sv_pred_sz, oper_i_alu_spr0__sv_pred_dz, oper_i_alu_spr0__sv_saturate, oper_i_alu_spr0__sv_ldstmode, oper_i_alu_spr0__SV_Ptype, \cu_issue_i$13 , \cu_busy_o$14 , \cu_rdmaskn_i$15 , oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__rc__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__oe__ok, oper_i_alu_div0__invert_in, oper_i_alu_div0__zero_a, oper_i_alu_div0__input_carry, oper_i_alu_div0__invert_out, oper_i_alu_div0__write_cr0, oper_i_alu_div0__output_carry, oper_i_alu_div0__is_32bit, oper_i_alu_div0__is_signed, oper_i_alu_div0__data_len, oper_i_alu_div0__insn, oper_i_alu_div0__sv_pred_sz, oper_i_alu_div0__sv_pred_dz, oper_i_alu_div0__sv_saturate, oper_i_alu_div0__sv_ldstmode, oper_i_alu_div0__SV_Ptype, \cu_issue_i$16 , \cu_busy_o$17 , \cu_rdmaskn_i$18 , oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__insn, oper_i_alu_mul0__sv_pred_sz, oper_i_alu_mul0__sv_pred_dz, oper_i_alu_mul0__sv_saturate, oper_i_alu_mul0__sv_ldstmode, oper_i_alu_mul0__SV_Ptype, \cu_issue_i$19 , \cu_busy_o$20 , \cu_rdmaskn_i$21 , oper_i_alu_shift_rot0__insn_type, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__insn, oper_i_alu_shift_rot0__sv_pred_sz, oper_i_alu_shift_rot0__sv_pred_dz, oper_i_alu_shift_rot0__sv_saturate, oper_i_alu_shift_rot0__sv_ldstmode, oper_i_alu_shift_rot0__SV_Ptype, \cu_issue_i$22 , \cu_busy_o$23 , \cu_rdmaskn_i$24 , oper_i_ldst_ldst0__insn_type, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__msr, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__insn, oper_i_ldst_ldst0__sv_pred_sz, oper_i_ldst_ldst0__sv_pred_dz, oper_i_ldst_ldst0__sv_saturate, oper_i_ldst_ldst0__sv_ldstmode, oper_i_ldst_ldst0__SV_Ptype, \cu_issue_i$25 , \cu_busy_o$26 , \cu_rdmaskn_i$27 , cu_rd__rel_o, cu_rd__go_i, src2_i, \cu_rd__rel_o$28 , \cu_rd__go_i$29 , \src2_i$30 , \cu_rd__rel_o$31 , \cu_rd__go_i$32 , \src2_i$33 , \cu_rd__rel_o$34 , \cu_rd__go_i$35 , \src2_i$36 , \cu_rd__rel_o$37 , \cu_rd__go_i$38 , \src2_i$39 , \cu_rd__rel_o$40 , \cu_rd__go_i$41 , \src2_i$42 , \cu_rd__rel_o$43 , \cu_rd__go_i$44 , \src2_i$45 , \cu_rd__rel_o$46 , \cu_rd__go_i$47 , \src2_i$48 , src3_i, \src3_i$49 , src1_i, \src1_i$50 , \src1_i$51 , \src1_i$52 , \cu_rd__rel_o$53 , \cu_rd__go_i$54 , \src1_i$55 , \src1_i$56 , \src1_i$57 , \src1_i$58 , \src1_i$59 , \src3_i$60 , \src3_i$61 , src4_i, \src3_i$62 , \src3_i$63 , \src4_i$64 , \src4_i$65 , src6_i, src5_i, \src5_i$66 , \src3_i$67 , \src4_i$68 , \cu_rd__rel_o$69 , \cu_rd__go_i$70 , \src3_i$71 , \src5_i$72 , \src6_i$73 , \src1_i$74 , \src3_i$75 , \src3_i$76 , \src2_i$77 , \src4_i$78 , \src5_i$79 , \src2_i$80 , o_ok, cu_wr__rel_o, cu_wr__go_i, \o_ok$81 , \cu_wr__rel_o$82 , \cu_wr__go_i$83 , \o_ok$84 , \cu_wr__rel_o$85 , \cu_wr__go_i$86 , \o_ok$87 , \cu_wr__rel_o$88 , \cu_wr__go_i$89 , \o_ok$90 , \cu_wr__rel_o$91 , \cu_wr__go_i$92 , \o_ok$93 , \cu_wr__rel_o$94 , \cu_wr__go_i$95 , \o_ok$96 , \cu_wr__rel_o$97 , \cu_wr__go_i$98 , \o_ok$99 , \cu_wr__rel_o$100 , \cu_wr__go_i$101 , \cu_wr__rel_o$102 , \cu_wr__go_i$103 , dest1_o, \dest1_o$104 , \dest1_o$105 , \dest1_o$106 , \dest1_o$107 , \dest1_o$108 , \dest1_o$109 , \dest1_o$110 , o, ea, full_cr_ok, dest2_o, cr_a_ok, \cr_a_ok$111 , \cr_a_ok$112 , \cr_a_ok$113 , \cr_a_ok$114 , \cr_a_ok$115 , \dest2_o$116 , dest3_o, \dest2_o$117 , \dest2_o$118 , \dest2_o$119 , \dest2_o$120 , xer_ca_ok, \xer_ca_ok$121 , \xer_ca_ok$122 , \dest3_o$123 , dest6_o, \dest3_o$124 , xer_ov_ok, \xer_ov_ok$125 , \xer_ov_ok$126 , \xer_ov_ok$127 , dest4_o, dest5_o, \dest3_o$128 , \dest3_o$129 , xer_so_ok, \xer_so_ok$130 , \xer_so_ok$131 , \xer_so_ok$132 , \dest5_o$133 , \dest4_o$134 , \dest4_o$135 , \dest4_o$136 , fast1_ok, \cu_wr__rel_o$137 , \cu_wr__go_i$138 , \fast1_ok$139 , \fast1_ok$140 , fast2_ok, \fast2_ok$141 , fast3_ok, \dest1_o$142 , \dest2_o$143 , \dest3_o$144 , \dest2_o$145 , \dest3_o$146 , \dest4_o$147 , nia_ok, \nia_ok$148 , \dest3_o$149 , \dest5_o$150 , msr_ok, \dest6_o$151 , svstate_ok, dest7_o, spr1_ok, \dest2_o$152 , ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, ldst_port0_exc_alignment, ldst_port0_exc_instr_fault, ldst_port0_exc_invalid, ldst_port0_exc_badtree, ldst_port0_exc_perm_error, ldst_port0_exc_rc_error, ldst_port0_exc_segment_fault, ldst_port0_exc_happened, ldst_port0_addr_ok_o, ldst_port0_msr_pr, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, coresync_clk);
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output cr_a_ok;
input oper_i_alu_alu0__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_alu0__rc__rc;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] oper_i_alu_alu0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_alu0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_branch0__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_branch0__lk;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] oper_i_alu_branch0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_branch0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [6:0] oper_i_alu_cr0__insn_type;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] oper_i_alu_cr0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_cr0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_div0__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_div0__rc__rc;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] oper_i_alu_div0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_div0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_logical0__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_logical0__rc__rc;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] oper_i_alu_logical0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_logical0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_mul0__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_mul0__rc__rc;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] oper_i_alu_mul0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_mul0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_shift_rot0__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_shift_rot0__rc__rc;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] oper_i_alu_shift_rot0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_shift_rot0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [6:0] oper_i_alu_spr0__insn_type;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_spr0__is_32bit;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] oper_i_alu_spr0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_spr0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [7:0] oper_i_alu_trap0__ldst_exc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] oper_i_alu_trap0__msr;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] oper_i_alu_trap0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_trap0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_ldst_ldst0__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_ldst_ldst0__sign_extend;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] oper_i_ldst_ldst0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_ldst_ldst0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
.oper_i_alu_alu0__output_carry(oper_i_alu_alu0__output_carry),
.oper_i_alu_alu0__rc__ok(oper_i_alu_alu0__rc__ok),
.oper_i_alu_alu0__rc__rc(oper_i_alu_alu0__rc__rc),
+ .oper_i_alu_alu0__sv_ldstmode(oper_i_alu_alu0__sv_ldstmode),
.oper_i_alu_alu0__sv_pred_dz(oper_i_alu_alu0__sv_pred_dz),
.oper_i_alu_alu0__sv_pred_sz(oper_i_alu_alu0__sv_pred_sz),
.oper_i_alu_alu0__sv_saturate(oper_i_alu_alu0__sv_saturate),
.oper_i_alu_branch0__insn_type(oper_i_alu_branch0__insn_type),
.oper_i_alu_branch0__is_32bit(oper_i_alu_branch0__is_32bit),
.oper_i_alu_branch0__lk(oper_i_alu_branch0__lk),
+ .oper_i_alu_branch0__sv_ldstmode(oper_i_alu_branch0__sv_ldstmode),
.oper_i_alu_branch0__sv_pred_dz(oper_i_alu_branch0__sv_pred_dz),
.oper_i_alu_branch0__sv_pred_sz(oper_i_alu_branch0__sv_pred_sz),
.oper_i_alu_branch0__sv_saturate(oper_i_alu_branch0__sv_saturate),
.oper_i_alu_cr0__fn_unit(oper_i_alu_cr0__fn_unit),
.oper_i_alu_cr0__insn(oper_i_alu_cr0__insn),
.oper_i_alu_cr0__insn_type(oper_i_alu_cr0__insn_type),
+ .oper_i_alu_cr0__sv_ldstmode(oper_i_alu_cr0__sv_ldstmode),
.oper_i_alu_cr0__sv_pred_dz(oper_i_alu_cr0__sv_pred_dz),
.oper_i_alu_cr0__sv_pred_sz(oper_i_alu_cr0__sv_pred_sz),
.oper_i_alu_cr0__sv_saturate(oper_i_alu_cr0__sv_saturate),
.oper_i_alu_div0__output_carry(oper_i_alu_div0__output_carry),
.oper_i_alu_div0__rc__ok(oper_i_alu_div0__rc__ok),
.oper_i_alu_div0__rc__rc(oper_i_alu_div0__rc__rc),
+ .oper_i_alu_div0__sv_ldstmode(oper_i_alu_div0__sv_ldstmode),
.oper_i_alu_div0__sv_pred_dz(oper_i_alu_div0__sv_pred_dz),
.oper_i_alu_div0__sv_pred_sz(oper_i_alu_div0__sv_pred_sz),
.oper_i_alu_div0__sv_saturate(oper_i_alu_div0__sv_saturate),
.oper_i_ldst_ldst0__rc__ok(oper_i_ldst_ldst0__rc__ok),
.oper_i_ldst_ldst0__rc__rc(oper_i_ldst_ldst0__rc__rc),
.oper_i_ldst_ldst0__sign_extend(oper_i_ldst_ldst0__sign_extend),
+ .oper_i_ldst_ldst0__sv_ldstmode(oper_i_ldst_ldst0__sv_ldstmode),
.oper_i_ldst_ldst0__sv_pred_dz(oper_i_ldst_ldst0__sv_pred_dz),
.oper_i_ldst_ldst0__sv_pred_sz(oper_i_ldst_ldst0__sv_pred_sz),
.oper_i_ldst_ldst0__sv_saturate(oper_i_ldst_ldst0__sv_saturate),
.oper_i_alu_logical0__output_carry(oper_i_alu_logical0__output_carry),
.oper_i_alu_logical0__rc__ok(oper_i_alu_logical0__rc__ok),
.oper_i_alu_logical0__rc__rc(oper_i_alu_logical0__rc__rc),
+ .oper_i_alu_logical0__sv_ldstmode(oper_i_alu_logical0__sv_ldstmode),
.oper_i_alu_logical0__sv_pred_dz(oper_i_alu_logical0__sv_pred_dz),
.oper_i_alu_logical0__sv_pred_sz(oper_i_alu_logical0__sv_pred_sz),
.oper_i_alu_logical0__sv_saturate(oper_i_alu_logical0__sv_saturate),
.oper_i_alu_mul0__oe__ok(oper_i_alu_mul0__oe__ok),
.oper_i_alu_mul0__rc__ok(oper_i_alu_mul0__rc__ok),
.oper_i_alu_mul0__rc__rc(oper_i_alu_mul0__rc__rc),
+ .oper_i_alu_mul0__sv_ldstmode(oper_i_alu_mul0__sv_ldstmode),
.oper_i_alu_mul0__sv_pred_dz(oper_i_alu_mul0__sv_pred_dz),
.oper_i_alu_mul0__sv_pred_sz(oper_i_alu_mul0__sv_pred_sz),
.oper_i_alu_mul0__sv_saturate(oper_i_alu_mul0__sv_saturate),
.oper_i_alu_shift_rot0__output_cr(oper_i_alu_shift_rot0__output_cr),
.oper_i_alu_shift_rot0__rc__ok(oper_i_alu_shift_rot0__rc__ok),
.oper_i_alu_shift_rot0__rc__rc(oper_i_alu_shift_rot0__rc__rc),
+ .oper_i_alu_shift_rot0__sv_ldstmode(oper_i_alu_shift_rot0__sv_ldstmode),
.oper_i_alu_shift_rot0__sv_pred_dz(oper_i_alu_shift_rot0__sv_pred_dz),
.oper_i_alu_shift_rot0__sv_pred_sz(oper_i_alu_shift_rot0__sv_pred_sz),
.oper_i_alu_shift_rot0__sv_saturate(oper_i_alu_shift_rot0__sv_saturate),
.oper_i_alu_spr0__insn(oper_i_alu_spr0__insn),
.oper_i_alu_spr0__insn_type(oper_i_alu_spr0__insn_type),
.oper_i_alu_spr0__is_32bit(oper_i_alu_spr0__is_32bit),
+ .oper_i_alu_spr0__sv_ldstmode(oper_i_alu_spr0__sv_ldstmode),
.oper_i_alu_spr0__sv_pred_dz(oper_i_alu_spr0__sv_pred_dz),
.oper_i_alu_spr0__sv_pred_sz(oper_i_alu_spr0__sv_pred_sz),
.oper_i_alu_spr0__sv_saturate(oper_i_alu_spr0__sv_saturate),
.oper_i_alu_trap0__is_32bit(oper_i_alu_trap0__is_32bit),
.oper_i_alu_trap0__ldst_exc(oper_i_alu_trap0__ldst_exc),
.oper_i_alu_trap0__msr(oper_i_alu_trap0__msr),
+ .oper_i_alu_trap0__sv_ldstmode(oper_i_alu_trap0__sv_ldstmode),
.oper_i_alu_trap0__sv_pred_dz(oper_i_alu_trap0__sv_pred_dz),
.oper_i_alu_trap0__sv_pred_sz(oper_i_alu_trap0__sv_pred_sz),
.oper_i_alu_trap0__sv_saturate(oper_i_alu_trap0__sv_saturate),
wire \$3 ;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:391" *)
wire \$5 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:68" *)
input TAP_bus__tdi;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:241" *)
reg [31:0] TAP_id_sr = 32'd0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_idx_l;
(* \nmigen.hierarchy = "test_issuer.ti.imem" *)
(* generator = "nMigen" *)
-module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en, ibus__cyc, ibus__ack, ibus__err, ibus__stb, ibus__sel, ibus__dat_r, ibus__adr, clk);
+module imem(coresync_rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en, ibus__cyc, ibus__ack, ibus__err, ibus__stb, ibus__sel, ibus__dat_r, ibus__adr, coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *)
wire \$1 ;
wire a_stall_i;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" *)
input a_valid_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
- input clk;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
+ input coresync_clk;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
+ input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" *)
reg [44:0] f_badaddr_o = 45'h000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" *)
reg [63:0] ibus_rdata = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" *)
reg [63:0] \ibus_rdata$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
- input rst;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:98" *)
input wb_icache_en;
assign \$9 = \$5 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) \$7 ;
assign \$11 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) a_stall_i;
assign \$51 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" *) f_stall_i;
assign \$5 = ibus__ack | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) ibus__err;
assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) f_valid_i;
- always @(posedge clk)
+ always @(posedge coresync_clk)
f_badaddr_o <= \f_badaddr_o$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
f_fetch_err_o <= \f_fetch_err_o$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
ibus__adr <= \ibus__adr$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
ibus_rdata <= \ibus_rdata$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
ibus__sel <= \ibus__sel$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
ibus__stb <= \ibus__stb$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
ibus__cyc <= \ibus__cyc$next ;
always @* begin
if (\initial ) begin end
endcase
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (rst)
+ casez (coresync_rst)
1'h1:
\ibus__cyc$next = 1'h0;
endcase
endcase
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (rst)
+ casez (coresync_rst)
1'h1:
\ibus__stb$next = 1'h0;
endcase
endcase
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (rst)
+ casez (coresync_rst)
1'h1:
\ibus__sel$next = 8'h00;
endcase
endcase
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (rst)
+ casez (coresync_rst)
1'h1:
\ibus_rdata$next = 64'h0000000000000000;
endcase
endcase
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (rst)
+ casez (coresync_rst)
1'h1:
\ibus__adr$next = 45'h000000000000;
endcase
endcase
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (rst)
+ casez (coresync_rst)
1'h1:
\f_fetch_err_o$next = 1'h0;
endcase
endcase
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (rst)
+ casez (coresync_rst)
1'h1:
\f_badaddr_o$next = 45'h000000000000;
endcase
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.input" *)
(* generator = "nMigen" *)
-module \input (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, alu_op__sv_pred_sz, alu_op__sv_pred_dz, alu_op__sv_saturate, alu_op__SV_Ptype, ra, rb, xer_so, xer_ca, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , \alu_op__sv_pred_sz$20 , \alu_op__sv_pred_dz$21 , \alu_op__sv_saturate$22 , \alu_op__SV_Ptype$23 , \ra$24 , \rb$25 , \xer_so$26 , \xer_ca$27 , muxid);
+module \input (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, alu_op__sv_pred_sz, alu_op__sv_pred_dz, alu_op__sv_saturate, alu_op__sv_ldstmode, alu_op__SV_Ptype, ra, rb, xer_so, xer_ca, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , \alu_op__sv_pred_sz$20 , \alu_op__sv_pred_dz$21 , \alu_op__sv_saturate$22 , \alu_op__sv_ldstmode$23 , \alu_op__SV_Ptype$24 , \ra$25 , \rb$26 , \xer_so$27 , \xer_ca$28 , muxid);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *)
- wire [63:0] \$28 ;
+ wire [63:0] \$29 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *)
- wire \$30 ;
+ wire \$31 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *)
- wire \$32 ;
+ wire \$33 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" *)
reg [63:0] a;
(* enum_base_type = "SVPtype" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \alu_op__SV_Ptype$23 ;
+ output [1:0] \alu_op__SV_Ptype$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [3:0] alu_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \alu_op__rc__rc$6 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] alu_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \alu_op__sv_ldstmode$23 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] ra;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output [63:0] \ra$24 ;
- reg [63:0] \ra$24 ;
+ output [63:0] \ra$25 ;
+ reg [63:0] \ra$25 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] rb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output [63:0] \rb$25 ;
- reg [63:0] \rb$25 ;
+ output [63:0] \rb$26 ;
+ reg [63:0] \rb$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [1:0] xer_ca;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output [1:0] \xer_ca$27 ;
- reg [1:0] \xer_ca$27 ;
+ output [1:0] \xer_ca$28 ;
+ reg [1:0] \xer_ca$28 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input xer_so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output \xer_so$26 ;
- assign \$28 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) ra;
- assign \$30 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *) alu_op__sv_pred_sz;
- assign \$32 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *) alu_op__sv_pred_sz;
+ output \xer_so$27 ;
+ assign \$29 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) ra;
+ assign \$31 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *) alu_op__sv_pred_sz;
+ assign \$33 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *) alu_op__sv_pred_sz;
always @* begin
if (\initial ) begin end
(* full_case = 32'd1 *)
casez (alu_op__invert_in)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" */
1'h1:
- a = \$28 ;
+ a = \$29 ;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:29" */
default:
a = ra;
end
always @* begin
if (\initial ) begin end
- \ra$24 = 64'h0000000000000000;
+ \ra$25 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *)
- casez (\$30 )
+ casez (\$31 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" */
1'h1:
- \ra$24 = a;
+ \ra$25 = a;
endcase
end
always @* begin
if (\initial ) begin end
- \rb$25 = rb;
+ \rb$26 = rb;
end
always @* begin
if (\initial ) begin end
- \xer_ca$27 = 2'h0;
+ \xer_ca$28 = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:59" *)
casez (alu_op__input_carry)
/* \nmigen.decoding = "ZERO/0" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:60" */
2'h0:
- \xer_ca$27 = 2'h0;
+ \xer_ca$28 = 2'h0;
/* \nmigen.decoding = "ONE/1" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:62" */
2'h1:
- \xer_ca$27 = 2'h3;
+ \xer_ca$28 = 2'h3;
/* \nmigen.decoding = "CA/2" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:64" */
2'h2:
- \xer_ca$27 = xer_ca;
+ \xer_ca$28 = xer_ca;
endcase
end
- assign { \alu_op__SV_Ptype$23 , \alu_op__sv_saturate$22 , \alu_op__sv_pred_dz$21 , \alu_op__sv_pred_sz$20 , \alu_op__insn$19 , \alu_op__data_len$18 , \alu_op__is_signed$17 , \alu_op__is_32bit$16 , \alu_op__output_carry$15 , \alu_op__input_carry$14 , \alu_op__write_cr0$13 , \alu_op__invert_out$12 , \alu_op__zero_a$11 , \alu_op__invert_in$10 , \alu_op__oe__ok$9 , \alu_op__oe__oe$8 , \alu_op__rc__ok$7 , \alu_op__rc__rc$6 , \alu_op__imm_data__ok$5 , \alu_op__imm_data__data$4 , \alu_op__fn_unit$3 , \alu_op__insn_type$2 } = { alu_op__SV_Ptype, alu_op__sv_saturate, alu_op__sv_pred_dz, alu_op__sv_pred_sz, alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type };
+ assign { \alu_op__SV_Ptype$24 , \alu_op__sv_ldstmode$23 , \alu_op__sv_saturate$22 , \alu_op__sv_pred_dz$21 , \alu_op__sv_pred_sz$20 , \alu_op__insn$19 , \alu_op__data_len$18 , \alu_op__is_signed$17 , \alu_op__is_32bit$16 , \alu_op__output_carry$15 , \alu_op__input_carry$14 , \alu_op__write_cr0$13 , \alu_op__invert_out$12 , \alu_op__zero_a$11 , \alu_op__invert_in$10 , \alu_op__oe__ok$9 , \alu_op__oe__oe$8 , \alu_op__rc__ok$7 , \alu_op__rc__rc$6 , \alu_op__imm_data__ok$5 , \alu_op__imm_data__data$4 , \alu_op__fn_unit$3 , \alu_op__insn_type$2 } = { alu_op__SV_Ptype, alu_op__sv_ldstmode, alu_op__sv_saturate, alu_op__sv_pred_dz, alu_op__sv_pred_sz, alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type };
assign \muxid$1 = muxid;
- assign \xer_so$26 = xer_so;
+ assign \xer_so$27 = xer_so;
assign b = rb;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.input" *)
(* generator = "nMigen" *)
-module \input$113 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, sr_op__sv_pred_sz, sr_op__sv_pred_dz, sr_op__sv_saturate, sr_op__SV_Ptype, ra, rb, rc, xer_so, xer_ca, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , \sr_op__sv_pred_sz$19 , \sr_op__sv_pred_dz$20 , \sr_op__sv_saturate$21 , \sr_op__SV_Ptype$22 , \ra$23 , \rb$24 , \rc$25 , \xer_so$26 , \xer_ca$27 , muxid);
+module \input$113 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, sr_op__sv_pred_sz, sr_op__sv_pred_dz, sr_op__sv_saturate, sr_op__sv_ldstmode, sr_op__SV_Ptype, ra, rb, rc, xer_so, xer_ca, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , \sr_op__sv_pred_sz$19 , \sr_op__sv_pred_dz$20 , \sr_op__sv_saturate$21 , \sr_op__sv_ldstmode$22 , \sr_op__SV_Ptype$23 , \ra$24 , \rb$25 , \rc$26 , \xer_so$27 , \xer_ca$28 , muxid);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *)
- wire [63:0] \$28 ;
+ wire [63:0] \$29 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *)
- wire \$30 ;
+ wire \$31 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *)
- wire \$32 ;
+ wire \$33 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" *)
reg [63:0] a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:41" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] ra;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output [63:0] \ra$23 ;
- reg [63:0] \ra$23 ;
+ output [63:0] \ra$24 ;
+ reg [63:0] \ra$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] rb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output [63:0] \rb$24 ;
- reg [63:0] \rb$24 ;
+ output [63:0] \rb$25 ;
+ reg [63:0] \rb$25 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output [63:0] \rc$25 ;
+ output [63:0] \rc$26 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \sr_op__SV_Ptype$22 ;
+ output [1:0] \sr_op__SV_Ptype$23 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
input sr_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \sr_op__rc__rc$6 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] sr_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \sr_op__sv_ldstmode$22 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [1:0] xer_ca;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output [1:0] \xer_ca$27 ;
- reg [1:0] \xer_ca$27 ;
+ output [1:0] \xer_ca$28 ;
+ reg [1:0] \xer_ca$28 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input xer_so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output \xer_so$26 ;
- assign \$28 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) ra;
- assign \$30 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *) sr_op__sv_pred_sz;
- assign \$32 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *) sr_op__sv_pred_sz;
+ output \xer_so$27 ;
+ assign \$29 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) ra;
+ assign \$31 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *) sr_op__sv_pred_sz;
+ assign \$33 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *) sr_op__sv_pred_sz;
always @* begin
if (\initial ) begin end
(* full_case = 32'd1 *)
casez (sr_op__invert_in)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" */
1'h1:
- a = \$28 ;
+ a = \$29 ;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:29" */
default:
a = ra;
end
always @* begin
if (\initial ) begin end
- \ra$23 = 64'h0000000000000000;
+ \ra$24 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *)
- casez (\$30 )
+ casez (\$31 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" */
1'h1:
- \ra$23 = a;
+ \ra$24 = a;
endcase
end
always @* begin
if (\initial ) begin end
- \rb$24 = 64'h0000000000000000;
+ \rb$25 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *)
- casez (\$32 )
+ casez (\$33 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" */
1'h1:
- \rb$24 = b;
+ \rb$25 = b;
endcase
end
always @* begin
if (\initial ) begin end
- \xer_ca$27 = 2'h0;
+ \xer_ca$28 = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:59" *)
casez (sr_op__input_carry)
/* \nmigen.decoding = "ZERO/0" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:60" */
2'h0:
- \xer_ca$27 = 2'h0;
+ \xer_ca$28 = 2'h0;
/* \nmigen.decoding = "ONE/1" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:62" */
2'h1:
- \xer_ca$27 = 2'h3;
+ \xer_ca$28 = 2'h3;
/* \nmigen.decoding = "CA/2" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:64" */
2'h2:
- \xer_ca$27 = xer_ca;
+ \xer_ca$28 = xer_ca;
endcase
end
- assign \rc$25 = rc;
- assign { \sr_op__SV_Ptype$22 , \sr_op__sv_saturate$21 , \sr_op__sv_pred_dz$20 , \sr_op__sv_pred_sz$19 , \sr_op__insn$18 , \sr_op__is_signed$17 , \sr_op__is_32bit$16 , \sr_op__output_cr$15 , \sr_op__input_cr$14 , \sr_op__output_carry$13 , \sr_op__input_carry$12 , \sr_op__invert_in$11 , \sr_op__write_cr0$10 , \sr_op__oe__ok$9 , \sr_op__oe__oe$8 , \sr_op__rc__ok$7 , \sr_op__rc__rc$6 , \sr_op__imm_data__ok$5 , \sr_op__imm_data__data$4 , \sr_op__fn_unit$3 , \sr_op__insn_type$2 } = { sr_op__SV_Ptype, sr_op__sv_saturate, sr_op__sv_pred_dz, sr_op__sv_pred_sz, sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type };
+ assign \rc$26 = rc;
+ assign { \sr_op__SV_Ptype$23 , \sr_op__sv_ldstmode$22 , \sr_op__sv_saturate$21 , \sr_op__sv_pred_dz$20 , \sr_op__sv_pred_sz$19 , \sr_op__insn$18 , \sr_op__is_signed$17 , \sr_op__is_32bit$16 , \sr_op__output_cr$15 , \sr_op__input_cr$14 , \sr_op__output_carry$13 , \sr_op__input_carry$12 , \sr_op__invert_in$11 , \sr_op__write_cr0$10 , \sr_op__oe__ok$9 , \sr_op__oe__oe$8 , \sr_op__rc__ok$7 , \sr_op__rc__rc$6 , \sr_op__imm_data__ok$5 , \sr_op__imm_data__data$4 , \sr_op__fn_unit$3 , \sr_op__insn_type$2 } = { sr_op__SV_Ptype, sr_op__sv_ldstmode, sr_op__sv_saturate, sr_op__sv_pred_dz, sr_op__sv_pred_sz, sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type };
assign \muxid$1 = muxid;
- assign \xer_so$26 = xer_so;
+ assign \xer_so$27 = xer_so;
assign b = rb;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.input" *)
(* generator = "nMigen" *)
-module \input$50 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, ra, rb, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__SV_Ptype$23 , \ra$24 , \rb$25 , \xer_so$26 , muxid);
+module \input$50 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__sv_ldstmode, logical_op__SV_Ptype, ra, rb, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__sv_ldstmode$23 , \logical_op__SV_Ptype$24 , \ra$25 , \rb$26 , \xer_so$27 , muxid);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *)
- wire \$27 ;
+ wire \$28 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:45" *)
- wire [63:0] \$29 ;
+ wire [63:0] \$30 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *)
- wire \$31 ;
+ wire \$32 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" *)
wire [63:0] a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:41" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \logical_op__SV_Ptype$23 ;
+ output [1:0] \logical_op__SV_Ptype$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [3:0] logical_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__rc__rc$6 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] logical_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \logical_op__sv_ldstmode$23 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] ra;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output [63:0] \ra$24 ;
- reg [63:0] \ra$24 ;
+ output [63:0] \ra$25 ;
+ reg [63:0] \ra$25 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] rb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output [63:0] \rb$25 ;
- reg [63:0] \rb$25 ;
+ output [63:0] \rb$26 ;
+ reg [63:0] \rb$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input xer_so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output \xer_so$26 ;
- assign \$27 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *) logical_op__sv_pred_sz;
- assign \$29 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:45" *) rb;
- assign \$31 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *) logical_op__sv_pred_sz;
+ output \xer_so$27 ;
+ assign \$28 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *) logical_op__sv_pred_sz;
+ assign \$30 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:45" *) rb;
+ assign \$32 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *) logical_op__sv_pred_sz;
always @* begin
if (\initial ) begin end
- \ra$24 = 64'h0000000000000000;
+ \ra$25 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *)
- casez (\$27 )
+ casez (\$28 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" */
1'h1:
- \ra$24 = a;
+ \ra$25 = a;
endcase
end
always @* begin
casez (logical_op__invert_in)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:44" */
1'h1:
- b = \$29 ;
+ b = \$30 ;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:46" */
default:
b = rb;
end
always @* begin
if (\initial ) begin end
- \rb$25 = 64'h0000000000000000;
+ \rb$26 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *)
- casez (\$31 )
+ casez (\$32 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" */
1'h1:
- \rb$25 = b;
+ \rb$26 = b;
endcase
end
- assign { \logical_op__SV_Ptype$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__SV_Ptype, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
+ assign { \logical_op__SV_Ptype$24 , \logical_op__sv_ldstmode$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__SV_Ptype, logical_op__sv_ldstmode, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
assign \muxid$1 = muxid;
- assign \xer_so$26 = xer_so;
+ assign \xer_so$27 = xer_so;
assign a = ra;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.input" *)
(* generator = "nMigen" *)
-module \input$78 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, ra, rb, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__SV_Ptype$23 , \ra$24 , \rb$25 , \xer_so$26 , muxid);
+module \input$78 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__sv_ldstmode, logical_op__SV_Ptype, ra, rb, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__sv_ldstmode$23 , \logical_op__SV_Ptype$24 , \ra$25 , \rb$26 , \xer_so$27 , muxid);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *)
- wire [63:0] \$27 ;
+ wire [63:0] \$28 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *)
- wire \$29 ;
+ wire \$30 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *)
- wire \$31 ;
+ wire \$32 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" *)
reg [63:0] a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:41" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \logical_op__SV_Ptype$23 ;
+ output [1:0] \logical_op__SV_Ptype$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [3:0] logical_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__rc__rc$6 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] logical_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \logical_op__sv_ldstmode$23 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] ra;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output [63:0] \ra$24 ;
- reg [63:0] \ra$24 ;
+ output [63:0] \ra$25 ;
+ reg [63:0] \ra$25 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] rb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output [63:0] \rb$25 ;
- reg [63:0] \rb$25 ;
+ output [63:0] \rb$26 ;
+ reg [63:0] \rb$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input xer_so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output \xer_so$26 ;
- assign \$27 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) ra;
- assign \$29 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *) logical_op__sv_pred_sz;
- assign \$31 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *) logical_op__sv_pred_sz;
+ output \xer_so$27 ;
+ assign \$28 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) ra;
+ assign \$30 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *) logical_op__sv_pred_sz;
+ assign \$32 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *) logical_op__sv_pred_sz;
always @* begin
if (\initial ) begin end
(* full_case = 32'd1 *)
casez (logical_op__invert_in)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" */
1'h1:
- a = \$27 ;
+ a = \$28 ;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:29" */
default:
a = ra;
end
always @* begin
if (\initial ) begin end
- \ra$24 = 64'h0000000000000000;
+ \ra$25 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *)
- casez (\$29 )
+ casez (\$30 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" */
1'h1:
- \ra$24 = a;
+ \ra$25 = a;
endcase
end
always @* begin
if (\initial ) begin end
- \rb$25 = rb;
+ \rb$26 = rb;
end
- assign { \logical_op__SV_Ptype$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__SV_Ptype, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
+ assign { \logical_op__SV_Ptype$24 , \logical_op__sv_ldstmode$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__SV_Ptype, logical_op__sv_ldstmode, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
assign \muxid$1 = muxid;
- assign \xer_so$26 = xer_so;
+ assign \xer_so$27 = xer_so;
assign b = rb;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.input" *)
(* generator = "nMigen" *)
-module \input$95 (mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__SV_Ptype, ra, rb, xer_so, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \mul_op__sv_pred_sz$14 , \mul_op__sv_pred_dz$15 , \mul_op__sv_saturate$16 , \mul_op__SV_Ptype$17 , \ra$18 , \rb$19 , \xer_so$20 , muxid);
+module \input$95 (mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__sv_ldstmode, mul_op__SV_Ptype, ra, rb, xer_so, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \mul_op__sv_pred_sz$14 , \mul_op__sv_pred_dz$15 , \mul_op__sv_saturate$16 , \mul_op__sv_ldstmode$17 , \mul_op__SV_Ptype$18 , \ra$19 , \rb$20 , \xer_so$21 , muxid);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *)
- wire \$21 ;
+ wire \$22 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *)
- wire \$23 ;
+ wire \$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" *)
wire [63:0] a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:41" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \mul_op__SV_Ptype$17 ;
+ output [1:0] \mul_op__SV_Ptype$18 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
input mul_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \mul_op__rc__rc$6 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] mul_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \mul_op__sv_ldstmode$17 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] ra;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output [63:0] \ra$18 ;
- reg [63:0] \ra$18 ;
+ output [63:0] \ra$19 ;
+ reg [63:0] \ra$19 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] rb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output [63:0] \rb$19 ;
- reg [63:0] \rb$19 ;
+ output [63:0] \rb$20 ;
+ reg [63:0] \rb$20 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input xer_so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output \xer_so$20 ;
- assign \$21 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *) mul_op__sv_pred_sz;
- assign \$23 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *) mul_op__sv_pred_sz;
+ output \xer_so$21 ;
+ assign \$22 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *) mul_op__sv_pred_sz;
+ assign \$24 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *) mul_op__sv_pred_sz;
always @* begin
if (\initial ) begin end
- \ra$18 = 64'h0000000000000000;
+ \ra$19 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *)
- casez (\$21 )
+ casez (\$22 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" */
1'h1:
- \ra$18 = a;
+ \ra$19 = a;
endcase
end
always @* begin
if (\initial ) begin end
- \rb$19 = rb;
+ \rb$20 = rb;
end
- assign { \mul_op__SV_Ptype$17 , \mul_op__sv_saturate$16 , \mul_op__sv_pred_dz$15 , \mul_op__sv_pred_sz$14 , \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 } = { mul_op__SV_Ptype, mul_op__sv_saturate, mul_op__sv_pred_dz, mul_op__sv_pred_sz, mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type };
+ assign { \mul_op__SV_Ptype$18 , \mul_op__sv_ldstmode$17 , \mul_op__sv_saturate$16 , \mul_op__sv_pred_dz$15 , \mul_op__sv_pred_sz$14 , \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 } = { mul_op__SV_Ptype, mul_op__sv_ldstmode, mul_op__sv_saturate, mul_op__sv_pred_dz, mul_op__sv_pred_sz, mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type };
assign \muxid$1 = muxid;
- assign \xer_so$20 = xer_so;
+ assign \xer_so$21 = xer_so;
assign b = rb;
assign a = ra;
endmodule
(* generator = "nMigen" *)
module \int (coresync_rst, dmi__addr, dmi__ren, dmi__data_o, src1__data_o, src1__addr, src1__ren, dest1__data_i, dest1__addr, dest1__wen, coresync_clk);
reg \initial = 0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [4:0] dest1__addr;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:373" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:68" *)
input TAP_bus__tdi;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" *)
input capture;
wire \$97 ;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *)
wire \$99 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:68" *)
input TAP_bus__tck;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:68" *)
input TAP_bus__tdi;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:68" *)
output TAP_bus__tdo;
reg TAP_bus__tdo;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:68" *)
input TAP_bus__tms;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:420" *)
reg TAP_tdo;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *)
input clk;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *)
input dmi0__ack_o;
reg dmi0_datasr_update_core_prev = 1'h0;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *)
reg \dmi0_datasr_update_core_prev$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output eint_0__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input eint_0__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output eint_1__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input eint_1__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output eint_2__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input eint_2__pad__i;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" *)
wire fsm_capture;
reg [2:0] \fsm_state$next ;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" *)
wire fsm_update;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e10__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e10__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e10__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e10__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e10__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e10__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e11__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e11__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e11__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e11__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e11__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e11__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e12__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e12__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e12__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e12__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e12__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e12__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e13__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e13__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e13__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e13__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e13__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e13__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e14__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e14__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e14__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e14__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e14__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e14__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e15__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e15__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e15__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e15__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e15__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e15__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e8__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e8__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e8__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e8__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e8__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e8__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e9__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e9__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e9__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e9__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e9__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e9__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s0__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s0__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s0__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s0__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s0__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s0__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s1__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s1__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s1__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s1__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s1__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s1__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s2__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s2__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s2__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s2__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s2__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s2__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s3__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s3__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s3__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s3__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s3__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s3__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s4__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s4__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s4__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s4__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s4__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s4__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s5__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s5__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s5__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s5__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s5__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s5__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s6__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s6__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s6__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s6__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s6__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s6__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s7__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s7__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s7__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s7__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s7__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s7__pad__oe;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:230" *)
wire idblock_TAP_id_tdo;
reg jtag_wb_datasr_update_core_prev = 1'h0;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *)
reg \jtag_wb_datasr_update_core_prev$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input mspi0_clk__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output mspi0_clk__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input mspi0_cs_n__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output mspi0_cs_n__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output mspi0_miso__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input mspi0_miso__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input mspi0_mosi__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output mspi0_mosi__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input mtwi_scl__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output mtwi_scl__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output mtwi_sda__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input mtwi_sda__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input mtwi_sda__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input mtwi_sda__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output mtwi_sda__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output mtwi_sda__pad__oe;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" *)
wire negjtag_clk;
wire posjtag_clk;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *)
wire posjtag_rst;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *)
input rst;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_0__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_0__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_10__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_10__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_11__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_11__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_12__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_12__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_1__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_1__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_2__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_2__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_3__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_3__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_4__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_4__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_5__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_5__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_6__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_6__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_7__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_7__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_8__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_8__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_9__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_9__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_ba_0__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_ba_0__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_ba_1__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_ba_1__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_cas_n__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_cas_n__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_cke__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_cke__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_clock__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_clock__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_cs_n__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_cs_n__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dm_0__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dm_0__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dm_1__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dm_1__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_0__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_0__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_0__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_0__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_0__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_0__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_10__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_10__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_10__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_10__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_10__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_10__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_11__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_11__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_11__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_11__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_11__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_11__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_12__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_12__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_12__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_12__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_12__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_12__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_13__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_13__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_13__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_13__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_13__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_13__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_14__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_14__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_14__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_14__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_14__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_14__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_15__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_15__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_15__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_15__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_15__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_15__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_1__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_1__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_1__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_1__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_1__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_1__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_2__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_2__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_2__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_2__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_2__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_2__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_3__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_3__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_3__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_3__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_3__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_3__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_4__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_4__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_4__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_4__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_4__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_4__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_5__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_5__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_5__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_5__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_5__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_5__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_6__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_6__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_6__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_6__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_6__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_6__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_7__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_7__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_7__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_7__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_7__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_7__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_8__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_8__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_8__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_8__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_8__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_8__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_9__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_9__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_9__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_9__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_9__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_9__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_ras_n__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_ras_n__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_we_n__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_we_n__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:81" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:83" *)
wire [2:0] sr0__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:81" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:83" *)
wire [2:0] sr0__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:81" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:83" *)
reg sr0__oe = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:81" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:83" *)
reg \sr0__oe$next ;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *)
wire sr0_capture;
reg sr0_update_core_prev = 1'h0;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *)
reg \sr0_update_core_prev$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:99" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:104" *)
reg [2:0] sr5__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:99" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:104" *)
wire sr5__ie;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:99" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:104" *)
wire [2:0] sr5__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:99" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:104" *)
reg sr5__oe = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:99" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:104" *)
reg \sr5__oe$next ;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *)
wire sr5_capture;
reg sr5_update_core_prev = 1'h0;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:669" *)
reg \sr5_update_core_prev$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:99" *)
output wb_dcache_en;
reg wb_dcache_en = 1'h1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:99" *)
reg \wb_dcache_en$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:98" *)
output wb_icache_en;
reg wb_icache_en = 1'h1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:98" *)
reg \wb_icache_en$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:100" *)
output wb_sram_en;
reg wb_sram_en = 1'h1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:100" *)
reg \wb_sram_en$next ;
assign \$9 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" *) 4'hf;
assign \$99 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:603" *) io_bd[24] : sdr_dq_6__core__o;
\wb_icache_en$next = wb_icache_en;
\wb_dcache_en$next = wb_dcache_en;
\wb_sram_en$next = wb_sram_en;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:108" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:113" *)
casez (sr5__oe)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:108" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:113" */
1'h1:
{ \wb_sram_en$next , \wb_dcache_en$next , \wb_icache_en$next } = sr5__o;
endcase
always @* begin
if (\initial ) begin end
sr5__i = 3'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:111" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:116" *)
casez (sr5__ie)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:111" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:116" */
1'h1:
sr5__i = { wb_sram_en, wb_dcache_en, wb_icache_en };
endcase
(* \nmigen.hierarchy = "test_issuer.ti.core.l0" *)
(* generator = "nMigen" *)
module l0(coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, ldst_port0_exc_alignment, ldst_port0_exc_instr_fault, ldst_port0_exc_invalid, ldst_port0_exc_badtree, ldst_port0_exc_perm_error, ldst_port0_exc_rc_error, ldst_port0_exc_segment_fault, ldst_port0_exc_happened, ldst_port0_addr_ok_o, ldst_port0_msr_pr, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, wb_dcache_en, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
input dbus__ack;
wire pimem_x_st_i;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" *)
wire pimem_x_valid_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:99" *)
input wb_dcache_en;
\l0$130 l0 (
.coresync_clk(coresync_clk),
wire [95:0] \$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:138" *)
wire [95:0] \$27 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
reg \idx_l$16 = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.ldst0" *)
(* generator = "nMigen" *)
-module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, exc_o_happened, oper_i_ldst_ldst0__insn_type, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__msr, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__insn, oper_i_ldst_ldst0__sv_pred_sz, oper_i_ldst_ldst0__sv_pred_dz, oper_i_ldst_ldst0__sv_saturate, oper_i_ldst_ldst0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src3_i, src1_i, cu_wr__rel_o, cu_wr__go_i, o, ea, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, ldst_port0_exc_alignment, ldst_port0_exc_instr_fault, ldst_port0_exc_invalid, ldst_port0_exc_badtree, ldst_port0_exc_perm_error, ldst_port0_exc_rc_error, ldst_port0_exc_segment_fault, ldst_port0_exc_happened, ldst_port0_addr_ok_o, ldst_port0_msr_pr, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, coresync_clk);
+module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, exc_o_happened, oper_i_ldst_ldst0__insn_type, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__msr, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__insn, oper_i_ldst_ldst0__sv_pred_sz, oper_i_ldst_ldst0__sv_pred_dz, oper_i_ldst_ldst0__sv_saturate, oper_i_ldst_ldst0__sv_ldstmode, oper_i_ldst_ldst0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src3_i, src1_i, cu_wr__rel_o, cu_wr__go_i, o, ea, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, ldst_port0_exc_alignment, ldst_port0_exc_instr_fault, ldst_port0_exc_invalid, ldst_port0_exc_badtree, ldst_port0_exc_perm_error, ldst_port0_exc_rc_error, ldst_port0_exc_segment_fault, ldst_port0_exc_happened, ldst_port0_addr_ok_o, ldst_port0_msr_pr, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" *)
wire \$1 ;
wire alu_valid;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:452" *)
wire cancel;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
input cu_ad__go_i;
input oper_i_ldst_ldst0__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_ldst_ldst0__sign_extend;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] oper_i_ldst_ldst0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_ldst_ldst0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg oper_r__sign_extend = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \oper_r__sign_extend$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] oper_r__sv_ldstmode = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \oper_r__sv_ldstmode$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg oper_r__sv_pred_dz = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
oper_r__sv_pred_dz <= \oper_r__sv_pred_dz$next ;
always @(posedge coresync_clk)
oper_r__sv_saturate <= \oper_r__sv_saturate$next ;
+ always @(posedge coresync_clk)
+ oper_r__sv_ldstmode <= \oper_r__sv_ldstmode$next ;
always @(posedge coresync_clk)
oper_r__SV_Ptype <= \oper_r__SV_Ptype$next ;
always @(posedge coresync_clk)
.r_wri(wri_l_r_wri),
.s_wri(wri_l_s_wri)
);
+ always @* begin
+ if (\initial ) begin end
+ (* full_case = 32'd1 *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:512" *)
+ casez (oper_r__byte_reverse)
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:512" */
+ 1'h1:
+ revnorev = lddata_r;
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:517" */
+ default:
+ revnorev = ldst_port0_ld_data_o;
+ endcase
+ end
always @* begin
if (\initial ) begin end
(* full_case = 32'd1 *)
\oper_r__sv_pred_sz$next = oper_r__sv_pred_sz;
\oper_r__sv_pred_dz$next = oper_r__sv_pred_dz;
\oper_r__sv_saturate$next = oper_r__sv_saturate;
+ \oper_r__sv_ldstmode$next = oper_r__sv_ldstmode;
\oper_r__SV_Ptype$next = oper_r__SV_Ptype;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:385" *)
casez (cu_issue_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:385" */
1'h1:
- { \oper_r__SV_Ptype$next , \oper_r__sv_saturate$next , \oper_r__sv_pred_dz$next , \oper_r__sv_pred_sz$next , \oper_r__insn$next , \oper_r__ldst_mode$next , \oper_r__sign_extend$next , \oper_r__byte_reverse$next , \oper_r__data_len$next , \oper_r__is_signed$next , \oper_r__is_32bit$next , \oper_r__msr$next , \oper_r__oe__ok$next , \oper_r__oe__oe$next , \oper_r__rc__ok$next , \oper_r__rc__rc$next , \oper_r__zero_a$next , \oper_r__imm_data__ok$next , \oper_r__imm_data__data$next , \oper_r__fn_unit$next , \oper_r__insn_type$next } = { oper_i_ldst_ldst0__SV_Ptype, oper_i_ldst_ldst0__sv_saturate, oper_i_ldst_ldst0__sv_pred_dz, oper_i_ldst_ldst0__sv_pred_sz, oper_i_ldst_ldst0__insn, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__msr, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__insn_type };
+ { \oper_r__SV_Ptype$next , \oper_r__sv_ldstmode$next , \oper_r__sv_saturate$next , \oper_r__sv_pred_dz$next , \oper_r__sv_pred_sz$next , \oper_r__insn$next , \oper_r__ldst_mode$next , \oper_r__sign_extend$next , \oper_r__byte_reverse$next , \oper_r__data_len$next , \oper_r__is_signed$next , \oper_r__is_32bit$next , \oper_r__msr$next , \oper_r__oe__ok$next , \oper_r__oe__oe$next , \oper_r__rc__ok$next , \oper_r__rc__rc$next , \oper_r__zero_a$next , \oper_r__imm_data__ok$next , \oper_r__imm_data__data$next , \oper_r__fn_unit$next , \oper_r__insn_type$next } = { oper_i_ldst_ldst0__SV_Ptype, oper_i_ldst_ldst0__sv_ldstmode, oper_i_ldst_ldst0__sv_saturate, oper_i_ldst_ldst0__sv_pred_dz, oper_i_ldst_ldst0__sv_pred_sz, oper_i_ldst_ldst0__insn, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__msr, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__insn_type };
endcase
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:387" *)
casez (cu_done_o)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:387" */
1'h1:
- { \oper_r__SV_Ptype$next , \oper_r__sv_saturate$next , \oper_r__sv_pred_dz$next , \oper_r__sv_pred_sz$next , \oper_r__insn$next , \oper_r__ldst_mode$next , \oper_r__sign_extend$next , \oper_r__byte_reverse$next , \oper_r__data_len$next , \oper_r__is_signed$next , \oper_r__is_32bit$next , \oper_r__msr$next , \oper_r__oe__ok$next , \oper_r__oe__oe$next , \oper_r__rc__ok$next , \oper_r__rc__rc$next , \oper_r__zero_a$next , \oper_r__imm_data__ok$next , \oper_r__imm_data__data$next , \oper_r__fn_unit$next , \oper_r__insn_type$next } = 204'h000000000000000000000000000000000000000000000000000;
+ { \oper_r__SV_Ptype$next , \oper_r__sv_ldstmode$next , \oper_r__sv_saturate$next , \oper_r__sv_pred_dz$next , \oper_r__sv_pred_sz$next , \oper_r__insn$next , \oper_r__ldst_mode$next , \oper_r__sign_extend$next , \oper_r__byte_reverse$next , \oper_r__data_len$next , \oper_r__is_signed$next , \oper_r__is_32bit$next , \oper_r__msr$next , \oper_r__oe__ok$next , \oper_r__oe__oe$next , \oper_r__rc__ok$next , \oper_r__rc__rc$next , \oper_r__zero_a$next , \oper_r__imm_data__ok$next , \oper_r__imm_data__data$next , \oper_r__fn_unit$next , \oper_r__insn_type$next } = 206'h0000000000000000000000000000000000000000000000000000;
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
endcase
endcase
end
- always @* begin
- if (\initial ) begin end
- (* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:512" *)
- casez (oper_r__byte_reverse)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:512" */
- 1'h1:
- revnorev = lddata_r;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:517" */
- default:
- revnorev = ldst_port0_ld_data_o;
- endcase
- end
assign \$31 = \$48 ;
assign \$66 = \$67 ;
assign \$161 = \$164 ;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0" *)
(* generator = "nMigen" *)
-module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__data_len, oper_i_alu_logical0__insn, oper_i_alu_logical0__sv_pred_sz, oper_i_alu_logical0__sv_pred_dz, oper_i_alu_logical0__sv_saturate, oper_i_alu_logical0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, coresync_clk);
+module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__data_len, oper_i_alu_logical0__insn, oper_i_alu_logical0__sv_pred_sz, oper_i_alu_logical0__sv_pred_dz, oper_i_alu_logical0__sv_saturate, oper_i_alu_logical0__sv_ldstmode, oper_i_alu_logical0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *)
wire \$1 ;
reg alu_logical0_logical_op__rc__rc = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_logical0_logical_op__rc__rc$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] alu_logical0_logical_op__sv_ldstmode = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \alu_logical0_logical_op__sv_ldstmode$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg alu_logical0_logical_op__sv_pred_dz = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output cr_a_ok;
input oper_i_alu_logical0__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_logical0__rc__rc;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] oper_i_alu_logical0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_logical0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
alu_logical0_logical_op__sv_pred_dz <= \alu_logical0_logical_op__sv_pred_dz$next ;
always @(posedge coresync_clk)
alu_logical0_logical_op__sv_saturate <= \alu_logical0_logical_op__sv_saturate$next ;
+ always @(posedge coresync_clk)
+ alu_logical0_logical_op__sv_ldstmode <= \alu_logical0_logical_op__sv_ldstmode$next ;
always @(posedge coresync_clk)
alu_logical0_logical_op__SV_Ptype <= \alu_logical0_logical_op__SV_Ptype$next ;
always @(posedge coresync_clk)
.logical_op__output_carry(alu_logical0_logical_op__output_carry),
.logical_op__rc__ok(alu_logical0_logical_op__rc__ok),
.logical_op__rc__rc(alu_logical0_logical_op__rc__rc),
+ .logical_op__sv_ldstmode(alu_logical0_logical_op__sv_ldstmode),
.logical_op__sv_pred_dz(alu_logical0_logical_op__sv_pred_dz),
.logical_op__sv_pred_sz(alu_logical0_logical_op__sv_pred_sz),
.logical_op__sv_saturate(alu_logical0_logical_op__sv_saturate),
\alu_logical0_logical_op__sv_pred_sz$next = alu_logical0_logical_op__sv_pred_sz;
\alu_logical0_logical_op__sv_pred_dz$next = alu_logical0_logical_op__sv_pred_dz;
\alu_logical0_logical_op__sv_saturate$next = alu_logical0_logical_op__sv_saturate;
+ \alu_logical0_logical_op__sv_ldstmode$next = alu_logical0_logical_op__sv_ldstmode;
\alu_logical0_logical_op__SV_Ptype$next = alu_logical0_logical_op__SV_Ptype;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *)
casez (cu_issue_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */
1'h1:
- { \alu_logical0_logical_op__SV_Ptype$next , \alu_logical0_logical_op__sv_saturate$next , \alu_logical0_logical_op__sv_pred_dz$next , \alu_logical0_logical_op__sv_pred_sz$next , \alu_logical0_logical_op__insn$next , \alu_logical0_logical_op__data_len$next , \alu_logical0_logical_op__is_signed$next , \alu_logical0_logical_op__is_32bit$next , \alu_logical0_logical_op__output_carry$next , \alu_logical0_logical_op__write_cr0$next , \alu_logical0_logical_op__invert_out$next , \alu_logical0_logical_op__input_carry$next , \alu_logical0_logical_op__zero_a$next , \alu_logical0_logical_op__invert_in$next , \alu_logical0_logical_op__oe__ok$next , \alu_logical0_logical_op__oe__oe$next , \alu_logical0_logical_op__rc__ok$next , \alu_logical0_logical_op__rc__rc$next , \alu_logical0_logical_op__imm_data__ok$next , \alu_logical0_logical_op__imm_data__data$next , \alu_logical0_logical_op__fn_unit$next , \alu_logical0_logical_op__insn_type$next } = { oper_i_alu_logical0__SV_Ptype, oper_i_alu_logical0__sv_saturate, oper_i_alu_logical0__sv_pred_dz, oper_i_alu_logical0__sv_pred_sz, oper_i_alu_logical0__insn, oper_i_alu_logical0__data_len, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__insn_type };
+ { \alu_logical0_logical_op__SV_Ptype$next , \alu_logical0_logical_op__sv_ldstmode$next , \alu_logical0_logical_op__sv_saturate$next , \alu_logical0_logical_op__sv_pred_dz$next , \alu_logical0_logical_op__sv_pred_sz$next , \alu_logical0_logical_op__insn$next , \alu_logical0_logical_op__data_len$next , \alu_logical0_logical_op__is_signed$next , \alu_logical0_logical_op__is_32bit$next , \alu_logical0_logical_op__output_carry$next , \alu_logical0_logical_op__write_cr0$next , \alu_logical0_logical_op__invert_out$next , \alu_logical0_logical_op__input_carry$next , \alu_logical0_logical_op__zero_a$next , \alu_logical0_logical_op__invert_in$next , \alu_logical0_logical_op__oe__ok$next , \alu_logical0_logical_op__oe__oe$next , \alu_logical0_logical_op__rc__ok$next , \alu_logical0_logical_op__rc__rc$next , \alu_logical0_logical_op__imm_data__ok$next , \alu_logical0_logical_op__imm_data__data$next , \alu_logical0_logical_op__fn_unit$next , \alu_logical0_logical_op__insn_type$next } = { oper_i_alu_logical0__SV_Ptype, oper_i_alu_logical0__sv_ldstmode, oper_i_alu_logical0__sv_saturate, oper_i_alu_logical0__sv_pred_dz, oper_i_alu_logical0__sv_pred_sz, oper_i_alu_logical0__insn, oper_i_alu_logical0__data_len, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__insn_type };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1" *)
(* generator = "nMigen" *)
-module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, o, o_ok, cr_a, cr_a_ok, xer_so, xer_so_ok, p_valid_i, p_ready_o, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__SV_Ptype$23 , ra, rb, \xer_so$24 , coresync_clk);
+module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__sv_ldstmode, logical_op__SV_Ptype, o, o_ok, cr_a, cr_a_ok, xer_so, xer_so_ok, p_valid_i, p_ready_o, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__sv_ldstmode$23 , \logical_op__SV_Ptype$24 , ra, rb, \xer_so$25 , coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
- wire \$76 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ wire \$79 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output [3:0] cr_a;
reg [3:0] cr_a = 4'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [3:0] \cr_a$103 ;
+ wire [3:0] \cr_a$107 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [3:0] \cr_a$105 ;
+ wire [3:0] \cr_a$109 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg [3:0] \cr_a$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output cr_a_ok;
reg cr_a_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \cr_a_ok$104 ;
+ wire \cr_a_ok$108 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \cr_a_ok$106 ;
+ wire \cr_a_ok$110 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \cr_a_ok$next ;
(* enum_base_type = "SVPtype" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \input_logical_op__SV_Ptype$47 ;
+ wire [1:0] \input_logical_op__SV_Ptype$49 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [3:0] input_logical_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [3:0] \input_logical_op__data_len$42 ;
+ wire [3:0] \input_logical_op__data_len$43 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \input_logical_op__fn_unit$27 ;
+ wire [14:0] \input_logical_op__fn_unit$28 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] input_logical_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \input_logical_op__imm_data__data$28 ;
+ wire [63:0] \input_logical_op__imm_data__data$29 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__imm_data__ok$29 ;
+ wire \input_logical_op__imm_data__ok$30 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \input_logical_op__input_carry$36 ;
+ wire [1:0] \input_logical_op__input_carry$37 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] input_logical_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \input_logical_op__insn$43 ;
+ wire [31:0] \input_logical_op__insn$44 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \input_logical_op__insn_type$26 ;
+ wire [6:0] \input_logical_op__insn_type$27 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__invert_in$34 ;
+ wire \input_logical_op__invert_in$35 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__invert_out;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__invert_out$37 ;
+ wire \input_logical_op__invert_out$38 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__is_32bit$40 ;
+ wire \input_logical_op__is_32bit$41 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__is_signed$41 ;
+ wire \input_logical_op__is_signed$42 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__oe__oe$32 ;
+ wire \input_logical_op__oe__oe$33 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__oe__ok$33 ;
+ wire \input_logical_op__oe__ok$34 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__output_carry;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__output_carry$39 ;
+ wire \input_logical_op__output_carry$40 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__rc__ok$31 ;
+ wire \input_logical_op__rc__ok$32 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__rc__rc$30 ;
+ wire \input_logical_op__rc__rc$31 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] input_logical_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \input_logical_op__sv_ldstmode$48 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__sv_pred_dz$45 ;
+ wire \input_logical_op__sv_pred_dz$46 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__sv_pred_sz$44 ;
+ wire \input_logical_op__sv_pred_sz$45 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \input_logical_op__sv_saturate$46 ;
+ wire [1:0] \input_logical_op__sv_saturate$47 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__write_cr0$38 ;
+ wire \input_logical_op__write_cr0$39 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__zero_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__zero_a$35 ;
+ wire \input_logical_op__zero_a$36 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] input_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \input_muxid$25 ;
+ wire [1:0] \input_muxid$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] input_ra;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \input_ra$48 ;
+ wire [63:0] \input_ra$50 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] input_rb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \input_rb$49 ;
+ wire [63:0] \input_rb$51 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire input_xer_so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire \input_xer_so$50 ;
+ wire \input_xer_so$52 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \logical_op__SV_Ptype$100 ;
+ wire [1:0] \logical_op__SV_Ptype$104 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- input [1:0] \logical_op__SV_Ptype$23 ;
+ input [1:0] \logical_op__SV_Ptype$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [1:0] \logical_op__SV_Ptype$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [3:0] \logical_op__data_len$18 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [3:0] \logical_op__data_len$95 ;
+ wire [3:0] \logical_op__data_len$98 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [3:0] \logical_op__data_len$next ;
(* enum_base_type = "Function" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \logical_op__fn_unit$80 ;
+ wire [14:0] \logical_op__fn_unit$83 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [14:0] \logical_op__fn_unit$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] \logical_op__imm_data__data$4 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \logical_op__imm_data__data$81 ;
+ wire [63:0] \logical_op__imm_data__data$84 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [63:0] \logical_op__imm_data__data$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \logical_op__imm_data__ok$5 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__imm_data__ok$82 ;
+ wire \logical_op__imm_data__ok$85 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__imm_data__ok$next ;
(* enum_base_type = "CryIn" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \logical_op__input_carry$89 ;
+ wire [1:0] \logical_op__input_carry$92 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [1:0] \logical_op__input_carry$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] \logical_op__insn$19 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \logical_op__insn$96 ;
+ wire [31:0] \logical_op__insn$99 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [31:0] \logical_op__insn$next ;
(* enum_base_type = "MicrOp" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \logical_op__insn_type$79 ;
+ wire [6:0] \logical_op__insn_type$82 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [6:0] \logical_op__insn_type$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \logical_op__invert_in$10 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__invert_in$87 ;
+ wire \logical_op__invert_in$90 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__invert_in$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \logical_op__invert_out$13 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__invert_out$90 ;
+ wire \logical_op__invert_out$93 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__invert_out$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \logical_op__is_32bit$16 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__is_32bit$93 ;
+ wire \logical_op__is_32bit$96 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__is_32bit$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \logical_op__is_signed$17 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__is_signed$94 ;
+ wire \logical_op__is_signed$97 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__is_signed$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \logical_op__oe__oe$8 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__oe__oe$85 ;
+ wire \logical_op__oe__oe$88 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__oe__oe$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output logical_op__oe__ok;
reg logical_op__oe__ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__oe__ok$86 ;
+ wire \logical_op__oe__ok$89 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \logical_op__oe__ok$9 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \logical_op__output_carry$15 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__output_carry$92 ;
+ wire \logical_op__output_carry$95 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__output_carry$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \logical_op__rc__ok$7 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__rc__ok$84 ;
+ wire \logical_op__rc__ok$87 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__rc__ok$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \logical_op__rc__rc$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__rc__rc$83 ;
+ wire \logical_op__rc__rc$86 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__rc__rc$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] logical_op__sv_ldstmode;
+ reg [1:0] logical_op__sv_ldstmode = 2'h0;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \logical_op__sv_ldstmode$103 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] \logical_op__sv_ldstmode$23 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \logical_op__sv_ldstmode$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output logical_op__sv_pred_dz;
reg logical_op__sv_pred_dz = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- input \logical_op__sv_pred_dz$21 ;
+ wire \logical_op__sv_pred_dz$101 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__sv_pred_dz$98 ;
+ input \logical_op__sv_pred_dz$21 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__sv_pred_dz$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output logical_op__sv_pred_sz;
reg logical_op__sv_pred_sz = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- input \logical_op__sv_pred_sz$20 ;
+ wire \logical_op__sv_pred_sz$100 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__sv_pred_sz$97 ;
+ input \logical_op__sv_pred_sz$20 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__sv_pred_sz$next ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- input [1:0] \logical_op__sv_saturate$22 ;
+ wire [1:0] \logical_op__sv_saturate$102 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \logical_op__sv_saturate$99 ;
+ input [1:0] \logical_op__sv_saturate$22 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [1:0] \logical_op__sv_saturate$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \logical_op__write_cr0$14 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__write_cr0$91 ;
+ wire \logical_op__write_cr0$94 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__write_cr0$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \logical_op__zero_a$11 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__zero_a$88 ;
+ wire \logical_op__zero_a$91 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__zero_a$next ;
(* enum_base_type = "SVPtype" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \main_logical_op__SV_Ptype$73 ;
+ wire [1:0] \main_logical_op__SV_Ptype$76 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [3:0] main_logical_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [3:0] \main_logical_op__data_len$68 ;
+ wire [3:0] \main_logical_op__data_len$70 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \main_logical_op__fn_unit$53 ;
+ wire [14:0] \main_logical_op__fn_unit$55 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] main_logical_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \main_logical_op__imm_data__data$54 ;
+ wire [63:0] \main_logical_op__imm_data__data$56 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_logical_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_logical_op__imm_data__ok$55 ;
+ wire \main_logical_op__imm_data__ok$57 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \main_logical_op__input_carry$62 ;
+ wire [1:0] \main_logical_op__input_carry$64 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] main_logical_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \main_logical_op__insn$69 ;
+ wire [31:0] \main_logical_op__insn$71 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \main_logical_op__insn_type$52 ;
+ wire [6:0] \main_logical_op__insn_type$54 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_logical_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_logical_op__invert_in$60 ;
+ wire \main_logical_op__invert_in$62 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_logical_op__invert_out;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_logical_op__invert_out$63 ;
+ wire \main_logical_op__invert_out$65 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_logical_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_logical_op__is_32bit$66 ;
+ wire \main_logical_op__is_32bit$68 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_logical_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_logical_op__is_signed$67 ;
+ wire \main_logical_op__is_signed$69 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_logical_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_logical_op__oe__oe$58 ;
+ wire \main_logical_op__oe__oe$60 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_logical_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_logical_op__oe__ok$59 ;
+ wire \main_logical_op__oe__ok$61 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_logical_op__output_carry;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_logical_op__output_carry$65 ;
+ wire \main_logical_op__output_carry$67 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_logical_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_logical_op__rc__ok$57 ;
+ wire \main_logical_op__rc__ok$59 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_logical_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_logical_op__rc__rc$56 ;
+ wire \main_logical_op__rc__rc$58 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] main_logical_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \main_logical_op__sv_ldstmode$75 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_logical_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_logical_op__sv_pred_dz$71 ;
+ wire \main_logical_op__sv_pred_dz$73 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_logical_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_logical_op__sv_pred_sz$70 ;
+ wire \main_logical_op__sv_pred_sz$72 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \main_logical_op__sv_saturate$72 ;
+ wire [1:0] \main_logical_op__sv_saturate$74 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_logical_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_logical_op__write_cr0$64 ;
+ wire \main_logical_op__write_cr0$66 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_logical_op__zero_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_logical_op__zero_a$61 ;
+ wire \main_logical_op__zero_a$63 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] main_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \main_muxid$51 ;
+ wire [1:0] \main_muxid$53 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [63:0] main_o;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire main_xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \main_xer_so$74 ;
+ wire \main_xer_so$77 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
output [1:0] muxid;
reg [1:0] muxid = 2'h0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
input [1:0] \muxid$1 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \muxid$78 ;
+ wire [1:0] \muxid$81 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
reg [1:0] \muxid$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
output [63:0] o;
reg [63:0] o = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \o$101 ;
+ wire [63:0] \o$105 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg [63:0] \o$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output o_ok;
reg o_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \o_ok$102 ;
+ wire \o_ok$106 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \o_ok$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
input p_valid_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
- wire \p_valid_i$75 ;
+ wire \p_valid_i$78 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
wire p_valid_i_p_ready_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
output xer_so;
reg xer_so = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_so$107 ;
+ wire \xer_so$111 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- input \xer_so$24 ;
+ input \xer_so$25 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \xer_so$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_so_ok;
reg xer_so_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_so_ok$108 ;
+ wire \xer_so_ok$112 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_so_ok$109 ;
+ wire \xer_so_ok$113 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \xer_so_ok$next ;
- assign \$76 = \p_valid_i$75 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
+ assign \$79 = \p_valid_i$78 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
+ always @(posedge coresync_clk)
+ xer_so <= \xer_so$next ;
always @(posedge coresync_clk)
xer_so_ok <= \xer_so_ok$next ;
always @(posedge coresync_clk)
logical_op__sv_pred_dz <= \logical_op__sv_pred_dz$next ;
always @(posedge coresync_clk)
logical_op__sv_saturate <= \logical_op__sv_saturate$next ;
+ always @(posedge coresync_clk)
+ logical_op__sv_ldstmode <= \logical_op__sv_ldstmode$next ;
always @(posedge coresync_clk)
logical_op__SV_Ptype <= \logical_op__SV_Ptype$next ;
always @(posedge coresync_clk)
muxid <= \muxid$next ;
always @(posedge coresync_clk)
r_busy <= \r_busy$next ;
- always @(posedge coresync_clk)
- xer_so <= \xer_so$next ;
\input$50 \input (
.logical_op__SV_Ptype(input_logical_op__SV_Ptype),
- .\logical_op__SV_Ptype$23 (\input_logical_op__SV_Ptype$47 ),
+ .\logical_op__SV_Ptype$24 (\input_logical_op__SV_Ptype$49 ),
.logical_op__data_len(input_logical_op__data_len),
- .\logical_op__data_len$18 (\input_logical_op__data_len$42 ),
+ .\logical_op__data_len$18 (\input_logical_op__data_len$43 ),
.logical_op__fn_unit(input_logical_op__fn_unit),
- .\logical_op__fn_unit$3 (\input_logical_op__fn_unit$27 ),
+ .\logical_op__fn_unit$3 (\input_logical_op__fn_unit$28 ),
.logical_op__imm_data__data(input_logical_op__imm_data__data),
- .\logical_op__imm_data__data$4 (\input_logical_op__imm_data__data$28 ),
+ .\logical_op__imm_data__data$4 (\input_logical_op__imm_data__data$29 ),
.logical_op__imm_data__ok(input_logical_op__imm_data__ok),
- .\logical_op__imm_data__ok$5 (\input_logical_op__imm_data__ok$29 ),
+ .\logical_op__imm_data__ok$5 (\input_logical_op__imm_data__ok$30 ),
.logical_op__input_carry(input_logical_op__input_carry),
- .\logical_op__input_carry$12 (\input_logical_op__input_carry$36 ),
+ .\logical_op__input_carry$12 (\input_logical_op__input_carry$37 ),
.logical_op__insn(input_logical_op__insn),
- .\logical_op__insn$19 (\input_logical_op__insn$43 ),
+ .\logical_op__insn$19 (\input_logical_op__insn$44 ),
.logical_op__insn_type(input_logical_op__insn_type),
- .\logical_op__insn_type$2 (\input_logical_op__insn_type$26 ),
+ .\logical_op__insn_type$2 (\input_logical_op__insn_type$27 ),
.logical_op__invert_in(input_logical_op__invert_in),
- .\logical_op__invert_in$10 (\input_logical_op__invert_in$34 ),
+ .\logical_op__invert_in$10 (\input_logical_op__invert_in$35 ),
.logical_op__invert_out(input_logical_op__invert_out),
- .\logical_op__invert_out$13 (\input_logical_op__invert_out$37 ),
+ .\logical_op__invert_out$13 (\input_logical_op__invert_out$38 ),
.logical_op__is_32bit(input_logical_op__is_32bit),
- .\logical_op__is_32bit$16 (\input_logical_op__is_32bit$40 ),
+ .\logical_op__is_32bit$16 (\input_logical_op__is_32bit$41 ),
.logical_op__is_signed(input_logical_op__is_signed),
- .\logical_op__is_signed$17 (\input_logical_op__is_signed$41 ),
+ .\logical_op__is_signed$17 (\input_logical_op__is_signed$42 ),
.logical_op__oe__oe(input_logical_op__oe__oe),
- .\logical_op__oe__oe$8 (\input_logical_op__oe__oe$32 ),
+ .\logical_op__oe__oe$8 (\input_logical_op__oe__oe$33 ),
.logical_op__oe__ok(input_logical_op__oe__ok),
- .\logical_op__oe__ok$9 (\input_logical_op__oe__ok$33 ),
+ .\logical_op__oe__ok$9 (\input_logical_op__oe__ok$34 ),
.logical_op__output_carry(input_logical_op__output_carry),
- .\logical_op__output_carry$15 (\input_logical_op__output_carry$39 ),
+ .\logical_op__output_carry$15 (\input_logical_op__output_carry$40 ),
.logical_op__rc__ok(input_logical_op__rc__ok),
- .\logical_op__rc__ok$7 (\input_logical_op__rc__ok$31 ),
+ .\logical_op__rc__ok$7 (\input_logical_op__rc__ok$32 ),
.logical_op__rc__rc(input_logical_op__rc__rc),
- .\logical_op__rc__rc$6 (\input_logical_op__rc__rc$30 ),
+ .\logical_op__rc__rc$6 (\input_logical_op__rc__rc$31 ),
+ .logical_op__sv_ldstmode(input_logical_op__sv_ldstmode),
+ .\logical_op__sv_ldstmode$23 (\input_logical_op__sv_ldstmode$48 ),
.logical_op__sv_pred_dz(input_logical_op__sv_pred_dz),
- .\logical_op__sv_pred_dz$21 (\input_logical_op__sv_pred_dz$45 ),
+ .\logical_op__sv_pred_dz$21 (\input_logical_op__sv_pred_dz$46 ),
.logical_op__sv_pred_sz(input_logical_op__sv_pred_sz),
- .\logical_op__sv_pred_sz$20 (\input_logical_op__sv_pred_sz$44 ),
+ .\logical_op__sv_pred_sz$20 (\input_logical_op__sv_pred_sz$45 ),
.logical_op__sv_saturate(input_logical_op__sv_saturate),
- .\logical_op__sv_saturate$22 (\input_logical_op__sv_saturate$46 ),
+ .\logical_op__sv_saturate$22 (\input_logical_op__sv_saturate$47 ),
.logical_op__write_cr0(input_logical_op__write_cr0),
- .\logical_op__write_cr0$14 (\input_logical_op__write_cr0$38 ),
+ .\logical_op__write_cr0$14 (\input_logical_op__write_cr0$39 ),
.logical_op__zero_a(input_logical_op__zero_a),
- .\logical_op__zero_a$11 (\input_logical_op__zero_a$35 ),
+ .\logical_op__zero_a$11 (\input_logical_op__zero_a$36 ),
.muxid(input_muxid),
- .\muxid$1 (\input_muxid$25 ),
+ .\muxid$1 (\input_muxid$26 ),
.ra(input_ra),
- .\ra$24 (\input_ra$48 ),
+ .\ra$25 (\input_ra$50 ),
.rb(input_rb),
- .\rb$25 (\input_rb$49 ),
+ .\rb$26 (\input_rb$51 ),
.xer_so(input_xer_so),
- .\xer_so$26 (\input_xer_so$50 )
+ .\xer_so$27 (\input_xer_so$52 )
);
\main$51 main (
.logical_op__SV_Ptype(main_logical_op__SV_Ptype),
- .\logical_op__SV_Ptype$23 (\main_logical_op__SV_Ptype$73 ),
+ .\logical_op__SV_Ptype$24 (\main_logical_op__SV_Ptype$76 ),
.logical_op__data_len(main_logical_op__data_len),
- .\logical_op__data_len$18 (\main_logical_op__data_len$68 ),
+ .\logical_op__data_len$18 (\main_logical_op__data_len$70 ),
.logical_op__fn_unit(main_logical_op__fn_unit),
- .\logical_op__fn_unit$3 (\main_logical_op__fn_unit$53 ),
+ .\logical_op__fn_unit$3 (\main_logical_op__fn_unit$55 ),
.logical_op__imm_data__data(main_logical_op__imm_data__data),
- .\logical_op__imm_data__data$4 (\main_logical_op__imm_data__data$54 ),
+ .\logical_op__imm_data__data$4 (\main_logical_op__imm_data__data$56 ),
.logical_op__imm_data__ok(main_logical_op__imm_data__ok),
- .\logical_op__imm_data__ok$5 (\main_logical_op__imm_data__ok$55 ),
+ .\logical_op__imm_data__ok$5 (\main_logical_op__imm_data__ok$57 ),
.logical_op__input_carry(main_logical_op__input_carry),
- .\logical_op__input_carry$12 (\main_logical_op__input_carry$62 ),
+ .\logical_op__input_carry$12 (\main_logical_op__input_carry$64 ),
.logical_op__insn(main_logical_op__insn),
- .\logical_op__insn$19 (\main_logical_op__insn$69 ),
+ .\logical_op__insn$19 (\main_logical_op__insn$71 ),
.logical_op__insn_type(main_logical_op__insn_type),
- .\logical_op__insn_type$2 (\main_logical_op__insn_type$52 ),
+ .\logical_op__insn_type$2 (\main_logical_op__insn_type$54 ),
.logical_op__invert_in(main_logical_op__invert_in),
- .\logical_op__invert_in$10 (\main_logical_op__invert_in$60 ),
+ .\logical_op__invert_in$10 (\main_logical_op__invert_in$62 ),
.logical_op__invert_out(main_logical_op__invert_out),
- .\logical_op__invert_out$13 (\main_logical_op__invert_out$63 ),
+ .\logical_op__invert_out$13 (\main_logical_op__invert_out$65 ),
.logical_op__is_32bit(main_logical_op__is_32bit),
- .\logical_op__is_32bit$16 (\main_logical_op__is_32bit$66 ),
+ .\logical_op__is_32bit$16 (\main_logical_op__is_32bit$68 ),
.logical_op__is_signed(main_logical_op__is_signed),
- .\logical_op__is_signed$17 (\main_logical_op__is_signed$67 ),
+ .\logical_op__is_signed$17 (\main_logical_op__is_signed$69 ),
.logical_op__oe__oe(main_logical_op__oe__oe),
- .\logical_op__oe__oe$8 (\main_logical_op__oe__oe$58 ),
+ .\logical_op__oe__oe$8 (\main_logical_op__oe__oe$60 ),
.logical_op__oe__ok(main_logical_op__oe__ok),
- .\logical_op__oe__ok$9 (\main_logical_op__oe__ok$59 ),
+ .\logical_op__oe__ok$9 (\main_logical_op__oe__ok$61 ),
.logical_op__output_carry(main_logical_op__output_carry),
- .\logical_op__output_carry$15 (\main_logical_op__output_carry$65 ),
+ .\logical_op__output_carry$15 (\main_logical_op__output_carry$67 ),
.logical_op__rc__ok(main_logical_op__rc__ok),
- .\logical_op__rc__ok$7 (\main_logical_op__rc__ok$57 ),
+ .\logical_op__rc__ok$7 (\main_logical_op__rc__ok$59 ),
.logical_op__rc__rc(main_logical_op__rc__rc),
- .\logical_op__rc__rc$6 (\main_logical_op__rc__rc$56 ),
+ .\logical_op__rc__rc$6 (\main_logical_op__rc__rc$58 ),
+ .logical_op__sv_ldstmode(main_logical_op__sv_ldstmode),
+ .\logical_op__sv_ldstmode$23 (\main_logical_op__sv_ldstmode$75 ),
.logical_op__sv_pred_dz(main_logical_op__sv_pred_dz),
- .\logical_op__sv_pred_dz$21 (\main_logical_op__sv_pred_dz$71 ),
+ .\logical_op__sv_pred_dz$21 (\main_logical_op__sv_pred_dz$73 ),
.logical_op__sv_pred_sz(main_logical_op__sv_pred_sz),
- .\logical_op__sv_pred_sz$20 (\main_logical_op__sv_pred_sz$70 ),
+ .\logical_op__sv_pred_sz$20 (\main_logical_op__sv_pred_sz$72 ),
.logical_op__sv_saturate(main_logical_op__sv_saturate),
- .\logical_op__sv_saturate$22 (\main_logical_op__sv_saturate$72 ),
+ .\logical_op__sv_saturate$22 (\main_logical_op__sv_saturate$74 ),
.logical_op__write_cr0(main_logical_op__write_cr0),
- .\logical_op__write_cr0$14 (\main_logical_op__write_cr0$64 ),
+ .\logical_op__write_cr0$14 (\main_logical_op__write_cr0$66 ),
.logical_op__zero_a(main_logical_op__zero_a),
- .\logical_op__zero_a$11 (\main_logical_op__zero_a$61 ),
+ .\logical_op__zero_a$11 (\main_logical_op__zero_a$63 ),
.muxid(main_muxid),
- .\muxid$1 (\main_muxid$51 ),
+ .\muxid$1 (\main_muxid$53 ),
.o(main_o),
.o_ok(main_o_ok),
.ra(main_ra),
.rb(main_rb),
.xer_so(main_xer_so),
- .\xer_so$24 (\main_xer_so$74 )
+ .\xer_so$25 (\main_xer_so$77 )
);
\n$49 n (
.n_ready_i(n_ready_i),
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \o_ok$next , \o$next } = { \o_ok$102 , \o$101 };
+ { \o_ok$next , \o$next } = { \o_ok$106 , \o$105 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \o_ok$next , \o$next } = { \o_ok$102 , \o$101 };
+ { \o_ok$next , \o$next } = { \o_ok$106 , \o$105 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$104 , \cr_a$103 };
+ { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$108 , \cr_a$107 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$104 , \cr_a$103 };
+ { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$108 , \cr_a$107 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$108 , \xer_so$107 };
+ { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$112 , \xer_so$111 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$108 , \xer_so$107 };
+ { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$112 , \xer_so$111 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \muxid$next = \muxid$78 ;
+ \muxid$next = \muxid$81 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \muxid$next = \muxid$78 ;
+ \muxid$next = \muxid$81 ;
endcase
end
always @* begin
\logical_op__sv_pred_sz$next = logical_op__sv_pred_sz;
\logical_op__sv_pred_dz$next = logical_op__sv_pred_dz;
\logical_op__sv_saturate$next = logical_op__sv_saturate;
+ \logical_op__sv_ldstmode$next = logical_op__sv_ldstmode;
\logical_op__SV_Ptype$next = logical_op__SV_Ptype;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \logical_op__SV_Ptype$next , \logical_op__sv_saturate$next , \logical_op__sv_pred_dz$next , \logical_op__sv_pred_sz$next , \logical_op__insn$next , \logical_op__data_len$next , \logical_op__is_signed$next , \logical_op__is_32bit$next , \logical_op__output_carry$next , \logical_op__write_cr0$next , \logical_op__invert_out$next , \logical_op__input_carry$next , \logical_op__zero_a$next , \logical_op__invert_in$next , \logical_op__oe__ok$next , \logical_op__oe__oe$next , \logical_op__rc__ok$next , \logical_op__rc__rc$next , \logical_op__imm_data__ok$next , \logical_op__imm_data__data$next , \logical_op__fn_unit$next , \logical_op__insn_type$next } = { \logical_op__SV_Ptype$100 , \logical_op__sv_saturate$99 , \logical_op__sv_pred_dz$98 , \logical_op__sv_pred_sz$97 , \logical_op__insn$96 , \logical_op__data_len$95 , \logical_op__is_signed$94 , \logical_op__is_32bit$93 , \logical_op__output_carry$92 , \logical_op__write_cr0$91 , \logical_op__invert_out$90 , \logical_op__input_carry$89 , \logical_op__zero_a$88 , \logical_op__invert_in$87 , \logical_op__oe__ok$86 , \logical_op__oe__oe$85 , \logical_op__rc__ok$84 , \logical_op__rc__rc$83 , \logical_op__imm_data__ok$82 , \logical_op__imm_data__data$81 , \logical_op__fn_unit$80 , \logical_op__insn_type$79 };
+ { \logical_op__SV_Ptype$next , \logical_op__sv_ldstmode$next , \logical_op__sv_saturate$next , \logical_op__sv_pred_dz$next , \logical_op__sv_pred_sz$next , \logical_op__insn$next , \logical_op__data_len$next , \logical_op__is_signed$next , \logical_op__is_32bit$next , \logical_op__output_carry$next , \logical_op__write_cr0$next , \logical_op__invert_out$next , \logical_op__input_carry$next , \logical_op__zero_a$next , \logical_op__invert_in$next , \logical_op__oe__ok$next , \logical_op__oe__oe$next , \logical_op__rc__ok$next , \logical_op__rc__rc$next , \logical_op__imm_data__ok$next , \logical_op__imm_data__data$next , \logical_op__fn_unit$next , \logical_op__insn_type$next } = { \logical_op__SV_Ptype$104 , \logical_op__sv_ldstmode$103 , \logical_op__sv_saturate$102 , \logical_op__sv_pred_dz$101 , \logical_op__sv_pred_sz$100 , \logical_op__insn$99 , \logical_op__data_len$98 , \logical_op__is_signed$97 , \logical_op__is_32bit$96 , \logical_op__output_carry$95 , \logical_op__write_cr0$94 , \logical_op__invert_out$93 , \logical_op__input_carry$92 , \logical_op__zero_a$91 , \logical_op__invert_in$90 , \logical_op__oe__ok$89 , \logical_op__oe__oe$88 , \logical_op__rc__ok$87 , \logical_op__rc__rc$86 , \logical_op__imm_data__ok$85 , \logical_op__imm_data__data$84 , \logical_op__fn_unit$83 , \logical_op__insn_type$82 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \logical_op__SV_Ptype$next , \logical_op__sv_saturate$next , \logical_op__sv_pred_dz$next , \logical_op__sv_pred_sz$next , \logical_op__insn$next , \logical_op__data_len$next , \logical_op__is_signed$next , \logical_op__is_32bit$next , \logical_op__output_carry$next , \logical_op__write_cr0$next , \logical_op__invert_out$next , \logical_op__input_carry$next , \logical_op__zero_a$next , \logical_op__invert_in$next , \logical_op__oe__ok$next , \logical_op__oe__oe$next , \logical_op__rc__ok$next , \logical_op__rc__rc$next , \logical_op__imm_data__ok$next , \logical_op__imm_data__data$next , \logical_op__fn_unit$next , \logical_op__insn_type$next } = { \logical_op__SV_Ptype$100 , \logical_op__sv_saturate$99 , \logical_op__sv_pred_dz$98 , \logical_op__sv_pred_sz$97 , \logical_op__insn$96 , \logical_op__data_len$95 , \logical_op__is_signed$94 , \logical_op__is_32bit$93 , \logical_op__output_carry$92 , \logical_op__write_cr0$91 , \logical_op__invert_out$90 , \logical_op__input_carry$89 , \logical_op__zero_a$88 , \logical_op__invert_in$87 , \logical_op__oe__ok$86 , \logical_op__oe__oe$85 , \logical_op__rc__ok$84 , \logical_op__rc__rc$83 , \logical_op__imm_data__ok$82 , \logical_op__imm_data__data$81 , \logical_op__fn_unit$80 , \logical_op__insn_type$79 };
+ { \logical_op__SV_Ptype$next , \logical_op__sv_ldstmode$next , \logical_op__sv_saturate$next , \logical_op__sv_pred_dz$next , \logical_op__sv_pred_sz$next , \logical_op__insn$next , \logical_op__data_len$next , \logical_op__is_signed$next , \logical_op__is_32bit$next , \logical_op__output_carry$next , \logical_op__write_cr0$next , \logical_op__invert_out$next , \logical_op__input_carry$next , \logical_op__zero_a$next , \logical_op__invert_in$next , \logical_op__oe__ok$next , \logical_op__oe__oe$next , \logical_op__rc__ok$next , \logical_op__rc__rc$next , \logical_op__imm_data__ok$next , \logical_op__imm_data__data$next , \logical_op__fn_unit$next , \logical_op__insn_type$next } = { \logical_op__SV_Ptype$104 , \logical_op__sv_ldstmode$103 , \logical_op__sv_saturate$102 , \logical_op__sv_pred_dz$101 , \logical_op__sv_pred_sz$100 , \logical_op__insn$99 , \logical_op__data_len$98 , \logical_op__is_signed$97 , \logical_op__is_32bit$96 , \logical_op__output_carry$95 , \logical_op__write_cr0$94 , \logical_op__invert_out$93 , \logical_op__input_carry$92 , \logical_op__zero_a$91 , \logical_op__invert_in$90 , \logical_op__oe__ok$89 , \logical_op__oe__oe$88 , \logical_op__rc__ok$87 , \logical_op__rc__rc$86 , \logical_op__imm_data__ok$85 , \logical_op__imm_data__data$84 , \logical_op__fn_unit$83 , \logical_op__insn_type$82 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
end
endcase
end
- assign \cr_a$105 = 4'h0;
- assign \cr_a_ok$106 = 1'h0;
- assign \xer_so_ok$109 = 1'h0;
+ assign \cr_a$109 = 4'h0;
+ assign \cr_a_ok$110 = 1'h0;
+ assign \xer_so_ok$113 = 1'h0;
assign p_ready_o = n_i_rdy_data;
assign n_valid_o = r_busy;
- assign { \xer_so_ok$108 , \xer_so$107 } = { 1'h0, \main_xer_so$74 };
- assign { \cr_a_ok$104 , \cr_a$103 } = 5'h00;
- assign { \o_ok$102 , \o$101 } = { main_o_ok, main_o };
- assign { \logical_op__SV_Ptype$100 , \logical_op__sv_saturate$99 , \logical_op__sv_pred_dz$98 , \logical_op__sv_pred_sz$97 , \logical_op__insn$96 , \logical_op__data_len$95 , \logical_op__is_signed$94 , \logical_op__is_32bit$93 , \logical_op__output_carry$92 , \logical_op__write_cr0$91 , \logical_op__invert_out$90 , \logical_op__input_carry$89 , \logical_op__zero_a$88 , \logical_op__invert_in$87 , \logical_op__oe__ok$86 , \logical_op__oe__oe$85 , \logical_op__rc__ok$84 , \logical_op__rc__rc$83 , \logical_op__imm_data__ok$82 , \logical_op__imm_data__data$81 , \logical_op__fn_unit$80 , \logical_op__insn_type$79 } = { \main_logical_op__SV_Ptype$73 , \main_logical_op__sv_saturate$72 , \main_logical_op__sv_pred_dz$71 , \main_logical_op__sv_pred_sz$70 , \main_logical_op__insn$69 , \main_logical_op__data_len$68 , \main_logical_op__is_signed$67 , \main_logical_op__is_32bit$66 , \main_logical_op__output_carry$65 , \main_logical_op__write_cr0$64 , \main_logical_op__invert_out$63 , \main_logical_op__input_carry$62 , \main_logical_op__zero_a$61 , \main_logical_op__invert_in$60 , \main_logical_op__oe__ok$59 , \main_logical_op__oe__oe$58 , \main_logical_op__rc__ok$57 , \main_logical_op__rc__rc$56 , \main_logical_op__imm_data__ok$55 , \main_logical_op__imm_data__data$54 , \main_logical_op__fn_unit$53 , \main_logical_op__insn_type$52 };
- assign \muxid$78 = \main_muxid$51 ;
- assign p_valid_i_p_ready_o = \$76 ;
+ assign { \xer_so_ok$112 , \xer_so$111 } = { 1'h0, \main_xer_so$77 };
+ assign { \cr_a_ok$108 , \cr_a$107 } = 5'h00;
+ assign { \o_ok$106 , \o$105 } = { main_o_ok, main_o };
+ assign { \logical_op__SV_Ptype$104 , \logical_op__sv_ldstmode$103 , \logical_op__sv_saturate$102 , \logical_op__sv_pred_dz$101 , \logical_op__sv_pred_sz$100 , \logical_op__insn$99 , \logical_op__data_len$98 , \logical_op__is_signed$97 , \logical_op__is_32bit$96 , \logical_op__output_carry$95 , \logical_op__write_cr0$94 , \logical_op__invert_out$93 , \logical_op__input_carry$92 , \logical_op__zero_a$91 , \logical_op__invert_in$90 , \logical_op__oe__ok$89 , \logical_op__oe__oe$88 , \logical_op__rc__ok$87 , \logical_op__rc__rc$86 , \logical_op__imm_data__ok$85 , \logical_op__imm_data__data$84 , \logical_op__fn_unit$83 , \logical_op__insn_type$82 } = { \main_logical_op__SV_Ptype$76 , \main_logical_op__sv_ldstmode$75 , \main_logical_op__sv_saturate$74 , \main_logical_op__sv_pred_dz$73 , \main_logical_op__sv_pred_sz$72 , \main_logical_op__insn$71 , \main_logical_op__data_len$70 , \main_logical_op__is_signed$69 , \main_logical_op__is_32bit$68 , \main_logical_op__output_carry$67 , \main_logical_op__write_cr0$66 , \main_logical_op__invert_out$65 , \main_logical_op__input_carry$64 , \main_logical_op__zero_a$63 , \main_logical_op__invert_in$62 , \main_logical_op__oe__ok$61 , \main_logical_op__oe__oe$60 , \main_logical_op__rc__ok$59 , \main_logical_op__rc__rc$58 , \main_logical_op__imm_data__ok$57 , \main_logical_op__imm_data__data$56 , \main_logical_op__fn_unit$55 , \main_logical_op__insn_type$54 };
+ assign \muxid$81 = \main_muxid$53 ;
+ assign p_valid_i_p_ready_o = \$79 ;
assign n_i_rdy_data = n_ready_i;
- assign \p_valid_i$75 = p_valid_i;
- assign main_xer_so = \input_xer_so$50 ;
- assign main_rb = \input_rb$49 ;
- assign main_ra = \input_ra$48 ;
- assign { main_logical_op__SV_Ptype, main_logical_op__sv_saturate, main_logical_op__sv_pred_dz, main_logical_op__sv_pred_sz, main_logical_op__insn, main_logical_op__data_len, main_logical_op__is_signed, main_logical_op__is_32bit, main_logical_op__output_carry, main_logical_op__write_cr0, main_logical_op__invert_out, main_logical_op__input_carry, main_logical_op__zero_a, main_logical_op__invert_in, main_logical_op__oe__ok, main_logical_op__oe__oe, main_logical_op__rc__ok, main_logical_op__rc__rc, main_logical_op__imm_data__ok, main_logical_op__imm_data__data, main_logical_op__fn_unit, main_logical_op__insn_type } = { \input_logical_op__SV_Ptype$47 , \input_logical_op__sv_saturate$46 , \input_logical_op__sv_pred_dz$45 , \input_logical_op__sv_pred_sz$44 , \input_logical_op__insn$43 , \input_logical_op__data_len$42 , \input_logical_op__is_signed$41 , \input_logical_op__is_32bit$40 , \input_logical_op__output_carry$39 , \input_logical_op__write_cr0$38 , \input_logical_op__invert_out$37 , \input_logical_op__input_carry$36 , \input_logical_op__zero_a$35 , \input_logical_op__invert_in$34 , \input_logical_op__oe__ok$33 , \input_logical_op__oe__oe$32 , \input_logical_op__rc__ok$31 , \input_logical_op__rc__rc$30 , \input_logical_op__imm_data__ok$29 , \input_logical_op__imm_data__data$28 , \input_logical_op__fn_unit$27 , \input_logical_op__insn_type$26 };
- assign main_muxid = \input_muxid$25 ;
- assign input_xer_so = \xer_so$24 ;
+ assign \p_valid_i$78 = p_valid_i;
+ assign main_xer_so = \input_xer_so$52 ;
+ assign main_rb = \input_rb$51 ;
+ assign main_ra = \input_ra$50 ;
+ assign { main_logical_op__SV_Ptype, main_logical_op__sv_ldstmode, main_logical_op__sv_saturate, main_logical_op__sv_pred_dz, main_logical_op__sv_pred_sz, main_logical_op__insn, main_logical_op__data_len, main_logical_op__is_signed, main_logical_op__is_32bit, main_logical_op__output_carry, main_logical_op__write_cr0, main_logical_op__invert_out, main_logical_op__input_carry, main_logical_op__zero_a, main_logical_op__invert_in, main_logical_op__oe__ok, main_logical_op__oe__oe, main_logical_op__rc__ok, main_logical_op__rc__rc, main_logical_op__imm_data__ok, main_logical_op__imm_data__data, main_logical_op__fn_unit, main_logical_op__insn_type } = { \input_logical_op__SV_Ptype$49 , \input_logical_op__sv_ldstmode$48 , \input_logical_op__sv_saturate$47 , \input_logical_op__sv_pred_dz$46 , \input_logical_op__sv_pred_sz$45 , \input_logical_op__insn$44 , \input_logical_op__data_len$43 , \input_logical_op__is_signed$42 , \input_logical_op__is_32bit$41 , \input_logical_op__output_carry$40 , \input_logical_op__write_cr0$39 , \input_logical_op__invert_out$38 , \input_logical_op__input_carry$37 , \input_logical_op__zero_a$36 , \input_logical_op__invert_in$35 , \input_logical_op__oe__ok$34 , \input_logical_op__oe__oe$33 , \input_logical_op__rc__ok$32 , \input_logical_op__rc__rc$31 , \input_logical_op__imm_data__ok$30 , \input_logical_op__imm_data__data$29 , \input_logical_op__fn_unit$28 , \input_logical_op__insn_type$27 };
+ assign main_muxid = \input_muxid$26 ;
+ assign input_xer_so = \xer_so$25 ;
assign input_rb = rb;
assign input_ra = ra;
- assign { input_logical_op__SV_Ptype, input_logical_op__sv_saturate, input_logical_op__sv_pred_dz, input_logical_op__sv_pred_sz, input_logical_op__insn, input_logical_op__data_len, input_logical_op__is_signed, input_logical_op__is_32bit, input_logical_op__output_carry, input_logical_op__write_cr0, input_logical_op__invert_out, input_logical_op__input_carry, input_logical_op__zero_a, input_logical_op__invert_in, input_logical_op__oe__ok, input_logical_op__oe__oe, input_logical_op__rc__ok, input_logical_op__rc__rc, input_logical_op__imm_data__ok, input_logical_op__imm_data__data, input_logical_op__fn_unit, input_logical_op__insn_type } = { \logical_op__SV_Ptype$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 };
+ assign { input_logical_op__SV_Ptype, input_logical_op__sv_ldstmode, input_logical_op__sv_saturate, input_logical_op__sv_pred_dz, input_logical_op__sv_pred_sz, input_logical_op__insn, input_logical_op__data_len, input_logical_op__is_signed, input_logical_op__is_32bit, input_logical_op__output_carry, input_logical_op__write_cr0, input_logical_op__invert_out, input_logical_op__input_carry, input_logical_op__zero_a, input_logical_op__invert_in, input_logical_op__oe__ok, input_logical_op__oe__oe, input_logical_op__rc__ok, input_logical_op__rc__rc, input_logical_op__imm_data__ok, input_logical_op__imm_data__data, input_logical_op__fn_unit, input_logical_op__insn_type } = { \logical_op__SV_Ptype$24 , \logical_op__sv_ldstmode$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 };
assign input_muxid = \muxid$1 ;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2" *)
(* generator = "nMigen" *)
-module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, o, o_ok, cr_a, cr_a_ok, xer_so, xer_so_ok, n_valid_o, n_ready_i, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__SV_Ptype$23 , \o$24 , \o_ok$25 , \cr_a$26 , \cr_a_ok$27 , coresync_clk);
+module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__sv_ldstmode, logical_op__SV_Ptype, o, o_ok, cr_a, cr_a_ok, xer_so, xer_so_ok, n_valid_o, n_ready_i, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__sv_ldstmode$23 , \logical_op__SV_Ptype$24 , \o$25 , \o_ok$26 , \cr_a$27 , \cr_a_ok$28 , coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
- wire \$57 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ wire \$59 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input [3:0] cr_a;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [3:0] \cr_a$26 ;
- reg [3:0] \cr_a$26 = 4'h0;
+ output [3:0] \cr_a$27 ;
+ reg [3:0] \cr_a$27 = 4'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg [3:0] \cr_a$26$next ;
+ reg [3:0] \cr_a$27$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [3:0] \cr_a$84 ;
+ wire [3:0] \cr_a$87 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input cr_a_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \cr_a_ok$27 ;
- reg \cr_a_ok$27 = 1'h0;
+ output \cr_a_ok$28 ;
+ reg \cr_a_ok$28 = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg \cr_a_ok$27$next ;
+ reg \cr_a_ok$28$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \cr_a_ok$54 ;
+ wire \cr_a_ok$56 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \cr_a_ok$85 ;
+ wire \cr_a_ok$88 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \logical_op__SV_Ptype$23 ;
- reg [1:0] \logical_op__SV_Ptype$23 = 2'h0;
+ output [1:0] \logical_op__SV_Ptype$24 ;
+ reg [1:0] \logical_op__SV_Ptype$24 = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [1:0] \logical_op__SV_Ptype$23$next ;
+ reg [1:0] \logical_op__SV_Ptype$24$next ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \logical_op__SV_Ptype$81 ;
+ wire [1:0] \logical_op__SV_Ptype$84 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [3:0] logical_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [3:0] \logical_op__data_len$18$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [3:0] \logical_op__data_len$76 ;
+ wire [3:0] \logical_op__data_len$78 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \logical_op__fn_unit$61 ;
+ wire [14:0] \logical_op__fn_unit$63 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] logical_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [63:0] \logical_op__imm_data__data$4$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \logical_op__imm_data__data$62 ;
+ wire [63:0] \logical_op__imm_data__data$64 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__imm_data__ok$5$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__imm_data__ok$63 ;
+ wire \logical_op__imm_data__ok$65 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \logical_op__input_carry$70 ;
+ wire [1:0] \logical_op__input_carry$72 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] logical_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [31:0] \logical_op__insn$19$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \logical_op__insn$77 ;
+ wire [31:0] \logical_op__insn$79 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \logical_op__insn_type$60 ;
+ wire [6:0] \logical_op__insn_type$62 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__invert_in$10$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__invert_in$68 ;
+ wire \logical_op__invert_in$70 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__invert_out;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__invert_out$13$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__invert_out$71 ;
+ wire \logical_op__invert_out$73 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__is_32bit$16$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__is_32bit$74 ;
+ wire \logical_op__is_32bit$76 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__is_signed$17$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__is_signed$75 ;
+ wire \logical_op__is_signed$77 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__oe__oe$66 ;
+ wire \logical_op__oe__oe$68 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__oe__oe$8 ;
reg \logical_op__oe__oe$8 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__oe__ok$67 ;
+ wire \logical_op__oe__ok$69 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__oe__ok$9 ;
reg \logical_op__oe__ok$9 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__output_carry$15$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__output_carry$73 ;
+ wire \logical_op__output_carry$75 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__rc__ok$65 ;
+ wire \logical_op__rc__ok$67 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__rc__ok$7 ;
reg \logical_op__rc__ok$7 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__rc__rc$6$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__rc__rc$64 ;
+ wire \logical_op__rc__rc$66 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] logical_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \logical_op__sv_ldstmode$23 ;
+ reg [1:0] \logical_op__sv_ldstmode$23 = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \logical_op__sv_ldstmode$23$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \logical_op__sv_ldstmode$83 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__sv_pred_dz$21$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__sv_pred_dz$79 ;
+ wire \logical_op__sv_pred_dz$81 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__sv_pred_sz$20$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__sv_pred_sz$78 ;
+ wire \logical_op__sv_pred_sz$80 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \logical_op__sv_saturate$80 ;
+ wire [1:0] \logical_op__sv_saturate$82 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__write_cr0$14$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__write_cr0$72 ;
+ wire \logical_op__write_cr0$74 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__zero_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__zero_a$11$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__zero_a$69 ;
+ wire \logical_op__zero_a$71 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
input [1:0] muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
reg [1:0] \muxid$1$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \muxid$59 ;
+ wire [1:0] \muxid$61 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
wire n_i_rdy_data;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input [63:0] o;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [63:0] \o$24 ;
- reg [63:0] \o$24 = 64'h0000000000000000;
+ output [63:0] \o$25 ;
+ reg [63:0] \o$25 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg [63:0] \o$24$next ;
+ reg [63:0] \o$25$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \o$82 ;
+ wire [63:0] \o$85 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input o_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \o_ok$25 ;
- reg \o_ok$25 = 1'h0;
+ output \o_ok$26 ;
+ reg \o_ok$26 = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg \o_ok$25$next ;
+ reg \o_ok$26$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \o_ok$83 ;
+ wire \o_ok$86 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [3:0] output_cr_a;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [3:0] \output_cr_a$53 ;
+ wire [3:0] \output_cr_a$55 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire output_cr_a_ok;
(* enum_base_type = "SVPtype" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \output_logical_op__SV_Ptype$50 ;
+ wire [1:0] \output_logical_op__SV_Ptype$52 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [3:0] output_logical_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [3:0] \output_logical_op__data_len$45 ;
+ wire [3:0] \output_logical_op__data_len$46 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \output_logical_op__fn_unit$30 ;
+ wire [14:0] \output_logical_op__fn_unit$31 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] output_logical_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \output_logical_op__imm_data__data$31 ;
+ wire [63:0] \output_logical_op__imm_data__data$32 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__imm_data__ok$32 ;
+ wire \output_logical_op__imm_data__ok$33 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \output_logical_op__input_carry$39 ;
+ wire [1:0] \output_logical_op__input_carry$40 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] output_logical_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \output_logical_op__insn$46 ;
+ wire [31:0] \output_logical_op__insn$47 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \output_logical_op__insn_type$29 ;
+ wire [6:0] \output_logical_op__insn_type$30 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__invert_in$37 ;
+ wire \output_logical_op__invert_in$38 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__invert_out;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__invert_out$40 ;
+ wire \output_logical_op__invert_out$41 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__is_32bit$43 ;
+ wire \output_logical_op__is_32bit$44 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__is_signed$44 ;
+ wire \output_logical_op__is_signed$45 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__oe__oe$35 ;
+ wire \output_logical_op__oe__oe$36 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__oe__ok$36 ;
+ wire \output_logical_op__oe__ok$37 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__output_carry;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__output_carry$42 ;
+ wire \output_logical_op__output_carry$43 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__rc__ok$34 ;
+ wire \output_logical_op__rc__ok$35 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__rc__rc$33 ;
+ wire \output_logical_op__rc__rc$34 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] output_logical_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \output_logical_op__sv_ldstmode$51 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__sv_pred_dz$48 ;
+ wire \output_logical_op__sv_pred_dz$49 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__sv_pred_sz$47 ;
+ wire \output_logical_op__sv_pred_sz$48 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \output_logical_op__sv_saturate$49 ;
+ wire [1:0] \output_logical_op__sv_saturate$50 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__write_cr0$41 ;
+ wire \output_logical_op__write_cr0$42 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__zero_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__zero_a$38 ;
+ wire \output_logical_op__zero_a$39 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] output_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \output_muxid$28 ;
+ wire [1:0] \output_muxid$29 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [63:0] output_o;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \output_o$51 ;
+ wire [63:0] \output_o$53 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire output_o_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \output_o_ok$52 ;
+ wire \output_o_ok$54 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire output_xer_so;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
input p_valid_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
- wire \p_valid_i$56 ;
+ wire \p_valid_i$58 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
wire p_valid_i_p_ready_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input xer_so_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_so_ok$55 ;
- assign \$57 = \p_valid_i$56 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
- always @(posedge coresync_clk)
- \cr_a$26 <= \cr_a$26$next ;
- always @(posedge coresync_clk)
- \cr_a_ok$27 <= \cr_a_ok$27$next ;
- always @(posedge coresync_clk)
- \o$24 <= \o$24$next ;
- always @(posedge coresync_clk)
- \o_ok$25 <= \o_ok$25$next ;
- always @(posedge coresync_clk)
- \logical_op__insn_type$2 <= \logical_op__insn_type$2$next ;
- always @(posedge coresync_clk)
- \logical_op__fn_unit$3 <= \logical_op__fn_unit$3$next ;
- always @(posedge coresync_clk)
- \logical_op__imm_data__data$4 <= \logical_op__imm_data__data$4$next ;
- always @(posedge coresync_clk)
- \logical_op__imm_data__ok$5 <= \logical_op__imm_data__ok$5$next ;
- always @(posedge coresync_clk)
- \logical_op__rc__rc$6 <= \logical_op__rc__rc$6$next ;
- always @(posedge coresync_clk)
- \logical_op__rc__ok$7 <= \logical_op__rc__ok$7$next ;
- always @(posedge coresync_clk)
- \logical_op__oe__oe$8 <= \logical_op__oe__oe$8$next ;
- always @(posedge coresync_clk)
- \logical_op__oe__ok$9 <= \logical_op__oe__ok$9$next ;
- always @(posedge coresync_clk)
- \logical_op__invert_in$10 <= \logical_op__invert_in$10$next ;
+ wire \xer_so_ok$57 ;
+ assign \$59 = \p_valid_i$58 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
always @(posedge coresync_clk)
\logical_op__zero_a$11 <= \logical_op__zero_a$11$next ;
always @(posedge coresync_clk)
always @(posedge coresync_clk)
\logical_op__sv_saturate$22 <= \logical_op__sv_saturate$22$next ;
always @(posedge coresync_clk)
- \logical_op__SV_Ptype$23 <= \logical_op__SV_Ptype$23$next ;
+ \logical_op__sv_ldstmode$23 <= \logical_op__sv_ldstmode$23$next ;
+ always @(posedge coresync_clk)
+ \logical_op__SV_Ptype$24 <= \logical_op__SV_Ptype$24$next ;
always @(posedge coresync_clk)
\muxid$1 <= \muxid$1$next ;
always @(posedge coresync_clk)
r_busy <= \r_busy$next ;
+ always @(posedge coresync_clk)
+ \cr_a$27 <= \cr_a$27$next ;
+ always @(posedge coresync_clk)
+ \cr_a_ok$28 <= \cr_a_ok$28$next ;
+ always @(posedge coresync_clk)
+ \o$25 <= \o$25$next ;
+ always @(posedge coresync_clk)
+ \o_ok$26 <= \o_ok$26$next ;
+ always @(posedge coresync_clk)
+ \logical_op__insn_type$2 <= \logical_op__insn_type$2$next ;
+ always @(posedge coresync_clk)
+ \logical_op__fn_unit$3 <= \logical_op__fn_unit$3$next ;
+ always @(posedge coresync_clk)
+ \logical_op__imm_data__data$4 <= \logical_op__imm_data__data$4$next ;
+ always @(posedge coresync_clk)
+ \logical_op__imm_data__ok$5 <= \logical_op__imm_data__ok$5$next ;
+ always @(posedge coresync_clk)
+ \logical_op__rc__rc$6 <= \logical_op__rc__rc$6$next ;
+ always @(posedge coresync_clk)
+ \logical_op__rc__ok$7 <= \logical_op__rc__ok$7$next ;
+ always @(posedge coresync_clk)
+ \logical_op__oe__oe$8 <= \logical_op__oe__oe$8$next ;
+ always @(posedge coresync_clk)
+ \logical_op__oe__ok$9 <= \logical_op__oe__ok$9$next ;
+ always @(posedge coresync_clk)
+ \logical_op__invert_in$10 <= \logical_op__invert_in$10$next ;
\n$53 n (
.n_ready_i(n_ready_i),
.n_valid_o(n_valid_o)
);
\output$54 \output (
.cr_a(output_cr_a),
- .\cr_a$26 (\output_cr_a$53 ),
+ .\cr_a$27 (\output_cr_a$55 ),
.cr_a_ok(output_cr_a_ok),
.logical_op__SV_Ptype(output_logical_op__SV_Ptype),
- .\logical_op__SV_Ptype$23 (\output_logical_op__SV_Ptype$50 ),
+ .\logical_op__SV_Ptype$24 (\output_logical_op__SV_Ptype$52 ),
.logical_op__data_len(output_logical_op__data_len),
- .\logical_op__data_len$18 (\output_logical_op__data_len$45 ),
+ .\logical_op__data_len$18 (\output_logical_op__data_len$46 ),
.logical_op__fn_unit(output_logical_op__fn_unit),
- .\logical_op__fn_unit$3 (\output_logical_op__fn_unit$30 ),
+ .\logical_op__fn_unit$3 (\output_logical_op__fn_unit$31 ),
.logical_op__imm_data__data(output_logical_op__imm_data__data),
- .\logical_op__imm_data__data$4 (\output_logical_op__imm_data__data$31 ),
+ .\logical_op__imm_data__data$4 (\output_logical_op__imm_data__data$32 ),
.logical_op__imm_data__ok(output_logical_op__imm_data__ok),
- .\logical_op__imm_data__ok$5 (\output_logical_op__imm_data__ok$32 ),
+ .\logical_op__imm_data__ok$5 (\output_logical_op__imm_data__ok$33 ),
.logical_op__input_carry(output_logical_op__input_carry),
- .\logical_op__input_carry$12 (\output_logical_op__input_carry$39 ),
+ .\logical_op__input_carry$12 (\output_logical_op__input_carry$40 ),
.logical_op__insn(output_logical_op__insn),
- .\logical_op__insn$19 (\output_logical_op__insn$46 ),
+ .\logical_op__insn$19 (\output_logical_op__insn$47 ),
.logical_op__insn_type(output_logical_op__insn_type),
- .\logical_op__insn_type$2 (\output_logical_op__insn_type$29 ),
+ .\logical_op__insn_type$2 (\output_logical_op__insn_type$30 ),
.logical_op__invert_in(output_logical_op__invert_in),
- .\logical_op__invert_in$10 (\output_logical_op__invert_in$37 ),
+ .\logical_op__invert_in$10 (\output_logical_op__invert_in$38 ),
.logical_op__invert_out(output_logical_op__invert_out),
- .\logical_op__invert_out$13 (\output_logical_op__invert_out$40 ),
+ .\logical_op__invert_out$13 (\output_logical_op__invert_out$41 ),
.logical_op__is_32bit(output_logical_op__is_32bit),
- .\logical_op__is_32bit$16 (\output_logical_op__is_32bit$43 ),
+ .\logical_op__is_32bit$16 (\output_logical_op__is_32bit$44 ),
.logical_op__is_signed(output_logical_op__is_signed),
- .\logical_op__is_signed$17 (\output_logical_op__is_signed$44 ),
+ .\logical_op__is_signed$17 (\output_logical_op__is_signed$45 ),
.logical_op__oe__oe(output_logical_op__oe__oe),
- .\logical_op__oe__oe$8 (\output_logical_op__oe__oe$35 ),
+ .\logical_op__oe__oe$8 (\output_logical_op__oe__oe$36 ),
.logical_op__oe__ok(output_logical_op__oe__ok),
- .\logical_op__oe__ok$9 (\output_logical_op__oe__ok$36 ),
+ .\logical_op__oe__ok$9 (\output_logical_op__oe__ok$37 ),
.logical_op__output_carry(output_logical_op__output_carry),
- .\logical_op__output_carry$15 (\output_logical_op__output_carry$42 ),
+ .\logical_op__output_carry$15 (\output_logical_op__output_carry$43 ),
.logical_op__rc__ok(output_logical_op__rc__ok),
- .\logical_op__rc__ok$7 (\output_logical_op__rc__ok$34 ),
+ .\logical_op__rc__ok$7 (\output_logical_op__rc__ok$35 ),
.logical_op__rc__rc(output_logical_op__rc__rc),
- .\logical_op__rc__rc$6 (\output_logical_op__rc__rc$33 ),
+ .\logical_op__rc__rc$6 (\output_logical_op__rc__rc$34 ),
+ .logical_op__sv_ldstmode(output_logical_op__sv_ldstmode),
+ .\logical_op__sv_ldstmode$23 (\output_logical_op__sv_ldstmode$51 ),
.logical_op__sv_pred_dz(output_logical_op__sv_pred_dz),
- .\logical_op__sv_pred_dz$21 (\output_logical_op__sv_pred_dz$48 ),
+ .\logical_op__sv_pred_dz$21 (\output_logical_op__sv_pred_dz$49 ),
.logical_op__sv_pred_sz(output_logical_op__sv_pred_sz),
- .\logical_op__sv_pred_sz$20 (\output_logical_op__sv_pred_sz$47 ),
+ .\logical_op__sv_pred_sz$20 (\output_logical_op__sv_pred_sz$48 ),
.logical_op__sv_saturate(output_logical_op__sv_saturate),
- .\logical_op__sv_saturate$22 (\output_logical_op__sv_saturate$49 ),
+ .\logical_op__sv_saturate$22 (\output_logical_op__sv_saturate$50 ),
.logical_op__write_cr0(output_logical_op__write_cr0),
- .\logical_op__write_cr0$14 (\output_logical_op__write_cr0$41 ),
+ .\logical_op__write_cr0$14 (\output_logical_op__write_cr0$42 ),
.logical_op__zero_a(output_logical_op__zero_a),
- .\logical_op__zero_a$11 (\output_logical_op__zero_a$38 ),
+ .\logical_op__zero_a$11 (\output_logical_op__zero_a$39 ),
.muxid(output_muxid),
- .\muxid$1 (\output_muxid$28 ),
+ .\muxid$1 (\output_muxid$29 ),
.o(output_o),
- .\o$24 (\output_o$51 ),
+ .\o$25 (\output_o$53 ),
.o_ok(output_o_ok),
- .\o_ok$25 (\output_o_ok$52 ),
+ .\o_ok$26 (\output_o_ok$54 ),
.xer_so(output_xer_so)
);
\p$52 p (
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \muxid$1$next = \muxid$59 ;
+ \muxid$1$next = \muxid$61 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \muxid$1$next = \muxid$59 ;
+ \muxid$1$next = \muxid$61 ;
endcase
end
always @* begin
\logical_op__sv_pred_sz$20$next = \logical_op__sv_pred_sz$20 ;
\logical_op__sv_pred_dz$21$next = \logical_op__sv_pred_dz$21 ;
\logical_op__sv_saturate$22$next = \logical_op__sv_saturate$22 ;
- \logical_op__SV_Ptype$23$next = \logical_op__SV_Ptype$23 ;
+ \logical_op__sv_ldstmode$23$next = \logical_op__sv_ldstmode$23 ;
+ \logical_op__SV_Ptype$24$next = \logical_op__SV_Ptype$24 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \logical_op__SV_Ptype$23$next , \logical_op__sv_saturate$22$next , \logical_op__sv_pred_dz$21$next , \logical_op__sv_pred_sz$20$next , \logical_op__insn$19$next , \logical_op__data_len$18$next , \logical_op__is_signed$17$next , \logical_op__is_32bit$16$next , \logical_op__output_carry$15$next , \logical_op__write_cr0$14$next , \logical_op__invert_out$13$next , \logical_op__input_carry$12$next , \logical_op__zero_a$11$next , \logical_op__invert_in$10$next , \logical_op__oe__ok$9$next , \logical_op__oe__oe$8$next , \logical_op__rc__ok$7$next , \logical_op__rc__rc$6$next , \logical_op__imm_data__ok$5$next , \logical_op__imm_data__data$4$next , \logical_op__fn_unit$3$next , \logical_op__insn_type$2$next } = { \logical_op__SV_Ptype$81 , \logical_op__sv_saturate$80 , \logical_op__sv_pred_dz$79 , \logical_op__sv_pred_sz$78 , \logical_op__insn$77 , \logical_op__data_len$76 , \logical_op__is_signed$75 , \logical_op__is_32bit$74 , \logical_op__output_carry$73 , \logical_op__write_cr0$72 , \logical_op__invert_out$71 , \logical_op__input_carry$70 , \logical_op__zero_a$69 , \logical_op__invert_in$68 , \logical_op__oe__ok$67 , \logical_op__oe__oe$66 , \logical_op__rc__ok$65 , \logical_op__rc__rc$64 , \logical_op__imm_data__ok$63 , \logical_op__imm_data__data$62 , \logical_op__fn_unit$61 , \logical_op__insn_type$60 };
+ { \logical_op__SV_Ptype$24$next , \logical_op__sv_ldstmode$23$next , \logical_op__sv_saturate$22$next , \logical_op__sv_pred_dz$21$next , \logical_op__sv_pred_sz$20$next , \logical_op__insn$19$next , \logical_op__data_len$18$next , \logical_op__is_signed$17$next , \logical_op__is_32bit$16$next , \logical_op__output_carry$15$next , \logical_op__write_cr0$14$next , \logical_op__invert_out$13$next , \logical_op__input_carry$12$next , \logical_op__zero_a$11$next , \logical_op__invert_in$10$next , \logical_op__oe__ok$9$next , \logical_op__oe__oe$8$next , \logical_op__rc__ok$7$next , \logical_op__rc__rc$6$next , \logical_op__imm_data__ok$5$next , \logical_op__imm_data__data$4$next , \logical_op__fn_unit$3$next , \logical_op__insn_type$2$next } = { \logical_op__SV_Ptype$84 , \logical_op__sv_ldstmode$83 , \logical_op__sv_saturate$82 , \logical_op__sv_pred_dz$81 , \logical_op__sv_pred_sz$80 , \logical_op__insn$79 , \logical_op__data_len$78 , \logical_op__is_signed$77 , \logical_op__is_32bit$76 , \logical_op__output_carry$75 , \logical_op__write_cr0$74 , \logical_op__invert_out$73 , \logical_op__input_carry$72 , \logical_op__zero_a$71 , \logical_op__invert_in$70 , \logical_op__oe__ok$69 , \logical_op__oe__oe$68 , \logical_op__rc__ok$67 , \logical_op__rc__rc$66 , \logical_op__imm_data__ok$65 , \logical_op__imm_data__data$64 , \logical_op__fn_unit$63 , \logical_op__insn_type$62 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \logical_op__SV_Ptype$23$next , \logical_op__sv_saturate$22$next , \logical_op__sv_pred_dz$21$next , \logical_op__sv_pred_sz$20$next , \logical_op__insn$19$next , \logical_op__data_len$18$next , \logical_op__is_signed$17$next , \logical_op__is_32bit$16$next , \logical_op__output_carry$15$next , \logical_op__write_cr0$14$next , \logical_op__invert_out$13$next , \logical_op__input_carry$12$next , \logical_op__zero_a$11$next , \logical_op__invert_in$10$next , \logical_op__oe__ok$9$next , \logical_op__oe__oe$8$next , \logical_op__rc__ok$7$next , \logical_op__rc__rc$6$next , \logical_op__imm_data__ok$5$next , \logical_op__imm_data__data$4$next , \logical_op__fn_unit$3$next , \logical_op__insn_type$2$next } = { \logical_op__SV_Ptype$81 , \logical_op__sv_saturate$80 , \logical_op__sv_pred_dz$79 , \logical_op__sv_pred_sz$78 , \logical_op__insn$77 , \logical_op__data_len$76 , \logical_op__is_signed$75 , \logical_op__is_32bit$74 , \logical_op__output_carry$73 , \logical_op__write_cr0$72 , \logical_op__invert_out$71 , \logical_op__input_carry$70 , \logical_op__zero_a$69 , \logical_op__invert_in$68 , \logical_op__oe__ok$67 , \logical_op__oe__oe$66 , \logical_op__rc__ok$65 , \logical_op__rc__rc$64 , \logical_op__imm_data__ok$63 , \logical_op__imm_data__data$62 , \logical_op__fn_unit$61 , \logical_op__insn_type$60 };
+ { \logical_op__SV_Ptype$24$next , \logical_op__sv_ldstmode$23$next , \logical_op__sv_saturate$22$next , \logical_op__sv_pred_dz$21$next , \logical_op__sv_pred_sz$20$next , \logical_op__insn$19$next , \logical_op__data_len$18$next , \logical_op__is_signed$17$next , \logical_op__is_32bit$16$next , \logical_op__output_carry$15$next , \logical_op__write_cr0$14$next , \logical_op__invert_out$13$next , \logical_op__input_carry$12$next , \logical_op__zero_a$11$next , \logical_op__invert_in$10$next , \logical_op__oe__ok$9$next , \logical_op__oe__oe$8$next , \logical_op__rc__ok$7$next , \logical_op__rc__rc$6$next , \logical_op__imm_data__ok$5$next , \logical_op__imm_data__data$4$next , \logical_op__fn_unit$3$next , \logical_op__insn_type$2$next } = { \logical_op__SV_Ptype$84 , \logical_op__sv_ldstmode$83 , \logical_op__sv_saturate$82 , \logical_op__sv_pred_dz$81 , \logical_op__sv_pred_sz$80 , \logical_op__insn$79 , \logical_op__data_len$78 , \logical_op__is_signed$77 , \logical_op__is_32bit$76 , \logical_op__output_carry$75 , \logical_op__write_cr0$74 , \logical_op__invert_out$73 , \logical_op__input_carry$72 , \logical_op__zero_a$71 , \logical_op__invert_in$70 , \logical_op__oe__ok$69 , \logical_op__oe__oe$68 , \logical_op__rc__ok$67 , \logical_op__rc__rc$66 , \logical_op__imm_data__ok$65 , \logical_op__imm_data__data$64 , \logical_op__fn_unit$63 , \logical_op__insn_type$62 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
end
always @* begin
if (\initial ) begin end
- \o$24$next = \o$24 ;
- \o_ok$25$next = \o_ok$25 ;
+ \o$25$next = \o$25 ;
+ \o_ok$26$next = \o_ok$26 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \o_ok$25$next , \o$24$next } = { \o_ok$83 , \o$82 };
+ { \o_ok$26$next , \o$25$next } = { \o_ok$86 , \o$85 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \o_ok$25$next , \o$24$next } = { \o_ok$83 , \o$82 };
+ { \o_ok$26$next , \o$25$next } = { \o_ok$86 , \o$85 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
1'h1:
- \o_ok$25$next = 1'h0;
+ \o_ok$26$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
- \cr_a$26$next = \cr_a$26 ;
- \cr_a_ok$27$next = \cr_a_ok$27 ;
+ \cr_a$27$next = \cr_a$27 ;
+ \cr_a_ok$28$next = \cr_a_ok$28 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \cr_a_ok$27$next , \cr_a$26$next } = { \cr_a_ok$85 , \cr_a$84 };
+ { \cr_a_ok$28$next , \cr_a$27$next } = { \cr_a_ok$88 , \cr_a$87 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \cr_a_ok$27$next , \cr_a$26$next } = { \cr_a_ok$85 , \cr_a$84 };
+ { \cr_a_ok$28$next , \cr_a$27$next } = { \cr_a_ok$88 , \cr_a$87 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
1'h1:
- \cr_a_ok$27$next = 1'h0;
+ \cr_a_ok$28$next = 1'h0;
endcase
end
assign p_ready_o = n_i_rdy_data;
assign n_valid_o = r_busy;
- assign { \cr_a_ok$85 , \cr_a$84 } = { output_cr_a_ok, \output_cr_a$53 };
- assign { \o_ok$83 , \o$82 } = { \output_o_ok$52 , \output_o$51 };
- assign { \logical_op__SV_Ptype$81 , \logical_op__sv_saturate$80 , \logical_op__sv_pred_dz$79 , \logical_op__sv_pred_sz$78 , \logical_op__insn$77 , \logical_op__data_len$76 , \logical_op__is_signed$75 , \logical_op__is_32bit$74 , \logical_op__output_carry$73 , \logical_op__write_cr0$72 , \logical_op__invert_out$71 , \logical_op__input_carry$70 , \logical_op__zero_a$69 , \logical_op__invert_in$68 , \logical_op__oe__ok$67 , \logical_op__oe__oe$66 , \logical_op__rc__ok$65 , \logical_op__rc__rc$64 , \logical_op__imm_data__ok$63 , \logical_op__imm_data__data$62 , \logical_op__fn_unit$61 , \logical_op__insn_type$60 } = { \output_logical_op__SV_Ptype$50 , \output_logical_op__sv_saturate$49 , \output_logical_op__sv_pred_dz$48 , \output_logical_op__sv_pred_sz$47 , \output_logical_op__insn$46 , \output_logical_op__data_len$45 , \output_logical_op__is_signed$44 , \output_logical_op__is_32bit$43 , \output_logical_op__output_carry$42 , \output_logical_op__write_cr0$41 , \output_logical_op__invert_out$40 , \output_logical_op__input_carry$39 , \output_logical_op__zero_a$38 , \output_logical_op__invert_in$37 , \output_logical_op__oe__ok$36 , \output_logical_op__oe__oe$35 , \output_logical_op__rc__ok$34 , \output_logical_op__rc__rc$33 , \output_logical_op__imm_data__ok$32 , \output_logical_op__imm_data__data$31 , \output_logical_op__fn_unit$30 , \output_logical_op__insn_type$29 };
- assign \muxid$59 = \output_muxid$28 ;
- assign p_valid_i_p_ready_o = \$57 ;
+ assign { \cr_a_ok$88 , \cr_a$87 } = { output_cr_a_ok, \output_cr_a$55 };
+ assign { \o_ok$86 , \o$85 } = { \output_o_ok$54 , \output_o$53 };
+ assign { \logical_op__SV_Ptype$84 , \logical_op__sv_ldstmode$83 , \logical_op__sv_saturate$82 , \logical_op__sv_pred_dz$81 , \logical_op__sv_pred_sz$80 , \logical_op__insn$79 , \logical_op__data_len$78 , \logical_op__is_signed$77 , \logical_op__is_32bit$76 , \logical_op__output_carry$75 , \logical_op__write_cr0$74 , \logical_op__invert_out$73 , \logical_op__input_carry$72 , \logical_op__zero_a$71 , \logical_op__invert_in$70 , \logical_op__oe__ok$69 , \logical_op__oe__oe$68 , \logical_op__rc__ok$67 , \logical_op__rc__rc$66 , \logical_op__imm_data__ok$65 , \logical_op__imm_data__data$64 , \logical_op__fn_unit$63 , \logical_op__insn_type$62 } = { \output_logical_op__SV_Ptype$52 , \output_logical_op__sv_ldstmode$51 , \output_logical_op__sv_saturate$50 , \output_logical_op__sv_pred_dz$49 , \output_logical_op__sv_pred_sz$48 , \output_logical_op__insn$47 , \output_logical_op__data_len$46 , \output_logical_op__is_signed$45 , \output_logical_op__is_32bit$44 , \output_logical_op__output_carry$43 , \output_logical_op__write_cr0$42 , \output_logical_op__invert_out$41 , \output_logical_op__input_carry$40 , \output_logical_op__zero_a$39 , \output_logical_op__invert_in$38 , \output_logical_op__oe__ok$37 , \output_logical_op__oe__oe$36 , \output_logical_op__rc__ok$35 , \output_logical_op__rc__rc$34 , \output_logical_op__imm_data__ok$33 , \output_logical_op__imm_data__data$32 , \output_logical_op__fn_unit$31 , \output_logical_op__insn_type$30 };
+ assign \muxid$61 = \output_muxid$29 ;
+ assign p_valid_i_p_ready_o = \$59 ;
assign n_i_rdy_data = n_ready_i;
- assign \p_valid_i$56 = p_valid_i;
- assign { \xer_so_ok$55 , output_xer_so } = { xer_so_ok, xer_so };
- assign { \cr_a_ok$54 , output_cr_a } = { cr_a_ok, cr_a };
+ assign \p_valid_i$58 = p_valid_i;
+ assign { \xer_so_ok$57 , output_xer_so } = { xer_so_ok, xer_so };
+ assign { \cr_a_ok$56 , output_cr_a } = { cr_a_ok, cr_a };
assign { output_o_ok, output_o } = { o_ok, o };
- assign { output_logical_op__SV_Ptype, output_logical_op__sv_saturate, output_logical_op__sv_pred_dz, output_logical_op__sv_pred_sz, output_logical_op__insn, output_logical_op__data_len, output_logical_op__is_signed, output_logical_op__is_32bit, output_logical_op__output_carry, output_logical_op__write_cr0, output_logical_op__invert_out, output_logical_op__input_carry, output_logical_op__zero_a, output_logical_op__invert_in, output_logical_op__oe__ok, output_logical_op__oe__oe, output_logical_op__rc__ok, output_logical_op__rc__rc, output_logical_op__imm_data__ok, output_logical_op__imm_data__data, output_logical_op__fn_unit, output_logical_op__insn_type } = { logical_op__SV_Ptype, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
+ assign { output_logical_op__SV_Ptype, output_logical_op__sv_ldstmode, output_logical_op__sv_saturate, output_logical_op__sv_pred_dz, output_logical_op__sv_pred_sz, output_logical_op__insn, output_logical_op__data_len, output_logical_op__is_signed, output_logical_op__is_32bit, output_logical_op__output_carry, output_logical_op__write_cr0, output_logical_op__invert_out, output_logical_op__input_carry, output_logical_op__zero_a, output_logical_op__invert_in, output_logical_op__oe__ok, output_logical_op__oe__oe, output_logical_op__rc__ok, output_logical_op__rc__rc, output_logical_op__imm_data__ok, output_logical_op__imm_data__data, output_logical_op__fn_unit, output_logical_op__insn_type } = { logical_op__SV_Ptype, logical_op__sv_ldstmode, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
assign output_muxid = muxid;
endmodule
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$93 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" *)
wire \$95 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
input dbus__ack;
reg \m_store_err_o$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:61" *)
input m_valid_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:99" *)
input wb_dcache_en;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" *)
input [47:0] x_addr_i;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.main" *)
(* generator = "nMigen" *)
-module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, alu_op__sv_pred_sz, alu_op__sv_pred_dz, alu_op__sv_saturate, alu_op__SV_Ptype, ra, rb, xer_so, xer_ca, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , \alu_op__sv_pred_sz$20 , \alu_op__sv_pred_dz$21 , \alu_op__sv_saturate$22 , \alu_op__SV_Ptype$23 , o, o_ok, cr_a, cr_a_ok, \xer_ca$24 , xer_ca_ok, xer_ov, xer_ov_ok, \xer_so$25 , muxid);
+module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, alu_op__sv_pred_sz, alu_op__sv_pred_dz, alu_op__sv_saturate, alu_op__sv_ldstmode, alu_op__SV_Ptype, ra, rb, xer_so, xer_ca, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , \alu_op__sv_pred_sz$20 , \alu_op__sv_pred_dz$21 , \alu_op__sv_saturate$22 , \alu_op__sv_ldstmode$23 , \alu_op__SV_Ptype$24 , o, o_ok, cr_a, cr_a_ok, \xer_ca$25 , xer_ca_ok, xer_ov, xer_ov_ok, \xer_so$26 , muxid);
reg \initial = 0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *)
+ wire \$100 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" *)
- wire \$101 ;
+ wire \$102 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" *)
- wire \$103 ;
+ wire \$104 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" *)
- wire \$105 ;
+ wire \$106 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" *)
- wire \$107 ;
+ wire \$108 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" *)
- wire \$109 ;
+ wire \$110 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" *)
- wire \$111 ;
+ wire \$112 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" *)
- wire \$113 ;
+ wire \$114 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" *)
- wire \$115 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *)
- wire \$117 ;
+ wire \$116 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *)
- wire \$119 ;
+ wire \$118 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *)
wire \$120 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *)
- wire \$123 ;
+ wire \$121 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *)
- wire \$125 ;
+ wire \$124 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *)
- wire \$127 ;
+ wire \$126 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *)
wire \$128 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *)
- wire \$131 ;
+ wire \$129 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *)
+ wire \$132 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *)
- wire \$133 ;
+ wire \$134 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *)
- wire \$135 ;
+ wire \$136 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *)
- wire \$137 ;
+ wire \$138 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *)
- wire \$139 ;
+ wire \$140 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *)
- wire \$141 ;
+ wire \$142 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *)
- wire \$143 ;
+ wire \$144 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *)
- wire \$145 ;
+ wire \$146 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *)
- wire \$147 ;
+ wire \$148 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" *)
- wire \$26 ;
+ wire \$27 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" *)
- wire \$28 ;
+ wire \$29 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *)
- wire \$30 ;
+ wire \$31 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *)
- wire \$32 ;
+ wire \$33 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *)
- wire \$34 ;
+ wire \$35 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *)
- wire \$36 ;
+ wire \$37 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *)
- wire \$38 ;
+ wire \$39 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *)
- wire \$40 ;
+ wire \$41 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *)
- wire \$42 ;
+ wire \$43 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *)
- wire \$44 ;
+ wire \$45 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *)
- wire \$46 ;
+ wire \$47 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *)
- wire \$48 ;
+ wire \$49 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *)
- wire \$50 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" *)
- wire [66:0] \$52 ;
+ wire \$51 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" *)
wire [66:0] \$53 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" *)
+ wire [66:0] \$54 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" *)
- wire [63:0] \$55 ;
+ wire [63:0] \$56 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" *)
- wire \$57 ;
+ wire \$58 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" *)
- wire \$59 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *)
- wire \$61 ;
+ wire \$60 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *)
wire \$62 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *)
- wire [31:0] \$63 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *)
- wire \$67 ;
+ wire \$63 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *)
+ wire [31:0] \$64 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *)
wire \$68 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *)
- wire [31:0] \$69 ;
+ wire \$69 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *)
+ wire [31:0] \$70 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *)
- wire \$73 ;
+ wire \$74 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *)
- wire \$75 ;
+ wire \$76 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *)
- wire \$77 ;
+ wire \$78 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" *)
- wire \$79 ;
+ wire \$80 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" *)
- wire \$81 ;
+ wire \$82 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *)
- wire \$83 ;
+ wire \$84 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *)
- wire \$85 ;
+ wire \$86 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" *)
- wire \$87 ;
+ wire \$88 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *)
- wire \$89 ;
+ wire \$90 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *)
- wire \$91 ;
+ wire \$92 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" *)
- wire \$93 ;
+ wire \$94 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *)
- wire \$95 ;
+ wire \$96 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *)
- wire \$97 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *)
- wire \$99 ;
+ wire \$98 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:65" *)
reg [63:0] a_i;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:99" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \alu_op__SV_Ptype$23 ;
+ output [1:0] \alu_op__SV_Ptype$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [3:0] alu_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \alu_op__rc__rc$6 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] alu_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \alu_op__sv_ldstmode$23 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [1:0] xer_ca;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [1:0] \xer_ca$24 ;
- reg [1:0] \xer_ca$24 ;
+ output [1:0] \xer_ca$25 ;
+ reg [1:0] \xer_ca$25 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_ca_ok;
reg xer_ca_ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \xer_so$25 ;
+ output \xer_so$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:103" *)
reg zerohi;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102" *)
reg zerolo;
- assign \$99 = msb_a != (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *) msb_b;
- assign \$101 = is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" *) carry_32 : carry_64;
- assign \$103 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" *) eqs;
- assign \$105 = alu_op__data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" *) 1'h1;
- assign \$107 = alu_op__data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" *) 2'h2;
- assign \$109 = alu_op__data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" *) 3'h4;
- assign \$111 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" *) eqs;
- assign \$113 = a_i[32] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" *) b_i[32];
- assign \$115 = add_o[33] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" *) \$113 ;
- assign \$117 = ca[0] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) add_o[64];
- assign \$120 = a_i[63] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) b_i[63];
- assign \$119 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) \$120 ;
- assign \$123 = \$117 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) \$119 ;
- assign \$125 = ca[1] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) add_o[32];
- assign \$128 = a_i[31] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) b_i[31];
- assign \$127 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) \$128 ;
- assign \$131 = \$125 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) \$127 ;
- assign \$133 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[7:0];
- assign \$135 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[15:8];
- assign \$137 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[23:16];
- assign \$139 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[31:24];
- assign \$141 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[39:32];
- assign \$143 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[47:40];
- assign \$145 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[55:48];
- assign \$147 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[63:56];
- assign \$26 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" *) 7'h0a;
- assign \$28 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" *) alu_op__insn[21];
- assign \$30 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *) 7'h0a;
- assign \$32 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *) 7'h0a;
- assign \$34 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *) 7'h02;
- assign \$36 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) 7'h0a;
- assign \$38 = \$34 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) \$36 ;
- assign \$40 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *) 7'h02;
- assign \$42 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) 7'h0a;
- assign \$44 = \$40 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) \$42 ;
- assign \$46 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *) 7'h02;
- assign \$48 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) 7'h0a;
- assign \$50 = \$46 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) \$48 ;
- assign \$53 = add_a + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" *) add_b;
- assign \$55 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" *) ra;
- assign \$57 = add_o[33] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" *) ra[32];
- assign \$59 = \$57 ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" *) rb[32];
- assign \$63 = a_n[31:0] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *) rb[31:0];
- assign \$62 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *) \$63 ;
- assign \$61 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *) \$62 ;
- assign \$69 = a_n[63:32] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *) rb[63:32];
- assign \$68 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *) \$69 ;
- assign \$67 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *) \$68 ;
- assign \$73 = is_32bit | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) zerohi;
- assign \$75 = zerolo & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) \$73 ;
- assign \$77 = msb_a != (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *) msb_b;
- assign \$79 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" *) a_lt;
- assign \$81 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" *) a_lt;
- assign \$83 = is_32bit | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) zerohi;
- assign \$85 = zerolo & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) \$83 ;
- assign \$87 = is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" *) a_n[31] : a_n[63];
- assign \$89 = is_32bit | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) zerohi;
- assign \$91 = zerolo & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) \$89 ;
- assign \$93 = is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" *) rb[31] : rb[63];
- assign \$95 = is_32bit | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) zerohi;
- assign \$97 = zerolo & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) \$95 ;
+ assign \$100 = msb_a != (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *) msb_b;
+ assign \$102 = is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" *) carry_32 : carry_64;
+ assign \$104 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" *) eqs;
+ assign \$106 = alu_op__data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" *) 1'h1;
+ assign \$108 = alu_op__data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" *) 2'h2;
+ assign \$110 = alu_op__data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" *) 3'h4;
+ assign \$112 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" *) eqs;
+ assign \$114 = a_i[32] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" *) b_i[32];
+ assign \$116 = add_o[33] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" *) \$114 ;
+ assign \$118 = ca[0] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) add_o[64];
+ assign \$121 = a_i[63] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) b_i[63];
+ assign \$120 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) \$121 ;
+ assign \$124 = \$118 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) \$120 ;
+ assign \$126 = ca[1] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) add_o[32];
+ assign \$129 = a_i[31] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) b_i[31];
+ assign \$128 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) \$129 ;
+ assign \$132 = \$126 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) \$128 ;
+ assign \$134 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[7:0];
+ assign \$136 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[15:8];
+ assign \$138 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[23:16];
+ assign \$140 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[31:24];
+ assign \$142 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[39:32];
+ assign \$144 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[47:40];
+ assign \$146 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[55:48];
+ assign \$148 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[63:56];
+ assign \$27 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" *) 7'h0a;
+ assign \$29 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" *) alu_op__insn[21];
+ assign \$31 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *) 7'h0a;
+ assign \$33 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *) 7'h0a;
+ assign \$35 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *) 7'h02;
+ assign \$37 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) 7'h0a;
+ assign \$39 = \$35 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) \$37 ;
+ assign \$41 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *) 7'h02;
+ assign \$43 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) 7'h0a;
+ assign \$45 = \$41 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) \$43 ;
+ assign \$47 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *) 7'h02;
+ assign \$49 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) 7'h0a;
+ assign \$51 = \$47 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) \$49 ;
+ assign \$54 = add_a + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" *) add_b;
+ assign \$56 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" *) ra;
+ assign \$58 = add_o[33] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" *) ra[32];
+ assign \$60 = \$58 ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" *) rb[32];
+ assign \$64 = a_n[31:0] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *) rb[31:0];
+ assign \$63 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *) \$64 ;
+ assign \$62 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *) \$63 ;
+ assign \$70 = a_n[63:32] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *) rb[63:32];
+ assign \$69 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *) \$70 ;
+ assign \$68 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *) \$69 ;
+ assign \$74 = is_32bit | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) zerohi;
+ assign \$76 = zerolo & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) \$74 ;
+ assign \$78 = msb_a != (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *) msb_b;
+ assign \$80 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" *) a_lt;
+ assign \$82 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" *) a_lt;
+ assign \$84 = is_32bit | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) zerohi;
+ assign \$86 = zerolo & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) \$84 ;
+ assign \$88 = is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" *) a_n[31] : a_n[63];
+ assign \$90 = is_32bit | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) zerohi;
+ assign \$92 = zerolo & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) \$90 ;
+ assign \$94 = is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" *) rb[31] : rb[63];
+ assign \$96 = is_32bit | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) zerohi;
+ assign \$98 = zerolo & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) \$96 ;
always @* begin
if (\initial ) begin end
is_32bit = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" *)
- casez (\$26 )
+ casez (\$27 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" */
1'h1:
- is_32bit = \$28 ;
+ is_32bit = \$29 ;
endcase
end
always @* begin
if (\initial ) begin end
(* full_case = 32'd1 *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *)
- casez ({ is_32bit, \$30 })
+ casez ({ is_32bit, \$31 })
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" */
2'b?1:
a_i = ra;
/* \nmigen.decoding = "OP_CMP/10" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */
7'h0a:
- zerohi = \$67 ;
+ zerohi = \$68 ;
endcase
end
always @* begin
7'h0a:
(* full_case = 32'd1 *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *)
- casez (\$75 )
+ casez (\$76 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" */
1'h1:
tval[2] = 1'h1;
default:
(* full_case = 32'd1 *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *)
- casez (\$77 )
+ casez (\$78 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" */
1'h1:
tval = { msb_a, msb_b, 1'h0, msb_b, msb_a };
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" */
default:
- tval = { a_lt, \$81 , 1'h0, a_lt, \$79 };
+ tval = { a_lt, \$82 , 1'h0, a_lt, \$80 };
endcase
endcase
endcase
7'h0a:
(* full_case = 32'd1 *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *)
- casez (\$85 )
+ casez (\$86 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" */
1'h1:
/* empty */;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" */
default:
- msb_a = \$87 ;
+ msb_a = \$88 ;
endcase
endcase
end
7'h0a:
(* full_case = 32'd1 *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *)
- casez (\$91 )
+ casez (\$92 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" */
1'h1:
/* empty */;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" */
default:
- msb_b = \$93 ;
+ msb_b = \$94 ;
endcase
endcase
end
7'h0a:
(* full_case = 32'd1 *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *)
- casez (\$97 )
+ casez (\$98 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" */
1'h1:
/* empty */;
default:
(* full_case = 32'd1 *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *)
- casez (\$99 )
+ casez (\$100 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" */
1'h1:
/* empty */;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" */
default:
- a_lt = \$101 ;
+ a_lt = \$102 ;
endcase
endcase
endcase
/* \nmigen.decoding = "OP_CMPEQB/12" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:177" */
7'h0c:
- cr_a = { 1'h0, \$103 , 2'h0 };
+ cr_a = { 1'h0, \$104 , 2'h0 };
endcase
end
always @* begin
7'h1f:
begin
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" *)
- casez (\$105 )
+ casez (\$106 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" */
1'h1:
o = { ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7:0] };
endcase
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" *)
- casez (\$107 )
+ casez (\$108 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" */
1'h1:
o = { ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15:0] };
endcase
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" *)
- casez (\$109 )
+ casez (\$110 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" */
1'h1:
o = { ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31:0] };
/* \nmigen.decoding = "OP_CMPEQB/12" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:177" */
7'h0c:
- o[0] = \$111 ;
+ o[0] = \$112 ;
endcase
end
always @* begin
7'h02:
begin
ca[0] = add_o[65];
- ca[1] = \$115 ;
+ ca[1] = \$116 ;
end
endcase
end
if (\initial ) begin end
(* full_case = 32'd1 *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *)
- casez ({ is_32bit, \$32 })
+ casez ({ is_32bit, \$33 })
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" */
2'b?1:
b_i = rb;
end
always @* begin
if (\initial ) begin end
- \xer_ca$24 = 2'h0;
+ \xer_ca$25 = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *)
casez (alu_op__insn_type)
/* \nmigen.decoding = "OP_CMP/10" */
/* \nmigen.decoding = "OP_ADD/2" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:143" */
7'h02:
- \xer_ca$24 = ca;
+ \xer_ca$25 = ca;
endcase
end
always @* begin
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:143" */
7'h02:
begin
- ov[0] = \$123 ;
- ov[1] = \$131 ;
+ ov[0] = \$124 ;
+ ov[1] = \$132 ;
end
endcase
end
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:177" */
7'h0c:
begin
- eqs[0] = \$133 ;
- eqs[1] = \$135 ;
- eqs[2] = \$137 ;
- eqs[3] = \$139 ;
- eqs[4] = \$141 ;
- eqs[5] = \$143 ;
- eqs[6] = \$145 ;
- eqs[7] = \$147 ;
+ eqs[0] = \$134 ;
+ eqs[1] = \$136 ;
+ eqs[2] = \$138 ;
+ eqs[3] = \$140 ;
+ eqs[4] = \$142 ;
+ eqs[5] = \$144 ;
+ eqs[6] = \$146 ;
+ eqs[7] = \$148 ;
end
endcase
end
if (\initial ) begin end
add_a = 66'h00000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *)
- casez (\$38 )
+ casez (\$39 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" */
1'h1:
add_a = { 1'h0, a_i, xer_ca[0] };
if (\initial ) begin end
add_b = 66'h00000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *)
- casez (\$44 )
+ casez (\$45 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" */
1'h1:
add_b = { 1'h0, b_i, 1'h1 };
if (\initial ) begin end
add_o = 66'h00000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *)
- casez (\$50 )
+ casez (\$51 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" */
1'h1:
- add_o = \$52 [65:0];
+ add_o = \$53 [65:0];
endcase
end
always @* begin
/* \nmigen.decoding = "OP_CMP/10" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */
7'h0a:
- a_n = \$55 ;
+ a_n = \$56 ;
endcase
end
always @* begin
/* \nmigen.decoding = "OP_CMP/10" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */
7'h0a:
- carry_32 = \$59 ;
+ carry_32 = \$60 ;
endcase
end
always @* begin
/* \nmigen.decoding = "OP_CMP/10" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */
7'h0a:
- zerolo = \$61 ;
+ zerolo = \$62 ;
endcase
end
- assign \$52 = \$53 ;
- assign { \alu_op__SV_Ptype$23 , \alu_op__sv_saturate$22 , \alu_op__sv_pred_dz$21 , \alu_op__sv_pred_sz$20 , \alu_op__insn$19 , \alu_op__data_len$18 , \alu_op__is_signed$17 , \alu_op__is_32bit$16 , \alu_op__output_carry$15 , \alu_op__input_carry$14 , \alu_op__write_cr0$13 , \alu_op__invert_out$12 , \alu_op__zero_a$11 , \alu_op__invert_in$10 , \alu_op__oe__ok$9 , \alu_op__oe__oe$8 , \alu_op__rc__ok$7 , \alu_op__rc__rc$6 , \alu_op__imm_data__ok$5 , \alu_op__imm_data__data$4 , \alu_op__fn_unit$3 , \alu_op__insn_type$2 } = { alu_op__SV_Ptype, alu_op__sv_saturate, alu_op__sv_pred_dz, alu_op__sv_pred_sz, alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type };
+ assign \$53 = \$54 ;
+ assign { \alu_op__SV_Ptype$24 , \alu_op__sv_ldstmode$23 , \alu_op__sv_saturate$22 , \alu_op__sv_pred_dz$21 , \alu_op__sv_pred_sz$20 , \alu_op__insn$19 , \alu_op__data_len$18 , \alu_op__is_signed$17 , \alu_op__is_32bit$16 , \alu_op__output_carry$15 , \alu_op__input_carry$14 , \alu_op__write_cr0$13 , \alu_op__invert_out$12 , \alu_op__zero_a$11 , \alu_op__invert_in$10 , \alu_op__oe__ok$9 , \alu_op__oe__oe$8 , \alu_op__rc__ok$7 , \alu_op__rc__rc$6 , \alu_op__imm_data__ok$5 , \alu_op__imm_data__data$4 , \alu_op__fn_unit$3 , \alu_op__insn_type$2 } = { alu_op__SV_Ptype, alu_op__sv_ldstmode, alu_op__sv_saturate, alu_op__sv_pred_dz, alu_op__sv_pred_sz, alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type };
assign \muxid$1 = muxid;
- assign \xer_so$25 = xer_so;
+ assign \xer_so$26 = xer_so;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main" *)
(* generator = "nMigen" *)
-module \main$114 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, sr_op__sv_pred_sz, sr_op__sv_pred_dz, sr_op__sv_saturate, sr_op__SV_Ptype, ra, rb, rc, xer_so, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , \sr_op__sv_pred_sz$19 , \sr_op__sv_pred_dz$20 , \sr_op__sv_saturate$21 , \sr_op__SV_Ptype$22 , o, o_ok, \xer_so$23 , xer_ca, muxid);
+module \main$114 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, sr_op__sv_pred_sz, sr_op__sv_pred_dz, sr_op__sv_saturate, sr_op__sv_ldstmode, sr_op__SV_Ptype, ra, rb, rc, xer_so, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , \sr_op__sv_pred_sz$19 , \sr_op__sv_pred_dz$20 , \sr_op__sv_saturate$21 , \sr_op__sv_ldstmode$22 , \sr_op__SV_Ptype$23 , o, o_ok, \xer_so$24 , xer_ca, muxid);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:46" *)
wire [4:0] mb;
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \sr_op__SV_Ptype$22 ;
+ output [1:0] \sr_op__SV_Ptype$23 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
input sr_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \sr_op__rc__rc$6 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] sr_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \sr_op__sv_ldstmode$22 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \xer_so$23 ;
+ output \xer_so$24 ;
rotator rotator (
.arith(rotator_arith),
.carry_out_o(rotator_carry_out_o),
mode = 4'h8;
endcase
end
- assign { \sr_op__SV_Ptype$22 , \sr_op__sv_saturate$21 , \sr_op__sv_pred_dz$20 , \sr_op__sv_pred_sz$19 , \sr_op__insn$18 , \sr_op__is_signed$17 , \sr_op__is_32bit$16 , \sr_op__output_cr$15 , \sr_op__input_cr$14 , \sr_op__output_carry$13 , \sr_op__input_carry$12 , \sr_op__invert_in$11 , \sr_op__write_cr0$10 , \sr_op__oe__ok$9 , \sr_op__oe__oe$8 , \sr_op__rc__ok$7 , \sr_op__rc__rc$6 , \sr_op__imm_data__ok$5 , \sr_op__imm_data__data$4 , \sr_op__fn_unit$3 , \sr_op__insn_type$2 } = { sr_op__SV_Ptype, sr_op__sv_saturate, sr_op__sv_pred_dz, sr_op__sv_pred_sz, sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type };
+ assign { \sr_op__SV_Ptype$23 , \sr_op__sv_ldstmode$22 , \sr_op__sv_saturate$21 , \sr_op__sv_pred_dz$20 , \sr_op__sv_pred_sz$19 , \sr_op__insn$18 , \sr_op__is_signed$17 , \sr_op__is_32bit$16 , \sr_op__output_cr$15 , \sr_op__input_cr$14 , \sr_op__output_carry$13 , \sr_op__input_carry$12 , \sr_op__invert_in$11 , \sr_op__write_cr0$10 , \sr_op__oe__ok$9 , \sr_op__oe__oe$8 , \sr_op__rc__ok$7 , \sr_op__rc__rc$6 , \sr_op__imm_data__ok$5 , \sr_op__imm_data__data$4 , \sr_op__fn_unit$3 , \sr_op__insn_type$2 } = { sr_op__SV_Ptype, sr_op__sv_ldstmode, sr_op__sv_saturate, sr_op__sv_pred_dz, sr_op__sv_pred_sz, sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type };
assign \muxid$1 = muxid;
- assign \xer_so$23 = xer_so;
+ assign \xer_so$24 = xer_so;
assign xer_ca = { rotator_carry_out_o, rotator_carry_out_o };
assign o = rotator_result_o;
assign { rotator_sign_ext_rs, rotator_clear_right, rotator_clear_left, rotator_right_shift } = mode;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.main" *)
(* generator = "nMigen" *)
-module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_op__imm_data__data, br_op__imm_data__ok, br_op__lk, br_op__is_32bit, br_op__sv_pred_sz, br_op__sv_pred_dz, br_op__sv_saturate, br_op__SV_Ptype, fast1, fast2, cr_a, \muxid$1 , \br_op__cia$2 , \br_op__insn_type$3 , \br_op__fn_unit$4 , \br_op__insn$5 , \br_op__imm_data__data$6 , \br_op__imm_data__ok$7 , \br_op__lk$8 , \br_op__is_32bit$9 , \br_op__sv_pred_sz$10 , \br_op__sv_pred_dz$11 , \br_op__sv_saturate$12 , \br_op__SV_Ptype$13 , \fast1$14 , fast1_ok, \fast2$15 , fast2_ok, nia, nia_ok, muxid);
+module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_op__imm_data__data, br_op__imm_data__ok, br_op__lk, br_op__is_32bit, br_op__sv_pred_sz, br_op__sv_pred_dz, br_op__sv_saturate, br_op__sv_ldstmode, br_op__SV_Ptype, fast1, fast2, cr_a, \muxid$1 , \br_op__cia$2 , \br_op__insn_type$3 , \br_op__fn_unit$4 , \br_op__insn$5 , \br_op__imm_data__data$6 , \br_op__imm_data__ok$7 , \br_op__lk$8 , \br_op__is_32bit$9 , \br_op__sv_pred_sz$10 , \br_op__sv_pred_dz$11 , \br_op__sv_saturate$12 , \br_op__sv_ldstmode$13 , \br_op__SV_Ptype$14 , \fast1$15 , fast1_ok, \fast2$16 , fast2_ok, nia, nia_ok, muxid);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *)
- wire \$16 ;
+ wire \$17 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *)
- wire \$18 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" *)
- wire [64:0] \$20 ;
+ wire \$19 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" *)
wire [64:0] \$21 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" *)
+ wire [64:0] \$22 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" *)
- wire \$23 ;
+ wire \$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" *)
- wire \$25 ;
+ wire \$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" *)
- wire \$27 ;
+ wire \$28 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" *)
- wire \$29 ;
+ wire \$30 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" *)
- wire \$31 ;
+ wire \$32 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" *)
- wire \$33 ;
+ wire \$34 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" *)
- wire \$35 ;
+ wire \$36 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" *)
- wire \$37 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" *)
- wire [64:0] \$39 ;
+ wire \$38 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" *)
wire [64:0] \$40 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" *)
+ wire [64:0] \$41 ;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *)
- wire [63:0] \$42 ;
+ wire [63:0] \$43 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" *)
- wire \$44 ;
+ wire \$45 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" *)
- wire \$46 ;
+ wire \$47 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" *)
- wire \$48 ;
+ wire \$49 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" *)
- wire \$50 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" *)
- wire [64:0] \$52 ;
+ wire \$51 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" *)
wire [64:0] \$53 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" *)
+ wire [64:0] \$54 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:119" *)
reg bc_taken;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:109" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \br_op__SV_Ptype$13 ;
+ output [1:0] \br_op__SV_Ptype$14 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] br_op__cia;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input br_op__lk;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \br_op__lk$8 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] br_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \br_op__sv_ldstmode$13 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input br_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] fast1;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [63:0] \fast1$14 ;
- reg [63:0] \fast1$14 ;
+ output [63:0] \fast1$15 ;
+ reg [63:0] \fast1$15 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output fast1_ok;
reg fast1_ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] fast2;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [63:0] \fast2$15 ;
- reg [63:0] \fast2$15 ;
+ output [63:0] \fast2$16 ;
+ reg [63:0] \fast2$16 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output fast2_ok;
reg fast2_ok;
output [63:0] nia;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output nia_ok;
- assign \$16 = br_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *) 7'h08;
- assign \$18 = br_op__insn[1] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *) \$16 ;
- assign \$21 = br_imm_addr + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" *) br_op__cia;
- assign \$23 = cr_bit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" *) bo[3];
- assign \$25 = \$23 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" *) bo[4];
- assign \$27 = bo[4:3] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" *) 1'h0;
- assign \$29 = bo[4:3] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" *) 1'h1;
- assign \$31 = bo[4] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" *) 1'h1;
- assign \$33 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" *) cr_bit;
- assign \$35 = ctr_zero_bo1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" *) \$33 ;
- assign \$37 = ctr_zero_bo1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" *) cr_bit;
- assign \$40 = fast1 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" *) 1'h1;
- assign \$42 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) fast1[31:0];
- assign \$44 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" *) ctr_n;
- assign \$46 = bo[1] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" *) \$44 ;
- assign \$48 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" *) br_op__insn[6];
- assign \$50 = br_op__insn[10] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" *) \$48 ;
- assign \$53 = br_op__cia + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" *) 3'h4;
+ assign \$17 = br_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *) 7'h08;
+ assign \$19 = br_op__insn[1] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *) \$17 ;
+ assign \$22 = br_imm_addr + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" *) br_op__cia;
+ assign \$24 = cr_bit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" *) bo[3];
+ assign \$26 = \$24 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" *) bo[4];
+ assign \$28 = bo[4:3] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" *) 1'h0;
+ assign \$30 = bo[4:3] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" *) 1'h1;
+ assign \$32 = bo[4] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" *) 1'h1;
+ assign \$34 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" *) cr_bit;
+ assign \$36 = ctr_zero_bo1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" *) \$34 ;
+ assign \$38 = ctr_zero_bo1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" *) cr_bit;
+ assign \$41 = fast1 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" *) 1'h1;
+ assign \$43 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) fast1[31:0];
+ assign \$45 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" *) ctr_n;
+ assign \$47 = bo[1] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" *) \$45 ;
+ assign \$49 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" *) br_op__insn[6];
+ assign \$51 = br_op__insn[10] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" *) \$49 ;
+ assign \$54 = br_op__cia + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" *) 3'h4;
always @* begin
if (\initial ) begin end
(* full_case = 32'd1 *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *)
- casez (\$18 )
+ casez (\$19 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" */
1'h1:
br_addr = br_imm_addr;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:94" */
default:
- br_addr = \$20 [63:0];
+ br_addr = \$21 [63:0];
endcase
end
always @* begin
7'h08:
(* full_case = 32'd1 *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" *)
- casez (\$50 )
+ casez (\$51 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" */
1'h1:
br_imm_addr = { fast1[63:2], 2'h0 };
end
always @* begin
if (\initial ) begin end
- \fast2$15 = 64'h0000000000000000;
+ \fast2$16 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" *)
casez (br_op__lk)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" */
1'h1:
- \fast2$15 = \$52 [63:0];
+ \fast2$16 = \$53 [63:0];
endcase
end
always @* begin
casez (bo[2])
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" */
1'h1:
- bc_taken = \$25 ;
+ bc_taken = \$26 ;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" */
default:
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" *)
- casez ({ \$31 , \$29 , \$27 })
+ casez ({ \$32 , \$30 , \$28 })
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" */
3'b??1:
- bc_taken = \$35 ;
+ bc_taken = \$36 ;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" */
3'b?1?:
- bc_taken = \$37 ;
+ bc_taken = \$38 ;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" */
3'b1??:
bc_taken = ctr_zero_bo1;
/* empty */;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" */
default:
- ctr_n = \$39 [63:0];
+ ctr_n = \$40 [63:0];
endcase
end
always @* begin
if (\initial ) begin end
- \fast1$14 = 64'h0000000000000000;
+ \fast1$15 = 64'h0000000000000000;
(* full_case = 32'd1 *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" *)
casez (bo[2])
/* empty */;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" */
default:
- \fast1$14 = ctr_n;
+ \fast1$15 = ctr_n;
endcase
end
always @* begin
casez (br_op__is_32bit)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130" */
1'h1:
- ctr_m = \$42 ;
+ ctr_m = \$43 ;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:132" */
default:
ctr_m = fast1;
/* empty */;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" */
default:
- ctr_zero_bo1 = \$46 ;
+ ctr_zero_bo1 = \$47 ;
endcase
end
- assign \$20 = \$21 ;
- assign \$39 = \$40 ;
- assign \$52 = \$53 ;
- assign { \br_op__SV_Ptype$13 , \br_op__sv_saturate$12 , \br_op__sv_pred_dz$11 , \br_op__sv_pred_sz$10 , \br_op__is_32bit$9 , \br_op__lk$8 , \br_op__imm_data__ok$7 , \br_op__imm_data__data$6 , \br_op__insn$5 , \br_op__fn_unit$4 , \br_op__insn_type$3 , \br_op__cia$2 } = { br_op__SV_Ptype, br_op__sv_saturate, br_op__sv_pred_dz, br_op__sv_pred_sz, br_op__is_32bit, br_op__lk, br_op__imm_data__ok, br_op__imm_data__data, br_op__insn, br_op__fn_unit, br_op__insn_type, br_op__cia };
+ assign \$21 = \$22 ;
+ assign \$40 = \$41 ;
+ assign \$53 = \$54 ;
+ assign { \br_op__SV_Ptype$14 , \br_op__sv_ldstmode$13 , \br_op__sv_saturate$12 , \br_op__sv_pred_dz$11 , \br_op__sv_pred_sz$10 , \br_op__is_32bit$9 , \br_op__lk$8 , \br_op__imm_data__ok$7 , \br_op__imm_data__data$6 , \br_op__insn$5 , \br_op__fn_unit$4 , \br_op__insn_type$3 , \br_op__cia$2 } = { br_op__SV_Ptype, br_op__sv_ldstmode, br_op__sv_saturate, br_op__sv_pred_dz, br_op__sv_pred_sz, br_op__is_32bit, br_op__lk, br_op__imm_data__ok, br_op__imm_data__data, br_op__insn, br_op__fn_unit, br_op__insn_type, br_op__cia };
assign \muxid$1 = muxid;
assign nia_ok = br_taken;
assign nia = br_addr;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.main" *)
(* generator = "nMigen" *)
-module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__svstate, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, trap_op__sv_pred_sz, trap_op__sv_pred_dz, trap_op__sv_saturate, trap_op__SV_Ptype, ra, rb, fast1, fast2, \muxid$1 , \trap_op__insn_type$2 , \trap_op__fn_unit$3 , \trap_op__insn$4 , \trap_op__msr$5 , \trap_op__cia$6 , \trap_op__svstate$7 , \trap_op__is_32bit$8 , \trap_op__traptype$9 , \trap_op__trapaddr$10 , \trap_op__ldst_exc$11 , \trap_op__sv_pred_sz$12 , \trap_op__sv_pred_dz$13 , \trap_op__sv_saturate$14 , \trap_op__SV_Ptype$15 , o, o_ok, \fast1$16 , fast1_ok, \fast2$17 , fast2_ok, fast3, fast3_ok, nia, nia_ok, msr, msr_ok, svstate, svstate_ok, muxid);
+module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__svstate, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, trap_op__sv_pred_sz, trap_op__sv_pred_dz, trap_op__sv_saturate, trap_op__sv_ldstmode, trap_op__SV_Ptype, ra, rb, fast1, fast2, \muxid$1 , \trap_op__insn_type$2 , \trap_op__fn_unit$3 , \trap_op__insn$4 , \trap_op__msr$5 , \trap_op__cia$6 , \trap_op__svstate$7 , \trap_op__is_32bit$8 , \trap_op__traptype$9 , \trap_op__trapaddr$10 , \trap_op__ldst_exc$11 , \trap_op__sv_pred_sz$12 , \trap_op__sv_pred_dz$13 , \trap_op__sv_saturate$14 , \trap_op__sv_ldstmode$15 , \trap_op__SV_Ptype$16 , o, o_ok, \fast1$17 , fast1_ok, \fast2$18 , fast2_ok, fast3, fast3_ok, nia, nia_ok, msr, msr_ok, svstate, svstate_ok, muxid);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *)
- wire [63:0] \$18 ;
+ wire [63:0] \$19 ;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *)
- wire [63:0] \$20 ;
+ wire [63:0] \$21 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171" *)
- wire \$22 ;
+ wire \$23 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:172" *)
- wire \$24 ;
+ wire \$25 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173" *)
- wire \$26 ;
+ wire \$27 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:174" *)
- wire \$28 ;
+ wire \$29 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175" *)
- wire \$30 ;
+ wire \$31 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" *)
- wire \$32 ;
+ wire \$33 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" *)
- wire [4:0] \$33 ;
+ wire [4:0] \$34 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" *)
- wire \$36 ;
+ wire \$37 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" *)
- wire \$38 ;
+ wire \$39 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" *)
- wire [63:0] \$40 ;
+ wire [63:0] \$41 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" *)
- wire [19:0] \$41 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:331" *)
- wire [64:0] \$44 ;
+ wire [19:0] \$42 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:331" *)
wire [64:0] \$45 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:331" *)
+ wire [64:0] \$46 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:198" *)
- wire \$47 ;
+ wire \$48 ;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
- wire \$49 ;
+ wire \$50 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:201" *)
- wire [7:0] \$50 ;
+ wire [7:0] \$51 ;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
- wire \$53 ;
+ wire \$54 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:203" *)
- wire [7:0] \$54 ;
+ wire [7:0] \$55 ;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
- wire \$57 ;
+ wire \$58 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:205" *)
- wire [7:0] \$58 ;
+ wire [7:0] \$59 ;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
- wire \$61 ;
+ wire \$62 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:207" *)
- wire [7:0] \$62 ;
+ wire [7:0] \$63 ;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
- wire \$65 ;
+ wire \$66 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:221" *)
- wire [7:0] \$66 ;
+ wire [7:0] \$67 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \$69 ;
+ wire [63:0] \$70 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \$71 ;
+ wire [63:0] \$72 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \$73 ;
+ wire [63:0] \$74 ;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
- wire \$75 ;
+ wire \$76 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:207" *)
- wire [7:0] \$76 ;
+ wire [7:0] \$77 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [64:0] \$79 ;
+ wire [64:0] \$80 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:246" *)
- wire \$81 ;
+ wire \$82 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:252" *)
- wire \$83 ;
+ wire \$84 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:253" *)
- wire \$85 ;
+ wire \$86 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:253" *)
- wire \$87 ;
+ wire \$88 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:268" *)
- wire \$89 ;
+ wire \$90 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:298" *)
- wire \$91 ;
+ wire \$92 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:311" *)
- wire \$93 ;
+ wire \$94 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:312" *)
- wire \$95 ;
+ wire \$96 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:312" *)
- wire \$97 ;
+ wire \$98 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149" *)
reg [63:0] a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:146" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] fast1;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [63:0] \fast1$16 ;
- reg [63:0] \fast1$16 ;
+ output [63:0] \fast1$17 ;
+ reg [63:0] \fast1$17 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output fast1_ok;
reg fast1_ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] fast2;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [63:0] \fast2$17 ;
- reg [63:0] \fast2$17 ;
+ output [63:0] \fast2$18 ;
+ reg [63:0] \fast2$18 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output fast2_ok;
reg fast2_ok;
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \trap_op__SV_Ptype$15 ;
+ output [1:0] \trap_op__SV_Ptype$16 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] trap_op__cia;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] trap_op__msr;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output [63:0] \trap_op__msr$5 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] trap_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \trap_op__sv_ldstmode$15 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input trap_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg trapexc_rc_error;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *)
reg trapexc_segment_fault;
- assign \$18 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) ra[31:0];
- assign \$20 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) rb[31:0];
- assign \$22 = $signed(a_s) < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171" *) $signed(b_s);
- assign \$24 = $signed(a_s) > (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:172" *) $signed(b_s);
- assign \$26 = a < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173" *) b;
- assign \$28 = a > (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:174" *) b;
- assign \$30 = a == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175" *) b;
- assign \$33 = trap_bits & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" *) to;
- assign \$32 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" *) \$33 ;
- assign \$36 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" *) trap_op__traptype;
- assign \$38 = \$32 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" *) \$36 ;
- assign \$41 = trap_op__trapaddr <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" *) 3'h4;
- assign \$40 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" *) \$41 ;
- assign \$45 = trap_op__cia + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:331" *) 3'h4;
- assign \$47 = trap_op__traptype == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:198" *) 1'h0;
- assign \$50 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:201" *) 2'h2;
- assign \$49 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$50 ;
- assign \$54 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:203" *) 1'h1;
- assign \$53 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$54 ;
- assign \$58 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:205" *) 4'h8;
- assign \$57 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$58 ;
- assign \$62 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:207" *) 7'h40;
- assign \$61 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$62 ;
- assign \$66 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:221" *) 8'h80;
- assign \$65 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$66 ;
- assign \$69 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) trap_op__svstate;
- assign \$71 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) trap_op__svstate;
- assign \$73 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) trap_op__svstate;
- assign \$76 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:207" *) 7'h40;
- assign \$75 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$76 ;
- assign \$79 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) trap_op__msr;
- assign \$81 = trap_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:246" *) 7'h48;
- assign \$83 = trap_op__msr[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:252" *) 3'h2;
- assign \$85 = ra[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:253" *) 3'h0;
- assign \$87 = \$83 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:253" *) \$85 ;
- assign \$89 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:268" *) trap_op__msr[60];
- assign \$91 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:298" *) trap_op__insn[9];
- assign \$93 = trap_op__msr[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:311" *) 3'h2;
- assign \$95 = fast2[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:312" *) 3'h0;
- assign \$97 = \$93 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:312" *) \$95 ;
+ assign \$19 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) ra[31:0];
+ assign \$21 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) rb[31:0];
+ assign \$23 = $signed(a_s) < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171" *) $signed(b_s);
+ assign \$25 = $signed(a_s) > (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:172" *) $signed(b_s);
+ assign \$27 = a < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173" *) b;
+ assign \$29 = a > (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:174" *) b;
+ assign \$31 = a == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175" *) b;
+ assign \$34 = trap_bits & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" *) to;
+ assign \$33 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" *) \$34 ;
+ assign \$37 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" *) trap_op__traptype;
+ assign \$39 = \$33 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" *) \$37 ;
+ assign \$42 = trap_op__trapaddr <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" *) 3'h4;
+ assign \$41 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" *) \$42 ;
+ assign \$46 = trap_op__cia + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:331" *) 3'h4;
+ assign \$48 = trap_op__traptype == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:198" *) 1'h0;
+ assign \$51 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:201" *) 2'h2;
+ assign \$50 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$51 ;
+ assign \$55 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:203" *) 1'h1;
+ assign \$54 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$55 ;
+ assign \$59 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:205" *) 4'h8;
+ assign \$58 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$59 ;
+ assign \$63 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:207" *) 7'h40;
+ assign \$62 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$63 ;
+ assign \$67 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:221" *) 8'h80;
+ assign \$66 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$67 ;
+ assign \$70 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) trap_op__svstate;
+ assign \$72 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) trap_op__svstate;
+ assign \$74 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) trap_op__svstate;
+ assign \$77 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:207" *) 7'h40;
+ assign \$76 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$77 ;
+ assign \$80 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) trap_op__msr;
+ assign \$82 = trap_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:246" *) 7'h48;
+ assign \$84 = trap_op__msr[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:252" *) 3'h2;
+ assign \$86 = ra[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:253" *) 3'h0;
+ assign \$88 = \$84 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:253" *) \$86 ;
+ assign \$90 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:268" *) trap_op__msr[60];
+ assign \$92 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:298" *) trap_op__insn[9];
+ assign \$94 = trap_op__msr[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:311" *) 3'h2;
+ assign \$96 = fast2[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:312" *) 3'h0;
+ assign \$98 = \$94 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:312" *) \$96 ;
always @* begin
if (\initial ) begin end
(* full_case = 32'd1 *)
casez (should_trap)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" */
1'h1:
- nia = \$40 ;
+ nia = \$41 ;
endcase
/* \nmigen.decoding = "OP_MTMSRD/72|OP_MTMSR/74" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235" */
end
always @* begin
if (\initial ) begin end
- \fast1$16 = 64'h0000000000000000;
+ \fast1$17 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" *)
casez (trap_op__insn_type)
/* \nmigen.decoding = "OP_TRAP/63" */
casez (should_trap)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" */
1'h1:
- \fast1$16 = trap_op__cia;
+ \fast1$17 = trap_op__cia;
endcase
/* \nmigen.decoding = "OP_MTMSRD/72|OP_MTMSR/74" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235" */
/* \nmigen.decoding = "OP_SC/73" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:320" */
7'h49:
- \fast1$16 = \$44 [63:0];
+ \fast1$17 = \$45 [63:0];
endcase
end
always @* begin
end
always @* begin
if (\initial ) begin end
- \fast2$17 = 64'h0000000000000000;
+ \fast2$18 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" *)
casez (trap_op__insn_type)
/* \nmigen.decoding = "OP_TRAP/63" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" */
1'h1:
begin
- \fast2$17 = 64'h0000000000000000;
- \fast2$17 [15:0] = trap_op__msr[15:0];
- \fast2$17 [26:22] = trap_op__msr[26:22];
- \fast2$17 [63:31] = trap_op__msr[63:31];
+ \fast2$18 = 64'h0000000000000000;
+ \fast2$18 [15:0] = trap_op__msr[15:0];
+ \fast2$18 [26:22] = trap_op__msr[26:22];
+ \fast2$18 [63:31] = trap_op__msr[63:31];
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:198" *)
- casez (\$47 )
+ casez (\$48 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:198" */
1'h1:
- \fast2$17 [17] = 1'h1;
+ \fast2$18 [17] = 1'h1;
endcase
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:201" *)
- casez (\$49 )
+ casez (\$50 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:201" */
1'h1:
- \fast2$17 [18] = 1'h1;
+ \fast2$18 [18] = 1'h1;
endcase
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:203" *)
- casez (\$53 )
+ casez (\$54 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:203" */
1'h1:
- \fast2$17 [20] = 1'h1;
+ \fast2$18 [20] = 1'h1;
endcase
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:205" *)
- casez (\$57 )
+ casez (\$58 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:205" */
1'h1:
- \fast2$17 [16] = 1'h1;
+ \fast2$18 [16] = 1'h1;
endcase
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:207" *)
- casez (\$61 )
+ casez (\$62 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:207" */
1'h1:
begin
- \fast2$17 [30] = trapexc_invalid;
- \fast2$17 [28] = trapexc_perm_error;
- \fast2$17 [19] = trapexc_badtree;
- \fast2$17 [18] = trapexc_rc_error;
+ \fast2$18 [30] = trapexc_invalid;
+ \fast2$18 [28] = trapexc_perm_error;
+ \fast2$18 [19] = trapexc_badtree;
+ \fast2$18 [18] = trapexc_rc_error;
end
endcase
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:221" *)
- casez (\$65 )
+ casez (\$66 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:221" */
1'h1:
- \fast2$17 [19] = 1'h1;
+ \fast2$18 [19] = 1'h1;
endcase
end
endcase
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:320" */
7'h49:
begin
- \fast2$17 = 64'h0000000000000000;
- \fast2$17 [15:0] = trap_op__msr[15:0];
- \fast2$17 [26:22] = trap_op__msr[26:22];
- \fast2$17 [63:31] = trap_op__msr[63:31];
+ \fast2$18 = 64'h0000000000000000;
+ \fast2$18 [15:0] = trap_op__msr[15:0];
+ \fast2$18 [26:22] = trap_op__msr[26:22];
+ \fast2$18 [63:31] = trap_op__msr[63:31];
end
endcase
end
casez (should_trap)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" */
1'h1:
- fast3 = \$71 ;
+ fast3 = \$72 ;
endcase
/* \nmigen.decoding = "OP_MTMSRD/72|OP_MTMSR/74" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235" */
/* \nmigen.decoding = "OP_SC/73" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:320" */
7'h49:
- fast3 = \$73 ;
+ fast3 = \$74 ;
endcase
end
always @* begin
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" */
1'h1:
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:207" *)
- casez (\$75 )
+ casez (\$76 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:207" */
1'h1:
{ trapexc_happened, trapexc_segment_fault, trapexc_rc_error, trapexc_perm_error, trapexc_badtree, trapexc_invalid, trapexc_instr_fault, trapexc_alignment } = trap_op__ldst_exc;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235" */
7'h48, 7'h4a:
begin
- { msr_ok, msr } = \$79 ;
+ { msr_ok, msr } = \$80 ;
(* full_case = 32'd1 *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:239" *)
casez (trap_op__insn[21])
begin
(* full_case = 32'd1 *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:246" *)
- casez (\$81 )
+ casez (\$82 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:246" */
1'h1:
begin
msr[59:13] = ra[59:13];
msr[63:61] = ra[63:61];
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:253" *)
- casez (\$87 )
+ casez (\$88 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:253" */
1'h1:
msr[34:32] = trap_op__msr[34:32];
end
endcase
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:268" *)
- casez (\$89 )
+ casez (\$90 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:268" */
1'h1:
begin
msr[26:22] = fast2[26:22];
msr[63:31] = fast2[63:31];
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:298" *)
- casez (\$91 )
+ casez (\$92 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:298" */
1'h1:
(* full_case = 32'd1 *)
end
endcase
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:312" *)
- casez (\$97 )
+ casez (\$98 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:312" */
1'h1:
msr[34:32] = trap_op__msr[34:32];
casez (trap_op__is_32bit)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:153" */
1'h1:
- a = \$18 ;
+ a = \$19 ;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158" */
default:
a = ra;
casez (trap_op__is_32bit)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:153" */
1'h1:
- b = \$20 ;
+ b = \$21 ;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158" */
default:
b = rb;
endcase
end
- assign \$44 = \$45 ;
- assign { \trap_op__SV_Ptype$15 , \trap_op__sv_saturate$14 , \trap_op__sv_pred_dz$13 , \trap_op__sv_pred_sz$12 , \trap_op__ldst_exc$11 , \trap_op__trapaddr$10 , \trap_op__traptype$9 , \trap_op__is_32bit$8 , \trap_op__svstate$7 , \trap_op__cia$6 , \trap_op__msr$5 , \trap_op__insn$4 , \trap_op__fn_unit$3 , \trap_op__insn_type$2 } = { trap_op__SV_Ptype, trap_op__sv_saturate, trap_op__sv_pred_dz, trap_op__sv_pred_sz, trap_op__ldst_exc, trap_op__trapaddr, trap_op__traptype, trap_op__is_32bit, trap_op__svstate, trap_op__cia, trap_op__msr, trap_op__insn, trap_op__fn_unit, trap_op__insn_type };
+ assign \$45 = \$46 ;
+ assign { \trap_op__SV_Ptype$16 , \trap_op__sv_ldstmode$15 , \trap_op__sv_saturate$14 , \trap_op__sv_pred_dz$13 , \trap_op__sv_pred_sz$12 , \trap_op__ldst_exc$11 , \trap_op__trapaddr$10 , \trap_op__traptype$9 , \trap_op__is_32bit$8 , \trap_op__svstate$7 , \trap_op__cia$6 , \trap_op__msr$5 , \trap_op__insn$4 , \trap_op__fn_unit$3 , \trap_op__insn_type$2 } = { trap_op__SV_Ptype, trap_op__sv_ldstmode, trap_op__sv_saturate, trap_op__sv_pred_dz, trap_op__sv_pred_sz, trap_op__ldst_exc, trap_op__trapaddr, trap_op__traptype, trap_op__is_32bit, trap_op__svstate, trap_op__cia, trap_op__msr, trap_op__insn, trap_op__fn_unit, trap_op__insn_type };
assign \muxid$1 = muxid;
- assign should_trap = \$38 ;
+ assign should_trap = \$39 ;
assign trap_bits = { lt_s, gt_s, equal, lt_u, gt_u };
- assign equal = \$30 ;
- assign gt_u = \$28 ;
- assign lt_u = \$26 ;
- assign gt_s = \$24 ;
- assign lt_s = \$22 ;
+ assign equal = \$31 ;
+ assign gt_u = \$29 ;
+ assign lt_u = \$27 ;
+ assign gt_s = \$25 ;
+ assign lt_s = \$23 ;
assign to = trap_op__insn[25:21];
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main" *)
(* generator = "nMigen" *)
-module \main$51 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, ra, rb, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__SV_Ptype$23 , o, o_ok, \xer_so$24 , muxid);
+module \main$51 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__sv_ldstmode, logical_op__SV_Ptype, ra, rb, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__sv_ldstmode$23 , \logical_op__SV_Ptype$24 , o, o_ok, \xer_so$25 , muxid);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$101 ;
+ wire \$100 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$103 ;
+ wire \$102 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$105 ;
+ wire \$104 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$107 ;
+ wire \$106 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$109 ;
+ wire \$108 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$111 ;
+ wire \$110 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$113 ;
+ wire \$112 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$115 ;
+ wire \$114 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$117 ;
+ wire \$116 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$119 ;
+ wire \$118 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$121 ;
+ wire \$120 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$123 ;
+ wire \$122 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$125 ;
+ wire \$124 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$127 ;
+ wire \$126 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$129 ;
+ wire \$128 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$131 ;
+ wire \$130 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$133 ;
+ wire \$132 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$135 ;
+ wire \$134 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$137 ;
+ wire \$136 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$139 ;
+ wire \$138 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$141 ;
+ wire \$140 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$143 ;
+ wire \$142 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$145 ;
+ wire \$144 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$147 ;
+ wire \$146 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$149 ;
+ wire \$148 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$151 ;
+ wire \$150 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$153 ;
+ wire \$152 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$155 ;
+ wire \$154 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$157 ;
+ wire \$156 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
+ wire \$158 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" *)
- wire \$159 ;
+ wire \$160 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" *)
- wire [63:0] \$161 ;
+ wire [63:0] \$162 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" *)
- wire \$162 ;
+ wire \$163 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *)
- wire [63:0] \$165 ;
+ wire [63:0] \$166 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *)
- wire [7:0] \$166 ;
+ wire [7:0] \$167 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" *)
- wire [7:0] \$168 ;
+ wire [7:0] \$169 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *)
- wire [7:0] \$170 ;
+ wire [7:0] \$171 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \$173 ;
+ wire [63:0] \$174 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" *)
- wire \$175 ;
+ wire \$176 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" *)
- wire \$177 ;
+ wire \$178 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" *)
- wire [63:0] \$179 ;
+ wire [63:0] \$180 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" *)
- wire [31:0] \$180 ;
+ wire [31:0] \$181 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" *)
- wire [63:0] \$183 ;
+ wire [63:0] \$184 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" *)
- wire [63:0] \$25 ;
+ wire [63:0] \$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" *)
- wire [63:0] \$27 ;
+ wire [63:0] \$28 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" *)
- wire [63:0] \$29 ;
+ wire [63:0] \$30 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$31 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$33 ;
+ wire \$32 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$35 ;
+ wire \$34 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$37 ;
+ wire \$36 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$39 ;
+ wire \$38 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$41 ;
+ wire \$40 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$43 ;
+ wire \$42 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$45 ;
+ wire \$44 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$47 ;
+ wire \$46 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$49 ;
+ wire \$48 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$51 ;
+ wire \$50 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$53 ;
+ wire \$52 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$55 ;
+ wire \$54 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$57 ;
+ wire \$56 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$59 ;
+ wire \$58 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$61 ;
+ wire \$60 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$63 ;
+ wire \$62 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$65 ;
+ wire \$64 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$67 ;
+ wire \$66 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$69 ;
+ wire \$68 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$71 ;
+ wire \$70 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$73 ;
+ wire \$72 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$75 ;
+ wire \$74 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$77 ;
+ wire \$76 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$79 ;
+ wire \$78 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$81 ;
+ wire \$80 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$83 ;
+ wire \$82 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$85 ;
+ wire \$84 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$87 ;
+ wire \$86 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$89 ;
+ wire \$88 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$91 ;
+ wire \$90 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$93 ;
+ wire \$92 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$95 ;
+ wire \$94 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$97 ;
+ wire \$96 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
- wire \$99 ;
+ wire \$98 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:103" *)
reg [31:0] a32;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:28" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \logical_op__SV_Ptype$23 ;
+ output [1:0] \logical_op__SV_Ptype$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [3:0] logical_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__rc__rc$6 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] logical_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \logical_op__sv_ldstmode$23 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \xer_so$24 ;
- assign \$99 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32];
- assign \$101 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32];
- assign \$103 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32];
- assign \$105 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32];
- assign \$107 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32];
- assign \$109 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32];
- assign \$111 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40];
- assign \$113 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40];
- assign \$115 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40];
- assign \$117 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40];
- assign \$119 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40];
- assign \$121 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40];
- assign \$123 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40];
- assign \$125 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40];
- assign \$127 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48];
- assign \$129 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48];
- assign \$131 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48];
- assign \$133 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48];
- assign \$135 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48];
- assign \$137 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48];
- assign \$139 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48];
- assign \$141 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48];
- assign \$143 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56];
- assign \$145 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56];
- assign \$147 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56];
- assign \$149 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56];
- assign \$151 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56];
- assign \$153 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56];
- assign \$155 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56];
- assign \$157 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56];
- assign \$159 = logical_op__data_len[3] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" *) 1'h1;
- assign \$162 = par0 ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" *) par1;
- assign \$161 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" *) \$162 ;
- assign \$166 = clz_lz - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *) 6'h20;
- assign \$168 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" *) clz_lz;
- assign \$170 = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *) \$166 : \$168 ;
- assign \$165 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *) \$170 ;
- assign \$173 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) logical_op__data_len;
- assign \$175 = ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" *) { ra[24], ra[16], ra[8], ra[0] };
- assign \$177 = ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" *) { ra[56], ra[48], ra[40], ra[32] };
- assign \$180 = count_right ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" *) { a32[0], a32[1], a32[2], a32[3], a32[4], a32[5], a32[6], a32[7], a32[8], a32[9], a32[10], a32[11], a32[12], a32[13], a32[14], a32[15], a32[16], a32[17], a32[18], a32[19], a32[20], a32[21], a32[22], a32[23], a32[24], a32[25], a32[26], a32[27], a32[28], a32[29], a32[30], a32[31] } : a32;
- assign \$179 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" *) \$180 ;
- assign \$183 = count_right ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" *) { ra[0], ra[1], ra[2], ra[3], ra[4], ra[5], ra[6], ra[7], ra[8], ra[9], ra[10], ra[11], ra[12], ra[13], ra[14], ra[15], ra[16], ra[17], ra[18], ra[19], ra[20], ra[21], ra[22], ra[23], ra[24], ra[25], ra[26], ra[27], ra[28], ra[29], ra[30], ra[31], ra[32], ra[33], ra[34], ra[35], ra[36], ra[37], ra[38], ra[39], ra[40], ra[41], ra[42], ra[43], ra[44], ra[45], ra[46], ra[47], ra[48], ra[49], ra[50], ra[51], ra[52], ra[53], ra[54], ra[55], ra[56], ra[57], ra[58], ra[59], ra[60], ra[61], ra[62], ra[63] } : ra;
- assign \$25 = ra & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" *) rb;
- assign \$27 = ra | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" *) rb;
- assign \$29 = ra ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" *) rb;
- assign \$31 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0];
- assign \$33 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0];
- assign \$35 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0];
- assign \$37 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0];
- assign \$39 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0];
- assign \$41 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0];
- assign \$43 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0];
- assign \$45 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0];
- assign \$47 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8];
- assign \$49 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8];
- assign \$51 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8];
- assign \$53 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8];
- assign \$55 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8];
- assign \$57 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8];
- assign \$59 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8];
- assign \$61 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8];
- assign \$63 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16];
- assign \$65 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16];
- assign \$67 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16];
- assign \$69 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16];
- assign \$71 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16];
- assign \$73 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16];
- assign \$75 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16];
- assign \$77 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16];
- assign \$79 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24];
- assign \$81 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24];
- assign \$83 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24];
- assign \$85 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24];
- assign \$87 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24];
- assign \$89 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24];
- assign \$91 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24];
- assign \$93 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24];
- assign \$95 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32];
- assign \$97 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32];
+ output \xer_so$25 ;
+ assign \$100 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32];
+ assign \$102 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32];
+ assign \$104 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32];
+ assign \$106 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32];
+ assign \$108 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32];
+ assign \$110 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32];
+ assign \$112 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40];
+ assign \$114 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40];
+ assign \$116 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40];
+ assign \$118 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40];
+ assign \$120 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40];
+ assign \$122 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40];
+ assign \$124 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40];
+ assign \$126 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40];
+ assign \$128 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48];
+ assign \$130 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48];
+ assign \$132 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48];
+ assign \$134 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48];
+ assign \$136 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48];
+ assign \$138 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48];
+ assign \$140 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48];
+ assign \$142 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48];
+ assign \$144 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56];
+ assign \$146 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56];
+ assign \$148 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56];
+ assign \$150 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56];
+ assign \$152 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56];
+ assign \$154 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56];
+ assign \$156 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56];
+ assign \$158 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56];
+ assign \$160 = logical_op__data_len[3] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" *) 1'h1;
+ assign \$163 = par0 ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" *) par1;
+ assign \$162 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" *) \$163 ;
+ assign \$167 = clz_lz - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *) 6'h20;
+ assign \$169 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" *) clz_lz;
+ assign \$171 = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *) \$167 : \$169 ;
+ assign \$166 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *) \$171 ;
+ assign \$174 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) logical_op__data_len;
+ assign \$176 = ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" *) { ra[24], ra[16], ra[8], ra[0] };
+ assign \$178 = ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" *) { ra[56], ra[48], ra[40], ra[32] };
+ assign \$181 = count_right ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" *) { a32[0], a32[1], a32[2], a32[3], a32[4], a32[5], a32[6], a32[7], a32[8], a32[9], a32[10], a32[11], a32[12], a32[13], a32[14], a32[15], a32[16], a32[17], a32[18], a32[19], a32[20], a32[21], a32[22], a32[23], a32[24], a32[25], a32[26], a32[27], a32[28], a32[29], a32[30], a32[31] } : a32;
+ assign \$180 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" *) \$181 ;
+ assign \$184 = count_right ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" *) { ra[0], ra[1], ra[2], ra[3], ra[4], ra[5], ra[6], ra[7], ra[8], ra[9], ra[10], ra[11], ra[12], ra[13], ra[14], ra[15], ra[16], ra[17], ra[18], ra[19], ra[20], ra[21], ra[22], ra[23], ra[24], ra[25], ra[26], ra[27], ra[28], ra[29], ra[30], ra[31], ra[32], ra[33], ra[34], ra[35], ra[36], ra[37], ra[38], ra[39], ra[40], ra[41], ra[42], ra[43], ra[44], ra[45], ra[46], ra[47], ra[48], ra[49], ra[50], ra[51], ra[52], ra[53], ra[54], ra[55], ra[56], ra[57], ra[58], ra[59], ra[60], ra[61], ra[62], ra[63] } : ra;
+ assign \$26 = ra & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" *) rb;
+ assign \$28 = ra | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" *) rb;
+ assign \$30 = ra ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" *) rb;
+ assign \$32 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0];
+ assign \$34 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0];
+ assign \$36 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0];
+ assign \$38 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0];
+ assign \$40 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0];
+ assign \$42 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0];
+ assign \$44 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0];
+ assign \$46 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0];
+ assign \$48 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8];
+ assign \$50 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8];
+ assign \$52 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8];
+ assign \$54 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8];
+ assign \$56 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8];
+ assign \$58 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8];
+ assign \$60 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8];
+ assign \$62 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8];
+ assign \$64 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16];
+ assign \$66 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16];
+ assign \$68 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16];
+ assign \$70 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16];
+ assign \$72 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16];
+ assign \$74 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16];
+ assign \$76 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16];
+ assign \$78 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16];
+ assign \$80 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24];
+ assign \$82 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24];
+ assign \$84 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24];
+ assign \$86 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24];
+ assign \$88 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24];
+ assign \$90 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24];
+ assign \$92 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24];
+ assign \$94 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24];
+ assign \$96 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32];
+ assign \$98 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32];
bpermd bpermd (
.ra(bpermd_ra),
.rb(bpermd_rb),
/* \nmigen.decoding = "OP_AND/4" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" */
7'h04:
- o = \$25 ;
+ o = \$26 ;
/* \nmigen.decoding = "OP_OR/53" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" */
7'h35:
- o = \$27 ;
+ o = \$28 ;
/* \nmigen.decoding = "OP_XOR/67" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" */
7'h43:
- o = \$29 ;
+ o = \$30 ;
/* \nmigen.decoding = "OP_CMPB/11" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" */
7'h0b:
- o = { \$143 , \$145 , \$147 , \$149 , \$151 , \$153 , \$155 , \$157 , \$127 , \$129 , \$131 , \$133 , \$135 , \$137 , \$139 , \$141 , \$111 , \$113 , \$115 , \$117 , \$119 , \$121 , \$123 , \$125 , \$95 , \$97 , \$99 , \$101 , \$103 , \$105 , \$107 , \$109 , \$79 , \$81 , \$83 , \$85 , \$87 , \$89 , \$91 , \$93 , \$63 , \$65 , \$67 , \$69 , \$71 , \$73 , \$75 , \$77 , \$47 , \$49 , \$51 , \$53 , \$55 , \$57 , \$59 , \$61 , \$31 , \$33 , \$35 , \$37 , \$39 , \$41 , \$43 , \$45 };
+ o = { \$144 , \$146 , \$148 , \$150 , \$152 , \$154 , \$156 , \$158 , \$128 , \$130 , \$132 , \$134 , \$136 , \$138 , \$140 , \$142 , \$112 , \$114 , \$116 , \$118 , \$120 , \$122 , \$124 , \$126 , \$96 , \$98 , \$100 , \$102 , \$104 , \$106 , \$108 , \$110 , \$80 , \$82 , \$84 , \$86 , \$88 , \$90 , \$92 , \$94 , \$64 , \$66 , \$68 , \$70 , \$72 , \$74 , \$76 , \$78 , \$48 , \$50 , \$52 , \$54 , \$56 , \$58 , \$60 , \$62 , \$32 , \$34 , \$36 , \$38 , \$40 , \$42 , \$44 , \$46 };
/* \nmigen.decoding = "OP_POPCNT/54" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" */
7'h36:
7'h37:
(* full_case = 32'd1 *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" *)
- casez (\$159 )
+ casez (\$160 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" */
1'h1:
- o = \$161 ;
+ o = \$162 ;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:90" */
default:
begin
/* \nmigen.decoding = "OP_CNTZ/14" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" */
7'h0e:
- o = \$165 ;
+ o = \$166 ;
/* \nmigen.decoding = "OP_BPERM/9" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" */
7'h09:
/* \nmigen.decoding = "OP_POPCNT/54" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" */
7'h36:
- popcount_data_len = \$173 ;
+ popcount_data_len = \$174 ;
endcase
end
always @* begin
/* \nmigen.decoding = "OP_PRTY/55" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" */
7'h37:
- par0 = \$175 ;
+ par0 = \$176 ;
endcase
end
always @* begin
/* \nmigen.decoding = "OP_PRTY/55" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" */
7'h37:
- par1 = \$177 ;
+ par1 = \$178 ;
endcase
end
always @* begin
casez (logical_op__is_32bit)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106" */
1'h1:
- cntz_i = \$179 ;
+ cntz_i = \$180 ;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:108" */
default:
- cntz_i = \$183 ;
+ cntz_i = \$184 ;
endcase
endcase
end
- assign { \logical_op__SV_Ptype$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__SV_Ptype, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
+ assign { \logical_op__SV_Ptype$24 , \logical_op__sv_ldstmode$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__SV_Ptype, logical_op__sv_ldstmode, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
assign \muxid$1 = muxid;
- assign \xer_so$24 = xer_so;
+ assign \xer_so$25 = xer_so;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.main" *)
(* generator = "nMigen" *)
-module \main$9 (cr_op__insn_type, cr_op__fn_unit, cr_op__insn, cr_op__sv_pred_sz, cr_op__sv_pred_dz, cr_op__sv_saturate, cr_op__SV_Ptype, ra, rb, full_cr, cr_a, cr_b, cr_c, \muxid$1 , \cr_op__insn_type$2 , \cr_op__fn_unit$3 , \cr_op__insn$4 , \cr_op__sv_pred_sz$5 , \cr_op__sv_pred_dz$6 , \cr_op__sv_saturate$7 , \cr_op__SV_Ptype$8 , o, o_ok, \full_cr$9 , full_cr_ok, \cr_a$10 , cr_a_ok, muxid);
+module \main$9 (cr_op__insn_type, cr_op__fn_unit, cr_op__insn, cr_op__sv_pred_sz, cr_op__sv_pred_dz, cr_op__sv_saturate, cr_op__sv_ldstmode, cr_op__SV_Ptype, ra, rb, full_cr, cr_a, cr_b, cr_c, \muxid$1 , \cr_op__insn_type$2 , \cr_op__fn_unit$3 , \cr_op__insn$4 , \cr_op__sv_pred_sz$5 , \cr_op__sv_pred_dz$6 , \cr_op__sv_saturate$7 , \cr_op__sv_ldstmode$8 , \cr_op__SV_Ptype$9 , o, o_ok, \full_cr$10 , full_cr_ok, \cr_a$11 , cr_a_ok, muxid);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [4:0] \$11 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" *)
- wire [2:0] \$13 ;
+ wire [4:0] \$12 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" *)
wire [2:0] \$14 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" *)
- wire [2:0] \$16 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" *)
+ wire [2:0] \$15 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" *)
wire [2:0] \$17 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" *)
- wire [2:0] \$19 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" *)
+ wire [2:0] \$18 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" *)
wire [2:0] \$20 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" *)
+ wire [2:0] \$21 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" *)
- wire \$22 ;
+ wire \$23 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" *)
- wire \$24 ;
+ wire \$25 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" *)
- wire \$26 ;
+ wire \$27 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \$28 ;
+ wire [63:0] \$29 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" *)
- wire [64:0] \$30 ;
+ wire [64:0] \$31 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" *)
- wire [63:0] \$31 ;
+ wire [63:0] \$32 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:131" *)
reg [1:0] BC;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:82" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [3:0] cr_a;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [3:0] \cr_a$10 ;
- reg [3:0] \cr_a$10 ;
+ output [3:0] \cr_a$11 ;
+ reg [3:0] \cr_a$11 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output cr_a_ok;
reg cr_a_ok;
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \cr_op__SV_Ptype$8 ;
+ output [1:0] \cr_op__SV_Ptype$9 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output [6:0] \cr_op__insn_type$2 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] cr_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \cr_op__sv_ldstmode$8 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input cr_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [31:0] full_cr;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [31:0] \full_cr$9 ;
- reg [31:0] \full_cr$9 ;
+ output [31:0] \full_cr$10 ;
+ reg [31:0] \full_cr$10 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output full_cr_ok;
reg full_cr_ok;
input [63:0] ra;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] rb;
- assign \$11 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) cr_a;
- assign \$14 = 2'h3 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" *) cr_op__insn[22:21];
- assign \$17 = 2'h3 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" *) cr_op__insn[17:16];
- assign \$20 = 2'h3 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" *) cr_op__insn[12:11];
- assign \$22 = bit_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" *) lut[3] : lut[1];
- assign \$24 = bit_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" *) lut[2] : lut[0];
- assign \$26 = bit_b ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" *) \$22 : \$24 ;
- assign \$28 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) full_cr;
- assign \$31 = cr_bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" *) ra : rb;
- assign \$30 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" *) \$31 ;
- always @* begin
- if (\initial ) begin end
- \cr_a$10 = 4'h0;
+ assign \$12 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) cr_a;
+ assign \$15 = 2'h3 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" *) cr_op__insn[22:21];
+ assign \$18 = 2'h3 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" *) cr_op__insn[17:16];
+ assign \$21 = 2'h3 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" *) cr_op__insn[12:11];
+ assign \$23 = bit_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" *) lut[3] : lut[1];
+ assign \$25 = bit_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" *) lut[2] : lut[0];
+ assign \$27 = bit_b ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" *) \$23 : \$25 ;
+ assign \$29 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) full_cr;
+ assign \$32 = cr_bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" *) ra : rb;
+ assign \$31 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" *) \$32 ;
+ always @* begin
+ if (\initial ) begin end
+ \cr_a$11 = 4'h0;
cr_a_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *)
casez (cr_op__insn_type)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" */
7'h2a:
begin
- { cr_a_ok, \cr_a$10 } = \$11 ;
+ { cr_a_ok, \cr_a$11 } = \$12 ;
cr_a_ok = 1'h1;
end
/* \nmigen.decoding = "OP_CROP/69" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" */
7'h45:
begin
- \cr_a$10 = cr_c;
+ \cr_a$11 = cr_c;
(* full_case = 32'd1 *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:105" *)
casez (bt)
2'h0:
- \cr_a$10 [0] = bit_o;
+ \cr_a$11 [0] = bit_o;
2'h1:
- \cr_a$10 [1] = bit_o;
+ \cr_a$11 [1] = bit_o;
2'h2:
- \cr_a$10 [2] = bit_o;
+ \cr_a$11 [2] = bit_o;
2'h?:
- \cr_a$10 [3] = bit_o;
+ \cr_a$11 [3] = bit_o;
endcase
begin
cr_a_ok = 1'h1;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" */
7'h2d:
begin
- o = \$28 ;
+ o = \$29 ;
o_ok = 1'h1;
end
/* \nmigen.decoding = "OP_ISEL/35" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" */
7'h23:
begin
- { o_ok, o } = \$30 ;
+ { o_ok, o } = \$31 ;
o_ok = 1'h1;
end
/* \nmigen.decoding = "OP_SETB/59" */
/* \nmigen.decoding = "OP_CROP/69" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" */
7'h45:
- bt = \$13 [1:0];
+ bt = \$14 [1:0];
endcase
end
always @* begin
/* \nmigen.decoding = "OP_CROP/69" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" */
7'h45:
- ba = \$16 [1:0];
+ ba = \$17 [1:0];
endcase
end
always @* begin
/* \nmigen.decoding = "OP_CROP/69" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" */
7'h45:
- bb = \$19 [1:0];
+ bb = \$20 [1:0];
endcase
end
always @* begin
/* \nmigen.decoding = "OP_CROP/69" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" */
7'h45:
- bit_o = \$26 ;
+ bit_o = \$27 ;
endcase
end
always @* begin
if (\initial ) begin end
- \full_cr$9 = 32'd0;
+ \full_cr$10 = 32'd0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *)
casez (cr_op__insn_type)
/* \nmigen.decoding = "OP_MCRF/42" */
/* \nmigen.decoding = "OP_MTCRF/48" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" */
7'h30:
- \full_cr$9 = ra[31:0];
+ \full_cr$10 = ra[31:0];
endcase
end
- assign \$13 = \$14 ;
- assign \$16 = \$17 ;
- assign \$19 = \$20 ;
- assign { \cr_op__SV_Ptype$8 , \cr_op__sv_saturate$7 , \cr_op__sv_pred_dz$6 , \cr_op__sv_pred_sz$5 , \cr_op__insn$4 , \cr_op__fn_unit$3 , \cr_op__insn_type$2 } = { cr_op__SV_Ptype, cr_op__sv_saturate, cr_op__sv_pred_dz, cr_op__sv_pred_sz, cr_op__insn, cr_op__fn_unit, cr_op__insn_type };
+ assign \$14 = \$15 ;
+ assign \$17 = \$18 ;
+ assign \$20 = \$21 ;
+ assign { \cr_op__SV_Ptype$9 , \cr_op__sv_ldstmode$8 , \cr_op__sv_saturate$7 , \cr_op__sv_pred_dz$6 , \cr_op__sv_pred_sz$5 , \cr_op__insn$4 , \cr_op__fn_unit$3 , \cr_op__insn_type$2 } = { cr_op__SV_Ptype, cr_op__sv_ldstmode, cr_op__sv_saturate, cr_op__sv_pred_dz, cr_op__sv_pred_sz, cr_op__insn, cr_op__fn_unit, cr_op__insn_type };
assign \muxid$1 = muxid;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0" *)
(* generator = "nMigen" *)
-module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__insn, oper_i_alu_mul0__sv_pred_sz, oper_i_alu_mul0__sv_pred_dz, oper_i_alu_mul0__sv_saturate, oper_i_alu_mul0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, xer_ov_ok, dest3_o, xer_so_ok, dest4_o, coresync_clk);
+module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__insn, oper_i_alu_mul0__sv_pred_sz, oper_i_alu_mul0__sv_pred_dz, oper_i_alu_mul0__sv_saturate, oper_i_alu_mul0__sv_ldstmode, oper_i_alu_mul0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, xer_ov_ok, dest3_o, xer_so_ok, dest4_o, coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
wire \$10 ;
reg alu_mul0_mul_op__rc__rc = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_mul0_mul_op__rc__rc$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] alu_mul0_mul_op__sv_ldstmode = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \alu_mul0_mul_op__sv_ldstmode$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg alu_mul0_mul_op__sv_pred_dz = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output cr_a_ok;
input oper_i_alu_mul0__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_mul0__rc__rc;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] oper_i_alu_mul0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_mul0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
alu_mul0_mul_op__sv_pred_dz <= \alu_mul0_mul_op__sv_pred_dz$next ;
always @(posedge coresync_clk)
alu_mul0_mul_op__sv_saturate <= \alu_mul0_mul_op__sv_saturate$next ;
+ always @(posedge coresync_clk)
+ alu_mul0_mul_op__sv_ldstmode <= \alu_mul0_mul_op__sv_ldstmode$next ;
always @(posedge coresync_clk)
alu_mul0_mul_op__SV_Ptype <= \alu_mul0_mul_op__SV_Ptype$next ;
always @(posedge coresync_clk)
.mul_op__oe__ok(alu_mul0_mul_op__oe__ok),
.mul_op__rc__ok(alu_mul0_mul_op__rc__ok),
.mul_op__rc__rc(alu_mul0_mul_op__rc__rc),
+ .mul_op__sv_ldstmode(alu_mul0_mul_op__sv_ldstmode),
.mul_op__sv_pred_dz(alu_mul0_mul_op__sv_pred_dz),
.mul_op__sv_pred_sz(alu_mul0_mul_op__sv_pred_sz),
.mul_op__sv_saturate(alu_mul0_mul_op__sv_saturate),
\alu_mul0_mul_op__sv_pred_sz$next = alu_mul0_mul_op__sv_pred_sz;
\alu_mul0_mul_op__sv_pred_dz$next = alu_mul0_mul_op__sv_pred_dz;
\alu_mul0_mul_op__sv_saturate$next = alu_mul0_mul_op__sv_saturate;
+ \alu_mul0_mul_op__sv_ldstmode$next = alu_mul0_mul_op__sv_ldstmode;
\alu_mul0_mul_op__SV_Ptype$next = alu_mul0_mul_op__SV_Ptype;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *)
casez (cu_issue_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */
1'h1:
- { \alu_mul0_mul_op__SV_Ptype$next , \alu_mul0_mul_op__sv_saturate$next , \alu_mul0_mul_op__sv_pred_dz$next , \alu_mul0_mul_op__sv_pred_sz$next , \alu_mul0_mul_op__insn$next , \alu_mul0_mul_op__is_signed$next , \alu_mul0_mul_op__is_32bit$next , \alu_mul0_mul_op__write_cr0$next , \alu_mul0_mul_op__oe__ok$next , \alu_mul0_mul_op__oe__oe$next , \alu_mul0_mul_op__rc__ok$next , \alu_mul0_mul_op__rc__rc$next , \alu_mul0_mul_op__imm_data__ok$next , \alu_mul0_mul_op__imm_data__data$next , \alu_mul0_mul_op__fn_unit$next , \alu_mul0_mul_op__insn_type$next } = { oper_i_alu_mul0__SV_Ptype, oper_i_alu_mul0__sv_saturate, oper_i_alu_mul0__sv_pred_dz, oper_i_alu_mul0__sv_pred_sz, oper_i_alu_mul0__insn, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__insn_type };
+ { \alu_mul0_mul_op__SV_Ptype$next , \alu_mul0_mul_op__sv_ldstmode$next , \alu_mul0_mul_op__sv_saturate$next , \alu_mul0_mul_op__sv_pred_dz$next , \alu_mul0_mul_op__sv_pred_sz$next , \alu_mul0_mul_op__insn$next , \alu_mul0_mul_op__is_signed$next , \alu_mul0_mul_op__is_32bit$next , \alu_mul0_mul_op__write_cr0$next , \alu_mul0_mul_op__oe__ok$next , \alu_mul0_mul_op__oe__oe$next , \alu_mul0_mul_op__rc__ok$next , \alu_mul0_mul_op__rc__rc$next , \alu_mul0_mul_op__imm_data__ok$next , \alu_mul0_mul_op__imm_data__data$next , \alu_mul0_mul_op__fn_unit$next , \alu_mul0_mul_op__insn_type$next } = { oper_i_alu_mul0__SV_Ptype, oper_i_alu_mul0__sv_ldstmode, oper_i_alu_mul0__sv_saturate, oper_i_alu_mul0__sv_pred_dz, oper_i_alu_mul0__sv_pred_sz, oper_i_alu_mul0__insn, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__insn_type };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.mul1" *)
(* generator = "nMigen" *)
-module mul1(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__SV_Ptype, ra, rb, xer_so, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \mul_op__sv_pred_sz$14 , \mul_op__sv_pred_dz$15 , \mul_op__sv_saturate$16 , \mul_op__SV_Ptype$17 , \ra$18 , \rb$19 , \xer_so$20 , neg_res, neg_res32, muxid);
+module mul1(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__sv_ldstmode, mul_op__SV_Ptype, ra, rb, xer_so, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \mul_op__sv_pred_sz$14 , \mul_op__sv_pred_dz$15 , \mul_op__sv_saturate$16 , \mul_op__sv_ldstmode$17 , \mul_op__SV_Ptype$18 , \ra$19 , \rb$20 , \xer_so$21 , neg_res, neg_res32, muxid);
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" *)
- wire \$21 ;
+ wire \$22 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" *)
- wire \$23 ;
+ wire \$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" *)
- wire \$25 ;
+ wire \$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" *)
- wire \$27 ;
+ wire \$28 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" *)
- wire \$29 ;
+ wire \$30 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" *)
- wire \$31 ;
+ wire \$32 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" *)
- wire \$33 ;
+ wire \$34 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" *)
- wire \$35 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *)
- wire [64:0] \$37 ;
+ wire \$36 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *)
wire [64:0] \$38 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *)
+ wire [64:0] \$39 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [64:0] \$40 ;
+ wire [64:0] \$41 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *)
- wire [64:0] \$42 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *)
- wire [64:0] \$44 ;
+ wire [64:0] \$43 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *)
wire [64:0] \$45 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *)
+ wire [64:0] \$46 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [64:0] \$47 ;
+ wire [64:0] \$48 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *)
- wire [64:0] \$49 ;
+ wire [64:0] \$50 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *)
- wire [31:0] \$51 ;
+ wire [31:0] \$52 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *)
- wire [31:0] \$53 ;
+ wire [31:0] \$54 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:50" *)
wire [63:0] abs_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:51" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \mul_op__SV_Ptype$17 ;
+ output [1:0] \mul_op__SV_Ptype$18 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
input mul_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \mul_op__rc__rc$6 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] mul_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \mul_op__sv_ldstmode$17 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] ra;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output [63:0] \ra$18 ;
+ output [63:0] \ra$19 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] rb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output [63:0] \rb$19 ;
+ output [63:0] \rb$20 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:33" *)
wire sign32_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:34" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input xer_so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output \xer_so$20 ;
- assign \$21 = mul_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" *) ra[31] : ra[63];
- assign \$23 = \$21 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" *) mul_op__is_signed;
- assign \$25 = mul_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" *) rb[31] : rb[63];
- assign \$27 = \$25 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" *) mul_op__is_signed;
- assign \$29 = ra[31] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" *) mul_op__is_signed;
- assign \$31 = rb[31] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" *) mul_op__is_signed;
- assign \$33 = sign_a ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" *) sign_b;
- assign \$35 = sign32_a ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" *) sign32_b;
- assign \$38 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *) ra;
- assign \$40 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) ra;
- assign \$42 = sign_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *) \$38 : \$40 ;
- assign \$45 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *) rb;
- assign \$47 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) rb;
- assign \$49 = sign_b ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *) \$45 : \$47 ;
- assign \$51 = is_32bit ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) 32'd0 : abs_a[63:32];
- assign \$53 = is_32bit ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) 32'd0 : abs_b[63:32];
- assign \$37 = \$42 ;
- assign \$44 = \$49 ;
- assign { \mul_op__SV_Ptype$17 , \mul_op__sv_saturate$16 , \mul_op__sv_pred_dz$15 , \mul_op__sv_pred_sz$14 , \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 } = { mul_op__SV_Ptype, mul_op__sv_saturate, mul_op__sv_pred_dz, mul_op__sv_pred_sz, mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type };
+ output \xer_so$21 ;
+ assign \$22 = mul_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" *) ra[31] : ra[63];
+ assign \$24 = \$22 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" *) mul_op__is_signed;
+ assign \$26 = mul_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" *) rb[31] : rb[63];
+ assign \$28 = \$26 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" *) mul_op__is_signed;
+ assign \$30 = ra[31] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" *) mul_op__is_signed;
+ assign \$32 = rb[31] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" *) mul_op__is_signed;
+ assign \$34 = sign_a ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" *) sign_b;
+ assign \$36 = sign32_a ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" *) sign32_b;
+ assign \$39 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *) ra;
+ assign \$41 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) ra;
+ assign \$43 = sign_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *) \$39 : \$41 ;
+ assign \$46 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *) rb;
+ assign \$48 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) rb;
+ assign \$50 = sign_b ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *) \$46 : \$48 ;
+ assign \$52 = is_32bit ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) 32'd0 : abs_a[63:32];
+ assign \$54 = is_32bit ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) 32'd0 : abs_b[63:32];
+ assign \$38 = \$43 ;
+ assign \$45 = \$50 ;
+ assign { \mul_op__SV_Ptype$18 , \mul_op__sv_ldstmode$17 , \mul_op__sv_saturate$16 , \mul_op__sv_pred_dz$15 , \mul_op__sv_pred_sz$14 , \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 } = { mul_op__SV_Ptype, mul_op__sv_ldstmode, mul_op__sv_saturate, mul_op__sv_pred_dz, mul_op__sv_pred_sz, mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type };
assign \muxid$1 = muxid;
- assign \xer_so$20 = xer_so;
- assign \rb$19 [63:32] = \$53 ;
- assign \rb$19 [31:0] = abs_b[31:0];
- assign \ra$18 [63:32] = \$51 ;
- assign \ra$18 [31:0] = abs_a[31:0];
- assign abs_b = \$49 [63:0];
- assign abs_a = \$42 [63:0];
- assign neg_res32 = \$35 ;
- assign neg_res = \$33 ;
- assign sign32_b = \$31 ;
- assign sign32_a = \$29 ;
- assign sign_b = \$27 ;
- assign sign_a = \$23 ;
+ assign \xer_so$21 = xer_so;
+ assign \rb$20 [63:32] = \$54 ;
+ assign \rb$20 [31:0] = abs_b[31:0];
+ assign \ra$19 [63:32] = \$52 ;
+ assign \ra$19 [31:0] = abs_a[31:0];
+ assign abs_b = \$50 [63:0];
+ assign abs_a = \$43 [63:0];
+ assign neg_res32 = \$36 ;
+ assign neg_res = \$34 ;
+ assign sign32_b = \$32 ;
+ assign sign32_a = \$30 ;
+ assign sign_b = \$28 ;
+ assign sign_a = \$24 ;
assign is_32bit = mul_op__is_32bit;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.mul2" *)
(* generator = "nMigen" *)
-module mul2(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__SV_Ptype, ra, rb, xer_so, neg_res, neg_res32, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \mul_op__sv_pred_sz$14 , \mul_op__sv_pred_dz$15 , \mul_op__sv_saturate$16 , \mul_op__SV_Ptype$17 , o, \xer_so$18 , \neg_res$19 , \neg_res32$20 , muxid);
+module mul2(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__sv_ldstmode, mul_op__SV_Ptype, ra, rb, xer_so, neg_res, neg_res32, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \mul_op__sv_pred_sz$14 , \mul_op__sv_pred_dz$15 , \mul_op__sv_saturate$16 , \mul_op__sv_ldstmode$17 , \mul_op__SV_Ptype$18 , o, \xer_so$19 , \neg_res$20 , \neg_res32$21 , muxid);
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" *)
- wire [128:0] \$21 ;
+ wire [128:0] \$22 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" *)
- wire [127:0] \$22 ;
+ wire [127:0] \$23 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \mul_op__SV_Ptype$17 ;
+ output [1:0] \mul_op__SV_Ptype$18 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
input mul_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \mul_op__rc__rc$6 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] mul_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \mul_op__sv_ldstmode$17 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *)
input neg_res;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *)
- output \neg_res$19 ;
+ output \neg_res$20 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *)
input neg_res32;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *)
- output \neg_res32$20 ;
+ output \neg_res32$21 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
output [128:0] o;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input xer_so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output \xer_so$18 ;
- assign \$22 = ra * (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" *) rb;
- assign \$21 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" *) \$22 ;
- assign { \mul_op__SV_Ptype$17 , \mul_op__sv_saturate$16 , \mul_op__sv_pred_dz$15 , \mul_op__sv_pred_sz$14 , \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 } = { mul_op__SV_Ptype, mul_op__sv_saturate, mul_op__sv_pred_dz, mul_op__sv_pred_sz, mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type };
+ output \xer_so$19 ;
+ assign \$23 = ra * (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" *) rb;
+ assign \$22 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" *) \$23 ;
+ assign { \mul_op__SV_Ptype$18 , \mul_op__sv_ldstmode$17 , \mul_op__sv_saturate$16 , \mul_op__sv_pred_dz$15 , \mul_op__sv_pred_sz$14 , \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 } = { mul_op__SV_Ptype, mul_op__sv_ldstmode, mul_op__sv_saturate, mul_op__sv_pred_dz, mul_op__sv_pred_sz, mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type };
assign \muxid$1 = muxid;
- assign \xer_so$18 = xer_so;
- assign \neg_res32$20 = neg_res32;
- assign \neg_res$19 = neg_res;
- assign o = \$21 ;
+ assign \xer_so$19 = xer_so;
+ assign \neg_res32$21 = neg_res32;
+ assign \neg_res$20 = neg_res;
+ assign o = \$22 ;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.mul3" *)
(* generator = "nMigen" *)
-module mul3(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__SV_Ptype, o, xer_so, neg_res, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \mul_op__sv_pred_sz$14 , \mul_op__sv_pred_dz$15 , \mul_op__sv_saturate$16 , \mul_op__SV_Ptype$17 , \o$18 , o_ok, xer_ov, xer_ov_ok, \xer_so$19 , xer_so_ok, muxid);
+module mul3(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__sv_ldstmode, mul_op__SV_Ptype, o, xer_so, neg_res, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \mul_op__sv_pred_sz$14 , \mul_op__sv_pred_dz$15 , \mul_op__sv_saturate$16 , \mul_op__sv_ldstmode$17 , \mul_op__SV_Ptype$18 , \o$19 , o_ok, xer_ov, xer_ov_ok, \xer_so$20 , xer_so_ok, muxid);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *)
- wire [129:0] \$20 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *)
wire [129:0] \$21 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *)
+ wire [129:0] \$22 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [129:0] \$23 ;
+ wire [129:0] \$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *)
- wire [129:0] \$25 ;
+ wire [129:0] \$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *)
- wire \$27 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *)
- wire \$29 ;
+ wire \$28 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *)
wire \$30 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *)
- wire \$33 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *)
- wire \$35 ;
+ wire \$31 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *)
+ wire \$34 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *)
- wire \$37 ;
+ wire \$36 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *)
wire \$38 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *)
- wire \$41 ;
+ wire \$39 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *)
+ wire \$42 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [1:0] \$43 ;
+ wire [1:0] \$44 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" *)
wire is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:40" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \mul_op__SV_Ptype$17 ;
+ output [1:0] \mul_op__SV_Ptype$18 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
input mul_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \mul_op__rc__rc$6 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] mul_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \mul_op__sv_ldstmode$17 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [128:0] o;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [63:0] \o$18 ;
- reg [63:0] \o$18 ;
+ output [63:0] \o$19 ;
+ reg [63:0] \o$19 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output o_ok;
reg o_ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \xer_so$19 ;
+ output \xer_so$20 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_so_ok;
- assign \$21 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *) o;
- assign \$23 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) o;
- assign \$25 = neg_res ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *) \$21 : \$23 ;
- assign \$27 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) mul_o[63:31];
- assign \$30 = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) mul_o[63:31];
- assign \$29 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) \$30 ;
- assign \$33 = \$27 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) \$29 ;
- assign \$35 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) mul_o[127:63];
- assign \$38 = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) mul_o[127:63];
- assign \$37 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) \$38 ;
- assign \$41 = \$35 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) \$37 ;
- assign \$43 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) xer_so;
- always @* begin
- if (\initial ) begin end
- \o$18 = 64'h0000000000000000;
+ assign \$22 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *) o;
+ assign \$24 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) o;
+ assign \$26 = neg_res ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *) \$22 : \$24 ;
+ assign \$28 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) mul_o[63:31];
+ assign \$31 = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) mul_o[63:31];
+ assign \$30 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) \$31 ;
+ assign \$34 = \$28 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) \$30 ;
+ assign \$36 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) mul_o[127:63];
+ assign \$39 = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) mul_o[127:63];
+ assign \$38 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) \$39 ;
+ assign \$42 = \$36 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) \$38 ;
+ assign \$44 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) xer_so;
+ always @* begin
+ if (\initial ) begin end
+ \o$19 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" *)
casez (mul_op__insn_type)
/* \nmigen.decoding = "OP_MUL_H32/52" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:46" */
7'h34:
- \o$18 = { mul_o[63:32], mul_o[63:32] };
+ \o$19 = { mul_o[63:32], mul_o[63:32] };
/* \nmigen.decoding = "OP_MUL_H64/51" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50" */
7'h33:
- \o$18 = mul_o[127:64];
+ \o$19 = mul_o[127:64];
/* \nmigen.decoding = "OP_MUL_L64/50" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:54" */
7'h32:
- \o$18 = mul_o[63:0];
+ \o$19 = mul_o[63:0];
endcase
end
always @* begin
casez (is_32bit)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:61" */
1'h1:
- mul_ov = \$33 ;
+ mul_ov = \$34 ;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:66" */
default:
- mul_ov = \$41 ;
+ mul_ov = \$42 ;
endcase
endcase
end
xer_ov_ok = 1'h1;
endcase
end
- assign \$20 = \$25 ;
- assign { \mul_op__SV_Ptype$17 , \mul_op__sv_saturate$16 , \mul_op__sv_pred_dz$15 , \mul_op__sv_pred_sz$14 , \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 } = { mul_op__SV_Ptype, mul_op__sv_saturate, mul_op__sv_pred_dz, mul_op__sv_pred_sz, mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type };
+ assign \$21 = \$26 ;
+ assign { \mul_op__SV_Ptype$18 , \mul_op__sv_ldstmode$17 , \mul_op__sv_saturate$16 , \mul_op__sv_pred_dz$15 , \mul_op__sv_pred_sz$14 , \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 } = { mul_op__SV_Ptype, mul_op__sv_ldstmode, mul_op__sv_saturate, mul_op__sv_pred_dz, mul_op__sv_pred_sz, mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type };
assign \muxid$1 = muxid;
- assign { xer_so_ok, \xer_so$19 } = \$43 ;
- assign mul_o = \$25 [128:0];
+ assign { xer_so_ok, \xer_so$20 } = \$44 ;
+ assign mul_o = \$26 [128:0];
assign is_32bit = mul_op__is_32bit;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1" *)
(* generator = "nMigen" *)
-module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__SV_Ptype, ra, rb, xer_so, neg_res, neg_res32, p_valid_i, p_ready_o, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \mul_op__sv_pred_sz$14 , \mul_op__sv_pred_dz$15 , \mul_op__sv_saturate$16 , \mul_op__SV_Ptype$17 , \ra$18 , \rb$19 , \xer_so$20 , coresync_clk);
+module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__sv_ldstmode, mul_op__SV_Ptype, ra, rb, xer_so, neg_res, neg_res32, p_valid_i, p_ready_o, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \mul_op__sv_pred_sz$14 , \mul_op__sv_pred_dz$15 , \mul_op__sv_saturate$16 , \mul_op__sv_ldstmode$17 , \mul_op__SV_Ptype$18 , \ra$19 , \rb$20 , \xer_so$21 , coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
- wire \$62 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ wire \$65 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \input_mul_op__SV_Ptype$37 ;
+ wire [1:0] \input_mul_op__SV_Ptype$39 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \input_mul_op__fn_unit$23 ;
+ wire [14:0] \input_mul_op__fn_unit$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] input_mul_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \input_mul_op__imm_data__data$24 ;
+ wire [63:0] \input_mul_op__imm_data__data$25 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_mul_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_mul_op__imm_data__ok$25 ;
+ wire \input_mul_op__imm_data__ok$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] input_mul_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \input_mul_op__insn$33 ;
+ wire [31:0] \input_mul_op__insn$34 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \input_mul_op__insn_type$22 ;
+ wire [6:0] \input_mul_op__insn_type$23 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_mul_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_mul_op__is_32bit$31 ;
+ wire \input_mul_op__is_32bit$32 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_mul_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_mul_op__is_signed$32 ;
+ wire \input_mul_op__is_signed$33 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_mul_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_mul_op__oe__oe$28 ;
+ wire \input_mul_op__oe__oe$29 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_mul_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_mul_op__oe__ok$29 ;
+ wire \input_mul_op__oe__ok$30 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_mul_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_mul_op__rc__ok$27 ;
+ wire \input_mul_op__rc__ok$28 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_mul_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_mul_op__rc__rc$26 ;
+ wire \input_mul_op__rc__rc$27 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] input_mul_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \input_mul_op__sv_ldstmode$38 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_mul_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_mul_op__sv_pred_dz$35 ;
+ wire \input_mul_op__sv_pred_dz$36 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_mul_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_mul_op__sv_pred_sz$34 ;
+ wire \input_mul_op__sv_pred_sz$35 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \input_mul_op__sv_saturate$36 ;
+ wire [1:0] \input_mul_op__sv_saturate$37 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_mul_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_mul_op__write_cr0$30 ;
+ wire \input_mul_op__write_cr0$31 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] input_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \input_muxid$21 ;
+ wire [1:0] \input_muxid$22 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] input_ra;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \input_ra$38 ;
+ wire [63:0] \input_ra$40 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] input_rb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \input_rb$39 ;
+ wire [63:0] \input_rb$41 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire input_xer_so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire \input_xer_so$40 ;
+ wire \input_xer_so$42 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \mul1_mul_op__SV_Ptype$57 ;
+ wire [1:0] \mul1_mul_op__SV_Ptype$60 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \mul1_mul_op__fn_unit$43 ;
+ wire [14:0] \mul1_mul_op__fn_unit$45 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] mul1_mul_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \mul1_mul_op__imm_data__data$44 ;
+ wire [63:0] \mul1_mul_op__imm_data__data$46 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul1_mul_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul1_mul_op__imm_data__ok$45 ;
+ wire \mul1_mul_op__imm_data__ok$47 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] mul1_mul_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \mul1_mul_op__insn$53 ;
+ wire [31:0] \mul1_mul_op__insn$55 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \mul1_mul_op__insn_type$42 ;
+ wire [6:0] \mul1_mul_op__insn_type$44 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul1_mul_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul1_mul_op__is_32bit$51 ;
+ wire \mul1_mul_op__is_32bit$53 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul1_mul_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul1_mul_op__is_signed$52 ;
+ wire \mul1_mul_op__is_signed$54 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul1_mul_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul1_mul_op__oe__oe$48 ;
+ wire \mul1_mul_op__oe__oe$50 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul1_mul_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul1_mul_op__oe__ok$49 ;
+ wire \mul1_mul_op__oe__ok$51 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul1_mul_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul1_mul_op__rc__ok$47 ;
+ wire \mul1_mul_op__rc__ok$49 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul1_mul_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul1_mul_op__rc__rc$46 ;
+ wire \mul1_mul_op__rc__rc$48 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] mul1_mul_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \mul1_mul_op__sv_ldstmode$59 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul1_mul_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul1_mul_op__sv_pred_dz$55 ;
+ wire \mul1_mul_op__sv_pred_dz$57 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul1_mul_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul1_mul_op__sv_pred_sz$54 ;
+ wire \mul1_mul_op__sv_pred_sz$56 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \mul1_mul_op__sv_saturate$56 ;
+ wire [1:0] \mul1_mul_op__sv_saturate$58 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul1_mul_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul1_mul_op__write_cr0$50 ;
+ wire \mul1_mul_op__write_cr0$52 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] mul1_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \mul1_muxid$41 ;
+ wire [1:0] \mul1_muxid$43 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *)
wire mul1_neg_res;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] mul1_ra;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \mul1_ra$58 ;
+ wire [63:0] \mul1_ra$61 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] mul1_rb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \mul1_rb$59 ;
+ wire [63:0] \mul1_rb$62 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire mul1_xer_so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire \mul1_xer_so$60 ;
+ wire \mul1_xer_so$63 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- input [1:0] \mul_op__SV_Ptype$17 ;
+ input [1:0] \mul_op__SV_Ptype$18 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \mul_op__SV_Ptype$80 ;
+ wire [1:0] \mul_op__SV_Ptype$84 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [1:0] \mul_op__SV_Ptype$next ;
(* enum_base_type = "Function" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \mul_op__fn_unit$66 ;
+ wire [14:0] \mul_op__fn_unit$69 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [14:0] \mul_op__fn_unit$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] \mul_op__imm_data__data$4 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \mul_op__imm_data__data$67 ;
+ wire [63:0] \mul_op__imm_data__data$70 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [63:0] \mul_op__imm_data__data$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \mul_op__imm_data__ok$5 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__imm_data__ok$68 ;
+ wire \mul_op__imm_data__ok$71 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \mul_op__imm_data__ok$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] \mul_op__insn$13 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \mul_op__insn$76 ;
+ wire [31:0] \mul_op__insn$79 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [31:0] \mul_op__insn$next ;
(* enum_base_type = "MicrOp" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \mul_op__insn_type$65 ;
+ wire [6:0] \mul_op__insn_type$68 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [6:0] \mul_op__insn_type$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \mul_op__is_32bit$11 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__is_32bit$74 ;
+ wire \mul_op__is_32bit$77 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \mul_op__is_32bit$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \mul_op__is_signed$12 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__is_signed$75 ;
+ wire \mul_op__is_signed$78 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \mul_op__is_signed$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output mul_op__oe__oe;
reg mul_op__oe__oe = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__oe__oe$71 ;
+ wire \mul_op__oe__oe$74 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \mul_op__oe__oe$8 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output mul_op__oe__ok;
reg mul_op__oe__ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__oe__ok$72 ;
+ wire \mul_op__oe__ok$75 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \mul_op__oe__ok$9 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \mul_op__rc__ok$7 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__rc__ok$70 ;
+ wire \mul_op__rc__ok$73 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \mul_op__rc__ok$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \mul_op__rc__rc$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__rc__rc$69 ;
+ wire \mul_op__rc__rc$72 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \mul_op__rc__rc$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] mul_op__sv_ldstmode;
+ reg [1:0] mul_op__sv_ldstmode = 2'h0;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] \mul_op__sv_ldstmode$17 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \mul_op__sv_ldstmode$83 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \mul_op__sv_ldstmode$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output mul_op__sv_pred_dz;
reg mul_op__sv_pred_dz = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \mul_op__sv_pred_dz$15 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__sv_pred_dz$78 ;
+ wire \mul_op__sv_pred_dz$81 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \mul_op__sv_pred_dz$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \mul_op__sv_pred_sz$14 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__sv_pred_sz$77 ;
+ wire \mul_op__sv_pred_sz$80 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \mul_op__sv_pred_sz$next ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \mul_op__sv_saturate$79 ;
+ wire [1:0] \mul_op__sv_saturate$82 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [1:0] \mul_op__sv_saturate$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \mul_op__write_cr0$10 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__write_cr0$73 ;
+ wire \mul_op__write_cr0$76 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \mul_op__write_cr0$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
input [1:0] \muxid$1 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \muxid$64 ;
+ wire [1:0] \muxid$67 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
reg [1:0] \muxid$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
output neg_res;
reg neg_res = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *)
- wire \neg_res$84 ;
+ wire \neg_res$88 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *)
reg \neg_res$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *)
output neg_res32;
reg neg_res32 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *)
- wire \neg_res32$85 ;
+ wire \neg_res32$89 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *)
reg \neg_res32$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
input p_valid_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
- wire \p_valid_i$61 ;
+ wire \p_valid_i$64 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
wire p_valid_i_p_ready_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
output [63:0] ra;
reg [63:0] ra = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- input [63:0] \ra$18 ;
+ input [63:0] \ra$19 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \ra$81 ;
+ wire [63:0] \ra$85 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
reg [63:0] \ra$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
output [63:0] rb;
reg [63:0] rb = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- input [63:0] \rb$19 ;
+ input [63:0] \rb$20 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \rb$82 ;
+ wire [63:0] \rb$86 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
reg [63:0] \rb$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
output xer_so;
reg xer_so = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- input \xer_so$20 ;
+ input \xer_so$21 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire \xer_so$83 ;
+ wire \xer_so$87 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
reg \xer_so$next ;
- assign \$62 = \p_valid_i$61 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
+ assign \$65 = \p_valid_i$64 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
always @(posedge coresync_clk)
neg_res32 <= \neg_res32$next ;
always @(posedge coresync_clk)
mul_op__sv_pred_dz <= \mul_op__sv_pred_dz$next ;
always @(posedge coresync_clk)
mul_op__sv_saturate <= \mul_op__sv_saturate$next ;
+ always @(posedge coresync_clk)
+ mul_op__sv_ldstmode <= \mul_op__sv_ldstmode$next ;
always @(posedge coresync_clk)
mul_op__SV_Ptype <= \mul_op__SV_Ptype$next ;
always @(posedge coresync_clk)
r_busy <= \r_busy$next ;
\input$95 \input (
.mul_op__SV_Ptype(input_mul_op__SV_Ptype),
- .\mul_op__SV_Ptype$17 (\input_mul_op__SV_Ptype$37 ),
+ .\mul_op__SV_Ptype$18 (\input_mul_op__SV_Ptype$39 ),
.mul_op__fn_unit(input_mul_op__fn_unit),
- .\mul_op__fn_unit$3 (\input_mul_op__fn_unit$23 ),
+ .\mul_op__fn_unit$3 (\input_mul_op__fn_unit$24 ),
.mul_op__imm_data__data(input_mul_op__imm_data__data),
- .\mul_op__imm_data__data$4 (\input_mul_op__imm_data__data$24 ),
+ .\mul_op__imm_data__data$4 (\input_mul_op__imm_data__data$25 ),
.mul_op__imm_data__ok(input_mul_op__imm_data__ok),
- .\mul_op__imm_data__ok$5 (\input_mul_op__imm_data__ok$25 ),
+ .\mul_op__imm_data__ok$5 (\input_mul_op__imm_data__ok$26 ),
.mul_op__insn(input_mul_op__insn),
- .\mul_op__insn$13 (\input_mul_op__insn$33 ),
+ .\mul_op__insn$13 (\input_mul_op__insn$34 ),
.mul_op__insn_type(input_mul_op__insn_type),
- .\mul_op__insn_type$2 (\input_mul_op__insn_type$22 ),
+ .\mul_op__insn_type$2 (\input_mul_op__insn_type$23 ),
.mul_op__is_32bit(input_mul_op__is_32bit),
- .\mul_op__is_32bit$11 (\input_mul_op__is_32bit$31 ),
+ .\mul_op__is_32bit$11 (\input_mul_op__is_32bit$32 ),
.mul_op__is_signed(input_mul_op__is_signed),
- .\mul_op__is_signed$12 (\input_mul_op__is_signed$32 ),
+ .\mul_op__is_signed$12 (\input_mul_op__is_signed$33 ),
.mul_op__oe__oe(input_mul_op__oe__oe),
- .\mul_op__oe__oe$8 (\input_mul_op__oe__oe$28 ),
+ .\mul_op__oe__oe$8 (\input_mul_op__oe__oe$29 ),
.mul_op__oe__ok(input_mul_op__oe__ok),
- .\mul_op__oe__ok$9 (\input_mul_op__oe__ok$29 ),
+ .\mul_op__oe__ok$9 (\input_mul_op__oe__ok$30 ),
.mul_op__rc__ok(input_mul_op__rc__ok),
- .\mul_op__rc__ok$7 (\input_mul_op__rc__ok$27 ),
+ .\mul_op__rc__ok$7 (\input_mul_op__rc__ok$28 ),
.mul_op__rc__rc(input_mul_op__rc__rc),
- .\mul_op__rc__rc$6 (\input_mul_op__rc__rc$26 ),
+ .\mul_op__rc__rc$6 (\input_mul_op__rc__rc$27 ),
+ .mul_op__sv_ldstmode(input_mul_op__sv_ldstmode),
+ .\mul_op__sv_ldstmode$17 (\input_mul_op__sv_ldstmode$38 ),
.mul_op__sv_pred_dz(input_mul_op__sv_pred_dz),
- .\mul_op__sv_pred_dz$15 (\input_mul_op__sv_pred_dz$35 ),
+ .\mul_op__sv_pred_dz$15 (\input_mul_op__sv_pred_dz$36 ),
.mul_op__sv_pred_sz(input_mul_op__sv_pred_sz),
- .\mul_op__sv_pred_sz$14 (\input_mul_op__sv_pred_sz$34 ),
+ .\mul_op__sv_pred_sz$14 (\input_mul_op__sv_pred_sz$35 ),
.mul_op__sv_saturate(input_mul_op__sv_saturate),
- .\mul_op__sv_saturate$16 (\input_mul_op__sv_saturate$36 ),
+ .\mul_op__sv_saturate$16 (\input_mul_op__sv_saturate$37 ),
.mul_op__write_cr0(input_mul_op__write_cr0),
- .\mul_op__write_cr0$10 (\input_mul_op__write_cr0$30 ),
+ .\mul_op__write_cr0$10 (\input_mul_op__write_cr0$31 ),
.muxid(input_muxid),
- .\muxid$1 (\input_muxid$21 ),
+ .\muxid$1 (\input_muxid$22 ),
.ra(input_ra),
- .\ra$18 (\input_ra$38 ),
+ .\ra$19 (\input_ra$40 ),
.rb(input_rb),
- .\rb$19 (\input_rb$39 ),
+ .\rb$20 (\input_rb$41 ),
.xer_so(input_xer_so),
- .\xer_so$20 (\input_xer_so$40 )
+ .\xer_so$21 (\input_xer_so$42 )
);
mul1 mul1 (
.mul_op__SV_Ptype(mul1_mul_op__SV_Ptype),
- .\mul_op__SV_Ptype$17 (\mul1_mul_op__SV_Ptype$57 ),
+ .\mul_op__SV_Ptype$18 (\mul1_mul_op__SV_Ptype$60 ),
.mul_op__fn_unit(mul1_mul_op__fn_unit),
- .\mul_op__fn_unit$3 (\mul1_mul_op__fn_unit$43 ),
+ .\mul_op__fn_unit$3 (\mul1_mul_op__fn_unit$45 ),
.mul_op__imm_data__data(mul1_mul_op__imm_data__data),
- .\mul_op__imm_data__data$4 (\mul1_mul_op__imm_data__data$44 ),
+ .\mul_op__imm_data__data$4 (\mul1_mul_op__imm_data__data$46 ),
.mul_op__imm_data__ok(mul1_mul_op__imm_data__ok),
- .\mul_op__imm_data__ok$5 (\mul1_mul_op__imm_data__ok$45 ),
+ .\mul_op__imm_data__ok$5 (\mul1_mul_op__imm_data__ok$47 ),
.mul_op__insn(mul1_mul_op__insn),
- .\mul_op__insn$13 (\mul1_mul_op__insn$53 ),
+ .\mul_op__insn$13 (\mul1_mul_op__insn$55 ),
.mul_op__insn_type(mul1_mul_op__insn_type),
- .\mul_op__insn_type$2 (\mul1_mul_op__insn_type$42 ),
+ .\mul_op__insn_type$2 (\mul1_mul_op__insn_type$44 ),
.mul_op__is_32bit(mul1_mul_op__is_32bit),
- .\mul_op__is_32bit$11 (\mul1_mul_op__is_32bit$51 ),
+ .\mul_op__is_32bit$11 (\mul1_mul_op__is_32bit$53 ),
.mul_op__is_signed(mul1_mul_op__is_signed),
- .\mul_op__is_signed$12 (\mul1_mul_op__is_signed$52 ),
+ .\mul_op__is_signed$12 (\mul1_mul_op__is_signed$54 ),
.mul_op__oe__oe(mul1_mul_op__oe__oe),
- .\mul_op__oe__oe$8 (\mul1_mul_op__oe__oe$48 ),
+ .\mul_op__oe__oe$8 (\mul1_mul_op__oe__oe$50 ),
.mul_op__oe__ok(mul1_mul_op__oe__ok),
- .\mul_op__oe__ok$9 (\mul1_mul_op__oe__ok$49 ),
+ .\mul_op__oe__ok$9 (\mul1_mul_op__oe__ok$51 ),
.mul_op__rc__ok(mul1_mul_op__rc__ok),
- .\mul_op__rc__ok$7 (\mul1_mul_op__rc__ok$47 ),
+ .\mul_op__rc__ok$7 (\mul1_mul_op__rc__ok$49 ),
.mul_op__rc__rc(mul1_mul_op__rc__rc),
- .\mul_op__rc__rc$6 (\mul1_mul_op__rc__rc$46 ),
+ .\mul_op__rc__rc$6 (\mul1_mul_op__rc__rc$48 ),
+ .mul_op__sv_ldstmode(mul1_mul_op__sv_ldstmode),
+ .\mul_op__sv_ldstmode$17 (\mul1_mul_op__sv_ldstmode$59 ),
.mul_op__sv_pred_dz(mul1_mul_op__sv_pred_dz),
- .\mul_op__sv_pred_dz$15 (\mul1_mul_op__sv_pred_dz$55 ),
+ .\mul_op__sv_pred_dz$15 (\mul1_mul_op__sv_pred_dz$57 ),
.mul_op__sv_pred_sz(mul1_mul_op__sv_pred_sz),
- .\mul_op__sv_pred_sz$14 (\mul1_mul_op__sv_pred_sz$54 ),
+ .\mul_op__sv_pred_sz$14 (\mul1_mul_op__sv_pred_sz$56 ),
.mul_op__sv_saturate(mul1_mul_op__sv_saturate),
- .\mul_op__sv_saturate$16 (\mul1_mul_op__sv_saturate$56 ),
+ .\mul_op__sv_saturate$16 (\mul1_mul_op__sv_saturate$58 ),
.mul_op__write_cr0(mul1_mul_op__write_cr0),
- .\mul_op__write_cr0$10 (\mul1_mul_op__write_cr0$50 ),
+ .\mul_op__write_cr0$10 (\mul1_mul_op__write_cr0$52 ),
.muxid(mul1_muxid),
- .\muxid$1 (\mul1_muxid$41 ),
+ .\muxid$1 (\mul1_muxid$43 ),
.neg_res(mul1_neg_res),
.neg_res32(mul1_neg_res32),
.ra(mul1_ra),
- .\ra$18 (\mul1_ra$58 ),
+ .\ra$19 (\mul1_ra$61 ),
.rb(mul1_rb),
- .\rb$19 (\mul1_rb$59 ),
+ .\rb$20 (\mul1_rb$62 ),
.xer_so(mul1_xer_so),
- .\xer_so$20 (\mul1_xer_so$60 )
+ .\xer_so$21 (\mul1_xer_so$63 )
);
\n$94 n (
.n_ready_i(n_ready_i),
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \muxid$next = \muxid$64 ;
+ \muxid$next = \muxid$67 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \muxid$next = \muxid$64 ;
+ \muxid$next = \muxid$67 ;
endcase
end
always @* begin
\mul_op__sv_pred_sz$next = mul_op__sv_pred_sz;
\mul_op__sv_pred_dz$next = mul_op__sv_pred_dz;
\mul_op__sv_saturate$next = mul_op__sv_saturate;
+ \mul_op__sv_ldstmode$next = mul_op__sv_ldstmode;
\mul_op__SV_Ptype$next = mul_op__SV_Ptype;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \mul_op__SV_Ptype$next , \mul_op__sv_saturate$next , \mul_op__sv_pred_dz$next , \mul_op__sv_pred_sz$next , \mul_op__insn$next , \mul_op__is_signed$next , \mul_op__is_32bit$next , \mul_op__write_cr0$next , \mul_op__oe__ok$next , \mul_op__oe__oe$next , \mul_op__rc__ok$next , \mul_op__rc__rc$next , \mul_op__imm_data__ok$next , \mul_op__imm_data__data$next , \mul_op__fn_unit$next , \mul_op__insn_type$next } = { \mul_op__SV_Ptype$80 , \mul_op__sv_saturate$79 , \mul_op__sv_pred_dz$78 , \mul_op__sv_pred_sz$77 , \mul_op__insn$76 , \mul_op__is_signed$75 , \mul_op__is_32bit$74 , \mul_op__write_cr0$73 , \mul_op__oe__ok$72 , \mul_op__oe__oe$71 , \mul_op__rc__ok$70 , \mul_op__rc__rc$69 , \mul_op__imm_data__ok$68 , \mul_op__imm_data__data$67 , \mul_op__fn_unit$66 , \mul_op__insn_type$65 };
+ { \mul_op__SV_Ptype$next , \mul_op__sv_ldstmode$next , \mul_op__sv_saturate$next , \mul_op__sv_pred_dz$next , \mul_op__sv_pred_sz$next , \mul_op__insn$next , \mul_op__is_signed$next , \mul_op__is_32bit$next , \mul_op__write_cr0$next , \mul_op__oe__ok$next , \mul_op__oe__oe$next , \mul_op__rc__ok$next , \mul_op__rc__rc$next , \mul_op__imm_data__ok$next , \mul_op__imm_data__data$next , \mul_op__fn_unit$next , \mul_op__insn_type$next } = { \mul_op__SV_Ptype$84 , \mul_op__sv_ldstmode$83 , \mul_op__sv_saturate$82 , \mul_op__sv_pred_dz$81 , \mul_op__sv_pred_sz$80 , \mul_op__insn$79 , \mul_op__is_signed$78 , \mul_op__is_32bit$77 , \mul_op__write_cr0$76 , \mul_op__oe__ok$75 , \mul_op__oe__oe$74 , \mul_op__rc__ok$73 , \mul_op__rc__rc$72 , \mul_op__imm_data__ok$71 , \mul_op__imm_data__data$70 , \mul_op__fn_unit$69 , \mul_op__insn_type$68 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \mul_op__SV_Ptype$next , \mul_op__sv_saturate$next , \mul_op__sv_pred_dz$next , \mul_op__sv_pred_sz$next , \mul_op__insn$next , \mul_op__is_signed$next , \mul_op__is_32bit$next , \mul_op__write_cr0$next , \mul_op__oe__ok$next , \mul_op__oe__oe$next , \mul_op__rc__ok$next , \mul_op__rc__rc$next , \mul_op__imm_data__ok$next , \mul_op__imm_data__data$next , \mul_op__fn_unit$next , \mul_op__insn_type$next } = { \mul_op__SV_Ptype$80 , \mul_op__sv_saturate$79 , \mul_op__sv_pred_dz$78 , \mul_op__sv_pred_sz$77 , \mul_op__insn$76 , \mul_op__is_signed$75 , \mul_op__is_32bit$74 , \mul_op__write_cr0$73 , \mul_op__oe__ok$72 , \mul_op__oe__oe$71 , \mul_op__rc__ok$70 , \mul_op__rc__rc$69 , \mul_op__imm_data__ok$68 , \mul_op__imm_data__data$67 , \mul_op__fn_unit$66 , \mul_op__insn_type$65 };
+ { \mul_op__SV_Ptype$next , \mul_op__sv_ldstmode$next , \mul_op__sv_saturate$next , \mul_op__sv_pred_dz$next , \mul_op__sv_pred_sz$next , \mul_op__insn$next , \mul_op__is_signed$next , \mul_op__is_32bit$next , \mul_op__write_cr0$next , \mul_op__oe__ok$next , \mul_op__oe__oe$next , \mul_op__rc__ok$next , \mul_op__rc__rc$next , \mul_op__imm_data__ok$next , \mul_op__imm_data__data$next , \mul_op__fn_unit$next , \mul_op__insn_type$next } = { \mul_op__SV_Ptype$84 , \mul_op__sv_ldstmode$83 , \mul_op__sv_saturate$82 , \mul_op__sv_pred_dz$81 , \mul_op__sv_pred_sz$80 , \mul_op__insn$79 , \mul_op__is_signed$78 , \mul_op__is_32bit$77 , \mul_op__write_cr0$76 , \mul_op__oe__ok$75 , \mul_op__oe__oe$74 , \mul_op__rc__ok$73 , \mul_op__rc__rc$72 , \mul_op__imm_data__ok$71 , \mul_op__imm_data__data$70 , \mul_op__fn_unit$69 , \mul_op__insn_type$68 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \ra$next = \ra$81 ;
+ \ra$next = \ra$85 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \ra$next = \ra$81 ;
+ \ra$next = \ra$85 ;
endcase
end
always @* begin
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \rb$next = \rb$82 ;
+ \rb$next = \rb$86 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \rb$next = \rb$82 ;
+ \rb$next = \rb$86 ;
endcase
end
always @* begin
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \xer_so$next = \xer_so$83 ;
+ \xer_so$next = \xer_so$87 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \xer_so$next = \xer_so$83 ;
+ \xer_so$next = \xer_so$87 ;
endcase
end
always @* begin
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \neg_res$next = \neg_res$84 ;
+ \neg_res$next = \neg_res$88 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \neg_res$next = \neg_res$84 ;
+ \neg_res$next = \neg_res$88 ;
endcase
end
always @* begin
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \neg_res32$next = \neg_res32$85 ;
+ \neg_res32$next = \neg_res32$89 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \neg_res32$next = \neg_res32$85 ;
+ \neg_res32$next = \neg_res32$89 ;
endcase
end
assign p_ready_o = n_i_rdy_data;
assign n_valid_o = r_busy;
- assign \neg_res32$85 = mul1_neg_res32;
- assign \neg_res$84 = mul1_neg_res;
- assign \xer_so$83 = \mul1_xer_so$60 ;
- assign \rb$82 = \mul1_rb$59 ;
- assign \ra$81 = \mul1_ra$58 ;
- assign { \mul_op__SV_Ptype$80 , \mul_op__sv_saturate$79 , \mul_op__sv_pred_dz$78 , \mul_op__sv_pred_sz$77 , \mul_op__insn$76 , \mul_op__is_signed$75 , \mul_op__is_32bit$74 , \mul_op__write_cr0$73 , \mul_op__oe__ok$72 , \mul_op__oe__oe$71 , \mul_op__rc__ok$70 , \mul_op__rc__rc$69 , \mul_op__imm_data__ok$68 , \mul_op__imm_data__data$67 , \mul_op__fn_unit$66 , \mul_op__insn_type$65 } = { \mul1_mul_op__SV_Ptype$57 , \mul1_mul_op__sv_saturate$56 , \mul1_mul_op__sv_pred_dz$55 , \mul1_mul_op__sv_pred_sz$54 , \mul1_mul_op__insn$53 , \mul1_mul_op__is_signed$52 , \mul1_mul_op__is_32bit$51 , \mul1_mul_op__write_cr0$50 , \mul1_mul_op__oe__ok$49 , \mul1_mul_op__oe__oe$48 , \mul1_mul_op__rc__ok$47 , \mul1_mul_op__rc__rc$46 , \mul1_mul_op__imm_data__ok$45 , \mul1_mul_op__imm_data__data$44 , \mul1_mul_op__fn_unit$43 , \mul1_mul_op__insn_type$42 };
- assign \muxid$64 = \mul1_muxid$41 ;
- assign p_valid_i_p_ready_o = \$62 ;
+ assign \neg_res32$89 = mul1_neg_res32;
+ assign \neg_res$88 = mul1_neg_res;
+ assign \xer_so$87 = \mul1_xer_so$63 ;
+ assign \rb$86 = \mul1_rb$62 ;
+ assign \ra$85 = \mul1_ra$61 ;
+ assign { \mul_op__SV_Ptype$84 , \mul_op__sv_ldstmode$83 , \mul_op__sv_saturate$82 , \mul_op__sv_pred_dz$81 , \mul_op__sv_pred_sz$80 , \mul_op__insn$79 , \mul_op__is_signed$78 , \mul_op__is_32bit$77 , \mul_op__write_cr0$76 , \mul_op__oe__ok$75 , \mul_op__oe__oe$74 , \mul_op__rc__ok$73 , \mul_op__rc__rc$72 , \mul_op__imm_data__ok$71 , \mul_op__imm_data__data$70 , \mul_op__fn_unit$69 , \mul_op__insn_type$68 } = { \mul1_mul_op__SV_Ptype$60 , \mul1_mul_op__sv_ldstmode$59 , \mul1_mul_op__sv_saturate$58 , \mul1_mul_op__sv_pred_dz$57 , \mul1_mul_op__sv_pred_sz$56 , \mul1_mul_op__insn$55 , \mul1_mul_op__is_signed$54 , \mul1_mul_op__is_32bit$53 , \mul1_mul_op__write_cr0$52 , \mul1_mul_op__oe__ok$51 , \mul1_mul_op__oe__oe$50 , \mul1_mul_op__rc__ok$49 , \mul1_mul_op__rc__rc$48 , \mul1_mul_op__imm_data__ok$47 , \mul1_mul_op__imm_data__data$46 , \mul1_mul_op__fn_unit$45 , \mul1_mul_op__insn_type$44 };
+ assign \muxid$67 = \mul1_muxid$43 ;
+ assign p_valid_i_p_ready_o = \$65 ;
assign n_i_rdy_data = n_ready_i;
- assign \p_valid_i$61 = p_valid_i;
- assign mul1_xer_so = \input_xer_so$40 ;
- assign mul1_rb = \input_rb$39 ;
- assign mul1_ra = \input_ra$38 ;
- assign { mul1_mul_op__SV_Ptype, mul1_mul_op__sv_saturate, mul1_mul_op__sv_pred_dz, mul1_mul_op__sv_pred_sz, mul1_mul_op__insn, mul1_mul_op__is_signed, mul1_mul_op__is_32bit, mul1_mul_op__write_cr0, mul1_mul_op__oe__ok, mul1_mul_op__oe__oe, mul1_mul_op__rc__ok, mul1_mul_op__rc__rc, mul1_mul_op__imm_data__ok, mul1_mul_op__imm_data__data, mul1_mul_op__fn_unit, mul1_mul_op__insn_type } = { \input_mul_op__SV_Ptype$37 , \input_mul_op__sv_saturate$36 , \input_mul_op__sv_pred_dz$35 , \input_mul_op__sv_pred_sz$34 , \input_mul_op__insn$33 , \input_mul_op__is_signed$32 , \input_mul_op__is_32bit$31 , \input_mul_op__write_cr0$30 , \input_mul_op__oe__ok$29 , \input_mul_op__oe__oe$28 , \input_mul_op__rc__ok$27 , \input_mul_op__rc__rc$26 , \input_mul_op__imm_data__ok$25 , \input_mul_op__imm_data__data$24 , \input_mul_op__fn_unit$23 , \input_mul_op__insn_type$22 };
- assign mul1_muxid = \input_muxid$21 ;
- assign input_xer_so = \xer_so$20 ;
- assign input_rb = \rb$19 ;
- assign input_ra = \ra$18 ;
- assign { input_mul_op__SV_Ptype, input_mul_op__sv_saturate, input_mul_op__sv_pred_dz, input_mul_op__sv_pred_sz, input_mul_op__insn, input_mul_op__is_signed, input_mul_op__is_32bit, input_mul_op__write_cr0, input_mul_op__oe__ok, input_mul_op__oe__oe, input_mul_op__rc__ok, input_mul_op__rc__rc, input_mul_op__imm_data__ok, input_mul_op__imm_data__data, input_mul_op__fn_unit, input_mul_op__insn_type } = { \mul_op__SV_Ptype$17 , \mul_op__sv_saturate$16 , \mul_op__sv_pred_dz$15 , \mul_op__sv_pred_sz$14 , \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 };
+ assign \p_valid_i$64 = p_valid_i;
+ assign mul1_xer_so = \input_xer_so$42 ;
+ assign mul1_rb = \input_rb$41 ;
+ assign mul1_ra = \input_ra$40 ;
+ assign { mul1_mul_op__SV_Ptype, mul1_mul_op__sv_ldstmode, mul1_mul_op__sv_saturate, mul1_mul_op__sv_pred_dz, mul1_mul_op__sv_pred_sz, mul1_mul_op__insn, mul1_mul_op__is_signed, mul1_mul_op__is_32bit, mul1_mul_op__write_cr0, mul1_mul_op__oe__ok, mul1_mul_op__oe__oe, mul1_mul_op__rc__ok, mul1_mul_op__rc__rc, mul1_mul_op__imm_data__ok, mul1_mul_op__imm_data__data, mul1_mul_op__fn_unit, mul1_mul_op__insn_type } = { \input_mul_op__SV_Ptype$39 , \input_mul_op__sv_ldstmode$38 , \input_mul_op__sv_saturate$37 , \input_mul_op__sv_pred_dz$36 , \input_mul_op__sv_pred_sz$35 , \input_mul_op__insn$34 , \input_mul_op__is_signed$33 , \input_mul_op__is_32bit$32 , \input_mul_op__write_cr0$31 , \input_mul_op__oe__ok$30 , \input_mul_op__oe__oe$29 , \input_mul_op__rc__ok$28 , \input_mul_op__rc__rc$27 , \input_mul_op__imm_data__ok$26 , \input_mul_op__imm_data__data$25 , \input_mul_op__fn_unit$24 , \input_mul_op__insn_type$23 };
+ assign mul1_muxid = \input_muxid$22 ;
+ assign input_xer_so = \xer_so$21 ;
+ assign input_rb = \rb$20 ;
+ assign input_ra = \ra$19 ;
+ assign { input_mul_op__SV_Ptype, input_mul_op__sv_ldstmode, input_mul_op__sv_saturate, input_mul_op__sv_pred_dz, input_mul_op__sv_pred_sz, input_mul_op__insn, input_mul_op__is_signed, input_mul_op__is_32bit, input_mul_op__write_cr0, input_mul_op__oe__ok, input_mul_op__oe__oe, input_mul_op__rc__ok, input_mul_op__rc__rc, input_mul_op__imm_data__ok, input_mul_op__imm_data__data, input_mul_op__fn_unit, input_mul_op__insn_type } = { \mul_op__SV_Ptype$18 , \mul_op__sv_ldstmode$17 , \mul_op__sv_saturate$16 , \mul_op__sv_pred_dz$15 , \mul_op__sv_pred_sz$14 , \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 };
assign input_muxid = \muxid$1 ;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2" *)
(* generator = "nMigen" *)
-module mul_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__SV_Ptype, ra, rb, xer_so, neg_res, neg_res32, n_valid_o, n_ready_i, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \mul_op__sv_pred_sz$14 , \mul_op__sv_pred_dz$15 , \mul_op__sv_saturate$16 , \mul_op__SV_Ptype$17 , o, \xer_so$18 , \neg_res$19 , \neg_res32$20 , coresync_clk);
+module mul_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__sv_ldstmode, mul_op__SV_Ptype, ra, rb, xer_so, neg_res, neg_res32, n_valid_o, n_ready_i, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \mul_op__sv_pred_sz$14 , \mul_op__sv_pred_dz$15 , \mul_op__sv_saturate$16 , \mul_op__sv_ldstmode$17 , \mul_op__SV_Ptype$18 , o, \xer_so$19 , \neg_res$20 , \neg_res32$21 , coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
- wire \$42 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ wire \$44 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \mul2_mul_op__SV_Ptype$37 ;
+ wire [1:0] \mul2_mul_op__SV_Ptype$39 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \mul2_mul_op__fn_unit$23 ;
+ wire [14:0] \mul2_mul_op__fn_unit$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] mul2_mul_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \mul2_mul_op__imm_data__data$24 ;
+ wire [63:0] \mul2_mul_op__imm_data__data$25 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul2_mul_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul2_mul_op__imm_data__ok$25 ;
+ wire \mul2_mul_op__imm_data__ok$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] mul2_mul_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \mul2_mul_op__insn$33 ;
+ wire [31:0] \mul2_mul_op__insn$34 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \mul2_mul_op__insn_type$22 ;
+ wire [6:0] \mul2_mul_op__insn_type$23 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul2_mul_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul2_mul_op__is_32bit$31 ;
+ wire \mul2_mul_op__is_32bit$32 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul2_mul_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul2_mul_op__is_signed$32 ;
+ wire \mul2_mul_op__is_signed$33 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul2_mul_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul2_mul_op__oe__oe$28 ;
+ wire \mul2_mul_op__oe__oe$29 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul2_mul_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul2_mul_op__oe__ok$29 ;
+ wire \mul2_mul_op__oe__ok$30 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul2_mul_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul2_mul_op__rc__ok$27 ;
+ wire \mul2_mul_op__rc__ok$28 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul2_mul_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul2_mul_op__rc__rc$26 ;
+ wire \mul2_mul_op__rc__rc$27 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] mul2_mul_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \mul2_mul_op__sv_ldstmode$38 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul2_mul_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul2_mul_op__sv_pred_dz$35 ;
+ wire \mul2_mul_op__sv_pred_dz$36 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul2_mul_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul2_mul_op__sv_pred_sz$34 ;
+ wire \mul2_mul_op__sv_pred_sz$35 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \mul2_mul_op__sv_saturate$36 ;
+ wire [1:0] \mul2_mul_op__sv_saturate$37 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul2_mul_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul2_mul_op__write_cr0$30 ;
+ wire \mul2_mul_op__write_cr0$31 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] mul2_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \mul2_muxid$21 ;
+ wire [1:0] \mul2_muxid$22 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *)
wire mul2_neg_res;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *)
- wire \mul2_neg_res$39 ;
+ wire \mul2_neg_res$41 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *)
wire mul2_neg_res32;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *)
- wire \mul2_neg_res32$40 ;
+ wire \mul2_neg_res32$42 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [128:0] mul2_o;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire mul2_xer_so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire \mul2_xer_so$38 ;
+ wire \mul2_xer_so$40 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \mul_op__SV_Ptype$17 ;
- reg [1:0] \mul_op__SV_Ptype$17 = 2'h0;
+ output [1:0] \mul_op__SV_Ptype$18 ;
+ reg [1:0] \mul_op__SV_Ptype$18 = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [1:0] \mul_op__SV_Ptype$17$next ;
+ reg [1:0] \mul_op__SV_Ptype$18$next ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \mul_op__SV_Ptype$60 ;
+ wire [1:0] \mul_op__SV_Ptype$63 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \mul_op__fn_unit$46 ;
+ wire [14:0] \mul_op__fn_unit$48 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] mul_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [63:0] \mul_op__imm_data__data$4$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \mul_op__imm_data__data$47 ;
+ wire [63:0] \mul_op__imm_data__data$49 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__imm_data__ok$48 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \mul_op__imm_data__ok$5 ;
reg \mul_op__imm_data__ok$5 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \mul_op__imm_data__ok$5$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire \mul_op__imm_data__ok$50 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] mul_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output [31:0] \mul_op__insn$13 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [31:0] \mul_op__insn$13$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \mul_op__insn$56 ;
+ wire [31:0] \mul_op__insn$58 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \mul_op__insn_type$45 ;
+ wire [6:0] \mul_op__insn_type$47 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \mul_op__is_32bit$11$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__is_32bit$54 ;
+ wire \mul_op__is_32bit$56 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \mul_op__is_signed$12$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__is_signed$55 ;
+ wire \mul_op__is_signed$57 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__oe__oe$51 ;
+ wire \mul_op__oe__oe$53 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \mul_op__oe__oe$8 ;
reg \mul_op__oe__oe$8 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__oe__ok$52 ;
+ wire \mul_op__oe__ok$54 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \mul_op__oe__ok$9 ;
reg \mul_op__oe__ok$9 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__rc__ok$50 ;
+ wire \mul_op__rc__ok$52 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \mul_op__rc__ok$7 ;
reg \mul_op__rc__ok$7 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__rc__rc$49 ;
+ wire \mul_op__rc__rc$51 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \mul_op__rc__rc$6 ;
reg \mul_op__rc__rc$6 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \mul_op__rc__rc$6$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] mul_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \mul_op__sv_ldstmode$17 ;
+ reg [1:0] \mul_op__sv_ldstmode$17 = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \mul_op__sv_ldstmode$17$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \mul_op__sv_ldstmode$62 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \mul_op__sv_pred_dz$15$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__sv_pred_dz$58 ;
+ wire \mul_op__sv_pred_dz$60 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \mul_op__sv_pred_sz$14$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__sv_pred_sz$57 ;
+ wire \mul_op__sv_pred_sz$59 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \mul_op__sv_saturate$59 ;
+ wire [1:0] \mul_op__sv_saturate$61 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \mul_op__write_cr0$10$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__write_cr0$53 ;
+ wire \mul_op__write_cr0$55 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
input [1:0] muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
reg [1:0] \muxid$1$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \muxid$44 ;
+ wire [1:0] \muxid$46 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
wire n_i_rdy_data;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *)
input neg_res;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *)
- output \neg_res$19 ;
- reg \neg_res$19 = 1'h0;
+ output \neg_res$20 ;
+ reg \neg_res$20 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *)
- reg \neg_res$19$next ;
+ reg \neg_res$20$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *)
- wire \neg_res$63 ;
+ wire \neg_res$66 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *)
input neg_res32;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *)
- output \neg_res32$20 ;
- reg \neg_res32$20 = 1'h0;
+ output \neg_res32$21 ;
+ reg \neg_res32$21 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *)
- reg \neg_res32$20$next ;
+ reg \neg_res32$21$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *)
- wire \neg_res32$64 ;
+ wire \neg_res32$67 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
output [128:0] o;
reg [128:0] o = 129'h000000000000000000000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [128:0] \o$61 ;
+ wire [128:0] \o$64 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
reg [128:0] \o$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
input p_valid_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
- wire \p_valid_i$41 ;
+ wire \p_valid_i$43 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
wire p_valid_i_p_ready_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input xer_so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output \xer_so$18 ;
- reg \xer_so$18 = 1'h0;
+ output \xer_so$19 ;
+ reg \xer_so$19 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- reg \xer_so$18$next ;
+ reg \xer_so$19$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire \xer_so$62 ;
- assign \$42 = \p_valid_i$41 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
+ wire \xer_so$65 ;
+ assign \$44 = \p_valid_i$43 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
always @(posedge coresync_clk)
- \neg_res32$20 <= \neg_res32$20$next ;
+ \neg_res32$21 <= \neg_res32$21$next ;
always @(posedge coresync_clk)
- \neg_res$19 <= \neg_res$19$next ;
+ \neg_res$20 <= \neg_res$20$next ;
always @(posedge coresync_clk)
- \xer_so$18 <= \xer_so$18$next ;
+ \xer_so$19 <= \xer_so$19$next ;
always @(posedge coresync_clk)
o <= \o$next ;
always @(posedge coresync_clk)
always @(posedge coresync_clk)
\mul_op__sv_saturate$16 <= \mul_op__sv_saturate$16$next ;
always @(posedge coresync_clk)
- \mul_op__SV_Ptype$17 <= \mul_op__SV_Ptype$17$next ;
+ \mul_op__sv_ldstmode$17 <= \mul_op__sv_ldstmode$17$next ;
+ always @(posedge coresync_clk)
+ \mul_op__SV_Ptype$18 <= \mul_op__SV_Ptype$18$next ;
always @(posedge coresync_clk)
\muxid$1 <= \muxid$1$next ;
always @(posedge coresync_clk)
r_busy <= \r_busy$next ;
mul2 mul2 (
.mul_op__SV_Ptype(mul2_mul_op__SV_Ptype),
- .\mul_op__SV_Ptype$17 (\mul2_mul_op__SV_Ptype$37 ),
+ .\mul_op__SV_Ptype$18 (\mul2_mul_op__SV_Ptype$39 ),
.mul_op__fn_unit(mul2_mul_op__fn_unit),
- .\mul_op__fn_unit$3 (\mul2_mul_op__fn_unit$23 ),
+ .\mul_op__fn_unit$3 (\mul2_mul_op__fn_unit$24 ),
.mul_op__imm_data__data(mul2_mul_op__imm_data__data),
- .\mul_op__imm_data__data$4 (\mul2_mul_op__imm_data__data$24 ),
+ .\mul_op__imm_data__data$4 (\mul2_mul_op__imm_data__data$25 ),
.mul_op__imm_data__ok(mul2_mul_op__imm_data__ok),
- .\mul_op__imm_data__ok$5 (\mul2_mul_op__imm_data__ok$25 ),
+ .\mul_op__imm_data__ok$5 (\mul2_mul_op__imm_data__ok$26 ),
.mul_op__insn(mul2_mul_op__insn),
- .\mul_op__insn$13 (\mul2_mul_op__insn$33 ),
+ .\mul_op__insn$13 (\mul2_mul_op__insn$34 ),
.mul_op__insn_type(mul2_mul_op__insn_type),
- .\mul_op__insn_type$2 (\mul2_mul_op__insn_type$22 ),
+ .\mul_op__insn_type$2 (\mul2_mul_op__insn_type$23 ),
.mul_op__is_32bit(mul2_mul_op__is_32bit),
- .\mul_op__is_32bit$11 (\mul2_mul_op__is_32bit$31 ),
+ .\mul_op__is_32bit$11 (\mul2_mul_op__is_32bit$32 ),
.mul_op__is_signed(mul2_mul_op__is_signed),
- .\mul_op__is_signed$12 (\mul2_mul_op__is_signed$32 ),
+ .\mul_op__is_signed$12 (\mul2_mul_op__is_signed$33 ),
.mul_op__oe__oe(mul2_mul_op__oe__oe),
- .\mul_op__oe__oe$8 (\mul2_mul_op__oe__oe$28 ),
+ .\mul_op__oe__oe$8 (\mul2_mul_op__oe__oe$29 ),
.mul_op__oe__ok(mul2_mul_op__oe__ok),
- .\mul_op__oe__ok$9 (\mul2_mul_op__oe__ok$29 ),
+ .\mul_op__oe__ok$9 (\mul2_mul_op__oe__ok$30 ),
.mul_op__rc__ok(mul2_mul_op__rc__ok),
- .\mul_op__rc__ok$7 (\mul2_mul_op__rc__ok$27 ),
+ .\mul_op__rc__ok$7 (\mul2_mul_op__rc__ok$28 ),
.mul_op__rc__rc(mul2_mul_op__rc__rc),
- .\mul_op__rc__rc$6 (\mul2_mul_op__rc__rc$26 ),
+ .\mul_op__rc__rc$6 (\mul2_mul_op__rc__rc$27 ),
+ .mul_op__sv_ldstmode(mul2_mul_op__sv_ldstmode),
+ .\mul_op__sv_ldstmode$17 (\mul2_mul_op__sv_ldstmode$38 ),
.mul_op__sv_pred_dz(mul2_mul_op__sv_pred_dz),
- .\mul_op__sv_pred_dz$15 (\mul2_mul_op__sv_pred_dz$35 ),
+ .\mul_op__sv_pred_dz$15 (\mul2_mul_op__sv_pred_dz$36 ),
.mul_op__sv_pred_sz(mul2_mul_op__sv_pred_sz),
- .\mul_op__sv_pred_sz$14 (\mul2_mul_op__sv_pred_sz$34 ),
+ .\mul_op__sv_pred_sz$14 (\mul2_mul_op__sv_pred_sz$35 ),
.mul_op__sv_saturate(mul2_mul_op__sv_saturate),
- .\mul_op__sv_saturate$16 (\mul2_mul_op__sv_saturate$36 ),
+ .\mul_op__sv_saturate$16 (\mul2_mul_op__sv_saturate$37 ),
.mul_op__write_cr0(mul2_mul_op__write_cr0),
- .\mul_op__write_cr0$10 (\mul2_mul_op__write_cr0$30 ),
+ .\mul_op__write_cr0$10 (\mul2_mul_op__write_cr0$31 ),
.muxid(mul2_muxid),
- .\muxid$1 (\mul2_muxid$21 ),
+ .\muxid$1 (\mul2_muxid$22 ),
.neg_res(mul2_neg_res),
- .\neg_res$19 (\mul2_neg_res$39 ),
+ .\neg_res$20 (\mul2_neg_res$41 ),
.neg_res32(mul2_neg_res32),
- .\neg_res32$20 (\mul2_neg_res32$40 ),
+ .\neg_res32$21 (\mul2_neg_res32$42 ),
.o(mul2_o),
.ra(mul2_ra),
.rb(mul2_rb),
.xer_so(mul2_xer_so),
- .\xer_so$18 (\mul2_xer_so$38 )
+ .\xer_so$19 (\mul2_xer_so$40 )
);
\n$97 n (
.n_ready_i(n_ready_i),
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \muxid$1$next = \muxid$44 ;
+ \muxid$1$next = \muxid$46 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \muxid$1$next = \muxid$44 ;
+ \muxid$1$next = \muxid$46 ;
endcase
end
always @* begin
\mul_op__sv_pred_sz$14$next = \mul_op__sv_pred_sz$14 ;
\mul_op__sv_pred_dz$15$next = \mul_op__sv_pred_dz$15 ;
\mul_op__sv_saturate$16$next = \mul_op__sv_saturate$16 ;
- \mul_op__SV_Ptype$17$next = \mul_op__SV_Ptype$17 ;
+ \mul_op__sv_ldstmode$17$next = \mul_op__sv_ldstmode$17 ;
+ \mul_op__SV_Ptype$18$next = \mul_op__SV_Ptype$18 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \mul_op__SV_Ptype$17$next , \mul_op__sv_saturate$16$next , \mul_op__sv_pred_dz$15$next , \mul_op__sv_pred_sz$14$next , \mul_op__insn$13$next , \mul_op__is_signed$12$next , \mul_op__is_32bit$11$next , \mul_op__write_cr0$10$next , \mul_op__oe__ok$9$next , \mul_op__oe__oe$8$next , \mul_op__rc__ok$7$next , \mul_op__rc__rc$6$next , \mul_op__imm_data__ok$5$next , \mul_op__imm_data__data$4$next , \mul_op__fn_unit$3$next , \mul_op__insn_type$2$next } = { \mul_op__SV_Ptype$60 , \mul_op__sv_saturate$59 , \mul_op__sv_pred_dz$58 , \mul_op__sv_pred_sz$57 , \mul_op__insn$56 , \mul_op__is_signed$55 , \mul_op__is_32bit$54 , \mul_op__write_cr0$53 , \mul_op__oe__ok$52 , \mul_op__oe__oe$51 , \mul_op__rc__ok$50 , \mul_op__rc__rc$49 , \mul_op__imm_data__ok$48 , \mul_op__imm_data__data$47 , \mul_op__fn_unit$46 , \mul_op__insn_type$45 };
+ { \mul_op__SV_Ptype$18$next , \mul_op__sv_ldstmode$17$next , \mul_op__sv_saturate$16$next , \mul_op__sv_pred_dz$15$next , \mul_op__sv_pred_sz$14$next , \mul_op__insn$13$next , \mul_op__is_signed$12$next , \mul_op__is_32bit$11$next , \mul_op__write_cr0$10$next , \mul_op__oe__ok$9$next , \mul_op__oe__oe$8$next , \mul_op__rc__ok$7$next , \mul_op__rc__rc$6$next , \mul_op__imm_data__ok$5$next , \mul_op__imm_data__data$4$next , \mul_op__fn_unit$3$next , \mul_op__insn_type$2$next } = { \mul_op__SV_Ptype$63 , \mul_op__sv_ldstmode$62 , \mul_op__sv_saturate$61 , \mul_op__sv_pred_dz$60 , \mul_op__sv_pred_sz$59 , \mul_op__insn$58 , \mul_op__is_signed$57 , \mul_op__is_32bit$56 , \mul_op__write_cr0$55 , \mul_op__oe__ok$54 , \mul_op__oe__oe$53 , \mul_op__rc__ok$52 , \mul_op__rc__rc$51 , \mul_op__imm_data__ok$50 , \mul_op__imm_data__data$49 , \mul_op__fn_unit$48 , \mul_op__insn_type$47 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \mul_op__SV_Ptype$17$next , \mul_op__sv_saturate$16$next , \mul_op__sv_pred_dz$15$next , \mul_op__sv_pred_sz$14$next , \mul_op__insn$13$next , \mul_op__is_signed$12$next , \mul_op__is_32bit$11$next , \mul_op__write_cr0$10$next , \mul_op__oe__ok$9$next , \mul_op__oe__oe$8$next , \mul_op__rc__ok$7$next , \mul_op__rc__rc$6$next , \mul_op__imm_data__ok$5$next , \mul_op__imm_data__data$4$next , \mul_op__fn_unit$3$next , \mul_op__insn_type$2$next } = { \mul_op__SV_Ptype$60 , \mul_op__sv_saturate$59 , \mul_op__sv_pred_dz$58 , \mul_op__sv_pred_sz$57 , \mul_op__insn$56 , \mul_op__is_signed$55 , \mul_op__is_32bit$54 , \mul_op__write_cr0$53 , \mul_op__oe__ok$52 , \mul_op__oe__oe$51 , \mul_op__rc__ok$50 , \mul_op__rc__rc$49 , \mul_op__imm_data__ok$48 , \mul_op__imm_data__data$47 , \mul_op__fn_unit$46 , \mul_op__insn_type$45 };
+ { \mul_op__SV_Ptype$18$next , \mul_op__sv_ldstmode$17$next , \mul_op__sv_saturate$16$next , \mul_op__sv_pred_dz$15$next , \mul_op__sv_pred_sz$14$next , \mul_op__insn$13$next , \mul_op__is_signed$12$next , \mul_op__is_32bit$11$next , \mul_op__write_cr0$10$next , \mul_op__oe__ok$9$next , \mul_op__oe__oe$8$next , \mul_op__rc__ok$7$next , \mul_op__rc__rc$6$next , \mul_op__imm_data__ok$5$next , \mul_op__imm_data__data$4$next , \mul_op__fn_unit$3$next , \mul_op__insn_type$2$next } = { \mul_op__SV_Ptype$63 , \mul_op__sv_ldstmode$62 , \mul_op__sv_saturate$61 , \mul_op__sv_pred_dz$60 , \mul_op__sv_pred_sz$59 , \mul_op__insn$58 , \mul_op__is_signed$57 , \mul_op__is_32bit$56 , \mul_op__write_cr0$55 , \mul_op__oe__ok$54 , \mul_op__oe__oe$53 , \mul_op__rc__ok$52 , \mul_op__rc__rc$51 , \mul_op__imm_data__ok$50 , \mul_op__imm_data__data$49 , \mul_op__fn_unit$48 , \mul_op__insn_type$47 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \o$next = \o$61 ;
+ \o$next = \o$64 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \o$next = \o$61 ;
+ \o$next = \o$64 ;
endcase
end
always @* begin
if (\initial ) begin end
- \xer_so$18$next = \xer_so$18 ;
+ \xer_so$19$next = \xer_so$19 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \xer_so$18$next = \xer_so$62 ;
+ \xer_so$19$next = \xer_so$65 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \xer_so$18$next = \xer_so$62 ;
+ \xer_so$19$next = \xer_so$65 ;
endcase
end
always @* begin
if (\initial ) begin end
- \neg_res$19$next = \neg_res$19 ;
+ \neg_res$20$next = \neg_res$20 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \neg_res$19$next = \neg_res$63 ;
+ \neg_res$20$next = \neg_res$66 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \neg_res$19$next = \neg_res$63 ;
+ \neg_res$20$next = \neg_res$66 ;
endcase
end
always @* begin
if (\initial ) begin end
- \neg_res32$20$next = \neg_res32$20 ;
+ \neg_res32$21$next = \neg_res32$21 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \neg_res32$20$next = \neg_res32$64 ;
+ \neg_res32$21$next = \neg_res32$67 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \neg_res32$20$next = \neg_res32$64 ;
+ \neg_res32$21$next = \neg_res32$67 ;
endcase
end
assign p_ready_o = n_i_rdy_data;
assign n_valid_o = r_busy;
- assign \neg_res32$64 = \mul2_neg_res32$40 ;
- assign \neg_res$63 = \mul2_neg_res$39 ;
- assign \xer_so$62 = \mul2_xer_so$38 ;
- assign \o$61 = mul2_o;
- assign { \mul_op__SV_Ptype$60 , \mul_op__sv_saturate$59 , \mul_op__sv_pred_dz$58 , \mul_op__sv_pred_sz$57 , \mul_op__insn$56 , \mul_op__is_signed$55 , \mul_op__is_32bit$54 , \mul_op__write_cr0$53 , \mul_op__oe__ok$52 , \mul_op__oe__oe$51 , \mul_op__rc__ok$50 , \mul_op__rc__rc$49 , \mul_op__imm_data__ok$48 , \mul_op__imm_data__data$47 , \mul_op__fn_unit$46 , \mul_op__insn_type$45 } = { \mul2_mul_op__SV_Ptype$37 , \mul2_mul_op__sv_saturate$36 , \mul2_mul_op__sv_pred_dz$35 , \mul2_mul_op__sv_pred_sz$34 , \mul2_mul_op__insn$33 , \mul2_mul_op__is_signed$32 , \mul2_mul_op__is_32bit$31 , \mul2_mul_op__write_cr0$30 , \mul2_mul_op__oe__ok$29 , \mul2_mul_op__oe__oe$28 , \mul2_mul_op__rc__ok$27 , \mul2_mul_op__rc__rc$26 , \mul2_mul_op__imm_data__ok$25 , \mul2_mul_op__imm_data__data$24 , \mul2_mul_op__fn_unit$23 , \mul2_mul_op__insn_type$22 };
- assign \muxid$44 = \mul2_muxid$21 ;
- assign p_valid_i_p_ready_o = \$42 ;
+ assign \neg_res32$67 = \mul2_neg_res32$42 ;
+ assign \neg_res$66 = \mul2_neg_res$41 ;
+ assign \xer_so$65 = \mul2_xer_so$40 ;
+ assign \o$64 = mul2_o;
+ assign { \mul_op__SV_Ptype$63 , \mul_op__sv_ldstmode$62 , \mul_op__sv_saturate$61 , \mul_op__sv_pred_dz$60 , \mul_op__sv_pred_sz$59 , \mul_op__insn$58 , \mul_op__is_signed$57 , \mul_op__is_32bit$56 , \mul_op__write_cr0$55 , \mul_op__oe__ok$54 , \mul_op__oe__oe$53 , \mul_op__rc__ok$52 , \mul_op__rc__rc$51 , \mul_op__imm_data__ok$50 , \mul_op__imm_data__data$49 , \mul_op__fn_unit$48 , \mul_op__insn_type$47 } = { \mul2_mul_op__SV_Ptype$39 , \mul2_mul_op__sv_ldstmode$38 , \mul2_mul_op__sv_saturate$37 , \mul2_mul_op__sv_pred_dz$36 , \mul2_mul_op__sv_pred_sz$35 , \mul2_mul_op__insn$34 , \mul2_mul_op__is_signed$33 , \mul2_mul_op__is_32bit$32 , \mul2_mul_op__write_cr0$31 , \mul2_mul_op__oe__ok$30 , \mul2_mul_op__oe__oe$29 , \mul2_mul_op__rc__ok$28 , \mul2_mul_op__rc__rc$27 , \mul2_mul_op__imm_data__ok$26 , \mul2_mul_op__imm_data__data$25 , \mul2_mul_op__fn_unit$24 , \mul2_mul_op__insn_type$23 };
+ assign \muxid$46 = \mul2_muxid$22 ;
+ assign p_valid_i_p_ready_o = \$44 ;
assign n_i_rdy_data = n_ready_i;
- assign \p_valid_i$41 = p_valid_i;
+ assign \p_valid_i$43 = p_valid_i;
assign mul2_neg_res32 = neg_res32;
assign mul2_neg_res = neg_res;
assign mul2_xer_so = xer_so;
assign mul2_rb = rb;
assign mul2_ra = ra;
- assign { mul2_mul_op__SV_Ptype, mul2_mul_op__sv_saturate, mul2_mul_op__sv_pred_dz, mul2_mul_op__sv_pred_sz, mul2_mul_op__insn, mul2_mul_op__is_signed, mul2_mul_op__is_32bit, mul2_mul_op__write_cr0, mul2_mul_op__oe__ok, mul2_mul_op__oe__oe, mul2_mul_op__rc__ok, mul2_mul_op__rc__rc, mul2_mul_op__imm_data__ok, mul2_mul_op__imm_data__data, mul2_mul_op__fn_unit, mul2_mul_op__insn_type } = { mul_op__SV_Ptype, mul_op__sv_saturate, mul_op__sv_pred_dz, mul_op__sv_pred_sz, mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type };
+ assign { mul2_mul_op__SV_Ptype, mul2_mul_op__sv_ldstmode, mul2_mul_op__sv_saturate, mul2_mul_op__sv_pred_dz, mul2_mul_op__sv_pred_sz, mul2_mul_op__insn, mul2_mul_op__is_signed, mul2_mul_op__is_32bit, mul2_mul_op__write_cr0, mul2_mul_op__oe__ok, mul2_mul_op__oe__oe, mul2_mul_op__rc__ok, mul2_mul_op__rc__rc, mul2_mul_op__imm_data__ok, mul2_mul_op__imm_data__data, mul2_mul_op__fn_unit, mul2_mul_op__insn_type } = { mul_op__SV_Ptype, mul_op__sv_ldstmode, mul_op__sv_saturate, mul_op__sv_pred_dz, mul_op__sv_pred_sz, mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type };
assign mul2_muxid = muxid;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3" *)
(* generator = "nMigen" *)
-module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__SV_Ptype, o, xer_so, neg_res, neg_res32, n_valid_o, n_ready_i, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \mul_op__sv_pred_sz$14 , \mul_op__sv_pred_dz$15 , \mul_op__sv_saturate$16 , \mul_op__SV_Ptype$17 , \o$18 , o_ok, cr_a, cr_a_ok, xer_ov, xer_ov_ok, \xer_so$19 , xer_so_ok, coresync_clk);
+module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__sv_ldstmode, mul_op__SV_Ptype, o, xer_so, neg_res, neg_res32, n_valid_o, n_ready_i, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \mul_op__sv_pred_sz$14 , \mul_op__sv_pred_dz$15 , \mul_op__sv_saturate$16 , \mul_op__sv_ldstmode$17 , \mul_op__SV_Ptype$18 , \o$19 , o_ok, cr_a, cr_a_ok, xer_ov, xer_ov_ok, \xer_so$20 , xer_so_ok, coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
- wire \$68 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ wire \$71 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output [3:0] cr_a;
reg [3:0] cr_a = 4'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [3:0] \cr_a$63 ;
+ wire [3:0] \cr_a$66 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [3:0] \cr_a$89 ;
+ wire [3:0] \cr_a$93 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg [3:0] \cr_a$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output cr_a_ok;
reg cr_a_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \cr_a_ok$62 ;
+ wire \cr_a_ok$65 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \cr_a_ok$64 ;
+ wire \cr_a_ok$67 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \cr_a_ok$90 ;
+ wire \cr_a_ok$94 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \cr_a_ok$next ;
(* enum_base_type = "SVPtype" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \mul3_mul_op__SV_Ptype$36 ;
+ wire [1:0] \mul3_mul_op__SV_Ptype$38 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \mul3_mul_op__fn_unit$22 ;
+ wire [14:0] \mul3_mul_op__fn_unit$23 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] mul3_mul_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \mul3_mul_op__imm_data__data$23 ;
+ wire [63:0] \mul3_mul_op__imm_data__data$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul3_mul_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul3_mul_op__imm_data__ok$24 ;
+ wire \mul3_mul_op__imm_data__ok$25 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] mul3_mul_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \mul3_mul_op__insn$32 ;
+ wire [31:0] \mul3_mul_op__insn$33 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \mul3_mul_op__insn_type$21 ;
+ wire [6:0] \mul3_mul_op__insn_type$22 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul3_mul_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul3_mul_op__is_32bit$30 ;
+ wire \mul3_mul_op__is_32bit$31 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul3_mul_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul3_mul_op__is_signed$31 ;
+ wire \mul3_mul_op__is_signed$32 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul3_mul_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul3_mul_op__oe__oe$27 ;
+ wire \mul3_mul_op__oe__oe$28 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul3_mul_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul3_mul_op__oe__ok$28 ;
+ wire \mul3_mul_op__oe__ok$29 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul3_mul_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul3_mul_op__rc__ok$26 ;
+ wire \mul3_mul_op__rc__ok$27 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul3_mul_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul3_mul_op__rc__rc$25 ;
+ wire \mul3_mul_op__rc__rc$26 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] mul3_mul_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \mul3_mul_op__sv_ldstmode$37 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul3_mul_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul3_mul_op__sv_pred_dz$34 ;
+ wire \mul3_mul_op__sv_pred_dz$35 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul3_mul_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul3_mul_op__sv_pred_sz$33 ;
+ wire \mul3_mul_op__sv_pred_sz$34 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \mul3_mul_op__sv_saturate$35 ;
+ wire [1:0] \mul3_mul_op__sv_saturate$36 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire mul3_mul_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul3_mul_op__write_cr0$29 ;
+ wire \mul3_mul_op__write_cr0$30 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] mul3_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \mul3_muxid$20 ;
+ wire [1:0] \mul3_muxid$21 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *)
wire mul3_neg_res;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [128:0] mul3_o;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \mul3_o$37 ;
+ wire [63:0] \mul3_o$39 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire mul3_o_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire mul3_xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \mul3_xer_so$38 ;
+ wire \mul3_xer_so$40 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire mul3_xer_so_ok;
(* enum_base_type = "SVPtype" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \mul_op__SV_Ptype$17 ;
- reg [1:0] \mul_op__SV_Ptype$17 = 2'h0;
+ output [1:0] \mul_op__SV_Ptype$18 ;
+ reg [1:0] \mul_op__SV_Ptype$18 = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [1:0] \mul_op__SV_Ptype$17$next ;
+ reg [1:0] \mul_op__SV_Ptype$18$next ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \mul_op__SV_Ptype$86 ;
+ wire [1:0] \mul_op__SV_Ptype$90 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \mul_op__fn_unit$72 ;
+ wire [14:0] \mul_op__fn_unit$75 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] mul_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [63:0] \mul_op__imm_data__data$4$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \mul_op__imm_data__data$73 ;
+ wire [63:0] \mul_op__imm_data__data$76 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \mul_op__imm_data__ok$5$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__imm_data__ok$74 ;
+ wire \mul_op__imm_data__ok$77 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] mul_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [31:0] \mul_op__insn$13$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \mul_op__insn$82 ;
+ wire [31:0] \mul_op__insn$85 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \mul_op__insn_type$71 ;
+ wire [6:0] \mul_op__insn_type$74 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \mul_op__is_32bit$11$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__is_32bit$80 ;
+ wire \mul_op__is_32bit$83 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \mul_op__is_signed$12$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__is_signed$81 ;
+ wire \mul_op__is_signed$84 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__oe__oe$77 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \mul_op__oe__oe$8 ;
reg \mul_op__oe__oe$8 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \mul_op__oe__oe$8$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire \mul_op__oe__oe$80 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__oe__ok$78 ;
+ wire \mul_op__oe__ok$81 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \mul_op__oe__ok$9 ;
reg \mul_op__oe__ok$9 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \mul_op__rc__ok$7$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__rc__ok$76 ;
+ wire \mul_op__rc__ok$79 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \mul_op__rc__rc$6$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__rc__rc$75 ;
+ wire \mul_op__rc__rc$78 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] mul_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \mul_op__sv_ldstmode$17 ;
+ reg [1:0] \mul_op__sv_ldstmode$17 = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \mul_op__sv_ldstmode$17$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \mul_op__sv_ldstmode$89 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \mul_op__sv_pred_dz$15$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__sv_pred_dz$84 ;
+ wire \mul_op__sv_pred_dz$87 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \mul_op__sv_pred_sz$14$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__sv_pred_sz$83 ;
+ wire \mul_op__sv_pred_sz$86 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \mul_op__sv_saturate$85 ;
+ wire [1:0] \mul_op__sv_saturate$88 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \mul_op__write_cr0$10$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \mul_op__write_cr0$79 ;
+ wire \mul_op__write_cr0$82 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
input [1:0] muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
reg [1:0] \muxid$1$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \muxid$70 ;
+ wire [1:0] \muxid$73 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
wire n_i_rdy_data;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *)
input neg_res32;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *)
- wire \neg_res32$61 ;
+ wire \neg_res32$64 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [128:0] o;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [63:0] \o$18 ;
- reg [63:0] \o$18 = 64'h0000000000000000;
+ output [63:0] \o$19 ;
+ reg [63:0] \o$19 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg [63:0] \o$18$next ;
+ reg [63:0] \o$19$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \o$87 ;
+ wire [63:0] \o$91 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output o_ok;
reg o_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \o_ok$88 ;
+ wire \o_ok$92 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \o_ok$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [3:0] output_cr_a;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [3:0] \output_cr_a$58 ;
+ wire [3:0] \output_cr_a$61 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire output_cr_a_ok;
(* enum_base_type = "SVPtype" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \output_mul_op__SV_Ptype$55 ;
+ wire [1:0] \output_mul_op__SV_Ptype$58 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \output_mul_op__fn_unit$41 ;
+ wire [14:0] \output_mul_op__fn_unit$43 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] output_mul_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \output_mul_op__imm_data__data$42 ;
+ wire [63:0] \output_mul_op__imm_data__data$44 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_mul_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_mul_op__imm_data__ok$43 ;
+ wire \output_mul_op__imm_data__ok$45 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] output_mul_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \output_mul_op__insn$51 ;
+ wire [31:0] \output_mul_op__insn$53 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \output_mul_op__insn_type$40 ;
+ wire [6:0] \output_mul_op__insn_type$42 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_mul_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_mul_op__is_32bit$49 ;
+ wire \output_mul_op__is_32bit$51 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_mul_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_mul_op__is_signed$50 ;
+ wire \output_mul_op__is_signed$52 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_mul_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_mul_op__oe__oe$46 ;
+ wire \output_mul_op__oe__oe$48 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_mul_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_mul_op__oe__ok$47 ;
+ wire \output_mul_op__oe__ok$49 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_mul_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_mul_op__rc__ok$45 ;
+ wire \output_mul_op__rc__ok$47 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_mul_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_mul_op__rc__rc$44 ;
+ wire \output_mul_op__rc__rc$46 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] output_mul_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \output_mul_op__sv_ldstmode$57 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_mul_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_mul_op__sv_pred_dz$53 ;
+ wire \output_mul_op__sv_pred_dz$55 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_mul_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_mul_op__sv_pred_sz$52 ;
+ wire \output_mul_op__sv_pred_sz$54 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \output_mul_op__sv_saturate$54 ;
+ wire [1:0] \output_mul_op__sv_saturate$56 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_mul_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_mul_op__write_cr0$48 ;
+ wire \output_mul_op__write_cr0$50 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] output_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \output_muxid$39 ;
+ wire [1:0] \output_muxid$41 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [63:0] output_o;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \output_o$56 ;
+ wire [63:0] \output_o$59 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire output_o_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \output_o_ok$57 ;
+ wire \output_o_ok$60 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [1:0] output_xer_ov;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [1:0] \output_xer_ov$59 ;
+ wire [1:0] \output_xer_ov$62 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire output_xer_ov_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire output_xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \output_xer_so$60 ;
+ wire \output_xer_so$63 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire output_xer_so_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
input p_valid_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
- wire \p_valid_i$67 ;
+ wire \p_valid_i$70 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
wire p_valid_i_p_ready_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
output [1:0] xer_ov;
reg [1:0] xer_ov = 2'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [1:0] \xer_ov$91 ;
+ wire [1:0] \xer_ov$95 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg [1:0] \xer_ov$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_ov_ok;
reg xer_ov_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_ov_ok$65 ;
+ wire \xer_ov_ok$68 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_ov_ok$92 ;
+ wire \xer_ov_ok$96 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \xer_ov_ok$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \xer_so$19 ;
- reg \xer_so$19 = 1'h0;
+ output \xer_so$20 ;
+ reg \xer_so$20 = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg \xer_so$19$next ;
+ reg \xer_so$20$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_so$93 ;
+ wire \xer_so$97 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_so_ok;
reg xer_so_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_so_ok$66 ;
+ wire \xer_so_ok$69 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_so_ok$94 ;
+ wire \xer_so_ok$98 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \xer_so_ok$next ;
- assign \$68 = \p_valid_i$67 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
+ assign \$71 = \p_valid_i$70 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
always @(posedge coresync_clk)
- \xer_so$19 <= \xer_so$19$next ;
+ \xer_so$20 <= \xer_so$20$next ;
always @(posedge coresync_clk)
xer_so_ok <= \xer_so_ok$next ;
always @(posedge coresync_clk)
always @(posedge coresync_clk)
cr_a_ok <= \cr_a_ok$next ;
always @(posedge coresync_clk)
- \o$18 <= \o$18$next ;
+ \o$19 <= \o$19$next ;
always @(posedge coresync_clk)
o_ok <= \o_ok$next ;
always @(posedge coresync_clk)
always @(posedge coresync_clk)
\mul_op__sv_saturate$16 <= \mul_op__sv_saturate$16$next ;
always @(posedge coresync_clk)
- \mul_op__SV_Ptype$17 <= \mul_op__SV_Ptype$17$next ;
+ \mul_op__sv_ldstmode$17 <= \mul_op__sv_ldstmode$17$next ;
+ always @(posedge coresync_clk)
+ \mul_op__SV_Ptype$18 <= \mul_op__SV_Ptype$18$next ;
always @(posedge coresync_clk)
\muxid$1 <= \muxid$1$next ;
always @(posedge coresync_clk)
r_busy <= \r_busy$next ;
mul3 mul3 (
.mul_op__SV_Ptype(mul3_mul_op__SV_Ptype),
- .\mul_op__SV_Ptype$17 (\mul3_mul_op__SV_Ptype$36 ),
+ .\mul_op__SV_Ptype$18 (\mul3_mul_op__SV_Ptype$38 ),
.mul_op__fn_unit(mul3_mul_op__fn_unit),
- .\mul_op__fn_unit$3 (\mul3_mul_op__fn_unit$22 ),
+ .\mul_op__fn_unit$3 (\mul3_mul_op__fn_unit$23 ),
.mul_op__imm_data__data(mul3_mul_op__imm_data__data),
- .\mul_op__imm_data__data$4 (\mul3_mul_op__imm_data__data$23 ),
+ .\mul_op__imm_data__data$4 (\mul3_mul_op__imm_data__data$24 ),
.mul_op__imm_data__ok(mul3_mul_op__imm_data__ok),
- .\mul_op__imm_data__ok$5 (\mul3_mul_op__imm_data__ok$24 ),
+ .\mul_op__imm_data__ok$5 (\mul3_mul_op__imm_data__ok$25 ),
.mul_op__insn(mul3_mul_op__insn),
- .\mul_op__insn$13 (\mul3_mul_op__insn$32 ),
+ .\mul_op__insn$13 (\mul3_mul_op__insn$33 ),
.mul_op__insn_type(mul3_mul_op__insn_type),
- .\mul_op__insn_type$2 (\mul3_mul_op__insn_type$21 ),
+ .\mul_op__insn_type$2 (\mul3_mul_op__insn_type$22 ),
.mul_op__is_32bit(mul3_mul_op__is_32bit),
- .\mul_op__is_32bit$11 (\mul3_mul_op__is_32bit$30 ),
+ .\mul_op__is_32bit$11 (\mul3_mul_op__is_32bit$31 ),
.mul_op__is_signed(mul3_mul_op__is_signed),
- .\mul_op__is_signed$12 (\mul3_mul_op__is_signed$31 ),
+ .\mul_op__is_signed$12 (\mul3_mul_op__is_signed$32 ),
.mul_op__oe__oe(mul3_mul_op__oe__oe),
- .\mul_op__oe__oe$8 (\mul3_mul_op__oe__oe$27 ),
+ .\mul_op__oe__oe$8 (\mul3_mul_op__oe__oe$28 ),
.mul_op__oe__ok(mul3_mul_op__oe__ok),
- .\mul_op__oe__ok$9 (\mul3_mul_op__oe__ok$28 ),
+ .\mul_op__oe__ok$9 (\mul3_mul_op__oe__ok$29 ),
.mul_op__rc__ok(mul3_mul_op__rc__ok),
- .\mul_op__rc__ok$7 (\mul3_mul_op__rc__ok$26 ),
+ .\mul_op__rc__ok$7 (\mul3_mul_op__rc__ok$27 ),
.mul_op__rc__rc(mul3_mul_op__rc__rc),
- .\mul_op__rc__rc$6 (\mul3_mul_op__rc__rc$25 ),
+ .\mul_op__rc__rc$6 (\mul3_mul_op__rc__rc$26 ),
+ .mul_op__sv_ldstmode(mul3_mul_op__sv_ldstmode),
+ .\mul_op__sv_ldstmode$17 (\mul3_mul_op__sv_ldstmode$37 ),
.mul_op__sv_pred_dz(mul3_mul_op__sv_pred_dz),
- .\mul_op__sv_pred_dz$15 (\mul3_mul_op__sv_pred_dz$34 ),
+ .\mul_op__sv_pred_dz$15 (\mul3_mul_op__sv_pred_dz$35 ),
.mul_op__sv_pred_sz(mul3_mul_op__sv_pred_sz),
- .\mul_op__sv_pred_sz$14 (\mul3_mul_op__sv_pred_sz$33 ),
+ .\mul_op__sv_pred_sz$14 (\mul3_mul_op__sv_pred_sz$34 ),
.mul_op__sv_saturate(mul3_mul_op__sv_saturate),
- .\mul_op__sv_saturate$16 (\mul3_mul_op__sv_saturate$35 ),
+ .\mul_op__sv_saturate$16 (\mul3_mul_op__sv_saturate$36 ),
.mul_op__write_cr0(mul3_mul_op__write_cr0),
- .\mul_op__write_cr0$10 (\mul3_mul_op__write_cr0$29 ),
+ .\mul_op__write_cr0$10 (\mul3_mul_op__write_cr0$30 ),
.muxid(mul3_muxid),
- .\muxid$1 (\mul3_muxid$20 ),
+ .\muxid$1 (\mul3_muxid$21 ),
.neg_res(mul3_neg_res),
.o(mul3_o),
- .\o$18 (\mul3_o$37 ),
+ .\o$19 (\mul3_o$39 ),
.o_ok(mul3_o_ok),
.xer_ov(mul3_xer_ov),
.xer_ov_ok(mul3_xer_ov_ok),
.xer_so(mul3_xer_so),
- .\xer_so$19 (\mul3_xer_so$38 ),
+ .\xer_so$20 (\mul3_xer_so$40 ),
.xer_so_ok(mul3_xer_so_ok)
);
\n$99 n (
);
\output$100 \output (
.cr_a(output_cr_a),
- .\cr_a$20 (\output_cr_a$58 ),
+ .\cr_a$21 (\output_cr_a$61 ),
.cr_a_ok(output_cr_a_ok),
.mul_op__SV_Ptype(output_mul_op__SV_Ptype),
- .\mul_op__SV_Ptype$17 (\output_mul_op__SV_Ptype$55 ),
+ .\mul_op__SV_Ptype$18 (\output_mul_op__SV_Ptype$58 ),
.mul_op__fn_unit(output_mul_op__fn_unit),
- .\mul_op__fn_unit$3 (\output_mul_op__fn_unit$41 ),
+ .\mul_op__fn_unit$3 (\output_mul_op__fn_unit$43 ),
.mul_op__imm_data__data(output_mul_op__imm_data__data),
- .\mul_op__imm_data__data$4 (\output_mul_op__imm_data__data$42 ),
+ .\mul_op__imm_data__data$4 (\output_mul_op__imm_data__data$44 ),
.mul_op__imm_data__ok(output_mul_op__imm_data__ok),
- .\mul_op__imm_data__ok$5 (\output_mul_op__imm_data__ok$43 ),
+ .\mul_op__imm_data__ok$5 (\output_mul_op__imm_data__ok$45 ),
.mul_op__insn(output_mul_op__insn),
- .\mul_op__insn$13 (\output_mul_op__insn$51 ),
+ .\mul_op__insn$13 (\output_mul_op__insn$53 ),
.mul_op__insn_type(output_mul_op__insn_type),
- .\mul_op__insn_type$2 (\output_mul_op__insn_type$40 ),
+ .\mul_op__insn_type$2 (\output_mul_op__insn_type$42 ),
.mul_op__is_32bit(output_mul_op__is_32bit),
- .\mul_op__is_32bit$11 (\output_mul_op__is_32bit$49 ),
+ .\mul_op__is_32bit$11 (\output_mul_op__is_32bit$51 ),
.mul_op__is_signed(output_mul_op__is_signed),
- .\mul_op__is_signed$12 (\output_mul_op__is_signed$50 ),
+ .\mul_op__is_signed$12 (\output_mul_op__is_signed$52 ),
.mul_op__oe__oe(output_mul_op__oe__oe),
- .\mul_op__oe__oe$8 (\output_mul_op__oe__oe$46 ),
+ .\mul_op__oe__oe$8 (\output_mul_op__oe__oe$48 ),
.mul_op__oe__ok(output_mul_op__oe__ok),
- .\mul_op__oe__ok$9 (\output_mul_op__oe__ok$47 ),
+ .\mul_op__oe__ok$9 (\output_mul_op__oe__ok$49 ),
.mul_op__rc__ok(output_mul_op__rc__ok),
- .\mul_op__rc__ok$7 (\output_mul_op__rc__ok$45 ),
+ .\mul_op__rc__ok$7 (\output_mul_op__rc__ok$47 ),
.mul_op__rc__rc(output_mul_op__rc__rc),
- .\mul_op__rc__rc$6 (\output_mul_op__rc__rc$44 ),
+ .\mul_op__rc__rc$6 (\output_mul_op__rc__rc$46 ),
+ .mul_op__sv_ldstmode(output_mul_op__sv_ldstmode),
+ .\mul_op__sv_ldstmode$17 (\output_mul_op__sv_ldstmode$57 ),
.mul_op__sv_pred_dz(output_mul_op__sv_pred_dz),
- .\mul_op__sv_pred_dz$15 (\output_mul_op__sv_pred_dz$53 ),
+ .\mul_op__sv_pred_dz$15 (\output_mul_op__sv_pred_dz$55 ),
.mul_op__sv_pred_sz(output_mul_op__sv_pred_sz),
- .\mul_op__sv_pred_sz$14 (\output_mul_op__sv_pred_sz$52 ),
+ .\mul_op__sv_pred_sz$14 (\output_mul_op__sv_pred_sz$54 ),
.mul_op__sv_saturate(output_mul_op__sv_saturate),
- .\mul_op__sv_saturate$16 (\output_mul_op__sv_saturate$54 ),
+ .\mul_op__sv_saturate$16 (\output_mul_op__sv_saturate$56 ),
.mul_op__write_cr0(output_mul_op__write_cr0),
- .\mul_op__write_cr0$10 (\output_mul_op__write_cr0$48 ),
+ .\mul_op__write_cr0$10 (\output_mul_op__write_cr0$50 ),
.muxid(output_muxid),
- .\muxid$1 (\output_muxid$39 ),
+ .\muxid$1 (\output_muxid$41 ),
.o(output_o),
- .\o$18 (\output_o$56 ),
+ .\o$19 (\output_o$59 ),
.o_ok(output_o_ok),
- .\o_ok$19 (\output_o_ok$57 ),
+ .\o_ok$20 (\output_o_ok$60 ),
.xer_ov(output_xer_ov),
- .\xer_ov$21 (\output_xer_ov$59 ),
+ .\xer_ov$22 (\output_xer_ov$62 ),
.xer_ov_ok(output_xer_ov_ok),
.xer_so(output_xer_so),
- .\xer_so$22 (\output_xer_so$60 ),
+ .\xer_so$23 (\output_xer_so$63 ),
.xer_so_ok(output_xer_so_ok)
);
\p$98 p (
.p_ready_o(p_ready_o),
.p_valid_i(p_valid_i)
);
+ always @* begin
+ if (\initial ) begin end
+ \xer_ov$next = xer_ov;
+ \xer_ov_ok$next = xer_ov_ok;
+ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
+ casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
+ /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
+ 2'b?1:
+ { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$96 , \xer_ov$95 };
+ /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
+ 2'b1?:
+ { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$96 , \xer_ov$95 };
+ endcase
+ (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
+ casez (coresync_rst)
+ 1'h1:
+ \xer_ov_ok$next = 1'h0;
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ \xer_so$20$next = \xer_so$20 ;
+ \xer_so_ok$next = xer_so_ok;
+ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
+ casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
+ /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
+ 2'b?1:
+ { \xer_so_ok$next , \xer_so$20$next } = { \xer_so_ok$98 , \xer_so$97 };
+ /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
+ 2'b1?:
+ { \xer_so_ok$next , \xer_so$20$next } = { \xer_so_ok$98 , \xer_so$97 };
+ endcase
+ (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
+ casez (coresync_rst)
+ 1'h1:
+ \xer_so_ok$next = 1'h0;
+ endcase
+ end
always @* begin
if (\initial ) begin end
\r_busy$next = r_busy;
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \muxid$1$next = \muxid$70 ;
+ \muxid$1$next = \muxid$73 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \muxid$1$next = \muxid$70 ;
+ \muxid$1$next = \muxid$73 ;
endcase
end
always @* begin
\mul_op__sv_pred_sz$14$next = \mul_op__sv_pred_sz$14 ;
\mul_op__sv_pred_dz$15$next = \mul_op__sv_pred_dz$15 ;
\mul_op__sv_saturate$16$next = \mul_op__sv_saturate$16 ;
- \mul_op__SV_Ptype$17$next = \mul_op__SV_Ptype$17 ;
+ \mul_op__sv_ldstmode$17$next = \mul_op__sv_ldstmode$17 ;
+ \mul_op__SV_Ptype$18$next = \mul_op__SV_Ptype$18 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \mul_op__SV_Ptype$17$next , \mul_op__sv_saturate$16$next , \mul_op__sv_pred_dz$15$next , \mul_op__sv_pred_sz$14$next , \mul_op__insn$13$next , \mul_op__is_signed$12$next , \mul_op__is_32bit$11$next , \mul_op__write_cr0$10$next , \mul_op__oe__ok$9$next , \mul_op__oe__oe$8$next , \mul_op__rc__ok$7$next , \mul_op__rc__rc$6$next , \mul_op__imm_data__ok$5$next , \mul_op__imm_data__data$4$next , \mul_op__fn_unit$3$next , \mul_op__insn_type$2$next } = { \mul_op__SV_Ptype$86 , \mul_op__sv_saturate$85 , \mul_op__sv_pred_dz$84 , \mul_op__sv_pred_sz$83 , \mul_op__insn$82 , \mul_op__is_signed$81 , \mul_op__is_32bit$80 , \mul_op__write_cr0$79 , \mul_op__oe__ok$78 , \mul_op__oe__oe$77 , \mul_op__rc__ok$76 , \mul_op__rc__rc$75 , \mul_op__imm_data__ok$74 , \mul_op__imm_data__data$73 , \mul_op__fn_unit$72 , \mul_op__insn_type$71 };
+ { \mul_op__SV_Ptype$18$next , \mul_op__sv_ldstmode$17$next , \mul_op__sv_saturate$16$next , \mul_op__sv_pred_dz$15$next , \mul_op__sv_pred_sz$14$next , \mul_op__insn$13$next , \mul_op__is_signed$12$next , \mul_op__is_32bit$11$next , \mul_op__write_cr0$10$next , \mul_op__oe__ok$9$next , \mul_op__oe__oe$8$next , \mul_op__rc__ok$7$next , \mul_op__rc__rc$6$next , \mul_op__imm_data__ok$5$next , \mul_op__imm_data__data$4$next , \mul_op__fn_unit$3$next , \mul_op__insn_type$2$next } = { \mul_op__SV_Ptype$90 , \mul_op__sv_ldstmode$89 , \mul_op__sv_saturate$88 , \mul_op__sv_pred_dz$87 , \mul_op__sv_pred_sz$86 , \mul_op__insn$85 , \mul_op__is_signed$84 , \mul_op__is_32bit$83 , \mul_op__write_cr0$82 , \mul_op__oe__ok$81 , \mul_op__oe__oe$80 , \mul_op__rc__ok$79 , \mul_op__rc__rc$78 , \mul_op__imm_data__ok$77 , \mul_op__imm_data__data$76 , \mul_op__fn_unit$75 , \mul_op__insn_type$74 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \mul_op__SV_Ptype$17$next , \mul_op__sv_saturate$16$next , \mul_op__sv_pred_dz$15$next , \mul_op__sv_pred_sz$14$next , \mul_op__insn$13$next , \mul_op__is_signed$12$next , \mul_op__is_32bit$11$next , \mul_op__write_cr0$10$next , \mul_op__oe__ok$9$next , \mul_op__oe__oe$8$next , \mul_op__rc__ok$7$next , \mul_op__rc__rc$6$next , \mul_op__imm_data__ok$5$next , \mul_op__imm_data__data$4$next , \mul_op__fn_unit$3$next , \mul_op__insn_type$2$next } = { \mul_op__SV_Ptype$86 , \mul_op__sv_saturate$85 , \mul_op__sv_pred_dz$84 , \mul_op__sv_pred_sz$83 , \mul_op__insn$82 , \mul_op__is_signed$81 , \mul_op__is_32bit$80 , \mul_op__write_cr0$79 , \mul_op__oe__ok$78 , \mul_op__oe__oe$77 , \mul_op__rc__ok$76 , \mul_op__rc__rc$75 , \mul_op__imm_data__ok$74 , \mul_op__imm_data__data$73 , \mul_op__fn_unit$72 , \mul_op__insn_type$71 };
+ { \mul_op__SV_Ptype$18$next , \mul_op__sv_ldstmode$17$next , \mul_op__sv_saturate$16$next , \mul_op__sv_pred_dz$15$next , \mul_op__sv_pred_sz$14$next , \mul_op__insn$13$next , \mul_op__is_signed$12$next , \mul_op__is_32bit$11$next , \mul_op__write_cr0$10$next , \mul_op__oe__ok$9$next , \mul_op__oe__oe$8$next , \mul_op__rc__ok$7$next , \mul_op__rc__rc$6$next , \mul_op__imm_data__ok$5$next , \mul_op__imm_data__data$4$next , \mul_op__fn_unit$3$next , \mul_op__insn_type$2$next } = { \mul_op__SV_Ptype$90 , \mul_op__sv_ldstmode$89 , \mul_op__sv_saturate$88 , \mul_op__sv_pred_dz$87 , \mul_op__sv_pred_sz$86 , \mul_op__insn$85 , \mul_op__is_signed$84 , \mul_op__is_32bit$83 , \mul_op__write_cr0$82 , \mul_op__oe__ok$81 , \mul_op__oe__oe$80 , \mul_op__rc__ok$79 , \mul_op__rc__rc$78 , \mul_op__imm_data__ok$77 , \mul_op__imm_data__data$76 , \mul_op__fn_unit$75 , \mul_op__insn_type$74 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
end
always @* begin
if (\initial ) begin end
- \o$18$next = \o$18 ;
+ \o$19$next = \o$19 ;
\o_ok$next = o_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \o_ok$next , \o$18$next } = { \o_ok$88 , \o$87 };
+ { \o_ok$next , \o$19$next } = { \o_ok$92 , \o$91 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \o_ok$next , \o$18$next } = { \o_ok$88 , \o$87 };
+ { \o_ok$next , \o$19$next } = { \o_ok$92 , \o$91 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$90 , \cr_a$89 };
+ { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$94 , \cr_a$93 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$90 , \cr_a$89 };
+ { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$94 , \cr_a$93 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
\cr_a_ok$next = 1'h0;
endcase
end
- always @* begin
- if (\initial ) begin end
- \xer_ov$next = xer_ov;
- \xer_ov_ok$next = xer_ov_ok;
- (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
- casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
- /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
- 2'b?1:
- { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$92 , \xer_ov$91 };
- /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
- 2'b1?:
- { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$92 , \xer_ov$91 };
- endcase
- (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (coresync_rst)
- 1'h1:
- \xer_ov_ok$next = 1'h0;
- endcase
- end
- always @* begin
- if (\initial ) begin end
- \xer_so$19$next = \xer_so$19 ;
- \xer_so_ok$next = xer_so_ok;
- (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
- casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
- /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
- 2'b?1:
- { \xer_so_ok$next , \xer_so$19$next } = { \xer_so_ok$94 , \xer_so$93 };
- /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
- 2'b1?:
- { \xer_so_ok$next , \xer_so$19$next } = { \xer_so_ok$94 , \xer_so$93 };
- endcase
- (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (coresync_rst)
- 1'h1:
- \xer_so_ok$next = 1'h0;
- endcase
- end
- assign \cr_a$63 = 4'h0;
- assign \cr_a_ok$64 = 1'h0;
+ assign \cr_a$66 = 4'h0;
+ assign \cr_a_ok$67 = 1'h0;
assign p_ready_o = n_i_rdy_data;
assign n_valid_o = r_busy;
- assign { \xer_so_ok$94 , \xer_so$93 } = { output_xer_so_ok, \output_xer_so$60 };
- assign { \xer_ov_ok$92 , \xer_ov$91 } = { output_xer_ov_ok, \output_xer_ov$59 };
- assign { \cr_a_ok$90 , \cr_a$89 } = { output_cr_a_ok, \output_cr_a$58 };
- assign { \o_ok$88 , \o$87 } = { \output_o_ok$57 , \output_o$56 };
- assign { \mul_op__SV_Ptype$86 , \mul_op__sv_saturate$85 , \mul_op__sv_pred_dz$84 , \mul_op__sv_pred_sz$83 , \mul_op__insn$82 , \mul_op__is_signed$81 , \mul_op__is_32bit$80 , \mul_op__write_cr0$79 , \mul_op__oe__ok$78 , \mul_op__oe__oe$77 , \mul_op__rc__ok$76 , \mul_op__rc__rc$75 , \mul_op__imm_data__ok$74 , \mul_op__imm_data__data$73 , \mul_op__fn_unit$72 , \mul_op__insn_type$71 } = { \output_mul_op__SV_Ptype$55 , \output_mul_op__sv_saturate$54 , \output_mul_op__sv_pred_dz$53 , \output_mul_op__sv_pred_sz$52 , \output_mul_op__insn$51 , \output_mul_op__is_signed$50 , \output_mul_op__is_32bit$49 , \output_mul_op__write_cr0$48 , \output_mul_op__oe__ok$47 , \output_mul_op__oe__oe$46 , \output_mul_op__rc__ok$45 , \output_mul_op__rc__rc$44 , \output_mul_op__imm_data__ok$43 , \output_mul_op__imm_data__data$42 , \output_mul_op__fn_unit$41 , \output_mul_op__insn_type$40 };
- assign \muxid$70 = \output_muxid$39 ;
- assign p_valid_i_p_ready_o = \$68 ;
+ assign { \xer_so_ok$98 , \xer_so$97 } = { output_xer_so_ok, \output_xer_so$63 };
+ assign { \xer_ov_ok$96 , \xer_ov$95 } = { output_xer_ov_ok, \output_xer_ov$62 };
+ assign { \cr_a_ok$94 , \cr_a$93 } = { output_cr_a_ok, \output_cr_a$61 };
+ assign { \o_ok$92 , \o$91 } = { \output_o_ok$60 , \output_o$59 };
+ assign { \mul_op__SV_Ptype$90 , \mul_op__sv_ldstmode$89 , \mul_op__sv_saturate$88 , \mul_op__sv_pred_dz$87 , \mul_op__sv_pred_sz$86 , \mul_op__insn$85 , \mul_op__is_signed$84 , \mul_op__is_32bit$83 , \mul_op__write_cr0$82 , \mul_op__oe__ok$81 , \mul_op__oe__oe$80 , \mul_op__rc__ok$79 , \mul_op__rc__rc$78 , \mul_op__imm_data__ok$77 , \mul_op__imm_data__data$76 , \mul_op__fn_unit$75 , \mul_op__insn_type$74 } = { \output_mul_op__SV_Ptype$58 , \output_mul_op__sv_ldstmode$57 , \output_mul_op__sv_saturate$56 , \output_mul_op__sv_pred_dz$55 , \output_mul_op__sv_pred_sz$54 , \output_mul_op__insn$53 , \output_mul_op__is_signed$52 , \output_mul_op__is_32bit$51 , \output_mul_op__write_cr0$50 , \output_mul_op__oe__ok$49 , \output_mul_op__oe__oe$48 , \output_mul_op__rc__ok$47 , \output_mul_op__rc__rc$46 , \output_mul_op__imm_data__ok$45 , \output_mul_op__imm_data__data$44 , \output_mul_op__fn_unit$43 , \output_mul_op__insn_type$42 };
+ assign \muxid$73 = \output_muxid$41 ;
+ assign p_valid_i_p_ready_o = \$71 ;
assign n_i_rdy_data = n_ready_i;
- assign \p_valid_i$67 = p_valid_i;
- assign { \xer_so_ok$66 , output_xer_so } = { mul3_xer_so_ok, \mul3_xer_so$38 };
- assign { \xer_ov_ok$65 , output_xer_ov } = { mul3_xer_ov_ok, mul3_xer_ov };
- assign { \cr_a_ok$62 , output_cr_a } = 5'h00;
- assign { output_o_ok, output_o } = { mul3_o_ok, \mul3_o$37 };
- assign { output_mul_op__SV_Ptype, output_mul_op__sv_saturate, output_mul_op__sv_pred_dz, output_mul_op__sv_pred_sz, output_mul_op__insn, output_mul_op__is_signed, output_mul_op__is_32bit, output_mul_op__write_cr0, output_mul_op__oe__ok, output_mul_op__oe__oe, output_mul_op__rc__ok, output_mul_op__rc__rc, output_mul_op__imm_data__ok, output_mul_op__imm_data__data, output_mul_op__fn_unit, output_mul_op__insn_type } = { \mul3_mul_op__SV_Ptype$36 , \mul3_mul_op__sv_saturate$35 , \mul3_mul_op__sv_pred_dz$34 , \mul3_mul_op__sv_pred_sz$33 , \mul3_mul_op__insn$32 , \mul3_mul_op__is_signed$31 , \mul3_mul_op__is_32bit$30 , \mul3_mul_op__write_cr0$29 , \mul3_mul_op__oe__ok$28 , \mul3_mul_op__oe__oe$27 , \mul3_mul_op__rc__ok$26 , \mul3_mul_op__rc__rc$25 , \mul3_mul_op__imm_data__ok$24 , \mul3_mul_op__imm_data__data$23 , \mul3_mul_op__fn_unit$22 , \mul3_mul_op__insn_type$21 };
- assign output_muxid = \mul3_muxid$20 ;
- assign \neg_res32$61 = neg_res32;
+ assign \p_valid_i$70 = p_valid_i;
+ assign { \xer_so_ok$69 , output_xer_so } = { mul3_xer_so_ok, \mul3_xer_so$40 };
+ assign { \xer_ov_ok$68 , output_xer_ov } = { mul3_xer_ov_ok, mul3_xer_ov };
+ assign { \cr_a_ok$65 , output_cr_a } = 5'h00;
+ assign { output_o_ok, output_o } = { mul3_o_ok, \mul3_o$39 };
+ assign { output_mul_op__SV_Ptype, output_mul_op__sv_ldstmode, output_mul_op__sv_saturate, output_mul_op__sv_pred_dz, output_mul_op__sv_pred_sz, output_mul_op__insn, output_mul_op__is_signed, output_mul_op__is_32bit, output_mul_op__write_cr0, output_mul_op__oe__ok, output_mul_op__oe__oe, output_mul_op__rc__ok, output_mul_op__rc__rc, output_mul_op__imm_data__ok, output_mul_op__imm_data__data, output_mul_op__fn_unit, output_mul_op__insn_type } = { \mul3_mul_op__SV_Ptype$38 , \mul3_mul_op__sv_ldstmode$37 , \mul3_mul_op__sv_saturate$36 , \mul3_mul_op__sv_pred_dz$35 , \mul3_mul_op__sv_pred_sz$34 , \mul3_mul_op__insn$33 , \mul3_mul_op__is_signed$32 , \mul3_mul_op__is_32bit$31 , \mul3_mul_op__write_cr0$30 , \mul3_mul_op__oe__ok$29 , \mul3_mul_op__oe__oe$28 , \mul3_mul_op__rc__ok$27 , \mul3_mul_op__rc__rc$26 , \mul3_mul_op__imm_data__ok$25 , \mul3_mul_op__imm_data__data$24 , \mul3_mul_op__fn_unit$23 , \mul3_mul_op__insn_type$22 };
+ assign output_muxid = \mul3_muxid$21 ;
+ assign \neg_res32$64 = neg_res32;
assign mul3_neg_res = neg_res;
assign mul3_xer_so = xer_so;
assign mul3_o = o;
- assign { mul3_mul_op__SV_Ptype, mul3_mul_op__sv_saturate, mul3_mul_op__sv_pred_dz, mul3_mul_op__sv_pred_sz, mul3_mul_op__insn, mul3_mul_op__is_signed, mul3_mul_op__is_32bit, mul3_mul_op__write_cr0, mul3_mul_op__oe__ok, mul3_mul_op__oe__oe, mul3_mul_op__rc__ok, mul3_mul_op__rc__rc, mul3_mul_op__imm_data__ok, mul3_mul_op__imm_data__data, mul3_mul_op__fn_unit, mul3_mul_op__insn_type } = { mul_op__SV_Ptype, mul_op__sv_saturate, mul_op__sv_pred_dz, mul_op__sv_pred_sz, mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type };
+ assign { mul3_mul_op__SV_Ptype, mul3_mul_op__sv_ldstmode, mul3_mul_op__sv_saturate, mul3_mul_op__sv_pred_dz, mul3_mul_op__sv_pred_sz, mul3_mul_op__insn, mul3_mul_op__is_signed, mul3_mul_op__is_32bit, mul3_mul_op__write_cr0, mul3_mul_op__oe__ok, mul3_mul_op__oe__oe, mul3_mul_op__rc__ok, mul3_mul_op__rc__rc, mul3_mul_op__imm_data__ok, mul3_mul_op__imm_data__data, mul3_mul_op__fn_unit, mul3_mul_op__insn_type } = { mul_op__SV_Ptype, mul_op__sv_ldstmode, mul_op__sv_saturate, mul_op__sv_pred_dz, mul_op__sv_pred_sz, mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type };
assign mul3_muxid = muxid;
endmodule
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.output" *)
(* generator = "nMigen" *)
-module \output (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, alu_op__sv_pred_sz, alu_op__sv_pred_dz, alu_op__sv_saturate, alu_op__SV_Ptype, o, o_ok, cr_a, xer_ca, xer_ov, xer_so, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , \alu_op__sv_pred_sz$20 , \alu_op__sv_pred_dz$21 , \alu_op__sv_saturate$22 , \alu_op__SV_Ptype$23 , \o$24 , \o_ok$25 , \cr_a$26 , cr_a_ok, \xer_ca$27 , xer_ca_ok, \xer_ov$28 , xer_ov_ok, \xer_so$29 , xer_so_ok, muxid);
+module \output (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, alu_op__sv_pred_sz, alu_op__sv_pred_dz, alu_op__sv_saturate, alu_op__sv_ldstmode, alu_op__SV_Ptype, o, o_ok, cr_a, xer_ca, xer_ov, xer_so, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , \alu_op__sv_pred_sz$20 , \alu_op__sv_pred_dz$21 , \alu_op__sv_saturate$22 , \alu_op__sv_ldstmode$23 , \alu_op__SV_Ptype$24 , \o$25 , \o_ok$26 , \cr_a$27 , cr_a_ok, \xer_ca$28 , xer_ca_ok, \xer_ov$29 , xer_ov_ok, \xer_so$30 , xer_so_ok, muxid);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *)
- wire \$30 ;
+ wire \$31 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *)
- wire \$33 ;
+ wire \$34 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *)
- wire [64:0] \$35 ;
+ wire [64:0] \$36 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *)
- wire [63:0] \$36 ;
+ wire [63:0] \$37 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [64:0] \$39 ;
+ wire [64:0] \$40 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" *)
- wire \$41 ;
+ wire \$42 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:80" *)
- wire \$43 ;
+ wire \$44 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *)
- wire \$45 ;
+ wire \$46 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *)
- wire \$47 ;
+ wire \$48 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *)
- wire \$49 ;
+ wire \$50 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *)
- wire \$51 ;
+ wire \$52 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:90" *)
- wire \$53 ;
+ wire \$54 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *)
- wire \$56 ;
+ wire \$57 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *)
- wire \$58 ;
+ wire \$59 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \alu_op__SV_Ptype$23 ;
+ output [1:0] \alu_op__SV_Ptype$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [3:0] alu_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \alu_op__rc__rc$6 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] alu_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \alu_op__sv_ldstmode$23 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input [3:0] cr_a;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [3:0] \cr_a$26 ;
+ output [3:0] \cr_a$27 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output cr_a_ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *)
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input [63:0] o;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [63:0] \o$24 ;
+ output [63:0] \o$25 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:39" *)
- reg [64:0] \o$32 ;
+ reg [64:0] \o$33 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input o_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \o_ok$25 ;
+ output \o_ok$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" *)
wire oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" *)
- wire \oe$55 ;
+ wire \oe$56 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" *)
reg so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52" *)
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input [1:0] xer_ca;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [1:0] \xer_ca$27 ;
+ output [1:0] \xer_ca$28 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_ca_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input [1:0] xer_ov;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [1:0] \xer_ov$28 ;
- reg [1:0] \xer_ov$28 ;
+ output [1:0] \xer_ov$29 ;
+ reg [1:0] \xer_ov$29 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_ov_ok;
reg xer_ov_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \xer_so$29 ;
- reg \xer_so$29 ;
+ output \xer_so$30 ;
+ reg \xer_so$30 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_so_ok;
reg xer_so_ok;
- assign \$30 = alu_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) alu_op__oe__ok;
- assign \$33 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *) alu_op__sv_pred_dz;
- assign \$36 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *) o;
- assign \$35 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *) \$36 ;
- assign \$39 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *) o;
- assign \$41 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" *) 7'h0a;
- assign \$43 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:80" *) 7'h0c;
- assign \$45 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) target;
- assign \$47 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) msb_test;
- assign \$49 = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) \$47 ;
- assign \$51 = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *) is_cmp;
- assign \$53 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:90" *) is_nzero;
- assign \$56 = alu_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *) alu_op__oe__ok;
- assign \$58 = xer_so | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) xer_ov[0];
+ assign \$31 = alu_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) alu_op__oe__ok;
+ assign \$34 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *) alu_op__sv_pred_dz;
+ assign \$37 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *) o;
+ assign \$36 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *) \$37 ;
+ assign \$40 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *) o;
+ assign \$42 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" *) 7'h0a;
+ assign \$44 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:80" *) 7'h0c;
+ assign \$46 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) target;
+ assign \$48 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) msb_test;
+ assign \$50 = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) \$48 ;
+ assign \$52 = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *) is_cmp;
+ assign \$54 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:90" *) is_nzero;
+ assign \$57 = alu_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *) alu_op__oe__ok;
+ assign \$59 = xer_so | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) xer_ov[0];
always @* begin
if (\initial ) begin end
(* full_case = 32'd1 *)
casez (oe)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" */
1'h1:
- so = \xer_so$29 ;
+ so = \xer_so$30 ;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:32" */
default:
so = xer_so;
if (\initial ) begin end
(* full_case = 32'd1 *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *)
- casez (\$51 )
+ casez (\$52 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" */
1'h1:
cr0 = cr_a;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:89" */
default:
- cr0 = { is_negative, is_positive, \$53 , so };
+ cr0 = { is_negative, is_positive, \$54 , so };
endcase
end
always @* begin
if (\initial ) begin end
- \o$32 = 65'h00000000000000000;
+ \o$33 = 65'h00000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *)
- casez (\$33 )
+ casez (\$34 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" */
1'h1:
(* full_case = 32'd1 *)
casez (alu_op__invert_out)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" */
1'h1:
- \o$32 = \$35 ;
+ \o$33 = \$36 ;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:43" */
default:
- \o$32 = \$39 ;
+ \o$33 = \$40 ;
endcase
endcase
end
always @* begin
if (\initial ) begin end
- \xer_so$29 = 1'h0;
+ \xer_so$30 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *)
- casez (\oe$55 )
+ casez (\oe$56 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */
1'h1:
- \xer_so$29 = \$58 ;
+ \xer_so$30 = \$59 ;
endcase
end
always @* begin
if (\initial ) begin end
xer_so_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *)
- casez (\oe$55 )
+ casez (\oe$56 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */
1'h1:
xer_so_ok = 1'h1;
end
always @* begin
if (\initial ) begin end
- \xer_ov$28 = 2'h0;
+ \xer_ov$29 = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *)
- casez (\oe$55 )
+ casez (\oe$56 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */
1'h1:
- \xer_ov$28 = xer_ov;
+ \xer_ov$29 = xer_ov;
endcase
end
always @* begin
if (\initial ) begin end
xer_ov_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *)
- casez (\oe$55 )
+ casez (\oe$56 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */
1'h1:
xer_ov_ok = 1'h1;
endcase
end
- assign \oe$55 = \$56 ;
- assign { \alu_op__SV_Ptype$23 , \alu_op__sv_saturate$22 , \alu_op__sv_pred_dz$21 , \alu_op__sv_pred_sz$20 , \alu_op__insn$19 , \alu_op__data_len$18 , \alu_op__is_signed$17 , \alu_op__is_32bit$16 , \alu_op__output_carry$15 , \alu_op__input_carry$14 , \alu_op__write_cr0$13 , \alu_op__invert_out$12 , \alu_op__zero_a$11 , \alu_op__invert_in$10 , \alu_op__oe__ok$9 , \alu_op__oe__oe$8 , \alu_op__rc__ok$7 , \alu_op__rc__rc$6 , \alu_op__imm_data__ok$5 , \alu_op__imm_data__data$4 , \alu_op__fn_unit$3 , \alu_op__insn_type$2 } = { alu_op__SV_Ptype, alu_op__sv_saturate, alu_op__sv_pred_dz, alu_op__sv_pred_sz, alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type };
+ assign \oe$56 = \$57 ;
+ assign { \alu_op__SV_Ptype$24 , \alu_op__sv_ldstmode$23 , \alu_op__sv_saturate$22 , \alu_op__sv_pred_dz$21 , \alu_op__sv_pred_sz$20 , \alu_op__insn$19 , \alu_op__data_len$18 , \alu_op__is_signed$17 , \alu_op__is_32bit$16 , \alu_op__output_carry$15 , \alu_op__input_carry$14 , \alu_op__write_cr0$13 , \alu_op__invert_out$12 , \alu_op__zero_a$11 , \alu_op__invert_in$10 , \alu_op__oe__ok$9 , \alu_op__oe__oe$8 , \alu_op__rc__ok$7 , \alu_op__rc__rc$6 , \alu_op__imm_data__ok$5 , \alu_op__imm_data__data$4 , \alu_op__fn_unit$3 , \alu_op__insn_type$2 } = { alu_op__SV_Ptype, alu_op__sv_ldstmode, alu_op__sv_saturate, alu_op__sv_pred_dz, alu_op__sv_pred_sz, alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type };
assign \muxid$1 = muxid;
assign cr_a_ok = alu_op__write_cr0;
- assign \cr_a$26 = cr0;
- assign \o_ok$25 = o_ok;
- assign \o$24 = \o$32 [63:0];
- assign is_positive = \$49 ;
+ assign \cr_a$27 = cr0;
+ assign \o_ok$26 = o_ok;
+ assign \o$25 = \o$33 [63:0];
+ assign is_positive = \$50 ;
assign is_negative = msb_test;
- assign is_nzero = \$45 ;
+ assign is_nzero = \$46 ;
assign msb_test = target[63];
- assign is_cmpeqb = \$43 ;
- assign is_cmp = \$41 ;
+ assign is_cmpeqb = \$44 ;
+ assign is_cmp = \$42 ;
assign xer_ca_ok = alu_op__output_carry;
- assign \xer_ca$27 = xer_ca;
- assign target = \o$32 [63:0];
- assign oe = \$30 ;
+ assign \xer_ca$28 = xer_ca;
+ assign target = \o$33 [63:0];
+ assign oe = \$31 ;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.output" *)
(* generator = "nMigen" *)
-module \output$100 (mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__SV_Ptype, o, o_ok, cr_a, xer_ov, xer_so, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \mul_op__sv_pred_sz$14 , \mul_op__sv_pred_dz$15 , \mul_op__sv_saturate$16 , \mul_op__SV_Ptype$17 , \o$18 , \o_ok$19 , \cr_a$20 , cr_a_ok, \xer_ov$21 , xer_ov_ok, \xer_so$22 , xer_so_ok, muxid);
+module \output$100 (mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__sv_ldstmode, mul_op__SV_Ptype, o, o_ok, cr_a, xer_ov, xer_so, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \mul_op__sv_pred_sz$14 , \mul_op__sv_pred_dz$15 , \mul_op__sv_saturate$16 , \mul_op__sv_ldstmode$17 , \mul_op__SV_Ptype$18 , \o$19 , \o_ok$20 , \cr_a$21 , cr_a_ok, \xer_ov$22 , xer_ov_ok, \xer_so$23 , xer_so_ok, muxid);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *)
- wire \$23 ;
+ wire \$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *)
- wire \$26 ;
+ wire \$27 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [64:0] \$28 ;
+ wire [64:0] \$29 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" *)
- wire \$30 ;
+ wire \$31 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:80" *)
- wire \$32 ;
+ wire \$33 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *)
- wire \$34 ;
+ wire \$35 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *)
- wire \$36 ;
+ wire \$37 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *)
- wire \$38 ;
+ wire \$39 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *)
- wire \$40 ;
+ wire \$41 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:90" *)
- wire \$42 ;
+ wire \$43 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *)
- wire \$45 ;
+ wire \$46 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *)
- wire \$47 ;
+ wire \$48 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:73" *)
reg [3:0] cr0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input [3:0] cr_a;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [3:0] \cr_a$20 ;
+ output [3:0] \cr_a$21 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output cr_a_ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \mul_op__SV_Ptype$17 ;
+ output [1:0] \mul_op__SV_Ptype$18 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
input mul_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \mul_op__rc__rc$6 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] mul_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \mul_op__sv_ldstmode$17 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input mul_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input [63:0] o;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [63:0] \o$18 ;
+ output [63:0] \o$19 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:39" *)
- reg [64:0] \o$25 ;
+ reg [64:0] \o$26 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input o_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \o_ok$19 ;
+ output \o_ok$20 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" *)
wire oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" *)
- wire \oe$44 ;
+ wire \oe$45 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" *)
reg so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52" *)
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input [1:0] xer_ov;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [1:0] \xer_ov$21 ;
- reg [1:0] \xer_ov$21 ;
+ output [1:0] \xer_ov$22 ;
+ reg [1:0] \xer_ov$22 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_ov_ok;
reg xer_ov_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \xer_so$22 ;
- reg \xer_so$22 ;
+ output \xer_so$23 ;
+ reg \xer_so$23 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_so_ok;
reg xer_so_ok;
- assign \$23 = mul_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) mul_op__oe__ok;
- assign \$26 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *) mul_op__sv_pred_dz;
- assign \$28 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *) o;
- assign \$30 = mul_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" *) 7'h0a;
- assign \$32 = mul_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:80" *) 7'h0c;
- assign \$34 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) target;
- assign \$36 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) msb_test;
- assign \$38 = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) \$36 ;
- assign \$40 = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *) is_cmp;
- assign \$42 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:90" *) is_nzero;
- assign \$45 = mul_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *) mul_op__oe__ok;
- assign \$47 = xer_so | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) xer_ov[0];
+ assign \$24 = mul_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) mul_op__oe__ok;
+ assign \$27 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *) mul_op__sv_pred_dz;
+ assign \$29 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *) o;
+ assign \$31 = mul_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" *) 7'h0a;
+ assign \$33 = mul_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:80" *) 7'h0c;
+ assign \$35 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) target;
+ assign \$37 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) msb_test;
+ assign \$39 = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) \$37 ;
+ assign \$41 = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *) is_cmp;
+ assign \$43 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:90" *) is_nzero;
+ assign \$46 = mul_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *) mul_op__oe__ok;
+ assign \$48 = xer_so | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) xer_ov[0];
always @* begin
if (\initial ) begin end
(* full_case = 32'd1 *)
casez (oe)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" */
1'h1:
- so = \xer_so$22 ;
+ so = \xer_so$23 ;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:32" */
default:
so = xer_so;
if (\initial ) begin end
(* full_case = 32'd1 *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *)
- casez (\$40 )
+ casez (\$41 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" */
1'h1:
cr0 = cr_a;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:89" */
default:
- cr0 = { is_negative, is_positive, \$42 , so };
+ cr0 = { is_negative, is_positive, \$43 , so };
endcase
end
always @* begin
if (\initial ) begin end
- \o$25 = 65'h00000000000000000;
+ \o$26 = 65'h00000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *)
- casez (\$26 )
+ casez (\$27 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" */
1'h1:
- \o$25 = \$28 ;
+ \o$26 = \$29 ;
endcase
end
always @* begin
if (\initial ) begin end
- \xer_so$22 = 1'h0;
+ \xer_so$23 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *)
- casez (\oe$44 )
+ casez (\oe$45 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */
1'h1:
- \xer_so$22 = \$47 ;
+ \xer_so$23 = \$48 ;
endcase
end
always @* begin
if (\initial ) begin end
xer_so_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *)
- casez (\oe$44 )
+ casez (\oe$45 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */
1'h1:
xer_so_ok = 1'h1;
end
always @* begin
if (\initial ) begin end
- \xer_ov$21 = 2'h0;
+ \xer_ov$22 = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *)
- casez (\oe$44 )
+ casez (\oe$45 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */
1'h1:
- \xer_ov$21 = xer_ov;
+ \xer_ov$22 = xer_ov;
endcase
end
always @* begin
if (\initial ) begin end
xer_ov_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *)
- casez (\oe$44 )
+ casez (\oe$45 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */
1'h1:
xer_ov_ok = 1'h1;
endcase
end
- assign \oe$44 = \$45 ;
- assign { \mul_op__SV_Ptype$17 , \mul_op__sv_saturate$16 , \mul_op__sv_pred_dz$15 , \mul_op__sv_pred_sz$14 , \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 } = { mul_op__SV_Ptype, mul_op__sv_saturate, mul_op__sv_pred_dz, mul_op__sv_pred_sz, mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type };
+ assign \oe$45 = \$46 ;
+ assign { \mul_op__SV_Ptype$18 , \mul_op__sv_ldstmode$17 , \mul_op__sv_saturate$16 , \mul_op__sv_pred_dz$15 , \mul_op__sv_pred_sz$14 , \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 } = { mul_op__SV_Ptype, mul_op__sv_ldstmode, mul_op__sv_saturate, mul_op__sv_pred_dz, mul_op__sv_pred_sz, mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type };
assign \muxid$1 = muxid;
assign cr_a_ok = mul_op__write_cr0;
- assign \cr_a$20 = cr0;
- assign \o_ok$19 = o_ok;
- assign \o$18 = \o$25 [63:0];
- assign is_positive = \$38 ;
+ assign \cr_a$21 = cr0;
+ assign \o_ok$20 = o_ok;
+ assign \o$19 = \o$26 [63:0];
+ assign is_positive = \$39 ;
assign is_negative = msb_test;
- assign is_nzero = \$34 ;
+ assign is_nzero = \$35 ;
assign msb_test = target[63];
- assign is_cmpeqb = \$32 ;
- assign is_cmp = \$30 ;
- assign target = \o$25 [63:0];
- assign oe = \$23 ;
+ assign is_cmpeqb = \$33 ;
+ assign is_cmp = \$31 ;
+ assign target = \o$26 [63:0];
+ assign oe = \$24 ;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.output" *)
(* generator = "nMigen" *)
-module \output$118 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, sr_op__sv_pred_sz, sr_op__sv_pred_dz, sr_op__sv_saturate, sr_op__SV_Ptype, o, o_ok, cr_a, xer_so, xer_ca, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , \sr_op__sv_pred_sz$19 , \sr_op__sv_pred_dz$20 , \sr_op__sv_saturate$21 , \sr_op__SV_Ptype$22 , \o$23 , \o_ok$24 , \cr_a$25 , cr_a_ok, \xer_ca$26 , xer_ca_ok, muxid);
+module \output$118 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, sr_op__sv_pred_sz, sr_op__sv_pred_dz, sr_op__sv_saturate, sr_op__sv_ldstmode, sr_op__SV_Ptype, o, o_ok, cr_a, xer_so, xer_ca, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , \sr_op__sv_pred_sz$19 , \sr_op__sv_pred_dz$20 , \sr_op__sv_saturate$21 , \sr_op__sv_ldstmode$22 , \sr_op__SV_Ptype$23 , \o$24 , \o_ok$25 , \cr_a$26 , cr_a_ok, \xer_ca$27 , xer_ca_ok, muxid);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *)
- wire \$28 ;
+ wire \$29 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [64:0] \$30 ;
+ wire [64:0] \$31 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" *)
- wire \$32 ;
+ wire \$33 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:80" *)
- wire \$34 ;
+ wire \$35 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *)
- wire \$36 ;
+ wire \$37 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *)
- wire \$38 ;
+ wire \$39 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *)
- wire \$40 ;
+ wire \$41 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *)
- wire \$42 ;
+ wire \$43 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:90" *)
- wire \$44 ;
+ wire \$45 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:73" *)
reg [3:0] cr0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input [3:0] cr_a;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [3:0] \cr_a$25 ;
+ output [3:0] \cr_a$26 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output cr_a_ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *)
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input [63:0] o;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [63:0] \o$23 ;
+ output [63:0] \o$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:39" *)
- reg [64:0] \o$27 ;
+ reg [64:0] \o$28 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input o_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \o_ok$24 ;
+ output \o_ok$25 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \sr_op__SV_Ptype$22 ;
+ output [1:0] \sr_op__SV_Ptype$23 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
input sr_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \sr_op__rc__rc$6 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] sr_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \sr_op__sv_ldstmode$22 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input [1:0] xer_ca;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [1:0] \xer_ca$26 ;
+ output [1:0] \xer_ca$27 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_ca_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input xer_so;
- assign \$28 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *) sr_op__sv_pred_dz;
- assign \$30 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *) o;
- assign \$32 = sr_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" *) 7'h0a;
- assign \$34 = sr_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:80" *) 7'h0c;
- assign \$36 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) target;
- assign \$38 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) msb_test;
- assign \$40 = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) \$38 ;
- assign \$42 = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *) is_cmp;
- assign \$44 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:90" *) is_nzero;
- always @* begin
- if (\initial ) begin end
- \o$27 = 65'h00000000000000000;
+ assign \$29 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *) sr_op__sv_pred_dz;
+ assign \$31 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *) o;
+ assign \$33 = sr_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" *) 7'h0a;
+ assign \$35 = sr_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:80" *) 7'h0c;
+ assign \$37 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) target;
+ assign \$39 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) msb_test;
+ assign \$41 = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) \$39 ;
+ assign \$43 = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *) is_cmp;
+ assign \$45 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:90" *) is_nzero;
+ always @* begin
+ if (\initial ) begin end
+ \o$28 = 65'h00000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *)
- casez (\$28 )
+ casez (\$29 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" */
1'h1:
- \o$27 = \$30 ;
+ \o$28 = \$31 ;
endcase
end
always @* begin
if (\initial ) begin end
(* full_case = 32'd1 *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *)
- casez (\$42 )
+ casez (\$43 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" */
1'h1:
cr0 = cr_a;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:89" */
default:
- cr0 = { is_negative, is_positive, \$44 , xer_so };
+ cr0 = { is_negative, is_positive, \$45 , xer_so };
endcase
end
- assign { \sr_op__SV_Ptype$22 , \sr_op__sv_saturate$21 , \sr_op__sv_pred_dz$20 , \sr_op__sv_pred_sz$19 , \sr_op__insn$18 , \sr_op__is_signed$17 , \sr_op__is_32bit$16 , \sr_op__output_cr$15 , \sr_op__input_cr$14 , \sr_op__output_carry$13 , \sr_op__input_carry$12 , \sr_op__invert_in$11 , \sr_op__write_cr0$10 , \sr_op__oe__ok$9 , \sr_op__oe__oe$8 , \sr_op__rc__ok$7 , \sr_op__rc__rc$6 , \sr_op__imm_data__ok$5 , \sr_op__imm_data__data$4 , \sr_op__fn_unit$3 , \sr_op__insn_type$2 } = { sr_op__SV_Ptype, sr_op__sv_saturate, sr_op__sv_pred_dz, sr_op__sv_pred_sz, sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type };
+ assign { \sr_op__SV_Ptype$23 , \sr_op__sv_ldstmode$22 , \sr_op__sv_saturate$21 , \sr_op__sv_pred_dz$20 , \sr_op__sv_pred_sz$19 , \sr_op__insn$18 , \sr_op__is_signed$17 , \sr_op__is_32bit$16 , \sr_op__output_cr$15 , \sr_op__input_cr$14 , \sr_op__output_carry$13 , \sr_op__input_carry$12 , \sr_op__invert_in$11 , \sr_op__write_cr0$10 , \sr_op__oe__ok$9 , \sr_op__oe__oe$8 , \sr_op__rc__ok$7 , \sr_op__rc__rc$6 , \sr_op__imm_data__ok$5 , \sr_op__imm_data__data$4 , \sr_op__fn_unit$3 , \sr_op__insn_type$2 } = { sr_op__SV_Ptype, sr_op__sv_ldstmode, sr_op__sv_saturate, sr_op__sv_pred_dz, sr_op__sv_pred_sz, sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type };
assign \muxid$1 = muxid;
assign cr_a_ok = sr_op__write_cr0;
- assign \cr_a$25 = cr0;
- assign \o_ok$24 = o_ok;
- assign \o$23 = \o$27 [63:0];
- assign is_positive = \$40 ;
+ assign \cr_a$26 = cr0;
+ assign \o_ok$25 = o_ok;
+ assign \o$24 = \o$28 [63:0];
+ assign is_positive = \$41 ;
assign is_negative = msb_test;
- assign is_nzero = \$36 ;
+ assign is_nzero = \$37 ;
assign msb_test = target[63];
- assign is_cmpeqb = \$34 ;
- assign is_cmp = \$32 ;
+ assign is_cmpeqb = \$35 ;
+ assign is_cmp = \$33 ;
assign xer_ca_ok = sr_op__output_carry;
- assign \xer_ca$26 = xer_ca;
- assign target = \o$27 [63:0];
+ assign \xer_ca$27 = xer_ca;
+ assign target = \o$28 [63:0];
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.output" *)
(* generator = "nMigen" *)
-module \output$54 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, o, o_ok, cr_a, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__SV_Ptype$23 , \o$24 , \o_ok$25 , \cr_a$26 , cr_a_ok, muxid);
+module \output$54 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__sv_ldstmode, logical_op__SV_Ptype, o, o_ok, cr_a, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__sv_ldstmode$23 , \logical_op__SV_Ptype$24 , \o$25 , \o_ok$26 , \cr_a$27 , cr_a_ok, muxid);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *)
- wire \$28 ;
+ wire \$29 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *)
- wire [64:0] \$30 ;
+ wire [64:0] \$31 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *)
- wire [63:0] \$31 ;
+ wire [63:0] \$32 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [64:0] \$34 ;
+ wire [64:0] \$35 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" *)
- wire \$36 ;
+ wire \$37 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:80" *)
- wire \$38 ;
+ wire \$39 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *)
- wire \$40 ;
+ wire \$41 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *)
- wire \$42 ;
+ wire \$43 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *)
- wire \$44 ;
+ wire \$45 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *)
- wire \$46 ;
+ wire \$47 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:90" *)
- wire \$48 ;
+ wire \$49 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:73" *)
reg [3:0] cr0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input [3:0] cr_a;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [3:0] \cr_a$26 ;
+ output [3:0] \cr_a$27 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output cr_a_ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \logical_op__SV_Ptype$23 ;
+ output [1:0] \logical_op__SV_Ptype$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [3:0] logical_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__rc__rc$6 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] logical_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \logical_op__sv_ldstmode$23 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input [63:0] o;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [63:0] \o$24 ;
+ output [63:0] \o$25 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:39" *)
- reg [64:0] \o$27 ;
+ reg [64:0] \o$28 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input o_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \o_ok$25 ;
+ output \o_ok$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52" *)
wire [63:0] target;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input xer_so;
- assign \$28 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *) logical_op__sv_pred_dz;
- assign \$31 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *) o;
- assign \$30 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *) \$31 ;
- assign \$34 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *) o;
- assign \$36 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" *) 7'h0a;
- assign \$38 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:80" *) 7'h0c;
- assign \$40 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) target;
- assign \$42 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) msb_test;
- assign \$44 = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) \$42 ;
- assign \$46 = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *) is_cmp;
- assign \$48 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:90" *) is_nzero;
- always @* begin
- if (\initial ) begin end
- \o$27 = 65'h00000000000000000;
+ assign \$29 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *) logical_op__sv_pred_dz;
+ assign \$32 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *) o;
+ assign \$31 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *) \$32 ;
+ assign \$35 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *) o;
+ assign \$37 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" *) 7'h0a;
+ assign \$39 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:80" *) 7'h0c;
+ assign \$41 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) target;
+ assign \$43 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) msb_test;
+ assign \$45 = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) \$43 ;
+ assign \$47 = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *) is_cmp;
+ assign \$49 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:90" *) is_nzero;
+ always @* begin
+ if (\initial ) begin end
+ \o$28 = 65'h00000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *)
- casez (\$28 )
+ casez (\$29 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" */
1'h1:
(* full_case = 32'd1 *)
casez (logical_op__invert_out)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" */
1'h1:
- \o$27 = \$30 ;
+ \o$28 = \$31 ;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:43" */
default:
- \o$27 = \$34 ;
+ \o$28 = \$35 ;
endcase
endcase
end
if (\initial ) begin end
(* full_case = 32'd1 *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *)
- casez (\$46 )
+ casez (\$47 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" */
1'h1:
cr0 = cr_a;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:89" */
default:
- cr0 = { is_negative, is_positive, \$48 , xer_so };
+ cr0 = { is_negative, is_positive, \$49 , xer_so };
endcase
end
- assign { \logical_op__SV_Ptype$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__SV_Ptype, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
+ assign { \logical_op__SV_Ptype$24 , \logical_op__sv_ldstmode$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__SV_Ptype, logical_op__sv_ldstmode, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
assign \muxid$1 = muxid;
assign cr_a_ok = logical_op__write_cr0;
- assign \cr_a$26 = cr0;
- assign \o_ok$25 = o_ok;
- assign \o$24 = \o$27 [63:0];
- assign is_positive = \$44 ;
+ assign \cr_a$27 = cr0;
+ assign \o_ok$26 = o_ok;
+ assign \o$25 = \o$28 [63:0];
+ assign is_positive = \$45 ;
assign is_negative = msb_test;
- assign is_nzero = \$40 ;
+ assign is_nzero = \$41 ;
assign msb_test = target[63];
- assign is_cmpeqb = \$38 ;
- assign is_cmp = \$36 ;
- assign target = \o$27 [63:0];
+ assign is_cmpeqb = \$39 ;
+ assign is_cmp = \$37 ;
+ assign target = \o$28 [63:0];
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output" *)
(* generator = "nMigen" *)
-module \output$83 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, o, o_ok, cr_a, xer_ov, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__SV_Ptype$23 , \o$24 , \o_ok$25 , \cr_a$26 , cr_a_ok, \xer_ov$27 , xer_ov_ok, \xer_so$28 , xer_so_ok, muxid);
+module \output$83 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__sv_ldstmode, logical_op__SV_Ptype, o, o_ok, cr_a, xer_ov, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__sv_ldstmode$23 , \logical_op__SV_Ptype$24 , \o$25 , \o_ok$26 , \cr_a$27 , cr_a_ok, \xer_ov$28 , xer_ov_ok, \xer_so$29 , xer_so_ok, muxid);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *)
- wire \$29 ;
+ wire \$30 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *)
- wire \$32 ;
+ wire \$33 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *)
- wire [64:0] \$34 ;
+ wire [64:0] \$35 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *)
- wire [63:0] \$35 ;
+ wire [63:0] \$36 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [64:0] \$38 ;
+ wire [64:0] \$39 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" *)
- wire \$40 ;
+ wire \$41 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:80" *)
- wire \$42 ;
+ wire \$43 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *)
- wire \$44 ;
+ wire \$45 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *)
- wire \$46 ;
+ wire \$47 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *)
- wire \$48 ;
+ wire \$49 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *)
- wire \$50 ;
+ wire \$51 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:90" *)
- wire \$52 ;
+ wire \$53 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *)
- wire \$55 ;
+ wire \$56 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *)
- wire \$57 ;
+ wire \$58 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:73" *)
reg [3:0] cr0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input [3:0] cr_a;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [3:0] \cr_a$26 ;
+ output [3:0] \cr_a$27 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output cr_a_ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \logical_op__SV_Ptype$23 ;
+ output [1:0] \logical_op__SV_Ptype$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [3:0] logical_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__rc__rc$6 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] logical_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \logical_op__sv_ldstmode$23 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input [63:0] o;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [63:0] \o$24 ;
+ output [63:0] \o$25 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:39" *)
- reg [64:0] \o$31 ;
+ reg [64:0] \o$32 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input o_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \o_ok$25 ;
+ output \o_ok$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" *)
wire oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" *)
- wire \oe$54 ;
+ wire \oe$55 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" *)
reg so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52" *)
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input [1:0] xer_ov;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [1:0] \xer_ov$27 ;
- reg [1:0] \xer_ov$27 ;
+ output [1:0] \xer_ov$28 ;
+ reg [1:0] \xer_ov$28 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_ov_ok;
reg xer_ov_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \xer_so$28 ;
- reg \xer_so$28 ;
+ output \xer_so$29 ;
+ reg \xer_so$29 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_so_ok;
reg xer_so_ok;
- assign \$29 = logical_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) logical_op__oe__ok;
- assign \$32 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *) logical_op__sv_pred_dz;
- assign \$35 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *) o;
- assign \$34 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *) \$35 ;
- assign \$38 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *) o;
- assign \$40 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" *) 7'h0a;
- assign \$42 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:80" *) 7'h0c;
- assign \$44 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) target;
- assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) msb_test;
- assign \$48 = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) \$46 ;
- assign \$50 = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *) is_cmp;
- assign \$52 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:90" *) is_nzero;
- assign \$55 = logical_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *) logical_op__oe__ok;
- assign \$57 = xer_so | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) xer_ov[0];
+ assign \$30 = logical_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) logical_op__oe__ok;
+ assign \$33 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *) logical_op__sv_pred_dz;
+ assign \$36 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *) o;
+ assign \$35 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *) \$36 ;
+ assign \$39 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *) o;
+ assign \$41 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" *) 7'h0a;
+ assign \$43 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:80" *) 7'h0c;
+ assign \$45 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) target;
+ assign \$47 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) msb_test;
+ assign \$49 = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) \$47 ;
+ assign \$51 = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *) is_cmp;
+ assign \$53 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:90" *) is_nzero;
+ assign \$56 = logical_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *) logical_op__oe__ok;
+ assign \$58 = xer_so | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) xer_ov[0];
always @* begin
if (\initial ) begin end
(* full_case = 32'd1 *)
casez (oe)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" */
1'h1:
- so = \xer_so$28 ;
+ so = \xer_so$29 ;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:32" */
default:
so = xer_so;
if (\initial ) begin end
(* full_case = 32'd1 *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *)
- casez (\$50 )
+ casez (\$51 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" */
1'h1:
cr0 = cr_a;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:89" */
default:
- cr0 = { is_negative, is_positive, \$52 , so };
+ cr0 = { is_negative, is_positive, \$53 , so };
endcase
end
always @* begin
if (\initial ) begin end
- \o$31 = 65'h00000000000000000;
+ \o$32 = 65'h00000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *)
- casez (\$32 )
+ casez (\$33 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" */
1'h1:
(* full_case = 32'd1 *)
casez (logical_op__invert_out)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" */
1'h1:
- \o$31 = \$34 ;
+ \o$32 = \$35 ;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:43" */
default:
- \o$31 = \$38 ;
+ \o$32 = \$39 ;
endcase
endcase
end
always @* begin
if (\initial ) begin end
- \xer_so$28 = 1'h0;
+ \xer_so$29 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *)
- casez (\oe$54 )
+ casez (\oe$55 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */
1'h1:
- \xer_so$28 = \$57 ;
+ \xer_so$29 = \$58 ;
endcase
end
always @* begin
if (\initial ) begin end
xer_so_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *)
- casez (\oe$54 )
+ casez (\oe$55 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */
1'h1:
xer_so_ok = 1'h1;
end
always @* begin
if (\initial ) begin end
- \xer_ov$27 = 2'h0;
+ \xer_ov$28 = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *)
- casez (\oe$54 )
+ casez (\oe$55 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */
1'h1:
- \xer_ov$27 = xer_ov;
+ \xer_ov$28 = xer_ov;
endcase
end
always @* begin
if (\initial ) begin end
xer_ov_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *)
- casez (\oe$54 )
+ casez (\oe$55 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */
1'h1:
xer_ov_ok = 1'h1;
endcase
end
- assign \oe$54 = \$55 ;
- assign { \logical_op__SV_Ptype$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__SV_Ptype, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
+ assign \oe$55 = \$56 ;
+ assign { \logical_op__SV_Ptype$24 , \logical_op__sv_ldstmode$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__SV_Ptype, logical_op__sv_ldstmode, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
assign \muxid$1 = muxid;
assign cr_a_ok = logical_op__write_cr0;
- assign \cr_a$26 = cr0;
- assign \o_ok$25 = o_ok;
- assign \o$24 = \o$31 [63:0];
- assign is_positive = \$48 ;
+ assign \cr_a$27 = cr0;
+ assign \o_ok$26 = o_ok;
+ assign \o$25 = \o$32 [63:0];
+ assign is_positive = \$49 ;
assign is_negative = msb_test;
- assign is_nzero = \$44 ;
+ assign is_nzero = \$45 ;
assign msb_test = target[63];
- assign is_cmpeqb = \$42 ;
- assign is_cmp = \$40 ;
- assign target = \o$31 [63:0];
- assign oe = \$29 ;
+ assign is_cmpeqb = \$43 ;
+ assign is_cmp = \$41 ;
+ assign target = \o$32 [63:0];
+ assign oe = \$30 ;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output_stage" *)
(* generator = "nMigen" *)
-module output_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, xer_so, divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, quotient_root, remainder, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__SV_Ptype$23 , o, o_ok, xer_ov, xer_ov_ok, \xer_so$24 , muxid);
+module output_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__sv_ldstmode, logical_op__SV_Ptype, xer_so, divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, quotient_root, remainder, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__sv_ldstmode$23 , \logical_op__SV_Ptype$24 , o, o_ok, xer_ov, xer_ov_ok, \xer_so$25 , muxid);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" *)
- wire \$25 ;
+ wire \$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" *)
- wire [64:0] \$27 ;
+ wire [64:0] \$28 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *)
- wire [64:0] \$29 ;
+ wire [64:0] \$30 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" *)
- wire [64:0] \$31 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *)
- wire [64:0] \$33 ;
+ wire [64:0] \$32 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *)
wire [64:0] \$34 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *)
+ wire [64:0] \$35 ;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *)
- wire [64:0] \$36 ;
+ wire [64:0] \$37 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *)
- wire [64:0] \$38 ;
+ wire [64:0] \$39 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" *)
- wire \$40 ;
+ wire \$41 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" *)
- wire \$42 ;
+ wire \$43 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" *)
- wire \$44 ;
+ wire \$45 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" *)
- wire \$46 ;
+ wire \$47 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" *)
- wire [63:0] \$48 ;
+ wire [63:0] \$49 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" *)
- wire \$50 ;
+ wire \$51 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" *)
- wire [63:0] \$52 ;
+ wire [63:0] \$53 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" *)
- wire [63:0] \$54 ;
+ wire [63:0] \$55 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" *)
- wire [63:0] \$56 ;
+ wire [63:0] \$57 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" *)
- wire [63:0] \$58 ;
+ wire [63:0] \$59 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" *)
- wire [63:0] \$60 ;
+ wire [63:0] \$61 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
input div_by_zero;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \logical_op__SV_Ptype$23 ;
+ output [1:0] \logical_op__SV_Ptype$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [3:0] logical_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__rc__rc$6 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] logical_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \logical_op__sv_ldstmode$23 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \xer_so$24 ;
- assign \$25 = dividend_neg ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" *) divisor_neg;
- assign \$27 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" *) quotient_root;
- assign \$29 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *) quotient_root;
- assign \$31 = quotient_neg ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" *) \$27 : \$29 ;
- assign \$34 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *) remainder[127:64];
- assign \$36 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) remainder[127:64];
- assign \$38 = remainder_neg ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *) \$34 : \$36 ;
- assign \$40 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" *) logical_op__is_32bit;
- assign \$42 = quotient_65[64] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" *) quotient_65[63];
- assign \$44 = logical_op__is_signed & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" *) \$42 ;
- assign \$46 = quotient_65[32] != (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" *) quotient_65[31];
- assign \$48 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" *) $signed(remainder_s32);
- assign \$50 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" *) ov;
- assign \$52 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" *) quotient_65[31:0];
- assign \$54 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" *) quotient_65[31:0];
- assign \$56 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" *) quotient_65[31:0];
- assign \$58 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" *) quotient_65[31:0];
- assign \$60 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" *) remainder_64[31:0];
+ output \xer_so$25 ;
+ assign \$26 = dividend_neg ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" *) divisor_neg;
+ assign \$28 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" *) quotient_root;
+ assign \$30 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *) quotient_root;
+ assign \$32 = quotient_neg ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" *) \$28 : \$30 ;
+ assign \$35 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *) remainder[127:64];
+ assign \$37 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) remainder[127:64];
+ assign \$39 = remainder_neg ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *) \$35 : \$37 ;
+ assign \$41 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" *) logical_op__is_32bit;
+ assign \$43 = quotient_65[64] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" *) quotient_65[63];
+ assign \$45 = logical_op__is_signed & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" *) \$43 ;
+ assign \$47 = quotient_65[32] != (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" *) quotient_65[31];
+ assign \$49 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" *) $signed(remainder_s32);
+ assign \$51 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" *) ov;
+ assign \$53 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" *) quotient_65[31:0];
+ assign \$55 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" *) quotient_65[31:0];
+ assign \$57 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" *) quotient_65[31:0];
+ assign \$59 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" *) quotient_65[31:0];
+ assign \$61 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" *) remainder_64[31:0];
always @* begin
if (\initial ) begin end
o = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" *)
- casez (\$50 )
+ casez (\$51 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" */
1'h1:
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:103" *)
casez (logical_op__is_signed)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:106" */
1'h1:
- o = \$52 ;
+ o = \$53 ;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:109" */
default:
- o = \$54 ;
+ o = \$55 ;
endcase
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111" */
default:
casez (logical_op__is_signed)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:115" */
1'h1:
- o = \$56 ;
+ o = \$57 ;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:118" */
default:
- o = \$58 ;
+ o = \$59 ;
endcase
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:120" */
default:
o = remainder_s32_as_s64;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:127" */
default:
- o = \$60 ;
+ o = \$61 ;
endcase
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:129" */
default:
if (\initial ) begin end
(* full_case = 32'd1 *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" *)
- casez ({ logical_op__is_signed, \$40 , div_by_zero })
+ casez ({ logical_op__is_signed, \$41 , div_by_zero })
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" */
3'b??1:
ov = 1'h1;
begin
ov = dive_abs_ov64;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" *)
- casez (\$44 )
+ casez (\$45 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" */
1'h1:
ov = 1'h1;
begin
ov = dive_abs_ov32;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" *)
- casez (\$46 )
+ casez (\$47 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" */
1'h1:
ov = 1'h1;
ov = dive_abs_ov32;
endcase
end
- assign \$33 = \$38 ;
- assign { \logical_op__SV_Ptype$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__SV_Ptype, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
+ assign \$34 = \$39 ;
+ assign { \logical_op__SV_Ptype$24 , \logical_op__sv_ldstmode$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__SV_Ptype, logical_op__sv_ldstmode, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
assign \muxid$1 = muxid;
- assign \xer_so$24 = xer_so;
- assign remainder_s32_as_s64 = \$48 ;
+ assign \xer_so$25 = xer_so;
+ assign remainder_s32_as_s64 = \$49 ;
assign remainder_s32 = remainder_64[31:0];
assign o_ok = 1'h1;
assign xer_ov = { ov, ov };
assign xer_ov_ok = 1'h1;
- assign remainder_64 = \$38 [63:0];
- assign quotient_65 = \$31 ;
+ assign remainder_64 = \$39 [63:0];
+ assign quotient_65 = \$32 ;
assign remainder_neg = dividend_neg;
- assign quotient_neg = \$25 ;
+ assign quotient_neg = \$26 ;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_alu0.p" *)
reg busy_l_r_busy;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
reg busy_l_s_busy;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
wire cyc_l_q_cyc;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0.alu_cr0.pipe" *)
(* generator = "nMigen" *)
-module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__fn_unit, cr_op__insn, cr_op__sv_pred_sz, cr_op__sv_pred_dz, cr_op__sv_saturate, cr_op__SV_Ptype, ra, rb, full_cr, cr_a, cr_b, cr_c, n_valid_o, n_ready_i, \muxid$1 , \cr_op__insn_type$2 , \cr_op__fn_unit$3 , \cr_op__insn$4 , \cr_op__sv_pred_sz$5 , \cr_op__sv_pred_dz$6 , \cr_op__sv_saturate$7 , \cr_op__SV_Ptype$8 , o, o_ok, \full_cr$9 , full_cr_ok, \cr_a$10 , cr_a_ok, coresync_clk);
+module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__fn_unit, cr_op__insn, cr_op__sv_pred_sz, cr_op__sv_pred_dz, cr_op__sv_saturate, cr_op__sv_ldstmode, cr_op__SV_Ptype, ra, rb, full_cr, cr_a, cr_b, cr_c, n_valid_o, n_ready_i, \muxid$1 , \cr_op__insn_type$2 , \cr_op__fn_unit$3 , \cr_op__insn$4 , \cr_op__sv_pred_sz$5 , \cr_op__sv_pred_dz$6 , \cr_op__sv_saturate$7 , \cr_op__sv_ldstmode$8 , \cr_op__SV_Ptype$9 , o, o_ok, \full_cr$10 , full_cr_ok, \cr_a$11 , cr_a_ok, coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
- wire \$22 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ wire \$24 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [3:0] cr_a;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [3:0] \cr_a$10 ;
- reg [3:0] \cr_a$10 = 4'h0;
+ output [3:0] \cr_a$11 ;
+ reg [3:0] \cr_a$11 = 4'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg [3:0] \cr_a$10$next ;
+ reg [3:0] \cr_a$11$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [3:0] \cr_a$36 ;
+ wire [3:0] \cr_a$39 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output cr_a_ok;
reg cr_a_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \cr_a_ok$37 ;
+ wire \cr_a_ok$40 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \cr_a_ok$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \cr_op__SV_Ptype$31 ;
+ wire [1:0] \cr_op__SV_Ptype$34 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \cr_op__SV_Ptype$8 ;
- reg [1:0] \cr_op__SV_Ptype$8 = 2'h0;
+ output [1:0] \cr_op__SV_Ptype$9 ;
+ reg [1:0] \cr_op__SV_Ptype$9 = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [1:0] \cr_op__SV_Ptype$8$next ;
+ reg [1:0] \cr_op__SV_Ptype$9$next ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \cr_op__fn_unit$26 ;
+ wire [14:0] \cr_op__fn_unit$28 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] cr_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \cr_op__insn$27 ;
+ wire [31:0] \cr_op__insn$29 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output [31:0] \cr_op__insn$4 ;
reg [31:0] \cr_op__insn$4 = 32'd0;
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \cr_op__insn_type$25 ;
+ wire [6:0] \cr_op__insn_type$27 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] cr_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \cr_op__sv_ldstmode$33 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \cr_op__sv_ldstmode$8 ;
+ reg [1:0] \cr_op__sv_ldstmode$8 = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \cr_op__sv_ldstmode$8$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input cr_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \cr_op__sv_pred_dz$29 ;
+ wire \cr_op__sv_pred_dz$31 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \cr_op__sv_pred_dz$6 ;
reg \cr_op__sv_pred_dz$6 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input cr_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \cr_op__sv_pred_sz$28 ;
+ wire \cr_op__sv_pred_sz$30 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \cr_op__sv_pred_sz$5 ;
reg \cr_op__sv_pred_sz$5 = 1'h0;
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \cr_op__sv_saturate$30 ;
+ wire [1:0] \cr_op__sv_saturate$32 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [31:0] full_cr;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [31:0] \full_cr$34 ;
+ output [31:0] \full_cr$10 ;
+ reg [31:0] \full_cr$10 = 32'd0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [31:0] \full_cr$9 ;
- reg [31:0] \full_cr$9 = 32'd0;
+ reg [31:0] \full_cr$10$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg [31:0] \full_cr$9$next ;
+ wire [31:0] \full_cr$37 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output full_cr_ok;
reg full_cr_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \full_cr_ok$35 ;
+ wire \full_cr_ok$38 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \full_cr_ok$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [3:0] main_cr_a;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [3:0] \main_cr_a$20 ;
+ wire [3:0] \main_cr_a$22 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire main_cr_a_ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \main_cr_op__SV_Ptype$18 ;
+ wire [1:0] \main_cr_op__SV_Ptype$20 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \main_cr_op__fn_unit$13 ;
+ wire [14:0] \main_cr_op__fn_unit$14 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] main_cr_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \main_cr_op__insn$14 ;
+ wire [31:0] \main_cr_op__insn$15 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \main_cr_op__insn_type$12 ;
+ wire [6:0] \main_cr_op__insn_type$13 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] main_cr_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \main_cr_op__sv_ldstmode$19 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_cr_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_cr_op__sv_pred_dz$16 ;
+ wire \main_cr_op__sv_pred_dz$17 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_cr_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_cr_op__sv_pred_sz$15 ;
+ wire \main_cr_op__sv_pred_sz$16 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \main_cr_op__sv_saturate$17 ;
+ wire [1:0] \main_cr_op__sv_saturate$18 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [31:0] main_full_cr;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [31:0] \main_full_cr$19 ;
+ wire [31:0] \main_full_cr$21 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire main_full_cr_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] main_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \main_muxid$11 ;
+ wire [1:0] \main_muxid$12 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [63:0] main_o;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
reg [1:0] \muxid$1$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \muxid$24 ;
+ wire [1:0] \muxid$26 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
wire n_i_rdy_data;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
output [63:0] o;
reg [63:0] o = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \o$32 ;
+ wire [63:0] \o$35 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg [63:0] \o$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output o_ok;
reg o_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \o_ok$33 ;
+ wire \o_ok$36 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \o_ok$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
input p_valid_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
- wire \p_valid_i$21 ;
+ wire \p_valid_i$23 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
wire p_valid_i_p_ready_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
input [63:0] ra;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] rb;
- assign \$22 = \p_valid_i$21 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
+ assign \$24 = \p_valid_i$23 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
always @(posedge coresync_clk)
- \cr_a$10 <= \cr_a$10$next ;
+ \cr_a$11 <= \cr_a$11$next ;
always @(posedge coresync_clk)
cr_a_ok <= \cr_a_ok$next ;
always @(posedge coresync_clk)
- \full_cr$9 <= \full_cr$9$next ;
+ \full_cr$10 <= \full_cr$10$next ;
always @(posedge coresync_clk)
full_cr_ok <= \full_cr_ok$next ;
always @(posedge coresync_clk)
always @(posedge coresync_clk)
\cr_op__sv_saturate$7 <= \cr_op__sv_saturate$7$next ;
always @(posedge coresync_clk)
- \cr_op__SV_Ptype$8 <= \cr_op__SV_Ptype$8$next ;
+ \cr_op__sv_ldstmode$8 <= \cr_op__sv_ldstmode$8$next ;
+ always @(posedge coresync_clk)
+ \cr_op__SV_Ptype$9 <= \cr_op__SV_Ptype$9$next ;
always @(posedge coresync_clk)
\muxid$1 <= \muxid$1$next ;
always @(posedge coresync_clk)
r_busy <= \r_busy$next ;
\main$9 main (
.cr_a(main_cr_a),
- .\cr_a$10 (\main_cr_a$20 ),
+ .\cr_a$11 (\main_cr_a$22 ),
.cr_a_ok(main_cr_a_ok),
.cr_b(main_cr_b),
.cr_c(main_cr_c),
.cr_op__SV_Ptype(main_cr_op__SV_Ptype),
- .\cr_op__SV_Ptype$8 (\main_cr_op__SV_Ptype$18 ),
+ .\cr_op__SV_Ptype$9 (\main_cr_op__SV_Ptype$20 ),
.cr_op__fn_unit(main_cr_op__fn_unit),
- .\cr_op__fn_unit$3 (\main_cr_op__fn_unit$13 ),
+ .\cr_op__fn_unit$3 (\main_cr_op__fn_unit$14 ),
.cr_op__insn(main_cr_op__insn),
- .\cr_op__insn$4 (\main_cr_op__insn$14 ),
+ .\cr_op__insn$4 (\main_cr_op__insn$15 ),
.cr_op__insn_type(main_cr_op__insn_type),
- .\cr_op__insn_type$2 (\main_cr_op__insn_type$12 ),
+ .\cr_op__insn_type$2 (\main_cr_op__insn_type$13 ),
+ .cr_op__sv_ldstmode(main_cr_op__sv_ldstmode),
+ .\cr_op__sv_ldstmode$8 (\main_cr_op__sv_ldstmode$19 ),
.cr_op__sv_pred_dz(main_cr_op__sv_pred_dz),
- .\cr_op__sv_pred_dz$6 (\main_cr_op__sv_pred_dz$16 ),
+ .\cr_op__sv_pred_dz$6 (\main_cr_op__sv_pred_dz$17 ),
.cr_op__sv_pred_sz(main_cr_op__sv_pred_sz),
- .\cr_op__sv_pred_sz$5 (\main_cr_op__sv_pred_sz$15 ),
+ .\cr_op__sv_pred_sz$5 (\main_cr_op__sv_pred_sz$16 ),
.cr_op__sv_saturate(main_cr_op__sv_saturate),
- .\cr_op__sv_saturate$7 (\main_cr_op__sv_saturate$17 ),
+ .\cr_op__sv_saturate$7 (\main_cr_op__sv_saturate$18 ),
.full_cr(main_full_cr),
- .\full_cr$9 (\main_full_cr$19 ),
+ .\full_cr$10 (\main_full_cr$21 ),
.full_cr_ok(main_full_cr_ok),
.muxid(main_muxid),
- .\muxid$1 (\main_muxid$11 ),
+ .\muxid$1 (\main_muxid$12 ),
.o(main_o),
.o_ok(main_o_ok),
.ra(main_ra),
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \muxid$1$next = \muxid$24 ;
+ \muxid$1$next = \muxid$26 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \muxid$1$next = \muxid$24 ;
+ \muxid$1$next = \muxid$26 ;
endcase
end
always @* begin
\cr_op__sv_pred_sz$5$next = \cr_op__sv_pred_sz$5 ;
\cr_op__sv_pred_dz$6$next = \cr_op__sv_pred_dz$6 ;
\cr_op__sv_saturate$7$next = \cr_op__sv_saturate$7 ;
- \cr_op__SV_Ptype$8$next = \cr_op__SV_Ptype$8 ;
+ \cr_op__sv_ldstmode$8$next = \cr_op__sv_ldstmode$8 ;
+ \cr_op__SV_Ptype$9$next = \cr_op__SV_Ptype$9 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \cr_op__SV_Ptype$8$next , \cr_op__sv_saturate$7$next , \cr_op__sv_pred_dz$6$next , \cr_op__sv_pred_sz$5$next , \cr_op__insn$4$next , \cr_op__fn_unit$3$next , \cr_op__insn_type$2$next } = { \cr_op__SV_Ptype$31 , \cr_op__sv_saturate$30 , \cr_op__sv_pred_dz$29 , \cr_op__sv_pred_sz$28 , \cr_op__insn$27 , \cr_op__fn_unit$26 , \cr_op__insn_type$25 };
+ { \cr_op__SV_Ptype$9$next , \cr_op__sv_ldstmode$8$next , \cr_op__sv_saturate$7$next , \cr_op__sv_pred_dz$6$next , \cr_op__sv_pred_sz$5$next , \cr_op__insn$4$next , \cr_op__fn_unit$3$next , \cr_op__insn_type$2$next } = { \cr_op__SV_Ptype$34 , \cr_op__sv_ldstmode$33 , \cr_op__sv_saturate$32 , \cr_op__sv_pred_dz$31 , \cr_op__sv_pred_sz$30 , \cr_op__insn$29 , \cr_op__fn_unit$28 , \cr_op__insn_type$27 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \cr_op__SV_Ptype$8$next , \cr_op__sv_saturate$7$next , \cr_op__sv_pred_dz$6$next , \cr_op__sv_pred_sz$5$next , \cr_op__insn$4$next , \cr_op__fn_unit$3$next , \cr_op__insn_type$2$next } = { \cr_op__SV_Ptype$31 , \cr_op__sv_saturate$30 , \cr_op__sv_pred_dz$29 , \cr_op__sv_pred_sz$28 , \cr_op__insn$27 , \cr_op__fn_unit$26 , \cr_op__insn_type$25 };
+ { \cr_op__SV_Ptype$9$next , \cr_op__sv_ldstmode$8$next , \cr_op__sv_saturate$7$next , \cr_op__sv_pred_dz$6$next , \cr_op__sv_pred_sz$5$next , \cr_op__insn$4$next , \cr_op__fn_unit$3$next , \cr_op__insn_type$2$next } = { \cr_op__SV_Ptype$34 , \cr_op__sv_ldstmode$33 , \cr_op__sv_saturate$32 , \cr_op__sv_pred_dz$31 , \cr_op__sv_pred_sz$30 , \cr_op__insn$29 , \cr_op__fn_unit$28 , \cr_op__insn_type$27 };
endcase
end
always @* begin
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \o_ok$next , \o$next } = { \o_ok$33 , \o$32 };
+ { \o_ok$next , \o$next } = { \o_ok$36 , \o$35 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \o_ok$next , \o$next } = { \o_ok$33 , \o$32 };
+ { \o_ok$next , \o$next } = { \o_ok$36 , \o$35 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
end
always @* begin
if (\initial ) begin end
- \full_cr$9$next = \full_cr$9 ;
+ \full_cr$10$next = \full_cr$10 ;
\full_cr_ok$next = full_cr_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \full_cr_ok$next , \full_cr$9$next } = { \full_cr_ok$35 , \full_cr$34 };
+ { \full_cr_ok$next , \full_cr$10$next } = { \full_cr_ok$38 , \full_cr$37 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \full_cr_ok$next , \full_cr$9$next } = { \full_cr_ok$35 , \full_cr$34 };
+ { \full_cr_ok$next , \full_cr$10$next } = { \full_cr_ok$38 , \full_cr$37 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
end
always @* begin
if (\initial ) begin end
- \cr_a$10$next = \cr_a$10 ;
+ \cr_a$11$next = \cr_a$11 ;
\cr_a_ok$next = cr_a_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \cr_a_ok$next , \cr_a$10$next } = { \cr_a_ok$37 , \cr_a$36 };
+ { \cr_a_ok$next , \cr_a$11$next } = { \cr_a_ok$40 , \cr_a$39 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \cr_a_ok$next , \cr_a$10$next } = { \cr_a_ok$37 , \cr_a$36 };
+ { \cr_a_ok$next , \cr_a$11$next } = { \cr_a_ok$40 , \cr_a$39 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
end
assign p_ready_o = n_i_rdy_data;
assign n_valid_o = r_busy;
- assign { \cr_a_ok$37 , \cr_a$36 } = { main_cr_a_ok, \main_cr_a$20 };
- assign { \full_cr_ok$35 , \full_cr$34 } = { main_full_cr_ok, \main_full_cr$19 };
- assign { \o_ok$33 , \o$32 } = { main_o_ok, main_o };
- assign { \cr_op__SV_Ptype$31 , \cr_op__sv_saturate$30 , \cr_op__sv_pred_dz$29 , \cr_op__sv_pred_sz$28 , \cr_op__insn$27 , \cr_op__fn_unit$26 , \cr_op__insn_type$25 } = { \main_cr_op__SV_Ptype$18 , \main_cr_op__sv_saturate$17 , \main_cr_op__sv_pred_dz$16 , \main_cr_op__sv_pred_sz$15 , \main_cr_op__insn$14 , \main_cr_op__fn_unit$13 , \main_cr_op__insn_type$12 };
- assign \muxid$24 = \main_muxid$11 ;
- assign p_valid_i_p_ready_o = \$22 ;
+ assign { \cr_a_ok$40 , \cr_a$39 } = { main_cr_a_ok, \main_cr_a$22 };
+ assign { \full_cr_ok$38 , \full_cr$37 } = { main_full_cr_ok, \main_full_cr$21 };
+ assign { \o_ok$36 , \o$35 } = { main_o_ok, main_o };
+ assign { \cr_op__SV_Ptype$34 , \cr_op__sv_ldstmode$33 , \cr_op__sv_saturate$32 , \cr_op__sv_pred_dz$31 , \cr_op__sv_pred_sz$30 , \cr_op__insn$29 , \cr_op__fn_unit$28 , \cr_op__insn_type$27 } = { \main_cr_op__SV_Ptype$20 , \main_cr_op__sv_ldstmode$19 , \main_cr_op__sv_saturate$18 , \main_cr_op__sv_pred_dz$17 , \main_cr_op__sv_pred_sz$16 , \main_cr_op__insn$15 , \main_cr_op__fn_unit$14 , \main_cr_op__insn_type$13 };
+ assign \muxid$26 = \main_muxid$12 ;
+ assign p_valid_i_p_ready_o = \$24 ;
assign n_i_rdy_data = n_ready_i;
- assign \p_valid_i$21 = p_valid_i;
+ assign \p_valid_i$23 = p_valid_i;
assign main_cr_c = cr_c;
assign main_cr_b = cr_b;
assign main_cr_a = cr_a;
assign main_full_cr = full_cr;
assign main_rb = rb;
assign main_ra = ra;
- assign { main_cr_op__SV_Ptype, main_cr_op__sv_saturate, main_cr_op__sv_pred_dz, main_cr_op__sv_pred_sz, main_cr_op__insn, main_cr_op__fn_unit, main_cr_op__insn_type } = { cr_op__SV_Ptype, cr_op__sv_saturate, cr_op__sv_pred_dz, cr_op__sv_pred_sz, cr_op__insn, cr_op__fn_unit, cr_op__insn_type };
+ assign { main_cr_op__SV_Ptype, main_cr_op__sv_ldstmode, main_cr_op__sv_saturate, main_cr_op__sv_pred_dz, main_cr_op__sv_pred_sz, main_cr_op__insn, main_cr_op__fn_unit, main_cr_op__insn_type } = { cr_op__SV_Ptype, cr_op__sv_ldstmode, cr_op__sv_saturate, cr_op__sv_pred_dz, cr_op__sv_pred_sz, cr_op__insn, cr_op__fn_unit, cr_op__insn_type };
assign main_muxid = muxid;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.branch0.alu_branch0.pipe" *)
(* generator = "nMigen" *)
-module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_op__imm_data__data, br_op__imm_data__ok, br_op__lk, br_op__is_32bit, br_op__sv_pred_sz, br_op__sv_pred_dz, br_op__sv_saturate, br_op__SV_Ptype, fast1, fast2, cr_a, n_valid_o, n_ready_i, \muxid$1 , \br_op__cia$2 , \br_op__insn_type$3 , \br_op__fn_unit$4 , \br_op__insn$5 , \br_op__imm_data__data$6 , \br_op__imm_data__ok$7 , \br_op__lk$8 , \br_op__is_32bit$9 , \br_op__sv_pred_sz$10 , \br_op__sv_pred_dz$11 , \br_op__sv_saturate$12 , \br_op__SV_Ptype$13 , \fast1$14 , fast1_ok, \fast2$15 , fast2_ok, nia, nia_ok, coresync_clk);
+module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_op__imm_data__data, br_op__imm_data__ok, br_op__lk, br_op__is_32bit, br_op__sv_pred_sz, br_op__sv_pred_dz, br_op__sv_saturate, br_op__sv_ldstmode, br_op__SV_Ptype, fast1, fast2, cr_a, n_valid_o, n_ready_i, \muxid$1 , \br_op__cia$2 , \br_op__insn_type$3 , \br_op__fn_unit$4 , \br_op__insn$5 , \br_op__imm_data__data$6 , \br_op__imm_data__ok$7 , \br_op__lk$8 , \br_op__is_32bit$9 , \br_op__sv_pred_sz$10 , \br_op__sv_pred_dz$11 , \br_op__sv_saturate$12 , \br_op__sv_ldstmode$13 , \br_op__SV_Ptype$14 , \fast1$15 , fast1_ok, \fast2$16 , fast2_ok, nia, nia_ok, coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
- wire \$32 ;
+ wire \$34 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \br_op__SV_Ptype$13 ;
- reg [1:0] \br_op__SV_Ptype$13 = 2'h0;
+ output [1:0] \br_op__SV_Ptype$14 ;
+ reg [1:0] \br_op__SV_Ptype$14 = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [1:0] \br_op__SV_Ptype$13$next ;
+ reg [1:0] \br_op__SV_Ptype$14$next ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \br_op__SV_Ptype$46 ;
+ wire [1:0] \br_op__SV_Ptype$49 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] br_op__cia;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [63:0] \br_op__cia$2$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \br_op__cia$35 ;
+ wire [63:0] \br_op__cia$37 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \br_op__fn_unit$37 ;
+ wire [14:0] \br_op__fn_unit$39 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] br_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \br_op__imm_data__data$39 ;
+ wire [63:0] \br_op__imm_data__data$41 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output [63:0] \br_op__imm_data__data$6 ;
reg [63:0] \br_op__imm_data__data$6 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input br_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \br_op__imm_data__ok$40 ;
+ wire \br_op__imm_data__ok$42 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \br_op__imm_data__ok$7 ;
reg \br_op__imm_data__ok$7 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] br_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \br_op__insn$38 ;
+ wire [31:0] \br_op__insn$40 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output [31:0] \br_op__insn$5 ;
reg [31:0] \br_op__insn$5 = 32'd0;
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \br_op__insn_type$36 ;
+ wire [6:0] \br_op__insn_type$38 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input br_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \br_op__is_32bit$42 ;
+ wire \br_op__is_32bit$44 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \br_op__is_32bit$9 ;
reg \br_op__is_32bit$9 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input br_op__lk;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \br_op__lk$41 ;
+ wire \br_op__lk$43 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \br_op__lk$8 ;
reg \br_op__lk$8 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \br_op__lk$8$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] br_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \br_op__sv_ldstmode$13 ;
+ reg [1:0] \br_op__sv_ldstmode$13 = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \br_op__sv_ldstmode$13$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \br_op__sv_ldstmode$48 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input br_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \br_op__sv_pred_dz$11$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \br_op__sv_pred_dz$44 ;
+ wire \br_op__sv_pred_dz$46 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input br_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \br_op__sv_pred_sz$10$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \br_op__sv_pred_sz$43 ;
+ wire \br_op__sv_pred_sz$45 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \br_op__sv_saturate$45 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ wire [1:0] \br_op__sv_saturate$47 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [3:0] cr_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] fast1;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [63:0] \fast1$14 ;
- reg [63:0] \fast1$14 = 64'h0000000000000000;
+ output [63:0] \fast1$15 ;
+ reg [63:0] \fast1$15 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg [63:0] \fast1$14$next ;
+ reg [63:0] \fast1$15$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \fast1$47 ;
+ wire [63:0] \fast1$50 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output fast1_ok;
reg fast1_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \fast1_ok$48 ;
+ wire \fast1_ok$51 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \fast1_ok$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] fast2;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [63:0] \fast2$15 ;
- reg [63:0] \fast2$15 = 64'h0000000000000000;
+ output [63:0] \fast2$16 ;
+ reg [63:0] \fast2$16 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg [63:0] \fast2$15$next ;
+ reg [63:0] \fast2$16$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \fast2$49 ;
+ wire [63:0] \fast2$52 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output fast2_ok;
reg fast2_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \fast2_ok$50 ;
+ wire \fast2_ok$53 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \fast2_ok$next ;
(* enum_base_type = "SVPtype" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \main_br_op__SV_Ptype$28 ;
+ wire [1:0] \main_br_op__SV_Ptype$30 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] main_br_op__cia;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \main_br_op__cia$17 ;
+ wire [63:0] \main_br_op__cia$18 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \main_br_op__fn_unit$19 ;
+ wire [14:0] \main_br_op__fn_unit$20 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] main_br_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \main_br_op__imm_data__data$21 ;
+ wire [63:0] \main_br_op__imm_data__data$22 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_br_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_br_op__imm_data__ok$22 ;
+ wire \main_br_op__imm_data__ok$23 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] main_br_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \main_br_op__insn$20 ;
+ wire [31:0] \main_br_op__insn$21 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \main_br_op__insn_type$18 ;
+ wire [6:0] \main_br_op__insn_type$19 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_br_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_br_op__is_32bit$24 ;
+ wire \main_br_op__is_32bit$25 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_br_op__lk;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_br_op__lk$23 ;
+ wire \main_br_op__lk$24 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] main_br_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \main_br_op__sv_ldstmode$29 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_br_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_br_op__sv_pred_dz$26 ;
+ wire \main_br_op__sv_pred_dz$27 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_br_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_br_op__sv_pred_sz$25 ;
+ wire \main_br_op__sv_pred_sz$26 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \main_br_op__sv_saturate$27 ;
+ wire [1:0] \main_br_op__sv_saturate$28 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [3:0] main_cr_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] main_fast1;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \main_fast1$29 ;
+ wire [63:0] \main_fast1$31 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire main_fast1_ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] main_fast2;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \main_fast2$30 ;
+ wire [63:0] \main_fast2$32 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire main_fast2_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] main_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \main_muxid$16 ;
+ wire [1:0] \main_muxid$17 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [63:0] main_nia;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
reg [1:0] \muxid$1$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \muxid$34 ;
+ wire [1:0] \muxid$36 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
wire n_i_rdy_data;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
output [63:0] nia;
reg [63:0] nia = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \nia$51 ;
+ wire [63:0] \nia$54 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg [63:0] \nia$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output nia_ok;
reg nia_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \nia_ok$52 ;
+ wire \nia_ok$55 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \nia_ok$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
input p_valid_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
- wire \p_valid_i$31 ;
+ wire \p_valid_i$33 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
wire p_valid_i_p_ready_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
reg r_busy = 1'h0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
reg \r_busy$next ;
- assign \$32 = \p_valid_i$31 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
+ assign \$34 = \p_valid_i$33 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
always @(posedge coresync_clk)
nia <= \nia$next ;
always @(posedge coresync_clk)
nia_ok <= \nia_ok$next ;
always @(posedge coresync_clk)
- \fast2$15 <= \fast2$15$next ;
+ \fast2$16 <= \fast2$16$next ;
always @(posedge coresync_clk)
fast2_ok <= \fast2_ok$next ;
always @(posedge coresync_clk)
- \fast1$14 <= \fast1$14$next ;
+ \fast1$15 <= \fast1$15$next ;
always @(posedge coresync_clk)
fast1_ok <= \fast1_ok$next ;
always @(posedge coresync_clk)
always @(posedge coresync_clk)
\br_op__sv_saturate$12 <= \br_op__sv_saturate$12$next ;
always @(posedge coresync_clk)
- \br_op__SV_Ptype$13 <= \br_op__SV_Ptype$13$next ;
+ \br_op__sv_ldstmode$13 <= \br_op__sv_ldstmode$13$next ;
+ always @(posedge coresync_clk)
+ \br_op__SV_Ptype$14 <= \br_op__SV_Ptype$14$next ;
always @(posedge coresync_clk)
\muxid$1 <= \muxid$1$next ;
always @(posedge coresync_clk)
r_busy <= \r_busy$next ;
\main$22 main (
.br_op__SV_Ptype(main_br_op__SV_Ptype),
- .\br_op__SV_Ptype$13 (\main_br_op__SV_Ptype$28 ),
+ .\br_op__SV_Ptype$14 (\main_br_op__SV_Ptype$30 ),
.br_op__cia(main_br_op__cia),
- .\br_op__cia$2 (\main_br_op__cia$17 ),
+ .\br_op__cia$2 (\main_br_op__cia$18 ),
.br_op__fn_unit(main_br_op__fn_unit),
- .\br_op__fn_unit$4 (\main_br_op__fn_unit$19 ),
+ .\br_op__fn_unit$4 (\main_br_op__fn_unit$20 ),
.br_op__imm_data__data(main_br_op__imm_data__data),
- .\br_op__imm_data__data$6 (\main_br_op__imm_data__data$21 ),
+ .\br_op__imm_data__data$6 (\main_br_op__imm_data__data$22 ),
.br_op__imm_data__ok(main_br_op__imm_data__ok),
- .\br_op__imm_data__ok$7 (\main_br_op__imm_data__ok$22 ),
+ .\br_op__imm_data__ok$7 (\main_br_op__imm_data__ok$23 ),
.br_op__insn(main_br_op__insn),
- .\br_op__insn$5 (\main_br_op__insn$20 ),
+ .\br_op__insn$5 (\main_br_op__insn$21 ),
.br_op__insn_type(main_br_op__insn_type),
- .\br_op__insn_type$3 (\main_br_op__insn_type$18 ),
+ .\br_op__insn_type$3 (\main_br_op__insn_type$19 ),
.br_op__is_32bit(main_br_op__is_32bit),
- .\br_op__is_32bit$9 (\main_br_op__is_32bit$24 ),
+ .\br_op__is_32bit$9 (\main_br_op__is_32bit$25 ),
.br_op__lk(main_br_op__lk),
- .\br_op__lk$8 (\main_br_op__lk$23 ),
+ .\br_op__lk$8 (\main_br_op__lk$24 ),
+ .br_op__sv_ldstmode(main_br_op__sv_ldstmode),
+ .\br_op__sv_ldstmode$13 (\main_br_op__sv_ldstmode$29 ),
.br_op__sv_pred_dz(main_br_op__sv_pred_dz),
- .\br_op__sv_pred_dz$11 (\main_br_op__sv_pred_dz$26 ),
+ .\br_op__sv_pred_dz$11 (\main_br_op__sv_pred_dz$27 ),
.br_op__sv_pred_sz(main_br_op__sv_pred_sz),
- .\br_op__sv_pred_sz$10 (\main_br_op__sv_pred_sz$25 ),
+ .\br_op__sv_pred_sz$10 (\main_br_op__sv_pred_sz$26 ),
.br_op__sv_saturate(main_br_op__sv_saturate),
- .\br_op__sv_saturate$12 (\main_br_op__sv_saturate$27 ),
+ .\br_op__sv_saturate$12 (\main_br_op__sv_saturate$28 ),
.cr_a(main_cr_a),
.fast1(main_fast1),
- .\fast1$14 (\main_fast1$29 ),
+ .\fast1$15 (\main_fast1$31 ),
.fast1_ok(main_fast1_ok),
.fast2(main_fast2),
- .\fast2$15 (\main_fast2$30 ),
+ .\fast2$16 (\main_fast2$32 ),
.fast2_ok(main_fast2_ok),
.muxid(main_muxid),
- .\muxid$1 (\main_muxid$16 ),
+ .\muxid$1 (\main_muxid$17 ),
.nia(main_nia),
.nia_ok(main_nia_ok)
);
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \muxid$1$next = \muxid$34 ;
+ \muxid$1$next = \muxid$36 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \muxid$1$next = \muxid$34 ;
+ \muxid$1$next = \muxid$36 ;
endcase
end
always @* begin
\br_op__sv_pred_sz$10$next = \br_op__sv_pred_sz$10 ;
\br_op__sv_pred_dz$11$next = \br_op__sv_pred_dz$11 ;
\br_op__sv_saturate$12$next = \br_op__sv_saturate$12 ;
- \br_op__SV_Ptype$13$next = \br_op__SV_Ptype$13 ;
+ \br_op__sv_ldstmode$13$next = \br_op__sv_ldstmode$13 ;
+ \br_op__SV_Ptype$14$next = \br_op__SV_Ptype$14 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \br_op__SV_Ptype$13$next , \br_op__sv_saturate$12$next , \br_op__sv_pred_dz$11$next , \br_op__sv_pred_sz$10$next , \br_op__is_32bit$9$next , \br_op__lk$8$next , \br_op__imm_data__ok$7$next , \br_op__imm_data__data$6$next , \br_op__insn$5$next , \br_op__fn_unit$4$next , \br_op__insn_type$3$next , \br_op__cia$2$next } = { \br_op__SV_Ptype$46 , \br_op__sv_saturate$45 , \br_op__sv_pred_dz$44 , \br_op__sv_pred_sz$43 , \br_op__is_32bit$42 , \br_op__lk$41 , \br_op__imm_data__ok$40 , \br_op__imm_data__data$39 , \br_op__insn$38 , \br_op__fn_unit$37 , \br_op__insn_type$36 , \br_op__cia$35 };
+ { \br_op__SV_Ptype$14$next , \br_op__sv_ldstmode$13$next , \br_op__sv_saturate$12$next , \br_op__sv_pred_dz$11$next , \br_op__sv_pred_sz$10$next , \br_op__is_32bit$9$next , \br_op__lk$8$next , \br_op__imm_data__ok$7$next , \br_op__imm_data__data$6$next , \br_op__insn$5$next , \br_op__fn_unit$4$next , \br_op__insn_type$3$next , \br_op__cia$2$next } = { \br_op__SV_Ptype$49 , \br_op__sv_ldstmode$48 , \br_op__sv_saturate$47 , \br_op__sv_pred_dz$46 , \br_op__sv_pred_sz$45 , \br_op__is_32bit$44 , \br_op__lk$43 , \br_op__imm_data__ok$42 , \br_op__imm_data__data$41 , \br_op__insn$40 , \br_op__fn_unit$39 , \br_op__insn_type$38 , \br_op__cia$37 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \br_op__SV_Ptype$13$next , \br_op__sv_saturate$12$next , \br_op__sv_pred_dz$11$next , \br_op__sv_pred_sz$10$next , \br_op__is_32bit$9$next , \br_op__lk$8$next , \br_op__imm_data__ok$7$next , \br_op__imm_data__data$6$next , \br_op__insn$5$next , \br_op__fn_unit$4$next , \br_op__insn_type$3$next , \br_op__cia$2$next } = { \br_op__SV_Ptype$46 , \br_op__sv_saturate$45 , \br_op__sv_pred_dz$44 , \br_op__sv_pred_sz$43 , \br_op__is_32bit$42 , \br_op__lk$41 , \br_op__imm_data__ok$40 , \br_op__imm_data__data$39 , \br_op__insn$38 , \br_op__fn_unit$37 , \br_op__insn_type$36 , \br_op__cia$35 };
+ { \br_op__SV_Ptype$14$next , \br_op__sv_ldstmode$13$next , \br_op__sv_saturate$12$next , \br_op__sv_pred_dz$11$next , \br_op__sv_pred_sz$10$next , \br_op__is_32bit$9$next , \br_op__lk$8$next , \br_op__imm_data__ok$7$next , \br_op__imm_data__data$6$next , \br_op__insn$5$next , \br_op__fn_unit$4$next , \br_op__insn_type$3$next , \br_op__cia$2$next } = { \br_op__SV_Ptype$49 , \br_op__sv_ldstmode$48 , \br_op__sv_saturate$47 , \br_op__sv_pred_dz$46 , \br_op__sv_pred_sz$45 , \br_op__is_32bit$44 , \br_op__lk$43 , \br_op__imm_data__ok$42 , \br_op__imm_data__data$41 , \br_op__insn$40 , \br_op__fn_unit$39 , \br_op__insn_type$38 , \br_op__cia$37 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
end
always @* begin
if (\initial ) begin end
- \fast1$14$next = \fast1$14 ;
+ \fast1$15$next = \fast1$15 ;
\fast1_ok$next = fast1_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \fast1_ok$next , \fast1$14$next } = { \fast1_ok$48 , \fast1$47 };
+ { \fast1_ok$next , \fast1$15$next } = { \fast1_ok$51 , \fast1$50 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \fast1_ok$next , \fast1$14$next } = { \fast1_ok$48 , \fast1$47 };
+ { \fast1_ok$next , \fast1$15$next } = { \fast1_ok$51 , \fast1$50 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
end
always @* begin
if (\initial ) begin end
- \fast2$15$next = \fast2$15 ;
+ \fast2$16$next = \fast2$16 ;
\fast2_ok$next = fast2_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \fast2_ok$next , \fast2$15$next } = { \fast2_ok$50 , \fast2$49 };
+ { \fast2_ok$next , \fast2$16$next } = { \fast2_ok$53 , \fast2$52 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \fast2_ok$next , \fast2$15$next } = { \fast2_ok$50 , \fast2$49 };
+ { \fast2_ok$next , \fast2$16$next } = { \fast2_ok$53 , \fast2$52 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \nia_ok$next , \nia$next } = { \nia_ok$52 , \nia$51 };
+ { \nia_ok$next , \nia$next } = { \nia_ok$55 , \nia$54 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \nia_ok$next , \nia$next } = { \nia_ok$52 , \nia$51 };
+ { \nia_ok$next , \nia$next } = { \nia_ok$55 , \nia$54 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
end
assign p_ready_o = n_i_rdy_data;
assign n_valid_o = r_busy;
- assign { \nia_ok$52 , \nia$51 } = { main_nia_ok, main_nia };
- assign { \fast2_ok$50 , \fast2$49 } = { main_fast2_ok, \main_fast2$30 };
- assign { \fast1_ok$48 , \fast1$47 } = { main_fast1_ok, \main_fast1$29 };
- assign { \br_op__SV_Ptype$46 , \br_op__sv_saturate$45 , \br_op__sv_pred_dz$44 , \br_op__sv_pred_sz$43 , \br_op__is_32bit$42 , \br_op__lk$41 , \br_op__imm_data__ok$40 , \br_op__imm_data__data$39 , \br_op__insn$38 , \br_op__fn_unit$37 , \br_op__insn_type$36 , \br_op__cia$35 } = { \main_br_op__SV_Ptype$28 , \main_br_op__sv_saturate$27 , \main_br_op__sv_pred_dz$26 , \main_br_op__sv_pred_sz$25 , \main_br_op__is_32bit$24 , \main_br_op__lk$23 , \main_br_op__imm_data__ok$22 , \main_br_op__imm_data__data$21 , \main_br_op__insn$20 , \main_br_op__fn_unit$19 , \main_br_op__insn_type$18 , \main_br_op__cia$17 };
- assign \muxid$34 = \main_muxid$16 ;
- assign p_valid_i_p_ready_o = \$32 ;
+ assign { \nia_ok$55 , \nia$54 } = { main_nia_ok, main_nia };
+ assign { \fast2_ok$53 , \fast2$52 } = { main_fast2_ok, \main_fast2$32 };
+ assign { \fast1_ok$51 , \fast1$50 } = { main_fast1_ok, \main_fast1$31 };
+ assign { \br_op__SV_Ptype$49 , \br_op__sv_ldstmode$48 , \br_op__sv_saturate$47 , \br_op__sv_pred_dz$46 , \br_op__sv_pred_sz$45 , \br_op__is_32bit$44 , \br_op__lk$43 , \br_op__imm_data__ok$42 , \br_op__imm_data__data$41 , \br_op__insn$40 , \br_op__fn_unit$39 , \br_op__insn_type$38 , \br_op__cia$37 } = { \main_br_op__SV_Ptype$30 , \main_br_op__sv_ldstmode$29 , \main_br_op__sv_saturate$28 , \main_br_op__sv_pred_dz$27 , \main_br_op__sv_pred_sz$26 , \main_br_op__is_32bit$25 , \main_br_op__lk$24 , \main_br_op__imm_data__ok$23 , \main_br_op__imm_data__data$22 , \main_br_op__insn$21 , \main_br_op__fn_unit$20 , \main_br_op__insn_type$19 , \main_br_op__cia$18 };
+ assign \muxid$36 = \main_muxid$17 ;
+ assign p_valid_i_p_ready_o = \$34 ;
assign n_i_rdy_data = n_ready_i;
- assign \p_valid_i$31 = p_valid_i;
+ assign \p_valid_i$33 = p_valid_i;
assign main_cr_a = cr_a;
assign main_fast2 = fast2;
assign main_fast1 = fast1;
- assign { main_br_op__SV_Ptype, main_br_op__sv_saturate, main_br_op__sv_pred_dz, main_br_op__sv_pred_sz, main_br_op__is_32bit, main_br_op__lk, main_br_op__imm_data__ok, main_br_op__imm_data__data, main_br_op__insn, main_br_op__fn_unit, main_br_op__insn_type, main_br_op__cia } = { br_op__SV_Ptype, br_op__sv_saturate, br_op__sv_pred_dz, br_op__sv_pred_sz, br_op__is_32bit, br_op__lk, br_op__imm_data__ok, br_op__imm_data__data, br_op__insn, br_op__fn_unit, br_op__insn_type, br_op__cia };
+ assign { main_br_op__SV_Ptype, main_br_op__sv_ldstmode, main_br_op__sv_saturate, main_br_op__sv_pred_dz, main_br_op__sv_pred_sz, main_br_op__is_32bit, main_br_op__lk, main_br_op__imm_data__ok, main_br_op__imm_data__data, main_br_op__insn, main_br_op__fn_unit, main_br_op__insn_type, main_br_op__cia } = { br_op__SV_Ptype, br_op__sv_ldstmode, br_op__sv_saturate, br_op__sv_pred_dz, br_op__sv_pred_sz, br_op__is_32bit, br_op__lk, br_op__imm_data__ok, br_op__imm_data__data, br_op__insn, br_op__fn_unit, br_op__insn_type, br_op__cia };
assign main_muxid = muxid;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0.alu_spr0.pipe" *)
(* generator = "nMigen" *)
-module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32bit, spr_op__sv_pred_sz, spr_op__sv_pred_dz, spr_op__sv_saturate, spr_op__SV_Ptype, ra, spr1, fast1, xer_so, xer_ov, xer_ca, n_valid_o, n_ready_i, \muxid$1 , \spr_op__insn_type$2 , \spr_op__fn_unit$3 , \spr_op__insn$4 , \spr_op__is_32bit$5 , \spr_op__sv_pred_sz$6 , \spr_op__sv_pred_dz$7 , \spr_op__sv_saturate$8 , \spr_op__SV_Ptype$9 , o, o_ok, \spr1$10 , spr1_ok, \fast1$11 , fast1_ok, \xer_so$12 , xer_so_ok, \xer_ov$13 , xer_ov_ok, \xer_ca$14 , xer_ca_ok, coresync_clk);
+module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32bit, spr_op__sv_pred_sz, spr_op__sv_pred_dz, spr_op__sv_saturate, spr_op__sv_ldstmode, spr_op__SV_Ptype, ra, spr1, fast1, xer_so, xer_ov, xer_ca, n_valid_o, n_ready_i, \muxid$1 , \spr_op__insn_type$2 , \spr_op__fn_unit$3 , \spr_op__insn$4 , \spr_op__is_32bit$5 , \spr_op__sv_pred_sz$6 , \spr_op__sv_pred_dz$7 , \spr_op__sv_saturate$8 , \spr_op__sv_ldstmode$9 , \spr_op__SV_Ptype$10 , o, o_ok, \spr1$11 , spr1_ok, \fast1$12 , fast1_ok, \xer_so$13 , xer_so_ok, \xer_ov$14 , xer_ov_ok, \xer_ca$15 , xer_ca_ok, coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
- wire \$30 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ wire \$32 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] fast1;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [63:0] \fast1$11 ;
- reg [63:0] \fast1$11 = 64'h0000000000000000;
+ output [63:0] \fast1$12 ;
+ reg [63:0] \fast1$12 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg [63:0] \fast1$11$next ;
+ reg [63:0] \fast1$12$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \fast1$45 ;
+ wire [63:0] \fast1$48 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output fast1_ok;
reg fast1_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \fast1_ok$46 ;
+ wire \fast1_ok$49 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \fast1_ok$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
reg [1:0] \muxid$1$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \muxid$32 ;
+ wire [1:0] \muxid$34 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
wire n_i_rdy_data;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
output [63:0] o;
reg [63:0] o = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \o$41 ;
+ wire [63:0] \o$44 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg [63:0] \o$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output o_ok;
reg o_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \o_ok$42 ;
+ wire \o_ok$45 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \o_ok$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
input p_valid_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
- wire \p_valid_i$29 ;
+ wire \p_valid_i$31 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
wire p_valid_i_p_ready_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] spr1;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [63:0] \spr1$10 ;
- reg [63:0] \spr1$10 = 64'h0000000000000000;
+ output [63:0] \spr1$11 ;
+ reg [63:0] \spr1$11 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg [63:0] \spr1$10$next ;
+ reg [63:0] \spr1$11$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \spr1$43 ;
+ wire [63:0] \spr1$46 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output spr1_ok;
reg spr1_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \spr1_ok$44 ;
+ wire \spr1_ok$47 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \spr1_ok$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] spr_main_fast1;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \spr_main_fast1$25 ;
+ wire [63:0] \spr_main_fast1$27 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire spr_main_fast1_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] spr_main_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \spr_main_muxid$15 ;
+ wire [1:0] \spr_main_muxid$16 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [63:0] spr_main_o;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] spr_main_spr1;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \spr_main_spr1$24 ;
+ wire [63:0] \spr_main_spr1$26 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire spr_main_spr1_ok;
(* enum_base_type = "SVPtype" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \spr_main_spr_op__SV_Ptype$23 ;
+ wire [1:0] \spr_main_spr_op__SV_Ptype$25 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \spr_main_spr_op__fn_unit$17 ;
+ wire [14:0] \spr_main_spr_op__fn_unit$18 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] spr_main_spr_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \spr_main_spr_op__insn$18 ;
+ wire [31:0] \spr_main_spr_op__insn$19 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \spr_main_spr_op__insn_type$16 ;
+ wire [6:0] \spr_main_spr_op__insn_type$17 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire spr_main_spr_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \spr_main_spr_op__is_32bit$19 ;
+ wire \spr_main_spr_op__is_32bit$20 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] spr_main_spr_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \spr_main_spr_op__sv_ldstmode$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire spr_main_spr_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \spr_main_spr_op__sv_pred_dz$21 ;
+ wire \spr_main_spr_op__sv_pred_dz$22 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire spr_main_spr_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \spr_main_spr_op__sv_pred_sz$20 ;
+ wire \spr_main_spr_op__sv_pred_sz$21 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \spr_main_spr_op__sv_saturate$22 ;
+ wire [1:0] \spr_main_spr_op__sv_saturate$23 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [1:0] spr_main_xer_ca;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [1:0] \spr_main_xer_ca$28 ;
+ wire [1:0] \spr_main_xer_ca$30 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire spr_main_xer_ca_ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [1:0] spr_main_xer_ov;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [1:0] \spr_main_xer_ov$27 ;
+ wire [1:0] \spr_main_xer_ov$29 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire spr_main_xer_ov_ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire spr_main_xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \spr_main_xer_so$26 ;
+ wire \spr_main_xer_so$28 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire spr_main_xer_so_ok;
(* enum_base_type = "SVPtype" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \spr_op__SV_Ptype$40 ;
+ output [1:0] \spr_op__SV_Ptype$10 ;
+ reg [1:0] \spr_op__SV_Ptype$10 = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \spr_op__SV_Ptype$10$next ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \spr_op__SV_Ptype$9 ;
- reg [1:0] \spr_op__SV_Ptype$9 = 2'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [1:0] \spr_op__SV_Ptype$9$next ;
+ wire [1:0] \spr_op__SV_Ptype$43 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \spr_op__fn_unit$34 ;
+ wire [14:0] \spr_op__fn_unit$36 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] spr_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \spr_op__insn$35 ;
+ wire [31:0] \spr_op__insn$37 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output [31:0] \spr_op__insn$4 ;
reg [31:0] \spr_op__insn$4 = 32'd0;
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \spr_op__insn_type$33 ;
+ wire [6:0] \spr_op__insn_type$35 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input spr_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \spr_op__is_32bit$36 ;
+ wire \spr_op__is_32bit$38 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \spr_op__is_32bit$5 ;
reg \spr_op__is_32bit$5 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \spr_op__is_32bit$5$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] spr_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \spr_op__sv_ldstmode$42 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \spr_op__sv_ldstmode$9 ;
+ reg [1:0] \spr_op__sv_ldstmode$9 = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \spr_op__sv_ldstmode$9$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input spr_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \spr_op__sv_pred_dz$38 ;
+ wire \spr_op__sv_pred_dz$40 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \spr_op__sv_pred_dz$7 ;
reg \spr_op__sv_pred_dz$7 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input spr_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \spr_op__sv_pred_sz$37 ;
+ wire \spr_op__sv_pred_sz$39 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \spr_op__sv_pred_sz$6 ;
reg \spr_op__sv_pred_sz$6 = 1'h0;
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \spr_op__sv_saturate$39 ;
+ wire [1:0] \spr_op__sv_saturate$41 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [1:0] xer_ca;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [1:0] \xer_ca$14 ;
- reg [1:0] \xer_ca$14 = 2'h0;
+ output [1:0] \xer_ca$15 ;
+ reg [1:0] \xer_ca$15 = 2'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg [1:0] \xer_ca$14$next ;
+ reg [1:0] \xer_ca$15$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [1:0] \xer_ca$51 ;
+ wire [1:0] \xer_ca$54 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_ca_ok;
reg xer_ca_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_ca_ok$52 ;
+ wire \xer_ca_ok$55 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \xer_ca_ok$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [1:0] xer_ov;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [1:0] \xer_ov$13 ;
- reg [1:0] \xer_ov$13 = 2'h0;
+ output [1:0] \xer_ov$14 ;
+ reg [1:0] \xer_ov$14 = 2'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg [1:0] \xer_ov$13$next ;
+ reg [1:0] \xer_ov$14$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [1:0] \xer_ov$49 ;
+ wire [1:0] \xer_ov$52 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_ov_ok;
reg xer_ov_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_ov_ok$50 ;
+ wire \xer_ov_ok$53 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \xer_ov_ok$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \xer_so$12 ;
- reg \xer_so$12 = 1'h0;
+ output \xer_so$13 ;
+ reg \xer_so$13 = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg \xer_so$12$next ;
+ reg \xer_so$13$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_so$47 ;
+ wire \xer_so$50 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_so_ok;
reg xer_so_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_so_ok$48 ;
+ wire \xer_so_ok$51 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \xer_so_ok$next ;
- assign \$30 = \p_valid_i$29 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
+ assign \$32 = \p_valid_i$31 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
always @(posedge coresync_clk)
- \xer_ca$14 <= \xer_ca$14$next ;
+ \xer_ca$15 <= \xer_ca$15$next ;
always @(posedge coresync_clk)
xer_ca_ok <= \xer_ca_ok$next ;
always @(posedge coresync_clk)
- \xer_ov$13 <= \xer_ov$13$next ;
+ \xer_ov$14 <= \xer_ov$14$next ;
always @(posedge coresync_clk)
xer_ov_ok <= \xer_ov_ok$next ;
always @(posedge coresync_clk)
- \xer_so$12 <= \xer_so$12$next ;
+ \xer_so$13 <= \xer_so$13$next ;
always @(posedge coresync_clk)
xer_so_ok <= \xer_so_ok$next ;
always @(posedge coresync_clk)
- \fast1$11 <= \fast1$11$next ;
+ \fast1$12 <= \fast1$12$next ;
always @(posedge coresync_clk)
fast1_ok <= \fast1_ok$next ;
always @(posedge coresync_clk)
- \spr1$10 <= \spr1$10$next ;
+ \spr1$11 <= \spr1$11$next ;
always @(posedge coresync_clk)
spr1_ok <= \spr1_ok$next ;
always @(posedge coresync_clk)
always @(posedge coresync_clk)
\spr_op__sv_saturate$8 <= \spr_op__sv_saturate$8$next ;
always @(posedge coresync_clk)
- \spr_op__SV_Ptype$9 <= \spr_op__SV_Ptype$9$next ;
+ \spr_op__sv_ldstmode$9 <= \spr_op__sv_ldstmode$9$next ;
+ always @(posedge coresync_clk)
+ \spr_op__SV_Ptype$10 <= \spr_op__SV_Ptype$10$next ;
always @(posedge coresync_clk)
\muxid$1 <= \muxid$1$next ;
always @(posedge coresync_clk)
);
spr_main spr_main (
.fast1(spr_main_fast1),
- .\fast1$11 (\spr_main_fast1$25 ),
+ .\fast1$12 (\spr_main_fast1$27 ),
.fast1_ok(spr_main_fast1_ok),
.muxid(spr_main_muxid),
- .\muxid$1 (\spr_main_muxid$15 ),
+ .\muxid$1 (\spr_main_muxid$16 ),
.o(spr_main_o),
.o_ok(spr_main_o_ok),
.ra(spr_main_ra),
.spr1(spr_main_spr1),
- .\spr1$10 (\spr_main_spr1$24 ),
+ .\spr1$11 (\spr_main_spr1$26 ),
.spr1_ok(spr_main_spr1_ok),
.spr_op__SV_Ptype(spr_main_spr_op__SV_Ptype),
- .\spr_op__SV_Ptype$9 (\spr_main_spr_op__SV_Ptype$23 ),
+ .\spr_op__SV_Ptype$10 (\spr_main_spr_op__SV_Ptype$25 ),
.spr_op__fn_unit(spr_main_spr_op__fn_unit),
- .\spr_op__fn_unit$3 (\spr_main_spr_op__fn_unit$17 ),
+ .\spr_op__fn_unit$3 (\spr_main_spr_op__fn_unit$18 ),
.spr_op__insn(spr_main_spr_op__insn),
- .\spr_op__insn$4 (\spr_main_spr_op__insn$18 ),
+ .\spr_op__insn$4 (\spr_main_spr_op__insn$19 ),
.spr_op__insn_type(spr_main_spr_op__insn_type),
- .\spr_op__insn_type$2 (\spr_main_spr_op__insn_type$16 ),
+ .\spr_op__insn_type$2 (\spr_main_spr_op__insn_type$17 ),
.spr_op__is_32bit(spr_main_spr_op__is_32bit),
- .\spr_op__is_32bit$5 (\spr_main_spr_op__is_32bit$19 ),
+ .\spr_op__is_32bit$5 (\spr_main_spr_op__is_32bit$20 ),
+ .spr_op__sv_ldstmode(spr_main_spr_op__sv_ldstmode),
+ .\spr_op__sv_ldstmode$9 (\spr_main_spr_op__sv_ldstmode$24 ),
.spr_op__sv_pred_dz(spr_main_spr_op__sv_pred_dz),
- .\spr_op__sv_pred_dz$7 (\spr_main_spr_op__sv_pred_dz$21 ),
+ .\spr_op__sv_pred_dz$7 (\spr_main_spr_op__sv_pred_dz$22 ),
.spr_op__sv_pred_sz(spr_main_spr_op__sv_pred_sz),
- .\spr_op__sv_pred_sz$6 (\spr_main_spr_op__sv_pred_sz$20 ),
+ .\spr_op__sv_pred_sz$6 (\spr_main_spr_op__sv_pred_sz$21 ),
.spr_op__sv_saturate(spr_main_spr_op__sv_saturate),
- .\spr_op__sv_saturate$8 (\spr_main_spr_op__sv_saturate$22 ),
+ .\spr_op__sv_saturate$8 (\spr_main_spr_op__sv_saturate$23 ),
.xer_ca(spr_main_xer_ca),
- .\xer_ca$14 (\spr_main_xer_ca$28 ),
+ .\xer_ca$15 (\spr_main_xer_ca$30 ),
.xer_ca_ok(spr_main_xer_ca_ok),
.xer_ov(spr_main_xer_ov),
- .\xer_ov$13 (\spr_main_xer_ov$27 ),
+ .\xer_ov$14 (\spr_main_xer_ov$29 ),
.xer_ov_ok(spr_main_xer_ov_ok),
.xer_so(spr_main_xer_so),
- .\xer_so$12 (\spr_main_xer_so$26 ),
+ .\xer_so$13 (\spr_main_xer_so$28 ),
.xer_so_ok(spr_main_xer_so_ok)
);
always @* begin
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \muxid$1$next = \muxid$32 ;
+ \muxid$1$next = \muxid$34 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \muxid$1$next = \muxid$32 ;
+ \muxid$1$next = \muxid$34 ;
endcase
end
always @* begin
\spr_op__sv_pred_sz$6$next = \spr_op__sv_pred_sz$6 ;
\spr_op__sv_pred_dz$7$next = \spr_op__sv_pred_dz$7 ;
\spr_op__sv_saturate$8$next = \spr_op__sv_saturate$8 ;
- \spr_op__SV_Ptype$9$next = \spr_op__SV_Ptype$9 ;
+ \spr_op__sv_ldstmode$9$next = \spr_op__sv_ldstmode$9 ;
+ \spr_op__SV_Ptype$10$next = \spr_op__SV_Ptype$10 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \spr_op__SV_Ptype$9$next , \spr_op__sv_saturate$8$next , \spr_op__sv_pred_dz$7$next , \spr_op__sv_pred_sz$6$next , \spr_op__is_32bit$5$next , \spr_op__insn$4$next , \spr_op__fn_unit$3$next , \spr_op__insn_type$2$next } = { \spr_op__SV_Ptype$40 , \spr_op__sv_saturate$39 , \spr_op__sv_pred_dz$38 , \spr_op__sv_pred_sz$37 , \spr_op__is_32bit$36 , \spr_op__insn$35 , \spr_op__fn_unit$34 , \spr_op__insn_type$33 };
+ { \spr_op__SV_Ptype$10$next , \spr_op__sv_ldstmode$9$next , \spr_op__sv_saturate$8$next , \spr_op__sv_pred_dz$7$next , \spr_op__sv_pred_sz$6$next , \spr_op__is_32bit$5$next , \spr_op__insn$4$next , \spr_op__fn_unit$3$next , \spr_op__insn_type$2$next } = { \spr_op__SV_Ptype$43 , \spr_op__sv_ldstmode$42 , \spr_op__sv_saturate$41 , \spr_op__sv_pred_dz$40 , \spr_op__sv_pred_sz$39 , \spr_op__is_32bit$38 , \spr_op__insn$37 , \spr_op__fn_unit$36 , \spr_op__insn_type$35 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \spr_op__SV_Ptype$9$next , \spr_op__sv_saturate$8$next , \spr_op__sv_pred_dz$7$next , \spr_op__sv_pred_sz$6$next , \spr_op__is_32bit$5$next , \spr_op__insn$4$next , \spr_op__fn_unit$3$next , \spr_op__insn_type$2$next } = { \spr_op__SV_Ptype$40 , \spr_op__sv_saturate$39 , \spr_op__sv_pred_dz$38 , \spr_op__sv_pred_sz$37 , \spr_op__is_32bit$36 , \spr_op__insn$35 , \spr_op__fn_unit$34 , \spr_op__insn_type$33 };
+ { \spr_op__SV_Ptype$10$next , \spr_op__sv_ldstmode$9$next , \spr_op__sv_saturate$8$next , \spr_op__sv_pred_dz$7$next , \spr_op__sv_pred_sz$6$next , \spr_op__is_32bit$5$next , \spr_op__insn$4$next , \spr_op__fn_unit$3$next , \spr_op__insn_type$2$next } = { \spr_op__SV_Ptype$43 , \spr_op__sv_ldstmode$42 , \spr_op__sv_saturate$41 , \spr_op__sv_pred_dz$40 , \spr_op__sv_pred_sz$39 , \spr_op__is_32bit$38 , \spr_op__insn$37 , \spr_op__fn_unit$36 , \spr_op__insn_type$35 };
endcase
end
always @* begin
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \o_ok$next , \o$next } = { \o_ok$42 , \o$41 };
+ { \o_ok$next , \o$next } = { \o_ok$45 , \o$44 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \o_ok$next , \o$next } = { \o_ok$42 , \o$41 };
+ { \o_ok$next , \o$next } = { \o_ok$45 , \o$44 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
end
always @* begin
if (\initial ) begin end
- \spr1$10$next = \spr1$10 ;
+ \spr1$11$next = \spr1$11 ;
\spr1_ok$next = spr1_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \spr1_ok$next , \spr1$10$next } = { \spr1_ok$44 , \spr1$43 };
+ { \spr1_ok$next , \spr1$11$next } = { \spr1_ok$47 , \spr1$46 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \spr1_ok$next , \spr1$10$next } = { \spr1_ok$44 , \spr1$43 };
+ { \spr1_ok$next , \spr1$11$next } = { \spr1_ok$47 , \spr1$46 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
end
always @* begin
if (\initial ) begin end
- \fast1$11$next = \fast1$11 ;
+ \fast1$12$next = \fast1$12 ;
\fast1_ok$next = fast1_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \fast1_ok$next , \fast1$11$next } = { \fast1_ok$46 , \fast1$45 };
+ { \fast1_ok$next , \fast1$12$next } = { \fast1_ok$49 , \fast1$48 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \fast1_ok$next , \fast1$11$next } = { \fast1_ok$46 , \fast1$45 };
+ { \fast1_ok$next , \fast1$12$next } = { \fast1_ok$49 , \fast1$48 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
end
always @* begin
if (\initial ) begin end
- \xer_so$12$next = \xer_so$12 ;
+ \xer_so$13$next = \xer_so$13 ;
\xer_so_ok$next = xer_so_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \xer_so_ok$next , \xer_so$12$next } = { \xer_so_ok$48 , \xer_so$47 };
+ { \xer_so_ok$next , \xer_so$13$next } = { \xer_so_ok$51 , \xer_so$50 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \xer_so_ok$next , \xer_so$12$next } = { \xer_so_ok$48 , \xer_so$47 };
+ { \xer_so_ok$next , \xer_so$13$next } = { \xer_so_ok$51 , \xer_so$50 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
end
always @* begin
if (\initial ) begin end
- \xer_ov$13$next = \xer_ov$13 ;
+ \xer_ov$14$next = \xer_ov$14 ;
\xer_ov_ok$next = xer_ov_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \xer_ov_ok$next , \xer_ov$13$next } = { \xer_ov_ok$50 , \xer_ov$49 };
+ { \xer_ov_ok$next , \xer_ov$14$next } = { \xer_ov_ok$53 , \xer_ov$52 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \xer_ov_ok$next , \xer_ov$13$next } = { \xer_ov_ok$50 , \xer_ov$49 };
+ { \xer_ov_ok$next , \xer_ov$14$next } = { \xer_ov_ok$53 , \xer_ov$52 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
end
always @* begin
if (\initial ) begin end
- \xer_ca$14$next = \xer_ca$14 ;
+ \xer_ca$15$next = \xer_ca$15 ;
\xer_ca_ok$next = xer_ca_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \xer_ca_ok$next , \xer_ca$14$next } = { \xer_ca_ok$52 , \xer_ca$51 };
+ { \xer_ca_ok$next , \xer_ca$15$next } = { \xer_ca_ok$55 , \xer_ca$54 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \xer_ca_ok$next , \xer_ca$14$next } = { \xer_ca_ok$52 , \xer_ca$51 };
+ { \xer_ca_ok$next , \xer_ca$15$next } = { \xer_ca_ok$55 , \xer_ca$54 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
end
assign p_ready_o = n_i_rdy_data;
assign n_valid_o = r_busy;
- assign { \xer_ca_ok$52 , \xer_ca$51 } = { spr_main_xer_ca_ok, \spr_main_xer_ca$28 };
- assign { \xer_ov_ok$50 , \xer_ov$49 } = { spr_main_xer_ov_ok, \spr_main_xer_ov$27 };
- assign { \xer_so_ok$48 , \xer_so$47 } = { spr_main_xer_so_ok, \spr_main_xer_so$26 };
- assign { \fast1_ok$46 , \fast1$45 } = { spr_main_fast1_ok, \spr_main_fast1$25 };
- assign { \spr1_ok$44 , \spr1$43 } = { spr_main_spr1_ok, \spr_main_spr1$24 };
- assign { \o_ok$42 , \o$41 } = { spr_main_o_ok, spr_main_o };
- assign { \spr_op__SV_Ptype$40 , \spr_op__sv_saturate$39 , \spr_op__sv_pred_dz$38 , \spr_op__sv_pred_sz$37 , \spr_op__is_32bit$36 , \spr_op__insn$35 , \spr_op__fn_unit$34 , \spr_op__insn_type$33 } = { \spr_main_spr_op__SV_Ptype$23 , \spr_main_spr_op__sv_saturate$22 , \spr_main_spr_op__sv_pred_dz$21 , \spr_main_spr_op__sv_pred_sz$20 , \spr_main_spr_op__is_32bit$19 , \spr_main_spr_op__insn$18 , \spr_main_spr_op__fn_unit$17 , \spr_main_spr_op__insn_type$16 };
- assign \muxid$32 = \spr_main_muxid$15 ;
- assign p_valid_i_p_ready_o = \$30 ;
+ assign { \xer_ca_ok$55 , \xer_ca$54 } = { spr_main_xer_ca_ok, \spr_main_xer_ca$30 };
+ assign { \xer_ov_ok$53 , \xer_ov$52 } = { spr_main_xer_ov_ok, \spr_main_xer_ov$29 };
+ assign { \xer_so_ok$51 , \xer_so$50 } = { spr_main_xer_so_ok, \spr_main_xer_so$28 };
+ assign { \fast1_ok$49 , \fast1$48 } = { spr_main_fast1_ok, \spr_main_fast1$27 };
+ assign { \spr1_ok$47 , \spr1$46 } = { spr_main_spr1_ok, \spr_main_spr1$26 };
+ assign { \o_ok$45 , \o$44 } = { spr_main_o_ok, spr_main_o };
+ assign { \spr_op__SV_Ptype$43 , \spr_op__sv_ldstmode$42 , \spr_op__sv_saturate$41 , \spr_op__sv_pred_dz$40 , \spr_op__sv_pred_sz$39 , \spr_op__is_32bit$38 , \spr_op__insn$37 , \spr_op__fn_unit$36 , \spr_op__insn_type$35 } = { \spr_main_spr_op__SV_Ptype$25 , \spr_main_spr_op__sv_ldstmode$24 , \spr_main_spr_op__sv_saturate$23 , \spr_main_spr_op__sv_pred_dz$22 , \spr_main_spr_op__sv_pred_sz$21 , \spr_main_spr_op__is_32bit$20 , \spr_main_spr_op__insn$19 , \spr_main_spr_op__fn_unit$18 , \spr_main_spr_op__insn_type$17 };
+ assign \muxid$34 = \spr_main_muxid$16 ;
+ assign p_valid_i_p_ready_o = \$32 ;
assign n_i_rdy_data = n_ready_i;
- assign \p_valid_i$29 = p_valid_i;
+ assign \p_valid_i$31 = p_valid_i;
assign spr_main_xer_ca = xer_ca;
assign spr_main_xer_ov = xer_ov;
assign spr_main_xer_so = xer_so;
assign spr_main_fast1 = fast1;
assign spr_main_spr1 = spr1;
assign spr_main_ra = ra;
- assign { spr_main_spr_op__SV_Ptype, spr_main_spr_op__sv_saturate, spr_main_spr_op__sv_pred_dz, spr_main_spr_op__sv_pred_sz, spr_main_spr_op__is_32bit, spr_main_spr_op__insn, spr_main_spr_op__fn_unit, spr_main_spr_op__insn_type } = { spr_op__SV_Ptype, spr_op__sv_saturate, spr_op__sv_pred_dz, spr_op__sv_pred_sz, spr_op__is_32bit, spr_op__insn, spr_op__fn_unit, spr_op__insn_type };
+ assign { spr_main_spr_op__SV_Ptype, spr_main_spr_op__sv_ldstmode, spr_main_spr_op__sv_saturate, spr_main_spr_op__sv_pred_dz, spr_main_spr_op__sv_pred_sz, spr_main_spr_op__is_32bit, spr_main_spr_op__insn, spr_main_spr_op__fn_unit, spr_main_spr_op__insn_type } = { spr_op__SV_Ptype, spr_op__sv_ldstmode, spr_op__sv_saturate, spr_op__sv_pred_dz, spr_op__sv_pred_sz, spr_op__is_32bit, spr_op__insn, spr_op__fn_unit, spr_op__insn_type };
assign spr_main_muxid = muxid;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1" *)
(* generator = "nMigen" *)
-module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, alu_op__sv_pred_sz, alu_op__sv_pred_dz, alu_op__sv_saturate, alu_op__SV_Ptype, o, o_ok, cr_a, cr_a_ok, xer_ca, xer_ca_ok, xer_ov, xer_ov_ok, xer_so, xer_so_ok, p_valid_i, p_ready_o, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , \alu_op__sv_pred_sz$20 , \alu_op__sv_pred_dz$21 , \alu_op__sv_saturate$22 , \alu_op__SV_Ptype$23 , ra, rb, \xer_so$24 , \xer_ca$25 , coresync_clk);
+module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, alu_op__sv_pred_sz, alu_op__sv_pred_dz, alu_op__sv_saturate, alu_op__sv_ldstmode, alu_op__SV_Ptype, o, o_ok, cr_a, cr_a_ok, xer_ca, xer_ca_ok, xer_ov, xer_ov_ok, xer_so, xer_so_ok, p_valid_i, p_ready_o, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , \alu_op__sv_pred_sz$20 , \alu_op__sv_pred_dz$21 , \alu_op__sv_saturate$22 , \alu_op__sv_ldstmode$23 , \alu_op__SV_Ptype$24 , ra, rb, \xer_so$25 , \xer_ca$26 , coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
- wire \$79 ;
+ wire \$82 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \alu_op__SV_Ptype$103 ;
+ wire [1:0] \alu_op__SV_Ptype$107 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- input [1:0] \alu_op__SV_Ptype$23 ;
+ input [1:0] \alu_op__SV_Ptype$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [1:0] \alu_op__SV_Ptype$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output [3:0] alu_op__data_len;
reg [3:0] alu_op__data_len = 4'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- input [3:0] \alu_op__data_len$18 ;
+ wire [3:0] \alu_op__data_len$101 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [3:0] \alu_op__data_len$98 ;
+ input [3:0] \alu_op__data_len$18 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [3:0] \alu_op__data_len$next ;
(* enum_base_type = "Function" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \alu_op__fn_unit$83 ;
+ wire [14:0] \alu_op__fn_unit$86 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [14:0] \alu_op__fn_unit$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] \alu_op__imm_data__data$4 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \alu_op__imm_data__data$84 ;
+ wire [63:0] \alu_op__imm_data__data$87 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [63:0] \alu_op__imm_data__data$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \alu_op__imm_data__ok$5 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__imm_data__ok$85 ;
+ wire \alu_op__imm_data__ok$88 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_op__imm_data__ok$next ;
(* enum_base_type = "CryIn" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \alu_op__input_carry$94 ;
+ wire [1:0] \alu_op__input_carry$97 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [1:0] \alu_op__input_carry$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output [31:0] alu_op__insn;
reg [31:0] alu_op__insn = 32'd0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- input [31:0] \alu_op__insn$19 ;
+ wire [31:0] \alu_op__insn$102 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \alu_op__insn$99 ;
+ input [31:0] \alu_op__insn$19 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [31:0] \alu_op__insn$next ;
(* enum_base_type = "MicrOp" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \alu_op__insn_type$82 ;
+ wire [6:0] \alu_op__insn_type$85 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [6:0] \alu_op__insn_type$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \alu_op__invert_in$10 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__invert_in$90 ;
+ wire \alu_op__invert_in$93 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_op__invert_in$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \alu_op__invert_out$12 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__invert_out$92 ;
+ wire \alu_op__invert_out$95 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_op__invert_out$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \alu_op__is_32bit$16 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__is_32bit$96 ;
+ wire \alu_op__is_32bit$99 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_op__is_32bit$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output alu_op__is_signed;
reg alu_op__is_signed = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- input \alu_op__is_signed$17 ;
+ wire \alu_op__is_signed$100 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__is_signed$97 ;
+ input \alu_op__is_signed$17 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_op__is_signed$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \alu_op__oe__oe$8 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__oe__oe$88 ;
+ wire \alu_op__oe__oe$91 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_op__oe__oe$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output alu_op__oe__ok;
reg alu_op__oe__ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__oe__ok$89 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \alu_op__oe__ok$9 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire \alu_op__oe__ok$92 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_op__oe__ok$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output alu_op__output_carry;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \alu_op__output_carry$15 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__output_carry$95 ;
+ wire \alu_op__output_carry$98 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_op__output_carry$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \alu_op__rc__ok$7 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__rc__ok$87 ;
+ wire \alu_op__rc__ok$90 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_op__rc__ok$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \alu_op__rc__rc$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__rc__rc$86 ;
+ wire \alu_op__rc__rc$89 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_op__rc__rc$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] alu_op__sv_ldstmode;
+ reg [1:0] alu_op__sv_ldstmode = 2'h0;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \alu_op__sv_ldstmode$106 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] \alu_op__sv_ldstmode$23 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \alu_op__sv_ldstmode$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output alu_op__sv_pred_dz;
reg alu_op__sv_pred_dz = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__sv_pred_dz$101 ;
+ wire \alu_op__sv_pred_dz$104 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \alu_op__sv_pred_dz$21 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output alu_op__sv_pred_sz;
reg alu_op__sv_pred_sz = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__sv_pred_sz$100 ;
+ wire \alu_op__sv_pred_sz$103 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \alu_op__sv_pred_sz$20 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \alu_op__sv_saturate$102 ;
+ wire [1:0] \alu_op__sv_saturate$105 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \alu_op__write_cr0$13 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__write_cr0$93 ;
+ wire \alu_op__write_cr0$96 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_op__write_cr0$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \alu_op__zero_a$11 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__zero_a$91 ;
+ wire \alu_op__zero_a$94 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_op__zero_a$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output [3:0] cr_a;
reg [3:0] cr_a = 4'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [3:0] \cr_a$106 ;
+ wire [3:0] \cr_a$110 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg [3:0] \cr_a$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output cr_a_ok;
reg cr_a_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \cr_a_ok$107 ;
+ wire \cr_a_ok$111 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \cr_a_ok$next ;
(* enum_base_type = "SVPtype" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \input_alu_op__SV_Ptype$48 ;
+ wire [1:0] \input_alu_op__SV_Ptype$50 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [3:0] input_alu_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [3:0] \input_alu_op__data_len$43 ;
+ wire [3:0] \input_alu_op__data_len$44 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \input_alu_op__fn_unit$28 ;
+ wire [14:0] \input_alu_op__fn_unit$29 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] input_alu_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \input_alu_op__imm_data__data$29 ;
+ wire [63:0] \input_alu_op__imm_data__data$30 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_alu_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_alu_op__imm_data__ok$30 ;
+ wire \input_alu_op__imm_data__ok$31 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \input_alu_op__input_carry$39 ;
+ wire [1:0] \input_alu_op__input_carry$40 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] input_alu_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \input_alu_op__insn$44 ;
+ wire [31:0] \input_alu_op__insn$45 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \input_alu_op__insn_type$27 ;
+ wire [6:0] \input_alu_op__insn_type$28 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_alu_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_alu_op__invert_in$35 ;
+ wire \input_alu_op__invert_in$36 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_alu_op__invert_out;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_alu_op__invert_out$37 ;
+ wire \input_alu_op__invert_out$38 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_alu_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_alu_op__is_32bit$41 ;
+ wire \input_alu_op__is_32bit$42 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_alu_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_alu_op__is_signed$42 ;
+ wire \input_alu_op__is_signed$43 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_alu_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_alu_op__oe__oe$33 ;
+ wire \input_alu_op__oe__oe$34 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_alu_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_alu_op__oe__ok$34 ;
+ wire \input_alu_op__oe__ok$35 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_alu_op__output_carry;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_alu_op__output_carry$40 ;
+ wire \input_alu_op__output_carry$41 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_alu_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_alu_op__rc__ok$32 ;
+ wire \input_alu_op__rc__ok$33 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_alu_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_alu_op__rc__rc$31 ;
+ wire \input_alu_op__rc__rc$32 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] input_alu_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \input_alu_op__sv_ldstmode$49 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_alu_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_alu_op__sv_pred_dz$46 ;
+ wire \input_alu_op__sv_pred_dz$47 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_alu_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_alu_op__sv_pred_sz$45 ;
+ wire \input_alu_op__sv_pred_sz$46 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \input_alu_op__sv_saturate$47 ;
+ wire [1:0] \input_alu_op__sv_saturate$48 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_alu_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_alu_op__write_cr0$38 ;
+ wire \input_alu_op__write_cr0$39 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_alu_op__zero_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_alu_op__zero_a$36 ;
+ wire \input_alu_op__zero_a$37 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] input_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \input_muxid$26 ;
+ wire [1:0] \input_muxid$27 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] input_ra;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \input_ra$49 ;
+ wire [63:0] \input_ra$51 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] input_rb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \input_rb$50 ;
+ wire [63:0] \input_rb$52 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [1:0] input_xer_ca;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [1:0] \input_xer_ca$52 ;
+ wire [1:0] \input_xer_ca$54 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire input_xer_so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire \input_xer_so$51 ;
+ wire \input_xer_so$53 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \main_alu_op__SV_Ptype$75 ;
+ wire [1:0] \main_alu_op__SV_Ptype$78 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [3:0] main_alu_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [3:0] \main_alu_op__data_len$70 ;
+ wire [3:0] \main_alu_op__data_len$72 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \main_alu_op__fn_unit$55 ;
+ wire [14:0] \main_alu_op__fn_unit$57 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] main_alu_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \main_alu_op__imm_data__data$56 ;
+ wire [63:0] \main_alu_op__imm_data__data$58 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_alu_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_alu_op__imm_data__ok$57 ;
+ wire \main_alu_op__imm_data__ok$59 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \main_alu_op__input_carry$66 ;
+ wire [1:0] \main_alu_op__input_carry$68 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] main_alu_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \main_alu_op__insn$71 ;
+ wire [31:0] \main_alu_op__insn$73 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \main_alu_op__insn_type$54 ;
+ wire [6:0] \main_alu_op__insn_type$56 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_alu_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_alu_op__invert_in$62 ;
+ wire \main_alu_op__invert_in$64 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_alu_op__invert_out;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_alu_op__invert_out$64 ;
+ wire \main_alu_op__invert_out$66 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_alu_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_alu_op__is_32bit$68 ;
+ wire \main_alu_op__is_32bit$70 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_alu_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_alu_op__is_signed$69 ;
+ wire \main_alu_op__is_signed$71 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_alu_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_alu_op__oe__oe$60 ;
+ wire \main_alu_op__oe__oe$62 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_alu_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_alu_op__oe__ok$61 ;
+ wire \main_alu_op__oe__ok$63 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_alu_op__output_carry;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_alu_op__output_carry$67 ;
+ wire \main_alu_op__output_carry$69 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_alu_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_alu_op__rc__ok$59 ;
+ wire \main_alu_op__rc__ok$61 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_alu_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_alu_op__rc__rc$58 ;
+ wire \main_alu_op__rc__rc$60 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] main_alu_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \main_alu_op__sv_ldstmode$77 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_alu_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_alu_op__sv_pred_dz$73 ;
+ wire \main_alu_op__sv_pred_dz$75 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_alu_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_alu_op__sv_pred_sz$72 ;
+ wire \main_alu_op__sv_pred_sz$74 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \main_alu_op__sv_saturate$74 ;
+ wire [1:0] \main_alu_op__sv_saturate$76 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_alu_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_alu_op__write_cr0$65 ;
+ wire \main_alu_op__write_cr0$67 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_alu_op__zero_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_alu_op__zero_a$63 ;
+ wire \main_alu_op__zero_a$65 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [3:0] main_cr_a;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] main_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \main_muxid$53 ;
+ wire [1:0] \main_muxid$55 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [63:0] main_o;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [1:0] main_xer_ca;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [1:0] \main_xer_ca$76 ;
+ wire [1:0] \main_xer_ca$79 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire main_xer_ca_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire main_xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \main_xer_so$77 ;
+ wire \main_xer_so$80 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
output [1:0] muxid;
reg [1:0] muxid = 2'h0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
input [1:0] \muxid$1 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \muxid$81 ;
+ wire [1:0] \muxid$84 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
reg [1:0] \muxid$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
output [63:0] o;
reg [63:0] o = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \o$104 ;
+ wire [63:0] \o$108 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg [63:0] \o$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output o_ok;
reg o_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \o_ok$105 ;
+ wire \o_ok$109 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \o_ok$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
input p_valid_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
- wire \p_valid_i$78 ;
+ wire \p_valid_i$81 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
wire p_valid_i_p_ready_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
output [1:0] xer_ca;
reg [1:0] xer_ca = 2'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [1:0] \xer_ca$108 ;
+ wire [1:0] \xer_ca$112 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- input [1:0] \xer_ca$25 ;
+ input [1:0] \xer_ca$26 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg [1:0] \xer_ca$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_ca_ok;
reg xer_ca_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_ca_ok$109 ;
+ wire \xer_ca_ok$113 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \xer_ca_ok$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output [1:0] xer_ov;
reg [1:0] xer_ov = 2'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [1:0] \xer_ov$110 ;
+ wire [1:0] \xer_ov$114 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg [1:0] \xer_ov$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_ov_ok;
reg xer_ov_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_ov_ok$111 ;
+ wire \xer_ov_ok$115 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \xer_ov_ok$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_so;
reg xer_so = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_so$112 ;
+ wire \xer_so$116 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- input \xer_so$24 ;
+ input \xer_so$25 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \xer_so$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_so_ok;
reg xer_so_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_so_ok$113 ;
+ wire \xer_so_ok$117 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_so_ok$114 ;
+ wire \xer_so_ok$118 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \xer_so_ok$next ;
- assign \$79 = \p_valid_i$78 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
+ assign \$82 = \p_valid_i$81 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
always @(posedge coresync_clk)
xer_so <= \xer_so$next ;
always @(posedge coresync_clk)
alu_op__sv_pred_dz <= \alu_op__sv_pred_dz$next ;
always @(posedge coresync_clk)
alu_op__sv_saturate <= \alu_op__sv_saturate$next ;
+ always @(posedge coresync_clk)
+ alu_op__sv_ldstmode <= \alu_op__sv_ldstmode$next ;
always @(posedge coresync_clk)
alu_op__SV_Ptype <= \alu_op__SV_Ptype$next ;
always @(posedge coresync_clk)
r_busy <= \r_busy$next ;
\input \input (
.alu_op__SV_Ptype(input_alu_op__SV_Ptype),
- .\alu_op__SV_Ptype$23 (\input_alu_op__SV_Ptype$48 ),
+ .\alu_op__SV_Ptype$24 (\input_alu_op__SV_Ptype$50 ),
.alu_op__data_len(input_alu_op__data_len),
- .\alu_op__data_len$18 (\input_alu_op__data_len$43 ),
+ .\alu_op__data_len$18 (\input_alu_op__data_len$44 ),
.alu_op__fn_unit(input_alu_op__fn_unit),
- .\alu_op__fn_unit$3 (\input_alu_op__fn_unit$28 ),
+ .\alu_op__fn_unit$3 (\input_alu_op__fn_unit$29 ),
.alu_op__imm_data__data(input_alu_op__imm_data__data),
- .\alu_op__imm_data__data$4 (\input_alu_op__imm_data__data$29 ),
+ .\alu_op__imm_data__data$4 (\input_alu_op__imm_data__data$30 ),
.alu_op__imm_data__ok(input_alu_op__imm_data__ok),
- .\alu_op__imm_data__ok$5 (\input_alu_op__imm_data__ok$30 ),
+ .\alu_op__imm_data__ok$5 (\input_alu_op__imm_data__ok$31 ),
.alu_op__input_carry(input_alu_op__input_carry),
- .\alu_op__input_carry$14 (\input_alu_op__input_carry$39 ),
+ .\alu_op__input_carry$14 (\input_alu_op__input_carry$40 ),
.alu_op__insn(input_alu_op__insn),
- .\alu_op__insn$19 (\input_alu_op__insn$44 ),
+ .\alu_op__insn$19 (\input_alu_op__insn$45 ),
.alu_op__insn_type(input_alu_op__insn_type),
- .\alu_op__insn_type$2 (\input_alu_op__insn_type$27 ),
+ .\alu_op__insn_type$2 (\input_alu_op__insn_type$28 ),
.alu_op__invert_in(input_alu_op__invert_in),
- .\alu_op__invert_in$10 (\input_alu_op__invert_in$35 ),
+ .\alu_op__invert_in$10 (\input_alu_op__invert_in$36 ),
.alu_op__invert_out(input_alu_op__invert_out),
- .\alu_op__invert_out$12 (\input_alu_op__invert_out$37 ),
+ .\alu_op__invert_out$12 (\input_alu_op__invert_out$38 ),
.alu_op__is_32bit(input_alu_op__is_32bit),
- .\alu_op__is_32bit$16 (\input_alu_op__is_32bit$41 ),
+ .\alu_op__is_32bit$16 (\input_alu_op__is_32bit$42 ),
.alu_op__is_signed(input_alu_op__is_signed),
- .\alu_op__is_signed$17 (\input_alu_op__is_signed$42 ),
+ .\alu_op__is_signed$17 (\input_alu_op__is_signed$43 ),
.alu_op__oe__oe(input_alu_op__oe__oe),
- .\alu_op__oe__oe$8 (\input_alu_op__oe__oe$33 ),
+ .\alu_op__oe__oe$8 (\input_alu_op__oe__oe$34 ),
.alu_op__oe__ok(input_alu_op__oe__ok),
- .\alu_op__oe__ok$9 (\input_alu_op__oe__ok$34 ),
+ .\alu_op__oe__ok$9 (\input_alu_op__oe__ok$35 ),
.alu_op__output_carry(input_alu_op__output_carry),
- .\alu_op__output_carry$15 (\input_alu_op__output_carry$40 ),
+ .\alu_op__output_carry$15 (\input_alu_op__output_carry$41 ),
.alu_op__rc__ok(input_alu_op__rc__ok),
- .\alu_op__rc__ok$7 (\input_alu_op__rc__ok$32 ),
+ .\alu_op__rc__ok$7 (\input_alu_op__rc__ok$33 ),
.alu_op__rc__rc(input_alu_op__rc__rc),
- .\alu_op__rc__rc$6 (\input_alu_op__rc__rc$31 ),
+ .\alu_op__rc__rc$6 (\input_alu_op__rc__rc$32 ),
+ .alu_op__sv_ldstmode(input_alu_op__sv_ldstmode),
+ .\alu_op__sv_ldstmode$23 (\input_alu_op__sv_ldstmode$49 ),
.alu_op__sv_pred_dz(input_alu_op__sv_pred_dz),
- .\alu_op__sv_pred_dz$21 (\input_alu_op__sv_pred_dz$46 ),
+ .\alu_op__sv_pred_dz$21 (\input_alu_op__sv_pred_dz$47 ),
.alu_op__sv_pred_sz(input_alu_op__sv_pred_sz),
- .\alu_op__sv_pred_sz$20 (\input_alu_op__sv_pred_sz$45 ),
+ .\alu_op__sv_pred_sz$20 (\input_alu_op__sv_pred_sz$46 ),
.alu_op__sv_saturate(input_alu_op__sv_saturate),
- .\alu_op__sv_saturate$22 (\input_alu_op__sv_saturate$47 ),
+ .\alu_op__sv_saturate$22 (\input_alu_op__sv_saturate$48 ),
.alu_op__write_cr0(input_alu_op__write_cr0),
- .\alu_op__write_cr0$13 (\input_alu_op__write_cr0$38 ),
+ .\alu_op__write_cr0$13 (\input_alu_op__write_cr0$39 ),
.alu_op__zero_a(input_alu_op__zero_a),
- .\alu_op__zero_a$11 (\input_alu_op__zero_a$36 ),
+ .\alu_op__zero_a$11 (\input_alu_op__zero_a$37 ),
.muxid(input_muxid),
- .\muxid$1 (\input_muxid$26 ),
+ .\muxid$1 (\input_muxid$27 ),
.ra(input_ra),
- .\ra$24 (\input_ra$49 ),
+ .\ra$25 (\input_ra$51 ),
.rb(input_rb),
- .\rb$25 (\input_rb$50 ),
+ .\rb$26 (\input_rb$52 ),
.xer_ca(input_xer_ca),
- .\xer_ca$27 (\input_xer_ca$52 ),
+ .\xer_ca$28 (\input_xer_ca$54 ),
.xer_so(input_xer_so),
- .\xer_so$26 (\input_xer_so$51 )
+ .\xer_so$27 (\input_xer_so$53 )
);
main main (
.alu_op__SV_Ptype(main_alu_op__SV_Ptype),
- .\alu_op__SV_Ptype$23 (\main_alu_op__SV_Ptype$75 ),
+ .\alu_op__SV_Ptype$24 (\main_alu_op__SV_Ptype$78 ),
.alu_op__data_len(main_alu_op__data_len),
- .\alu_op__data_len$18 (\main_alu_op__data_len$70 ),
+ .\alu_op__data_len$18 (\main_alu_op__data_len$72 ),
.alu_op__fn_unit(main_alu_op__fn_unit),
- .\alu_op__fn_unit$3 (\main_alu_op__fn_unit$55 ),
+ .\alu_op__fn_unit$3 (\main_alu_op__fn_unit$57 ),
.alu_op__imm_data__data(main_alu_op__imm_data__data),
- .\alu_op__imm_data__data$4 (\main_alu_op__imm_data__data$56 ),
+ .\alu_op__imm_data__data$4 (\main_alu_op__imm_data__data$58 ),
.alu_op__imm_data__ok(main_alu_op__imm_data__ok),
- .\alu_op__imm_data__ok$5 (\main_alu_op__imm_data__ok$57 ),
+ .\alu_op__imm_data__ok$5 (\main_alu_op__imm_data__ok$59 ),
.alu_op__input_carry(main_alu_op__input_carry),
- .\alu_op__input_carry$14 (\main_alu_op__input_carry$66 ),
+ .\alu_op__input_carry$14 (\main_alu_op__input_carry$68 ),
.alu_op__insn(main_alu_op__insn),
- .\alu_op__insn$19 (\main_alu_op__insn$71 ),
+ .\alu_op__insn$19 (\main_alu_op__insn$73 ),
.alu_op__insn_type(main_alu_op__insn_type),
- .\alu_op__insn_type$2 (\main_alu_op__insn_type$54 ),
+ .\alu_op__insn_type$2 (\main_alu_op__insn_type$56 ),
.alu_op__invert_in(main_alu_op__invert_in),
- .\alu_op__invert_in$10 (\main_alu_op__invert_in$62 ),
+ .\alu_op__invert_in$10 (\main_alu_op__invert_in$64 ),
.alu_op__invert_out(main_alu_op__invert_out),
- .\alu_op__invert_out$12 (\main_alu_op__invert_out$64 ),
+ .\alu_op__invert_out$12 (\main_alu_op__invert_out$66 ),
.alu_op__is_32bit(main_alu_op__is_32bit),
- .\alu_op__is_32bit$16 (\main_alu_op__is_32bit$68 ),
+ .\alu_op__is_32bit$16 (\main_alu_op__is_32bit$70 ),
.alu_op__is_signed(main_alu_op__is_signed),
- .\alu_op__is_signed$17 (\main_alu_op__is_signed$69 ),
+ .\alu_op__is_signed$17 (\main_alu_op__is_signed$71 ),
.alu_op__oe__oe(main_alu_op__oe__oe),
- .\alu_op__oe__oe$8 (\main_alu_op__oe__oe$60 ),
+ .\alu_op__oe__oe$8 (\main_alu_op__oe__oe$62 ),
.alu_op__oe__ok(main_alu_op__oe__ok),
- .\alu_op__oe__ok$9 (\main_alu_op__oe__ok$61 ),
+ .\alu_op__oe__ok$9 (\main_alu_op__oe__ok$63 ),
.alu_op__output_carry(main_alu_op__output_carry),
- .\alu_op__output_carry$15 (\main_alu_op__output_carry$67 ),
+ .\alu_op__output_carry$15 (\main_alu_op__output_carry$69 ),
.alu_op__rc__ok(main_alu_op__rc__ok),
- .\alu_op__rc__ok$7 (\main_alu_op__rc__ok$59 ),
+ .\alu_op__rc__ok$7 (\main_alu_op__rc__ok$61 ),
.alu_op__rc__rc(main_alu_op__rc__rc),
- .\alu_op__rc__rc$6 (\main_alu_op__rc__rc$58 ),
+ .\alu_op__rc__rc$6 (\main_alu_op__rc__rc$60 ),
+ .alu_op__sv_ldstmode(main_alu_op__sv_ldstmode),
+ .\alu_op__sv_ldstmode$23 (\main_alu_op__sv_ldstmode$77 ),
.alu_op__sv_pred_dz(main_alu_op__sv_pred_dz),
- .\alu_op__sv_pred_dz$21 (\main_alu_op__sv_pred_dz$73 ),
+ .\alu_op__sv_pred_dz$21 (\main_alu_op__sv_pred_dz$75 ),
.alu_op__sv_pred_sz(main_alu_op__sv_pred_sz),
- .\alu_op__sv_pred_sz$20 (\main_alu_op__sv_pred_sz$72 ),
+ .\alu_op__sv_pred_sz$20 (\main_alu_op__sv_pred_sz$74 ),
.alu_op__sv_saturate(main_alu_op__sv_saturate),
- .\alu_op__sv_saturate$22 (\main_alu_op__sv_saturate$74 ),
+ .\alu_op__sv_saturate$22 (\main_alu_op__sv_saturate$76 ),
.alu_op__write_cr0(main_alu_op__write_cr0),
- .\alu_op__write_cr0$13 (\main_alu_op__write_cr0$65 ),
+ .\alu_op__write_cr0$13 (\main_alu_op__write_cr0$67 ),
.alu_op__zero_a(main_alu_op__zero_a),
- .\alu_op__zero_a$11 (\main_alu_op__zero_a$63 ),
+ .\alu_op__zero_a$11 (\main_alu_op__zero_a$65 ),
.cr_a(main_cr_a),
.cr_a_ok(main_cr_a_ok),
.muxid(main_muxid),
- .\muxid$1 (\main_muxid$53 ),
+ .\muxid$1 (\main_muxid$55 ),
.o(main_o),
.o_ok(main_o_ok),
.ra(main_ra),
.rb(main_rb),
.xer_ca(main_xer_ca),
- .\xer_ca$24 (\main_xer_ca$76 ),
+ .\xer_ca$25 (\main_xer_ca$79 ),
.xer_ca_ok(main_xer_ca_ok),
.xer_ov(main_xer_ov),
.xer_ov_ok(main_xer_ov_ok),
.xer_so(main_xer_so),
- .\xer_so$25 (\main_xer_so$77 )
+ .\xer_so$26 (\main_xer_so$80 )
);
\n$2 n (
.n_ready_i(n_ready_i),
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \o_ok$next , \o$next } = { \o_ok$105 , \o$104 };
+ { \o_ok$next , \o$next } = { \o_ok$109 , \o$108 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \o_ok$next , \o$next } = { \o_ok$105 , \o$104 };
+ { \o_ok$next , \o$next } = { \o_ok$109 , \o$108 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$107 , \cr_a$106 };
+ { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$111 , \cr_a$110 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$107 , \cr_a$106 };
+ { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$111 , \cr_a$110 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \xer_ca_ok$next , \xer_ca$next } = { \xer_ca_ok$109 , \xer_ca$108 };
+ { \xer_ca_ok$next , \xer_ca$next } = { \xer_ca_ok$113 , \xer_ca$112 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \xer_ca_ok$next , \xer_ca$next } = { \xer_ca_ok$109 , \xer_ca$108 };
+ { \xer_ca_ok$next , \xer_ca$next } = { \xer_ca_ok$113 , \xer_ca$112 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$111 , \xer_ov$110 };
+ { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$115 , \xer_ov$114 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$111 , \xer_ov$110 };
+ { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$115 , \xer_ov$114 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$113 , \xer_so$112 };
+ { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$117 , \xer_so$116 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$113 , \xer_so$112 };
+ { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$117 , \xer_so$116 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \muxid$next = \muxid$81 ;
+ \muxid$next = \muxid$84 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \muxid$next = \muxid$81 ;
+ \muxid$next = \muxid$84 ;
endcase
end
always @* begin
\alu_op__sv_pred_sz$next = alu_op__sv_pred_sz;
\alu_op__sv_pred_dz$next = alu_op__sv_pred_dz;
\alu_op__sv_saturate$next = alu_op__sv_saturate;
+ \alu_op__sv_ldstmode$next = alu_op__sv_ldstmode;
\alu_op__SV_Ptype$next = alu_op__SV_Ptype;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \alu_op__SV_Ptype$next , \alu_op__sv_saturate$next , \alu_op__sv_pred_dz$next , \alu_op__sv_pred_sz$next , \alu_op__insn$next , \alu_op__data_len$next , \alu_op__is_signed$next , \alu_op__is_32bit$next , \alu_op__output_carry$next , \alu_op__input_carry$next , \alu_op__write_cr0$next , \alu_op__invert_out$next , \alu_op__zero_a$next , \alu_op__invert_in$next , \alu_op__oe__ok$next , \alu_op__oe__oe$next , \alu_op__rc__ok$next , \alu_op__rc__rc$next , \alu_op__imm_data__ok$next , \alu_op__imm_data__data$next , \alu_op__fn_unit$next , \alu_op__insn_type$next } = { \alu_op__SV_Ptype$103 , \alu_op__sv_saturate$102 , \alu_op__sv_pred_dz$101 , \alu_op__sv_pred_sz$100 , \alu_op__insn$99 , \alu_op__data_len$98 , \alu_op__is_signed$97 , \alu_op__is_32bit$96 , \alu_op__output_carry$95 , \alu_op__input_carry$94 , \alu_op__write_cr0$93 , \alu_op__invert_out$92 , \alu_op__zero_a$91 , \alu_op__invert_in$90 , \alu_op__oe__ok$89 , \alu_op__oe__oe$88 , \alu_op__rc__ok$87 , \alu_op__rc__rc$86 , \alu_op__imm_data__ok$85 , \alu_op__imm_data__data$84 , \alu_op__fn_unit$83 , \alu_op__insn_type$82 };
+ { \alu_op__SV_Ptype$next , \alu_op__sv_ldstmode$next , \alu_op__sv_saturate$next , \alu_op__sv_pred_dz$next , \alu_op__sv_pred_sz$next , \alu_op__insn$next , \alu_op__data_len$next , \alu_op__is_signed$next , \alu_op__is_32bit$next , \alu_op__output_carry$next , \alu_op__input_carry$next , \alu_op__write_cr0$next , \alu_op__invert_out$next , \alu_op__zero_a$next , \alu_op__invert_in$next , \alu_op__oe__ok$next , \alu_op__oe__oe$next , \alu_op__rc__ok$next , \alu_op__rc__rc$next , \alu_op__imm_data__ok$next , \alu_op__imm_data__data$next , \alu_op__fn_unit$next , \alu_op__insn_type$next } = { \alu_op__SV_Ptype$107 , \alu_op__sv_ldstmode$106 , \alu_op__sv_saturate$105 , \alu_op__sv_pred_dz$104 , \alu_op__sv_pred_sz$103 , \alu_op__insn$102 , \alu_op__data_len$101 , \alu_op__is_signed$100 , \alu_op__is_32bit$99 , \alu_op__output_carry$98 , \alu_op__input_carry$97 , \alu_op__write_cr0$96 , \alu_op__invert_out$95 , \alu_op__zero_a$94 , \alu_op__invert_in$93 , \alu_op__oe__ok$92 , \alu_op__oe__oe$91 , \alu_op__rc__ok$90 , \alu_op__rc__rc$89 , \alu_op__imm_data__ok$88 , \alu_op__imm_data__data$87 , \alu_op__fn_unit$86 , \alu_op__insn_type$85 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \alu_op__SV_Ptype$next , \alu_op__sv_saturate$next , \alu_op__sv_pred_dz$next , \alu_op__sv_pred_sz$next , \alu_op__insn$next , \alu_op__data_len$next , \alu_op__is_signed$next , \alu_op__is_32bit$next , \alu_op__output_carry$next , \alu_op__input_carry$next , \alu_op__write_cr0$next , \alu_op__invert_out$next , \alu_op__zero_a$next , \alu_op__invert_in$next , \alu_op__oe__ok$next , \alu_op__oe__oe$next , \alu_op__rc__ok$next , \alu_op__rc__rc$next , \alu_op__imm_data__ok$next , \alu_op__imm_data__data$next , \alu_op__fn_unit$next , \alu_op__insn_type$next } = { \alu_op__SV_Ptype$103 , \alu_op__sv_saturate$102 , \alu_op__sv_pred_dz$101 , \alu_op__sv_pred_sz$100 , \alu_op__insn$99 , \alu_op__data_len$98 , \alu_op__is_signed$97 , \alu_op__is_32bit$96 , \alu_op__output_carry$95 , \alu_op__input_carry$94 , \alu_op__write_cr0$93 , \alu_op__invert_out$92 , \alu_op__zero_a$91 , \alu_op__invert_in$90 , \alu_op__oe__ok$89 , \alu_op__oe__oe$88 , \alu_op__rc__ok$87 , \alu_op__rc__rc$86 , \alu_op__imm_data__ok$85 , \alu_op__imm_data__data$84 , \alu_op__fn_unit$83 , \alu_op__insn_type$82 };
+ { \alu_op__SV_Ptype$next , \alu_op__sv_ldstmode$next , \alu_op__sv_saturate$next , \alu_op__sv_pred_dz$next , \alu_op__sv_pred_sz$next , \alu_op__insn$next , \alu_op__data_len$next , \alu_op__is_signed$next , \alu_op__is_32bit$next , \alu_op__output_carry$next , \alu_op__input_carry$next , \alu_op__write_cr0$next , \alu_op__invert_out$next , \alu_op__zero_a$next , \alu_op__invert_in$next , \alu_op__oe__ok$next , \alu_op__oe__oe$next , \alu_op__rc__ok$next , \alu_op__rc__rc$next , \alu_op__imm_data__ok$next , \alu_op__imm_data__data$next , \alu_op__fn_unit$next , \alu_op__insn_type$next } = { \alu_op__SV_Ptype$107 , \alu_op__sv_ldstmode$106 , \alu_op__sv_saturate$105 , \alu_op__sv_pred_dz$104 , \alu_op__sv_pred_sz$103 , \alu_op__insn$102 , \alu_op__data_len$101 , \alu_op__is_signed$100 , \alu_op__is_32bit$99 , \alu_op__output_carry$98 , \alu_op__input_carry$97 , \alu_op__write_cr0$96 , \alu_op__invert_out$95 , \alu_op__zero_a$94 , \alu_op__invert_in$93 , \alu_op__oe__ok$92 , \alu_op__oe__oe$91 , \alu_op__rc__ok$90 , \alu_op__rc__rc$89 , \alu_op__imm_data__ok$88 , \alu_op__imm_data__data$87 , \alu_op__fn_unit$86 , \alu_op__insn_type$85 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
end
endcase
end
- assign \xer_so_ok$114 = 1'h0;
+ assign \xer_so_ok$118 = 1'h0;
assign p_ready_o = n_i_rdy_data;
assign n_valid_o = r_busy;
- assign { \xer_so_ok$113 , \xer_so$112 } = { 1'h0, \main_xer_so$77 };
- assign { \xer_ov_ok$111 , \xer_ov$110 } = { main_xer_ov_ok, main_xer_ov };
- assign { \xer_ca_ok$109 , \xer_ca$108 } = { main_xer_ca_ok, \main_xer_ca$76 };
- assign { \cr_a_ok$107 , \cr_a$106 } = { main_cr_a_ok, main_cr_a };
- assign { \o_ok$105 , \o$104 } = { main_o_ok, main_o };
- assign { \alu_op__SV_Ptype$103 , \alu_op__sv_saturate$102 , \alu_op__sv_pred_dz$101 , \alu_op__sv_pred_sz$100 , \alu_op__insn$99 , \alu_op__data_len$98 , \alu_op__is_signed$97 , \alu_op__is_32bit$96 , \alu_op__output_carry$95 , \alu_op__input_carry$94 , \alu_op__write_cr0$93 , \alu_op__invert_out$92 , \alu_op__zero_a$91 , \alu_op__invert_in$90 , \alu_op__oe__ok$89 , \alu_op__oe__oe$88 , \alu_op__rc__ok$87 , \alu_op__rc__rc$86 , \alu_op__imm_data__ok$85 , \alu_op__imm_data__data$84 , \alu_op__fn_unit$83 , \alu_op__insn_type$82 } = { \main_alu_op__SV_Ptype$75 , \main_alu_op__sv_saturate$74 , \main_alu_op__sv_pred_dz$73 , \main_alu_op__sv_pred_sz$72 , \main_alu_op__insn$71 , \main_alu_op__data_len$70 , \main_alu_op__is_signed$69 , \main_alu_op__is_32bit$68 , \main_alu_op__output_carry$67 , \main_alu_op__input_carry$66 , \main_alu_op__write_cr0$65 , \main_alu_op__invert_out$64 , \main_alu_op__zero_a$63 , \main_alu_op__invert_in$62 , \main_alu_op__oe__ok$61 , \main_alu_op__oe__oe$60 , \main_alu_op__rc__ok$59 , \main_alu_op__rc__rc$58 , \main_alu_op__imm_data__ok$57 , \main_alu_op__imm_data__data$56 , \main_alu_op__fn_unit$55 , \main_alu_op__insn_type$54 };
- assign \muxid$81 = \main_muxid$53 ;
- assign p_valid_i_p_ready_o = \$79 ;
+ assign { \xer_so_ok$117 , \xer_so$116 } = { 1'h0, \main_xer_so$80 };
+ assign { \xer_ov_ok$115 , \xer_ov$114 } = { main_xer_ov_ok, main_xer_ov };
+ assign { \xer_ca_ok$113 , \xer_ca$112 } = { main_xer_ca_ok, \main_xer_ca$79 };
+ assign { \cr_a_ok$111 , \cr_a$110 } = { main_cr_a_ok, main_cr_a };
+ assign { \o_ok$109 , \o$108 } = { main_o_ok, main_o };
+ assign { \alu_op__SV_Ptype$107 , \alu_op__sv_ldstmode$106 , \alu_op__sv_saturate$105 , \alu_op__sv_pred_dz$104 , \alu_op__sv_pred_sz$103 , \alu_op__insn$102 , \alu_op__data_len$101 , \alu_op__is_signed$100 , \alu_op__is_32bit$99 , \alu_op__output_carry$98 , \alu_op__input_carry$97 , \alu_op__write_cr0$96 , \alu_op__invert_out$95 , \alu_op__zero_a$94 , \alu_op__invert_in$93 , \alu_op__oe__ok$92 , \alu_op__oe__oe$91 , \alu_op__rc__ok$90 , \alu_op__rc__rc$89 , \alu_op__imm_data__ok$88 , \alu_op__imm_data__data$87 , \alu_op__fn_unit$86 , \alu_op__insn_type$85 } = { \main_alu_op__SV_Ptype$78 , \main_alu_op__sv_ldstmode$77 , \main_alu_op__sv_saturate$76 , \main_alu_op__sv_pred_dz$75 , \main_alu_op__sv_pred_sz$74 , \main_alu_op__insn$73 , \main_alu_op__data_len$72 , \main_alu_op__is_signed$71 , \main_alu_op__is_32bit$70 , \main_alu_op__output_carry$69 , \main_alu_op__input_carry$68 , \main_alu_op__write_cr0$67 , \main_alu_op__invert_out$66 , \main_alu_op__zero_a$65 , \main_alu_op__invert_in$64 , \main_alu_op__oe__ok$63 , \main_alu_op__oe__oe$62 , \main_alu_op__rc__ok$61 , \main_alu_op__rc__rc$60 , \main_alu_op__imm_data__ok$59 , \main_alu_op__imm_data__data$58 , \main_alu_op__fn_unit$57 , \main_alu_op__insn_type$56 };
+ assign \muxid$84 = \main_muxid$55 ;
+ assign p_valid_i_p_ready_o = \$82 ;
assign n_i_rdy_data = n_ready_i;
- assign \p_valid_i$78 = p_valid_i;
- assign main_xer_ca = \input_xer_ca$52 ;
- assign main_xer_so = \input_xer_so$51 ;
- assign main_rb = \input_rb$50 ;
- assign main_ra = \input_ra$49 ;
- assign { main_alu_op__SV_Ptype, main_alu_op__sv_saturate, main_alu_op__sv_pred_dz, main_alu_op__sv_pred_sz, main_alu_op__insn, main_alu_op__data_len, main_alu_op__is_signed, main_alu_op__is_32bit, main_alu_op__output_carry, main_alu_op__input_carry, main_alu_op__write_cr0, main_alu_op__invert_out, main_alu_op__zero_a, main_alu_op__invert_in, main_alu_op__oe__ok, main_alu_op__oe__oe, main_alu_op__rc__ok, main_alu_op__rc__rc, main_alu_op__imm_data__ok, main_alu_op__imm_data__data, main_alu_op__fn_unit, main_alu_op__insn_type } = { \input_alu_op__SV_Ptype$48 , \input_alu_op__sv_saturate$47 , \input_alu_op__sv_pred_dz$46 , \input_alu_op__sv_pred_sz$45 , \input_alu_op__insn$44 , \input_alu_op__data_len$43 , \input_alu_op__is_signed$42 , \input_alu_op__is_32bit$41 , \input_alu_op__output_carry$40 , \input_alu_op__input_carry$39 , \input_alu_op__write_cr0$38 , \input_alu_op__invert_out$37 , \input_alu_op__zero_a$36 , \input_alu_op__invert_in$35 , \input_alu_op__oe__ok$34 , \input_alu_op__oe__oe$33 , \input_alu_op__rc__ok$32 , \input_alu_op__rc__rc$31 , \input_alu_op__imm_data__ok$30 , \input_alu_op__imm_data__data$29 , \input_alu_op__fn_unit$28 , \input_alu_op__insn_type$27 };
- assign main_muxid = \input_muxid$26 ;
- assign input_xer_ca = \xer_ca$25 ;
- assign input_xer_so = \xer_so$24 ;
+ assign \p_valid_i$81 = p_valid_i;
+ assign main_xer_ca = \input_xer_ca$54 ;
+ assign main_xer_so = \input_xer_so$53 ;
+ assign main_rb = \input_rb$52 ;
+ assign main_ra = \input_ra$51 ;
+ assign { main_alu_op__SV_Ptype, main_alu_op__sv_ldstmode, main_alu_op__sv_saturate, main_alu_op__sv_pred_dz, main_alu_op__sv_pred_sz, main_alu_op__insn, main_alu_op__data_len, main_alu_op__is_signed, main_alu_op__is_32bit, main_alu_op__output_carry, main_alu_op__input_carry, main_alu_op__write_cr0, main_alu_op__invert_out, main_alu_op__zero_a, main_alu_op__invert_in, main_alu_op__oe__ok, main_alu_op__oe__oe, main_alu_op__rc__ok, main_alu_op__rc__rc, main_alu_op__imm_data__ok, main_alu_op__imm_data__data, main_alu_op__fn_unit, main_alu_op__insn_type } = { \input_alu_op__SV_Ptype$50 , \input_alu_op__sv_ldstmode$49 , \input_alu_op__sv_saturate$48 , \input_alu_op__sv_pred_dz$47 , \input_alu_op__sv_pred_sz$46 , \input_alu_op__insn$45 , \input_alu_op__data_len$44 , \input_alu_op__is_signed$43 , \input_alu_op__is_32bit$42 , \input_alu_op__output_carry$41 , \input_alu_op__input_carry$40 , \input_alu_op__write_cr0$39 , \input_alu_op__invert_out$38 , \input_alu_op__zero_a$37 , \input_alu_op__invert_in$36 , \input_alu_op__oe__ok$35 , \input_alu_op__oe__oe$34 , \input_alu_op__rc__ok$33 , \input_alu_op__rc__rc$32 , \input_alu_op__imm_data__ok$31 , \input_alu_op__imm_data__data$30 , \input_alu_op__fn_unit$29 , \input_alu_op__insn_type$28 };
+ assign main_muxid = \input_muxid$27 ;
+ assign input_xer_ca = \xer_ca$26 ;
+ assign input_xer_so = \xer_so$25 ;
assign input_rb = rb;
assign input_ra = ra;
- assign { input_alu_op__SV_Ptype, input_alu_op__sv_saturate, input_alu_op__sv_pred_dz, input_alu_op__sv_pred_sz, input_alu_op__insn, input_alu_op__data_len, input_alu_op__is_signed, input_alu_op__is_32bit, input_alu_op__output_carry, input_alu_op__input_carry, input_alu_op__write_cr0, input_alu_op__invert_out, input_alu_op__zero_a, input_alu_op__invert_in, input_alu_op__oe__ok, input_alu_op__oe__oe, input_alu_op__rc__ok, input_alu_op__rc__rc, input_alu_op__imm_data__ok, input_alu_op__imm_data__data, input_alu_op__fn_unit, input_alu_op__insn_type } = { \alu_op__SV_Ptype$23 , \alu_op__sv_saturate$22 , \alu_op__sv_pred_dz$21 , \alu_op__sv_pred_sz$20 , \alu_op__insn$19 , \alu_op__data_len$18 , \alu_op__is_signed$17 , \alu_op__is_32bit$16 , \alu_op__output_carry$15 , \alu_op__input_carry$14 , \alu_op__write_cr0$13 , \alu_op__invert_out$12 , \alu_op__zero_a$11 , \alu_op__invert_in$10 , \alu_op__oe__ok$9 , \alu_op__oe__oe$8 , \alu_op__rc__ok$7 , \alu_op__rc__rc$6 , \alu_op__imm_data__ok$5 , \alu_op__imm_data__data$4 , \alu_op__fn_unit$3 , \alu_op__insn_type$2 };
+ assign { input_alu_op__SV_Ptype, input_alu_op__sv_ldstmode, input_alu_op__sv_saturate, input_alu_op__sv_pred_dz, input_alu_op__sv_pred_sz, input_alu_op__insn, input_alu_op__data_len, input_alu_op__is_signed, input_alu_op__is_32bit, input_alu_op__output_carry, input_alu_op__input_carry, input_alu_op__write_cr0, input_alu_op__invert_out, input_alu_op__zero_a, input_alu_op__invert_in, input_alu_op__oe__ok, input_alu_op__oe__oe, input_alu_op__rc__ok, input_alu_op__rc__rc, input_alu_op__imm_data__ok, input_alu_op__imm_data__data, input_alu_op__fn_unit, input_alu_op__insn_type } = { \alu_op__SV_Ptype$24 , \alu_op__sv_ldstmode$23 , \alu_op__sv_saturate$22 , \alu_op__sv_pred_dz$21 , \alu_op__sv_pred_sz$20 , \alu_op__insn$19 , \alu_op__data_len$18 , \alu_op__is_signed$17 , \alu_op__is_32bit$16 , \alu_op__output_carry$15 , \alu_op__input_carry$14 , \alu_op__write_cr0$13 , \alu_op__invert_out$12 , \alu_op__zero_a$11 , \alu_op__invert_in$10 , \alu_op__oe__ok$9 , \alu_op__oe__oe$8 , \alu_op__rc__ok$7 , \alu_op__rc__rc$6 , \alu_op__imm_data__ok$5 , \alu_op__imm_data__data$4 , \alu_op__fn_unit$3 , \alu_op__insn_type$2 };
assign input_muxid = \muxid$1 ;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1" *)
(* generator = "nMigen" *)
-module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, sr_op__sv_pred_sz, sr_op__sv_pred_dz, sr_op__sv_saturate, sr_op__SV_Ptype, o, o_ok, cr_a, cr_a_ok, xer_so, xer_so_ok, xer_ca, xer_ca_ok, p_valid_i, p_ready_o, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , \sr_op__sv_pred_sz$19 , \sr_op__sv_pred_dz$20 , \sr_op__sv_saturate$21 , \sr_op__SV_Ptype$22 , ra, rb, rc, \xer_so$23 , \xer_ca$24 , coresync_clk);
+module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, sr_op__sv_pred_sz, sr_op__sv_pred_dz, sr_op__sv_saturate, sr_op__sv_ldstmode, sr_op__SV_Ptype, o, o_ok, cr_a, cr_a_ok, xer_so, xer_so_ok, xer_ca, xer_ca_ok, p_valid_i, p_ready_o, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , \sr_op__sv_pred_sz$19 , \sr_op__sv_pred_dz$20 , \sr_op__sv_saturate$21 , \sr_op__sv_ldstmode$22 , \sr_op__SV_Ptype$23 , ra, rb, rc, \xer_so$24 , \xer_ca$25 , coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
- wire \$77 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ wire \$80 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output [3:0] cr_a;
reg [3:0] cr_a = 4'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [3:0] \cr_a$103 ;
+ wire [3:0] \cr_a$107 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [3:0] \cr_a$105 ;
+ wire [3:0] \cr_a$109 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg [3:0] \cr_a$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output cr_a_ok;
reg cr_a_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \cr_a_ok$104 ;
+ wire \cr_a_ok$108 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \cr_a_ok$106 ;
+ wire \cr_a_ok$110 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \cr_a_ok$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] input_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \input_muxid$25 ;
+ wire [1:0] \input_muxid$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] input_ra;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \input_ra$47 ;
+ wire [63:0] \input_ra$49 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] input_rb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \input_rb$48 ;
+ wire [63:0] \input_rb$50 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] input_rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \input_rc$49 ;
+ wire [63:0] \input_rc$51 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \input_sr_op__SV_Ptype$46 ;
+ wire [1:0] \input_sr_op__SV_Ptype$48 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \input_sr_op__fn_unit$27 ;
+ wire [14:0] \input_sr_op__fn_unit$28 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] input_sr_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \input_sr_op__imm_data__data$28 ;
+ wire [63:0] \input_sr_op__imm_data__data$29 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_sr_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_sr_op__imm_data__ok$29 ;
+ wire \input_sr_op__imm_data__ok$30 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \input_sr_op__input_carry$36 ;
+ wire [1:0] \input_sr_op__input_carry$37 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_sr_op__input_cr;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_sr_op__input_cr$38 ;
+ wire \input_sr_op__input_cr$39 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] input_sr_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \input_sr_op__insn$42 ;
+ wire [31:0] \input_sr_op__insn$43 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \input_sr_op__insn_type$26 ;
+ wire [6:0] \input_sr_op__insn_type$27 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_sr_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_sr_op__invert_in$35 ;
+ wire \input_sr_op__invert_in$36 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_sr_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_sr_op__is_32bit$40 ;
+ wire \input_sr_op__is_32bit$41 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_sr_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_sr_op__is_signed$41 ;
+ wire \input_sr_op__is_signed$42 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_sr_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_sr_op__oe__oe$32 ;
+ wire \input_sr_op__oe__oe$33 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_sr_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_sr_op__oe__ok$33 ;
+ wire \input_sr_op__oe__ok$34 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_sr_op__output_carry;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_sr_op__output_carry$37 ;
+ wire \input_sr_op__output_carry$38 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_sr_op__output_cr;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_sr_op__output_cr$39 ;
+ wire \input_sr_op__output_cr$40 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_sr_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_sr_op__rc__ok$31 ;
+ wire \input_sr_op__rc__ok$32 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_sr_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_sr_op__rc__rc$30 ;
+ wire \input_sr_op__rc__rc$31 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] input_sr_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \input_sr_op__sv_ldstmode$47 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_sr_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_sr_op__sv_pred_dz$44 ;
+ wire \input_sr_op__sv_pred_dz$45 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_sr_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_sr_op__sv_pred_sz$43 ;
+ wire \input_sr_op__sv_pred_sz$44 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \input_sr_op__sv_saturate$45 ;
+ wire [1:0] \input_sr_op__sv_saturate$46 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_sr_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_sr_op__write_cr0$34 ;
+ wire \input_sr_op__write_cr0$35 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [1:0] input_xer_ca;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [1:0] \input_xer_ca$51 ;
+ wire [1:0] \input_xer_ca$53 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire input_xer_so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire \input_xer_so$50 ;
+ wire \input_xer_so$52 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] main_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \main_muxid$52 ;
+ wire [1:0] \main_muxid$54 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [63:0] main_o;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \main_sr_op__SV_Ptype$73 ;
+ wire [1:0] \main_sr_op__SV_Ptype$76 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \main_sr_op__fn_unit$54 ;
+ wire [14:0] \main_sr_op__fn_unit$56 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] main_sr_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \main_sr_op__imm_data__data$55 ;
+ wire [63:0] \main_sr_op__imm_data__data$57 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_sr_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_sr_op__imm_data__ok$56 ;
+ wire \main_sr_op__imm_data__ok$58 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \main_sr_op__input_carry$63 ;
+ wire [1:0] \main_sr_op__input_carry$65 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_sr_op__input_cr;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_sr_op__input_cr$65 ;
+ wire \main_sr_op__input_cr$67 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] main_sr_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \main_sr_op__insn$69 ;
+ wire [31:0] \main_sr_op__insn$71 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \main_sr_op__insn_type$53 ;
+ wire [6:0] \main_sr_op__insn_type$55 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_sr_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_sr_op__invert_in$62 ;
+ wire \main_sr_op__invert_in$64 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_sr_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_sr_op__is_32bit$67 ;
+ wire \main_sr_op__is_32bit$69 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_sr_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_sr_op__is_signed$68 ;
+ wire \main_sr_op__is_signed$70 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_sr_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_sr_op__oe__oe$59 ;
+ wire \main_sr_op__oe__oe$61 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_sr_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_sr_op__oe__ok$60 ;
+ wire \main_sr_op__oe__ok$62 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_sr_op__output_carry;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_sr_op__output_carry$64 ;
+ wire \main_sr_op__output_carry$66 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_sr_op__output_cr;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_sr_op__output_cr$66 ;
+ wire \main_sr_op__output_cr$68 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_sr_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_sr_op__rc__ok$58 ;
+ wire \main_sr_op__rc__ok$60 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_sr_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_sr_op__rc__rc$57 ;
+ wire \main_sr_op__rc__rc$59 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] main_sr_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \main_sr_op__sv_ldstmode$75 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_sr_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_sr_op__sv_pred_dz$71 ;
+ wire \main_sr_op__sv_pred_dz$73 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_sr_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_sr_op__sv_pred_sz$70 ;
+ wire \main_sr_op__sv_pred_sz$72 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \main_sr_op__sv_saturate$72 ;
+ wire [1:0] \main_sr_op__sv_saturate$74 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_sr_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_sr_op__write_cr0$61 ;
+ wire \main_sr_op__write_cr0$63 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [1:0] main_xer_ca;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire main_xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \main_xer_so$74 ;
+ wire \main_xer_so$77 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
output [1:0] muxid;
reg [1:0] muxid = 2'h0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
input [1:0] \muxid$1 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \muxid$79 ;
+ wire [1:0] \muxid$82 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
reg [1:0] \muxid$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
output [63:0] o;
reg [63:0] o = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \o$101 ;
+ wire [63:0] \o$105 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg [63:0] \o$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output o_ok;
reg o_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \o_ok$102 ;
+ wire \o_ok$106 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \o_ok$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
input p_valid_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
- wire \p_valid_i$76 ;
+ wire \p_valid_i$79 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
wire p_valid_i_p_ready_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \sr_op__SV_Ptype$100 ;
+ wire [1:0] \sr_op__SV_Ptype$104 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- input [1:0] \sr_op__SV_Ptype$22 ;
+ input [1:0] \sr_op__SV_Ptype$23 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [1:0] \sr_op__SV_Ptype$next ;
(* enum_base_type = "Function" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \sr_op__fn_unit$81 ;
+ wire [14:0] \sr_op__fn_unit$84 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [14:0] \sr_op__fn_unit$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] \sr_op__imm_data__data$4 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \sr_op__imm_data__data$82 ;
+ wire [63:0] \sr_op__imm_data__data$85 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [63:0] \sr_op__imm_data__data$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \sr_op__imm_data__ok$5 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__imm_data__ok$83 ;
+ wire \sr_op__imm_data__ok$86 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \sr_op__imm_data__ok$next ;
(* enum_base_type = "CryIn" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \sr_op__input_carry$90 ;
+ wire [1:0] \sr_op__input_carry$93 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [1:0] \sr_op__input_carry$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \sr_op__input_cr$14 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__input_cr$92 ;
+ wire \sr_op__input_cr$95 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \sr_op__input_cr$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] \sr_op__insn$18 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \sr_op__insn$96 ;
+ wire [31:0] \sr_op__insn$99 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [31:0] \sr_op__insn$next ;
(* enum_base_type = "MicrOp" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \sr_op__insn_type$80 ;
+ wire [6:0] \sr_op__insn_type$83 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [6:0] \sr_op__insn_type$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \sr_op__invert_in$11 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__invert_in$89 ;
+ wire \sr_op__invert_in$92 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \sr_op__invert_in$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \sr_op__is_32bit$16 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__is_32bit$94 ;
+ wire \sr_op__is_32bit$97 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \sr_op__is_32bit$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \sr_op__is_signed$17 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__is_signed$95 ;
+ wire \sr_op__is_signed$98 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \sr_op__is_signed$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \sr_op__oe__oe$8 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__oe__oe$86 ;
+ wire \sr_op__oe__oe$89 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \sr_op__oe__oe$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output sr_op__oe__ok;
reg sr_op__oe__ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__oe__ok$87 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \sr_op__oe__ok$9 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire \sr_op__oe__ok$90 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \sr_op__oe__ok$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output sr_op__output_carry;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \sr_op__output_carry$13 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__output_carry$91 ;
+ wire \sr_op__output_carry$94 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \sr_op__output_carry$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \sr_op__output_cr$15 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__output_cr$93 ;
+ wire \sr_op__output_cr$96 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \sr_op__output_cr$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \sr_op__rc__ok$7 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__rc__ok$85 ;
+ wire \sr_op__rc__ok$88 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \sr_op__rc__ok$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \sr_op__rc__rc$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__rc__rc$84 ;
+ wire \sr_op__rc__rc$87 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \sr_op__rc__rc$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] sr_op__sv_ldstmode;
+ reg [1:0] sr_op__sv_ldstmode = 2'h0;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \sr_op__sv_ldstmode$103 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] \sr_op__sv_ldstmode$22 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \sr_op__sv_ldstmode$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output sr_op__sv_pred_dz;
reg sr_op__sv_pred_dz = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- input \sr_op__sv_pred_dz$20 ;
+ wire \sr_op__sv_pred_dz$101 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__sv_pred_dz$98 ;
+ input \sr_op__sv_pred_dz$20 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \sr_op__sv_pred_dz$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output sr_op__sv_pred_sz;
reg sr_op__sv_pred_sz = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- input \sr_op__sv_pred_sz$19 ;
+ wire \sr_op__sv_pred_sz$100 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__sv_pred_sz$97 ;
+ input \sr_op__sv_pred_sz$19 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \sr_op__sv_pred_sz$next ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- input [1:0] \sr_op__sv_saturate$21 ;
+ wire [1:0] \sr_op__sv_saturate$102 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \sr_op__sv_saturate$99 ;
+ input [1:0] \sr_op__sv_saturate$21 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [1:0] \sr_op__sv_saturate$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \sr_op__write_cr0$10 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__write_cr0$88 ;
+ wire \sr_op__write_cr0$91 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \sr_op__write_cr0$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output [1:0] xer_ca;
reg [1:0] xer_ca = 2'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [1:0] \xer_ca$110 ;
+ wire [1:0] \xer_ca$114 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- input [1:0] \xer_ca$24 ;
+ input [1:0] \xer_ca$25 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [1:0] \xer_ca$75 ;
+ wire [1:0] \xer_ca$78 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg [1:0] \xer_ca$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_ca_ok;
reg xer_ca_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_ca_ok$111 ;
+ wire \xer_ca_ok$115 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_ca_ok$112 ;
+ wire \xer_ca_ok$116 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \xer_ca_ok$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_so;
reg xer_so = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_so$107 ;
+ wire \xer_so$111 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- input \xer_so$23 ;
+ input \xer_so$24 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \xer_so$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_so_ok;
reg xer_so_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_so_ok$108 ;
+ wire \xer_so_ok$112 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_so_ok$109 ;
+ wire \xer_so_ok$113 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \xer_so_ok$next ;
- assign \$77 = \p_valid_i$76 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
+ assign \$80 = \p_valid_i$79 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
always @(posedge coresync_clk)
xer_ca <= \xer_ca$next ;
always @(posedge coresync_clk)
sr_op__sv_pred_dz <= \sr_op__sv_pred_dz$next ;
always @(posedge coresync_clk)
sr_op__sv_saturate <= \sr_op__sv_saturate$next ;
+ always @(posedge coresync_clk)
+ sr_op__sv_ldstmode <= \sr_op__sv_ldstmode$next ;
always @(posedge coresync_clk)
sr_op__SV_Ptype <= \sr_op__SV_Ptype$next ;
always @(posedge coresync_clk)
r_busy <= \r_busy$next ;
\input$113 \input (
.muxid(input_muxid),
- .\muxid$1 (\input_muxid$25 ),
+ .\muxid$1 (\input_muxid$26 ),
.ra(input_ra),
- .\ra$23 (\input_ra$47 ),
+ .\ra$24 (\input_ra$49 ),
.rb(input_rb),
- .\rb$24 (\input_rb$48 ),
+ .\rb$25 (\input_rb$50 ),
.rc(input_rc),
- .\rc$25 (\input_rc$49 ),
+ .\rc$26 (\input_rc$51 ),
.sr_op__SV_Ptype(input_sr_op__SV_Ptype),
- .\sr_op__SV_Ptype$22 (\input_sr_op__SV_Ptype$46 ),
+ .\sr_op__SV_Ptype$23 (\input_sr_op__SV_Ptype$48 ),
.sr_op__fn_unit(input_sr_op__fn_unit),
- .\sr_op__fn_unit$3 (\input_sr_op__fn_unit$27 ),
+ .\sr_op__fn_unit$3 (\input_sr_op__fn_unit$28 ),
.sr_op__imm_data__data(input_sr_op__imm_data__data),
- .\sr_op__imm_data__data$4 (\input_sr_op__imm_data__data$28 ),
+ .\sr_op__imm_data__data$4 (\input_sr_op__imm_data__data$29 ),
.sr_op__imm_data__ok(input_sr_op__imm_data__ok),
- .\sr_op__imm_data__ok$5 (\input_sr_op__imm_data__ok$29 ),
+ .\sr_op__imm_data__ok$5 (\input_sr_op__imm_data__ok$30 ),
.sr_op__input_carry(input_sr_op__input_carry),
- .\sr_op__input_carry$12 (\input_sr_op__input_carry$36 ),
+ .\sr_op__input_carry$12 (\input_sr_op__input_carry$37 ),
.sr_op__input_cr(input_sr_op__input_cr),
- .\sr_op__input_cr$14 (\input_sr_op__input_cr$38 ),
+ .\sr_op__input_cr$14 (\input_sr_op__input_cr$39 ),
.sr_op__insn(input_sr_op__insn),
- .\sr_op__insn$18 (\input_sr_op__insn$42 ),
+ .\sr_op__insn$18 (\input_sr_op__insn$43 ),
.sr_op__insn_type(input_sr_op__insn_type),
- .\sr_op__insn_type$2 (\input_sr_op__insn_type$26 ),
+ .\sr_op__insn_type$2 (\input_sr_op__insn_type$27 ),
.sr_op__invert_in(input_sr_op__invert_in),
- .\sr_op__invert_in$11 (\input_sr_op__invert_in$35 ),
+ .\sr_op__invert_in$11 (\input_sr_op__invert_in$36 ),
.sr_op__is_32bit(input_sr_op__is_32bit),
- .\sr_op__is_32bit$16 (\input_sr_op__is_32bit$40 ),
+ .\sr_op__is_32bit$16 (\input_sr_op__is_32bit$41 ),
.sr_op__is_signed(input_sr_op__is_signed),
- .\sr_op__is_signed$17 (\input_sr_op__is_signed$41 ),
+ .\sr_op__is_signed$17 (\input_sr_op__is_signed$42 ),
.sr_op__oe__oe(input_sr_op__oe__oe),
- .\sr_op__oe__oe$8 (\input_sr_op__oe__oe$32 ),
+ .\sr_op__oe__oe$8 (\input_sr_op__oe__oe$33 ),
.sr_op__oe__ok(input_sr_op__oe__ok),
- .\sr_op__oe__ok$9 (\input_sr_op__oe__ok$33 ),
+ .\sr_op__oe__ok$9 (\input_sr_op__oe__ok$34 ),
.sr_op__output_carry(input_sr_op__output_carry),
- .\sr_op__output_carry$13 (\input_sr_op__output_carry$37 ),
+ .\sr_op__output_carry$13 (\input_sr_op__output_carry$38 ),
.sr_op__output_cr(input_sr_op__output_cr),
- .\sr_op__output_cr$15 (\input_sr_op__output_cr$39 ),
+ .\sr_op__output_cr$15 (\input_sr_op__output_cr$40 ),
.sr_op__rc__ok(input_sr_op__rc__ok),
- .\sr_op__rc__ok$7 (\input_sr_op__rc__ok$31 ),
+ .\sr_op__rc__ok$7 (\input_sr_op__rc__ok$32 ),
.sr_op__rc__rc(input_sr_op__rc__rc),
- .\sr_op__rc__rc$6 (\input_sr_op__rc__rc$30 ),
+ .\sr_op__rc__rc$6 (\input_sr_op__rc__rc$31 ),
+ .sr_op__sv_ldstmode(input_sr_op__sv_ldstmode),
+ .\sr_op__sv_ldstmode$22 (\input_sr_op__sv_ldstmode$47 ),
.sr_op__sv_pred_dz(input_sr_op__sv_pred_dz),
- .\sr_op__sv_pred_dz$20 (\input_sr_op__sv_pred_dz$44 ),
+ .\sr_op__sv_pred_dz$20 (\input_sr_op__sv_pred_dz$45 ),
.sr_op__sv_pred_sz(input_sr_op__sv_pred_sz),
- .\sr_op__sv_pred_sz$19 (\input_sr_op__sv_pred_sz$43 ),
+ .\sr_op__sv_pred_sz$19 (\input_sr_op__sv_pred_sz$44 ),
.sr_op__sv_saturate(input_sr_op__sv_saturate),
- .\sr_op__sv_saturate$21 (\input_sr_op__sv_saturate$45 ),
+ .\sr_op__sv_saturate$21 (\input_sr_op__sv_saturate$46 ),
.sr_op__write_cr0(input_sr_op__write_cr0),
- .\sr_op__write_cr0$10 (\input_sr_op__write_cr0$34 ),
+ .\sr_op__write_cr0$10 (\input_sr_op__write_cr0$35 ),
.xer_ca(input_xer_ca),
- .\xer_ca$27 (\input_xer_ca$51 ),
+ .\xer_ca$28 (\input_xer_ca$53 ),
.xer_so(input_xer_so),
- .\xer_so$26 (\input_xer_so$50 )
+ .\xer_so$27 (\input_xer_so$52 )
);
\main$114 main (
.muxid(main_muxid),
- .\muxid$1 (\main_muxid$52 ),
+ .\muxid$1 (\main_muxid$54 ),
.o(main_o),
.o_ok(main_o_ok),
.ra(main_ra),
.rb(main_rb),
.rc(main_rc),
.sr_op__SV_Ptype(main_sr_op__SV_Ptype),
- .\sr_op__SV_Ptype$22 (\main_sr_op__SV_Ptype$73 ),
+ .\sr_op__SV_Ptype$23 (\main_sr_op__SV_Ptype$76 ),
.sr_op__fn_unit(main_sr_op__fn_unit),
- .\sr_op__fn_unit$3 (\main_sr_op__fn_unit$54 ),
+ .\sr_op__fn_unit$3 (\main_sr_op__fn_unit$56 ),
.sr_op__imm_data__data(main_sr_op__imm_data__data),
- .\sr_op__imm_data__data$4 (\main_sr_op__imm_data__data$55 ),
+ .\sr_op__imm_data__data$4 (\main_sr_op__imm_data__data$57 ),
.sr_op__imm_data__ok(main_sr_op__imm_data__ok),
- .\sr_op__imm_data__ok$5 (\main_sr_op__imm_data__ok$56 ),
+ .\sr_op__imm_data__ok$5 (\main_sr_op__imm_data__ok$58 ),
.sr_op__input_carry(main_sr_op__input_carry),
- .\sr_op__input_carry$12 (\main_sr_op__input_carry$63 ),
+ .\sr_op__input_carry$12 (\main_sr_op__input_carry$65 ),
.sr_op__input_cr(main_sr_op__input_cr),
- .\sr_op__input_cr$14 (\main_sr_op__input_cr$65 ),
+ .\sr_op__input_cr$14 (\main_sr_op__input_cr$67 ),
.sr_op__insn(main_sr_op__insn),
- .\sr_op__insn$18 (\main_sr_op__insn$69 ),
+ .\sr_op__insn$18 (\main_sr_op__insn$71 ),
.sr_op__insn_type(main_sr_op__insn_type),
- .\sr_op__insn_type$2 (\main_sr_op__insn_type$53 ),
+ .\sr_op__insn_type$2 (\main_sr_op__insn_type$55 ),
.sr_op__invert_in(main_sr_op__invert_in),
- .\sr_op__invert_in$11 (\main_sr_op__invert_in$62 ),
+ .\sr_op__invert_in$11 (\main_sr_op__invert_in$64 ),
.sr_op__is_32bit(main_sr_op__is_32bit),
- .\sr_op__is_32bit$16 (\main_sr_op__is_32bit$67 ),
+ .\sr_op__is_32bit$16 (\main_sr_op__is_32bit$69 ),
.sr_op__is_signed(main_sr_op__is_signed),
- .\sr_op__is_signed$17 (\main_sr_op__is_signed$68 ),
+ .\sr_op__is_signed$17 (\main_sr_op__is_signed$70 ),
.sr_op__oe__oe(main_sr_op__oe__oe),
- .\sr_op__oe__oe$8 (\main_sr_op__oe__oe$59 ),
+ .\sr_op__oe__oe$8 (\main_sr_op__oe__oe$61 ),
.sr_op__oe__ok(main_sr_op__oe__ok),
- .\sr_op__oe__ok$9 (\main_sr_op__oe__ok$60 ),
+ .\sr_op__oe__ok$9 (\main_sr_op__oe__ok$62 ),
.sr_op__output_carry(main_sr_op__output_carry),
- .\sr_op__output_carry$13 (\main_sr_op__output_carry$64 ),
+ .\sr_op__output_carry$13 (\main_sr_op__output_carry$66 ),
.sr_op__output_cr(main_sr_op__output_cr),
- .\sr_op__output_cr$15 (\main_sr_op__output_cr$66 ),
+ .\sr_op__output_cr$15 (\main_sr_op__output_cr$68 ),
.sr_op__rc__ok(main_sr_op__rc__ok),
- .\sr_op__rc__ok$7 (\main_sr_op__rc__ok$58 ),
+ .\sr_op__rc__ok$7 (\main_sr_op__rc__ok$60 ),
.sr_op__rc__rc(main_sr_op__rc__rc),
- .\sr_op__rc__rc$6 (\main_sr_op__rc__rc$57 ),
+ .\sr_op__rc__rc$6 (\main_sr_op__rc__rc$59 ),
+ .sr_op__sv_ldstmode(main_sr_op__sv_ldstmode),
+ .\sr_op__sv_ldstmode$22 (\main_sr_op__sv_ldstmode$75 ),
.sr_op__sv_pred_dz(main_sr_op__sv_pred_dz),
- .\sr_op__sv_pred_dz$20 (\main_sr_op__sv_pred_dz$71 ),
+ .\sr_op__sv_pred_dz$20 (\main_sr_op__sv_pred_dz$73 ),
.sr_op__sv_pred_sz(main_sr_op__sv_pred_sz),
- .\sr_op__sv_pred_sz$19 (\main_sr_op__sv_pred_sz$70 ),
+ .\sr_op__sv_pred_sz$19 (\main_sr_op__sv_pred_sz$72 ),
.sr_op__sv_saturate(main_sr_op__sv_saturate),
- .\sr_op__sv_saturate$21 (\main_sr_op__sv_saturate$72 ),
+ .\sr_op__sv_saturate$21 (\main_sr_op__sv_saturate$74 ),
.sr_op__write_cr0(main_sr_op__write_cr0),
- .\sr_op__write_cr0$10 (\main_sr_op__write_cr0$61 ),
+ .\sr_op__write_cr0$10 (\main_sr_op__write_cr0$63 ),
.xer_ca(main_xer_ca),
.xer_so(main_xer_so),
- .\xer_so$23 (\main_xer_so$74 )
+ .\xer_so$24 (\main_xer_so$77 )
);
\n$112 n (
.n_ready_i(n_ready_i),
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \o_ok$next , \o$next } = { \o_ok$102 , \o$101 };
+ { \o_ok$next , \o$next } = { \o_ok$106 , \o$105 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \o_ok$next , \o$next } = { \o_ok$102 , \o$101 };
+ { \o_ok$next , \o$next } = { \o_ok$106 , \o$105 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$104 , \cr_a$103 };
+ { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$108 , \cr_a$107 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$104 , \cr_a$103 };
+ { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$108 , \cr_a$107 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$108 , \xer_so$107 };
+ { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$112 , \xer_so$111 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$108 , \xer_so$107 };
+ { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$112 , \xer_so$111 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \xer_ca_ok$next , \xer_ca$next } = { \xer_ca_ok$111 , \xer_ca$110 };
+ { \xer_ca_ok$next , \xer_ca$next } = { \xer_ca_ok$115 , \xer_ca$114 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \xer_ca_ok$next , \xer_ca$next } = { \xer_ca_ok$111 , \xer_ca$110 };
+ { \xer_ca_ok$next , \xer_ca$next } = { \xer_ca_ok$115 , \xer_ca$114 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \muxid$next = \muxid$79 ;
+ \muxid$next = \muxid$82 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \muxid$next = \muxid$79 ;
+ \muxid$next = \muxid$82 ;
endcase
end
always @* begin
\sr_op__sv_pred_sz$next = sr_op__sv_pred_sz;
\sr_op__sv_pred_dz$next = sr_op__sv_pred_dz;
\sr_op__sv_saturate$next = sr_op__sv_saturate;
+ \sr_op__sv_ldstmode$next = sr_op__sv_ldstmode;
\sr_op__SV_Ptype$next = sr_op__SV_Ptype;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \sr_op__SV_Ptype$next , \sr_op__sv_saturate$next , \sr_op__sv_pred_dz$next , \sr_op__sv_pred_sz$next , \sr_op__insn$next , \sr_op__is_signed$next , \sr_op__is_32bit$next , \sr_op__output_cr$next , \sr_op__input_cr$next , \sr_op__output_carry$next , \sr_op__input_carry$next , \sr_op__invert_in$next , \sr_op__write_cr0$next , \sr_op__oe__ok$next , \sr_op__oe__oe$next , \sr_op__rc__ok$next , \sr_op__rc__rc$next , \sr_op__imm_data__ok$next , \sr_op__imm_data__data$next , \sr_op__fn_unit$next , \sr_op__insn_type$next } = { \sr_op__SV_Ptype$100 , \sr_op__sv_saturate$99 , \sr_op__sv_pred_dz$98 , \sr_op__sv_pred_sz$97 , \sr_op__insn$96 , \sr_op__is_signed$95 , \sr_op__is_32bit$94 , \sr_op__output_cr$93 , \sr_op__input_cr$92 , \sr_op__output_carry$91 , \sr_op__input_carry$90 , \sr_op__invert_in$89 , \sr_op__write_cr0$88 , \sr_op__oe__ok$87 , \sr_op__oe__oe$86 , \sr_op__rc__ok$85 , \sr_op__rc__rc$84 , \sr_op__imm_data__ok$83 , \sr_op__imm_data__data$82 , \sr_op__fn_unit$81 , \sr_op__insn_type$80 };
+ { \sr_op__SV_Ptype$next , \sr_op__sv_ldstmode$next , \sr_op__sv_saturate$next , \sr_op__sv_pred_dz$next , \sr_op__sv_pred_sz$next , \sr_op__insn$next , \sr_op__is_signed$next , \sr_op__is_32bit$next , \sr_op__output_cr$next , \sr_op__input_cr$next , \sr_op__output_carry$next , \sr_op__input_carry$next , \sr_op__invert_in$next , \sr_op__write_cr0$next , \sr_op__oe__ok$next , \sr_op__oe__oe$next , \sr_op__rc__ok$next , \sr_op__rc__rc$next , \sr_op__imm_data__ok$next , \sr_op__imm_data__data$next , \sr_op__fn_unit$next , \sr_op__insn_type$next } = { \sr_op__SV_Ptype$104 , \sr_op__sv_ldstmode$103 , \sr_op__sv_saturate$102 , \sr_op__sv_pred_dz$101 , \sr_op__sv_pred_sz$100 , \sr_op__insn$99 , \sr_op__is_signed$98 , \sr_op__is_32bit$97 , \sr_op__output_cr$96 , \sr_op__input_cr$95 , \sr_op__output_carry$94 , \sr_op__input_carry$93 , \sr_op__invert_in$92 , \sr_op__write_cr0$91 , \sr_op__oe__ok$90 , \sr_op__oe__oe$89 , \sr_op__rc__ok$88 , \sr_op__rc__rc$87 , \sr_op__imm_data__ok$86 , \sr_op__imm_data__data$85 , \sr_op__fn_unit$84 , \sr_op__insn_type$83 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \sr_op__SV_Ptype$next , \sr_op__sv_saturate$next , \sr_op__sv_pred_dz$next , \sr_op__sv_pred_sz$next , \sr_op__insn$next , \sr_op__is_signed$next , \sr_op__is_32bit$next , \sr_op__output_cr$next , \sr_op__input_cr$next , \sr_op__output_carry$next , \sr_op__input_carry$next , \sr_op__invert_in$next , \sr_op__write_cr0$next , \sr_op__oe__ok$next , \sr_op__oe__oe$next , \sr_op__rc__ok$next , \sr_op__rc__rc$next , \sr_op__imm_data__ok$next , \sr_op__imm_data__data$next , \sr_op__fn_unit$next , \sr_op__insn_type$next } = { \sr_op__SV_Ptype$100 , \sr_op__sv_saturate$99 , \sr_op__sv_pred_dz$98 , \sr_op__sv_pred_sz$97 , \sr_op__insn$96 , \sr_op__is_signed$95 , \sr_op__is_32bit$94 , \sr_op__output_cr$93 , \sr_op__input_cr$92 , \sr_op__output_carry$91 , \sr_op__input_carry$90 , \sr_op__invert_in$89 , \sr_op__write_cr0$88 , \sr_op__oe__ok$87 , \sr_op__oe__oe$86 , \sr_op__rc__ok$85 , \sr_op__rc__rc$84 , \sr_op__imm_data__ok$83 , \sr_op__imm_data__data$82 , \sr_op__fn_unit$81 , \sr_op__insn_type$80 };
+ { \sr_op__SV_Ptype$next , \sr_op__sv_ldstmode$next , \sr_op__sv_saturate$next , \sr_op__sv_pred_dz$next , \sr_op__sv_pred_sz$next , \sr_op__insn$next , \sr_op__is_signed$next , \sr_op__is_32bit$next , \sr_op__output_cr$next , \sr_op__input_cr$next , \sr_op__output_carry$next , \sr_op__input_carry$next , \sr_op__invert_in$next , \sr_op__write_cr0$next , \sr_op__oe__ok$next , \sr_op__oe__oe$next , \sr_op__rc__ok$next , \sr_op__rc__rc$next , \sr_op__imm_data__ok$next , \sr_op__imm_data__data$next , \sr_op__fn_unit$next , \sr_op__insn_type$next } = { \sr_op__SV_Ptype$104 , \sr_op__sv_ldstmode$103 , \sr_op__sv_saturate$102 , \sr_op__sv_pred_dz$101 , \sr_op__sv_pred_sz$100 , \sr_op__insn$99 , \sr_op__is_signed$98 , \sr_op__is_32bit$97 , \sr_op__output_cr$96 , \sr_op__input_cr$95 , \sr_op__output_carry$94 , \sr_op__input_carry$93 , \sr_op__invert_in$92 , \sr_op__write_cr0$91 , \sr_op__oe__ok$90 , \sr_op__oe__oe$89 , \sr_op__rc__ok$88 , \sr_op__rc__rc$87 , \sr_op__imm_data__ok$86 , \sr_op__imm_data__data$85 , \sr_op__fn_unit$84 , \sr_op__insn_type$83 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
end
endcase
end
- assign \cr_a$105 = 4'h0;
- assign \cr_a_ok$106 = 1'h0;
- assign \xer_so_ok$109 = 1'h0;
- assign \xer_ca_ok$112 = 1'h0;
+ assign \cr_a$109 = 4'h0;
+ assign \cr_a_ok$110 = 1'h0;
+ assign \xer_so_ok$113 = 1'h0;
+ assign \xer_ca_ok$116 = 1'h0;
assign p_ready_o = n_i_rdy_data;
assign n_valid_o = r_busy;
- assign { \xer_ca_ok$111 , \xer_ca$110 } = { 1'h0, main_xer_ca };
- assign { \xer_so_ok$108 , \xer_so$107 } = { 1'h0, \main_xer_so$74 };
- assign { \cr_a_ok$104 , \cr_a$103 } = 5'h00;
- assign { \o_ok$102 , \o$101 } = { main_o_ok, main_o };
- assign { \sr_op__SV_Ptype$100 , \sr_op__sv_saturate$99 , \sr_op__sv_pred_dz$98 , \sr_op__sv_pred_sz$97 , \sr_op__insn$96 , \sr_op__is_signed$95 , \sr_op__is_32bit$94 , \sr_op__output_cr$93 , \sr_op__input_cr$92 , \sr_op__output_carry$91 , \sr_op__input_carry$90 , \sr_op__invert_in$89 , \sr_op__write_cr0$88 , \sr_op__oe__ok$87 , \sr_op__oe__oe$86 , \sr_op__rc__ok$85 , \sr_op__rc__rc$84 , \sr_op__imm_data__ok$83 , \sr_op__imm_data__data$82 , \sr_op__fn_unit$81 , \sr_op__insn_type$80 } = { \main_sr_op__SV_Ptype$73 , \main_sr_op__sv_saturate$72 , \main_sr_op__sv_pred_dz$71 , \main_sr_op__sv_pred_sz$70 , \main_sr_op__insn$69 , \main_sr_op__is_signed$68 , \main_sr_op__is_32bit$67 , \main_sr_op__output_cr$66 , \main_sr_op__input_cr$65 , \main_sr_op__output_carry$64 , \main_sr_op__input_carry$63 , \main_sr_op__invert_in$62 , \main_sr_op__write_cr0$61 , \main_sr_op__oe__ok$60 , \main_sr_op__oe__oe$59 , \main_sr_op__rc__ok$58 , \main_sr_op__rc__rc$57 , \main_sr_op__imm_data__ok$56 , \main_sr_op__imm_data__data$55 , \main_sr_op__fn_unit$54 , \main_sr_op__insn_type$53 };
- assign \muxid$79 = \main_muxid$52 ;
- assign p_valid_i_p_ready_o = \$77 ;
+ assign { \xer_ca_ok$115 , \xer_ca$114 } = { 1'h0, main_xer_ca };
+ assign { \xer_so_ok$112 , \xer_so$111 } = { 1'h0, \main_xer_so$77 };
+ assign { \cr_a_ok$108 , \cr_a$107 } = 5'h00;
+ assign { \o_ok$106 , \o$105 } = { main_o_ok, main_o };
+ assign { \sr_op__SV_Ptype$104 , \sr_op__sv_ldstmode$103 , \sr_op__sv_saturate$102 , \sr_op__sv_pred_dz$101 , \sr_op__sv_pred_sz$100 , \sr_op__insn$99 , \sr_op__is_signed$98 , \sr_op__is_32bit$97 , \sr_op__output_cr$96 , \sr_op__input_cr$95 , \sr_op__output_carry$94 , \sr_op__input_carry$93 , \sr_op__invert_in$92 , \sr_op__write_cr0$91 , \sr_op__oe__ok$90 , \sr_op__oe__oe$89 , \sr_op__rc__ok$88 , \sr_op__rc__rc$87 , \sr_op__imm_data__ok$86 , \sr_op__imm_data__data$85 , \sr_op__fn_unit$84 , \sr_op__insn_type$83 } = { \main_sr_op__SV_Ptype$76 , \main_sr_op__sv_ldstmode$75 , \main_sr_op__sv_saturate$74 , \main_sr_op__sv_pred_dz$73 , \main_sr_op__sv_pred_sz$72 , \main_sr_op__insn$71 , \main_sr_op__is_signed$70 , \main_sr_op__is_32bit$69 , \main_sr_op__output_cr$68 , \main_sr_op__input_cr$67 , \main_sr_op__output_carry$66 , \main_sr_op__input_carry$65 , \main_sr_op__invert_in$64 , \main_sr_op__write_cr0$63 , \main_sr_op__oe__ok$62 , \main_sr_op__oe__oe$61 , \main_sr_op__rc__ok$60 , \main_sr_op__rc__rc$59 , \main_sr_op__imm_data__ok$58 , \main_sr_op__imm_data__data$57 , \main_sr_op__fn_unit$56 , \main_sr_op__insn_type$55 };
+ assign \muxid$82 = \main_muxid$54 ;
+ assign p_valid_i_p_ready_o = \$80 ;
assign n_i_rdy_data = n_ready_i;
- assign \p_valid_i$76 = p_valid_i;
- assign \xer_ca$75 = \input_xer_ca$51 ;
- assign main_xer_so = \input_xer_so$50 ;
- assign main_rc = \input_rc$49 ;
- assign main_rb = \input_rb$48 ;
- assign main_ra = \input_ra$47 ;
- assign { main_sr_op__SV_Ptype, main_sr_op__sv_saturate, main_sr_op__sv_pred_dz, main_sr_op__sv_pred_sz, main_sr_op__insn, main_sr_op__is_signed, main_sr_op__is_32bit, main_sr_op__output_cr, main_sr_op__input_cr, main_sr_op__output_carry, main_sr_op__input_carry, main_sr_op__invert_in, main_sr_op__write_cr0, main_sr_op__oe__ok, main_sr_op__oe__oe, main_sr_op__rc__ok, main_sr_op__rc__rc, main_sr_op__imm_data__ok, main_sr_op__imm_data__data, main_sr_op__fn_unit, main_sr_op__insn_type } = { \input_sr_op__SV_Ptype$46 , \input_sr_op__sv_saturate$45 , \input_sr_op__sv_pred_dz$44 , \input_sr_op__sv_pred_sz$43 , \input_sr_op__insn$42 , \input_sr_op__is_signed$41 , \input_sr_op__is_32bit$40 , \input_sr_op__output_cr$39 , \input_sr_op__input_cr$38 , \input_sr_op__output_carry$37 , \input_sr_op__input_carry$36 , \input_sr_op__invert_in$35 , \input_sr_op__write_cr0$34 , \input_sr_op__oe__ok$33 , \input_sr_op__oe__oe$32 , \input_sr_op__rc__ok$31 , \input_sr_op__rc__rc$30 , \input_sr_op__imm_data__ok$29 , \input_sr_op__imm_data__data$28 , \input_sr_op__fn_unit$27 , \input_sr_op__insn_type$26 };
- assign main_muxid = \input_muxid$25 ;
- assign input_xer_ca = \xer_ca$24 ;
- assign input_xer_so = \xer_so$23 ;
+ assign \p_valid_i$79 = p_valid_i;
+ assign \xer_ca$78 = \input_xer_ca$53 ;
+ assign main_xer_so = \input_xer_so$52 ;
+ assign main_rc = \input_rc$51 ;
+ assign main_rb = \input_rb$50 ;
+ assign main_ra = \input_ra$49 ;
+ assign { main_sr_op__SV_Ptype, main_sr_op__sv_ldstmode, main_sr_op__sv_saturate, main_sr_op__sv_pred_dz, main_sr_op__sv_pred_sz, main_sr_op__insn, main_sr_op__is_signed, main_sr_op__is_32bit, main_sr_op__output_cr, main_sr_op__input_cr, main_sr_op__output_carry, main_sr_op__input_carry, main_sr_op__invert_in, main_sr_op__write_cr0, main_sr_op__oe__ok, main_sr_op__oe__oe, main_sr_op__rc__ok, main_sr_op__rc__rc, main_sr_op__imm_data__ok, main_sr_op__imm_data__data, main_sr_op__fn_unit, main_sr_op__insn_type } = { \input_sr_op__SV_Ptype$48 , \input_sr_op__sv_ldstmode$47 , \input_sr_op__sv_saturate$46 , \input_sr_op__sv_pred_dz$45 , \input_sr_op__sv_pred_sz$44 , \input_sr_op__insn$43 , \input_sr_op__is_signed$42 , \input_sr_op__is_32bit$41 , \input_sr_op__output_cr$40 , \input_sr_op__input_cr$39 , \input_sr_op__output_carry$38 , \input_sr_op__input_carry$37 , \input_sr_op__invert_in$36 , \input_sr_op__write_cr0$35 , \input_sr_op__oe__ok$34 , \input_sr_op__oe__oe$33 , \input_sr_op__rc__ok$32 , \input_sr_op__rc__rc$31 , \input_sr_op__imm_data__ok$30 , \input_sr_op__imm_data__data$29 , \input_sr_op__fn_unit$28 , \input_sr_op__insn_type$27 };
+ assign main_muxid = \input_muxid$26 ;
+ assign input_xer_ca = \xer_ca$25 ;
+ assign input_xer_so = \xer_so$24 ;
assign input_rc = rc;
assign input_rb = rb;
assign input_ra = ra;
- assign { input_sr_op__SV_Ptype, input_sr_op__sv_saturate, input_sr_op__sv_pred_dz, input_sr_op__sv_pred_sz, input_sr_op__insn, input_sr_op__is_signed, input_sr_op__is_32bit, input_sr_op__output_cr, input_sr_op__input_cr, input_sr_op__output_carry, input_sr_op__input_carry, input_sr_op__invert_in, input_sr_op__write_cr0, input_sr_op__oe__ok, input_sr_op__oe__oe, input_sr_op__rc__ok, input_sr_op__rc__rc, input_sr_op__imm_data__ok, input_sr_op__imm_data__data, input_sr_op__fn_unit, input_sr_op__insn_type } = { \sr_op__SV_Ptype$22 , \sr_op__sv_saturate$21 , \sr_op__sv_pred_dz$20 , \sr_op__sv_pred_sz$19 , \sr_op__insn$18 , \sr_op__is_signed$17 , \sr_op__is_32bit$16 , \sr_op__output_cr$15 , \sr_op__input_cr$14 , \sr_op__output_carry$13 , \sr_op__input_carry$12 , \sr_op__invert_in$11 , \sr_op__write_cr0$10 , \sr_op__oe__ok$9 , \sr_op__oe__oe$8 , \sr_op__rc__ok$7 , \sr_op__rc__rc$6 , \sr_op__imm_data__ok$5 , \sr_op__imm_data__data$4 , \sr_op__fn_unit$3 , \sr_op__insn_type$2 };
+ assign { input_sr_op__SV_Ptype, input_sr_op__sv_ldstmode, input_sr_op__sv_saturate, input_sr_op__sv_pred_dz, input_sr_op__sv_pred_sz, input_sr_op__insn, input_sr_op__is_signed, input_sr_op__is_32bit, input_sr_op__output_cr, input_sr_op__input_cr, input_sr_op__output_carry, input_sr_op__input_carry, input_sr_op__invert_in, input_sr_op__write_cr0, input_sr_op__oe__ok, input_sr_op__oe__oe, input_sr_op__rc__ok, input_sr_op__rc__rc, input_sr_op__imm_data__ok, input_sr_op__imm_data__data, input_sr_op__fn_unit, input_sr_op__insn_type } = { \sr_op__SV_Ptype$23 , \sr_op__sv_ldstmode$22 , \sr_op__sv_saturate$21 , \sr_op__sv_pred_dz$20 , \sr_op__sv_pred_sz$19 , \sr_op__insn$18 , \sr_op__is_signed$17 , \sr_op__is_32bit$16 , \sr_op__output_cr$15 , \sr_op__input_cr$14 , \sr_op__output_carry$13 , \sr_op__input_carry$12 , \sr_op__invert_in$11 , \sr_op__write_cr0$10 , \sr_op__oe__ok$9 , \sr_op__oe__oe$8 , \sr_op__rc__ok$7 , \sr_op__rc__rc$6 , \sr_op__imm_data__ok$5 , \sr_op__imm_data__data$4 , \sr_op__fn_unit$3 , \sr_op__insn_type$2 };
assign input_muxid = \muxid$1 ;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1" *)
(* generator = "nMigen" *)
-module \pipe1$32 (coresync_rst, n_valid_o, n_ready_i, muxid, trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__svstate, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, trap_op__sv_pred_sz, trap_op__sv_pred_dz, trap_op__sv_saturate, trap_op__SV_Ptype, ra, rb, fast1, fast2, fast3, p_valid_i, p_ready_o, \muxid$1 , \trap_op__insn_type$2 , \trap_op__fn_unit$3 , \trap_op__insn$4 , \trap_op__msr$5 , \trap_op__cia$6 , \trap_op__svstate$7 , \trap_op__is_32bit$8 , \trap_op__traptype$9 , \trap_op__trapaddr$10 , \trap_op__ldst_exc$11 , \trap_op__sv_pred_sz$12 , \trap_op__sv_pred_dz$13 , \trap_op__sv_saturate$14 , \trap_op__SV_Ptype$15 , \ra$16 , \rb$17 , \fast1$18 , \fast2$19 , \fast3$20 , coresync_clk);
+module \pipe1$32 (coresync_rst, n_valid_o, n_ready_i, muxid, trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__svstate, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, trap_op__sv_pred_sz, trap_op__sv_pred_dz, trap_op__sv_saturate, trap_op__sv_ldstmode, trap_op__SV_Ptype, ra, rb, fast1, fast2, fast3, p_valid_i, p_ready_o, \muxid$1 , \trap_op__insn_type$2 , \trap_op__fn_unit$3 , \trap_op__insn$4 , \trap_op__msr$5 , \trap_op__cia$6 , \trap_op__svstate$7 , \trap_op__is_32bit$8 , \trap_op__traptype$9 , \trap_op__trapaddr$10 , \trap_op__ldst_exc$11 , \trap_op__sv_pred_sz$12 , \trap_op__sv_pred_dz$13 , \trap_op__sv_saturate$14 , \trap_op__sv_ldstmode$15 , \trap_op__SV_Ptype$16 , \ra$17 , \rb$18 , \fast1$19 , \fast2$20 , \fast3$21 , coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
- wire \$42 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ wire \$44 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] dummy_fast1;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \dummy_fast1$38 ;
+ wire [63:0] \dummy_fast1$40 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] dummy_fast2;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \dummy_fast2$39 ;
+ wire [63:0] \dummy_fast2$41 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] dummy_fast3;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \dummy_fast3$40 ;
+ wire [63:0] \dummy_fast3$42 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] dummy_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \dummy_muxid$21 ;
+ wire [1:0] \dummy_muxid$22 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] dummy_ra;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \dummy_ra$36 ;
+ wire [63:0] \dummy_ra$38 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] dummy_rb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \dummy_rb$37 ;
+ wire [63:0] \dummy_rb$39 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \dummy_trap_op__SV_Ptype$35 ;
+ wire [1:0] \dummy_trap_op__SV_Ptype$37 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] dummy_trap_op__cia;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \dummy_trap_op__cia$26 ;
+ wire [63:0] \dummy_trap_op__cia$27 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \dummy_trap_op__fn_unit$23 ;
+ wire [14:0] \dummy_trap_op__fn_unit$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] dummy_trap_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \dummy_trap_op__insn$24 ;
+ wire [31:0] \dummy_trap_op__insn$25 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \dummy_trap_op__insn_type$22 ;
+ wire [6:0] \dummy_trap_op__insn_type$23 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire dummy_trap_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \dummy_trap_op__is_32bit$28 ;
+ wire \dummy_trap_op__is_32bit$29 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [7:0] dummy_trap_op__ldst_exc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [7:0] \dummy_trap_op__ldst_exc$31 ;
+ wire [7:0] \dummy_trap_op__ldst_exc$32 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] dummy_trap_op__msr;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \dummy_trap_op__msr$25 ;
+ wire [63:0] \dummy_trap_op__msr$26 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] dummy_trap_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \dummy_trap_op__sv_ldstmode$36 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire dummy_trap_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \dummy_trap_op__sv_pred_dz$33 ;
+ wire \dummy_trap_op__sv_pred_dz$34 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire dummy_trap_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \dummy_trap_op__sv_pred_sz$32 ;
+ wire \dummy_trap_op__sv_pred_sz$33 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \dummy_trap_op__sv_saturate$34 ;
+ wire [1:0] \dummy_trap_op__sv_saturate$35 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] dummy_trap_op__svstate;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \dummy_trap_op__svstate$27 ;
+ wire [31:0] \dummy_trap_op__svstate$28 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [12:0] dummy_trap_op__trapaddr;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [12:0] \dummy_trap_op__trapaddr$30 ;
+ wire [12:0] \dummy_trap_op__trapaddr$31 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [7:0] dummy_trap_op__traptype;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [7:0] \dummy_trap_op__traptype$29 ;
+ wire [7:0] \dummy_trap_op__traptype$30 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
output [63:0] fast1;
reg [63:0] fast1 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- input [63:0] \fast1$18 ;
+ input [63:0] \fast1$19 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \fast1$61 ;
+ wire [63:0] \fast1$64 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
reg [63:0] \fast1$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
output [63:0] fast2;
reg [63:0] fast2 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- input [63:0] \fast2$19 ;
+ input [63:0] \fast2$20 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \fast2$62 ;
+ wire [63:0] \fast2$65 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
reg [63:0] \fast2$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
output [63:0] fast3;
reg [63:0] fast3 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- input [63:0] \fast3$20 ;
+ input [63:0] \fast3$21 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \fast3$63 ;
+ wire [63:0] \fast3$66 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
reg [63:0] \fast3$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
input [1:0] \muxid$1 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \muxid$44 ;
+ wire [1:0] \muxid$46 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
reg [1:0] \muxid$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
input p_valid_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
- wire \p_valid_i$41 ;
+ wire \p_valid_i$43 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
wire p_valid_i_p_ready_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
output [63:0] ra;
reg [63:0] ra = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- input [63:0] \ra$16 ;
+ input [63:0] \ra$17 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \ra$59 ;
+ wire [63:0] \ra$62 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
reg [63:0] \ra$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
output [63:0] rb;
reg [63:0] rb = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- input [63:0] \rb$17 ;
+ input [63:0] \rb$18 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \rb$60 ;
+ wire [63:0] \rb$63 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
reg [63:0] \rb$next ;
(* enum_base_type = "SVPtype" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- input [1:0] \trap_op__SV_Ptype$15 ;
+ input [1:0] \trap_op__SV_Ptype$16 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \trap_op__SV_Ptype$58 ;
+ wire [1:0] \trap_op__SV_Ptype$61 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [1:0] \trap_op__SV_Ptype$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output [63:0] trap_op__cia;
reg [63:0] trap_op__cia = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \trap_op__cia$49 ;
+ wire [63:0] \trap_op__cia$51 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] \trap_op__cia$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \trap_op__fn_unit$46 ;
+ wire [14:0] \trap_op__fn_unit$48 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [14:0] \trap_op__fn_unit$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] \trap_op__insn$4 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \trap_op__insn$47 ;
+ wire [31:0] \trap_op__insn$49 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [31:0] \trap_op__insn$next ;
(* enum_base_type = "MicrOp" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \trap_op__insn_type$45 ;
+ wire [6:0] \trap_op__insn_type$47 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [6:0] \trap_op__insn_type$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output trap_op__is_32bit;
reg trap_op__is_32bit = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \trap_op__is_32bit$51 ;
+ wire \trap_op__is_32bit$53 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \trap_op__is_32bit$8 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [7:0] \trap_op__ldst_exc$11 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [7:0] \trap_op__ldst_exc$54 ;
+ wire [7:0] \trap_op__ldst_exc$56 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [7:0] \trap_op__ldst_exc$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output [63:0] trap_op__msr;
reg [63:0] trap_op__msr = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \trap_op__msr$48 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] \trap_op__msr$5 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [63:0] \trap_op__msr$50 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [63:0] \trap_op__msr$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] trap_op__sv_ldstmode;
+ reg [1:0] trap_op__sv_ldstmode = 2'h0;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] \trap_op__sv_ldstmode$15 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \trap_op__sv_ldstmode$60 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \trap_op__sv_ldstmode$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output trap_op__sv_pred_dz;
reg trap_op__sv_pred_dz = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \trap_op__sv_pred_dz$13 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \trap_op__sv_pred_dz$56 ;
+ wire \trap_op__sv_pred_dz$58 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \trap_op__sv_pred_dz$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \trap_op__sv_pred_sz$12 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \trap_op__sv_pred_sz$55 ;
+ wire \trap_op__sv_pred_sz$57 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \trap_op__sv_pred_sz$next ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \trap_op__sv_saturate$57 ;
+ wire [1:0] \trap_op__sv_saturate$59 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [1:0] \trap_op__sv_saturate$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output [31:0] trap_op__svstate;
reg [31:0] trap_op__svstate = 32'd0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \trap_op__svstate$50 ;
+ wire [31:0] \trap_op__svstate$52 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] \trap_op__svstate$7 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [12:0] \trap_op__trapaddr$10 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [12:0] \trap_op__trapaddr$53 ;
+ wire [12:0] \trap_op__trapaddr$55 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [12:0] \trap_op__trapaddr$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output [7:0] trap_op__traptype;
reg [7:0] trap_op__traptype = 8'h00;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [7:0] \trap_op__traptype$52 ;
+ wire [7:0] \trap_op__traptype$54 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [7:0] \trap_op__traptype$9 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [7:0] \trap_op__traptype$next ;
- assign \$42 = \p_valid_i$41 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
+ assign \$44 = \p_valid_i$43 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
always @(posedge coresync_clk)
fast3 <= \fast3$next ;
always @(posedge coresync_clk)
trap_op__sv_pred_dz <= \trap_op__sv_pred_dz$next ;
always @(posedge coresync_clk)
trap_op__sv_saturate <= \trap_op__sv_saturate$next ;
+ always @(posedge coresync_clk)
+ trap_op__sv_ldstmode <= \trap_op__sv_ldstmode$next ;
always @(posedge coresync_clk)
trap_op__SV_Ptype <= \trap_op__SV_Ptype$next ;
always @(posedge coresync_clk)
r_busy <= \r_busy$next ;
dummy dummy (
.fast1(dummy_fast1),
- .\fast1$18 (\dummy_fast1$38 ),
+ .\fast1$19 (\dummy_fast1$40 ),
.fast2(dummy_fast2),
- .\fast2$19 (\dummy_fast2$39 ),
+ .\fast2$20 (\dummy_fast2$41 ),
.fast3(dummy_fast3),
- .\fast3$20 (\dummy_fast3$40 ),
+ .\fast3$21 (\dummy_fast3$42 ),
.muxid(dummy_muxid),
- .\muxid$1 (\dummy_muxid$21 ),
+ .\muxid$1 (\dummy_muxid$22 ),
.ra(dummy_ra),
- .\ra$16 (\dummy_ra$36 ),
+ .\ra$17 (\dummy_ra$38 ),
.rb(dummy_rb),
- .\rb$17 (\dummy_rb$37 ),
+ .\rb$18 (\dummy_rb$39 ),
.trap_op__SV_Ptype(dummy_trap_op__SV_Ptype),
- .\trap_op__SV_Ptype$15 (\dummy_trap_op__SV_Ptype$35 ),
+ .\trap_op__SV_Ptype$16 (\dummy_trap_op__SV_Ptype$37 ),
.trap_op__cia(dummy_trap_op__cia),
- .\trap_op__cia$6 (\dummy_trap_op__cia$26 ),
+ .\trap_op__cia$6 (\dummy_trap_op__cia$27 ),
.trap_op__fn_unit(dummy_trap_op__fn_unit),
- .\trap_op__fn_unit$3 (\dummy_trap_op__fn_unit$23 ),
+ .\trap_op__fn_unit$3 (\dummy_trap_op__fn_unit$24 ),
.trap_op__insn(dummy_trap_op__insn),
- .\trap_op__insn$4 (\dummy_trap_op__insn$24 ),
+ .\trap_op__insn$4 (\dummy_trap_op__insn$25 ),
.trap_op__insn_type(dummy_trap_op__insn_type),
- .\trap_op__insn_type$2 (\dummy_trap_op__insn_type$22 ),
+ .\trap_op__insn_type$2 (\dummy_trap_op__insn_type$23 ),
.trap_op__is_32bit(dummy_trap_op__is_32bit),
- .\trap_op__is_32bit$8 (\dummy_trap_op__is_32bit$28 ),
+ .\trap_op__is_32bit$8 (\dummy_trap_op__is_32bit$29 ),
.trap_op__ldst_exc(dummy_trap_op__ldst_exc),
- .\trap_op__ldst_exc$11 (\dummy_trap_op__ldst_exc$31 ),
+ .\trap_op__ldst_exc$11 (\dummy_trap_op__ldst_exc$32 ),
.trap_op__msr(dummy_trap_op__msr),
- .\trap_op__msr$5 (\dummy_trap_op__msr$25 ),
+ .\trap_op__msr$5 (\dummy_trap_op__msr$26 ),
+ .trap_op__sv_ldstmode(dummy_trap_op__sv_ldstmode),
+ .\trap_op__sv_ldstmode$15 (\dummy_trap_op__sv_ldstmode$36 ),
.trap_op__sv_pred_dz(dummy_trap_op__sv_pred_dz),
- .\trap_op__sv_pred_dz$13 (\dummy_trap_op__sv_pred_dz$33 ),
+ .\trap_op__sv_pred_dz$13 (\dummy_trap_op__sv_pred_dz$34 ),
.trap_op__sv_pred_sz(dummy_trap_op__sv_pred_sz),
- .\trap_op__sv_pred_sz$12 (\dummy_trap_op__sv_pred_sz$32 ),
+ .\trap_op__sv_pred_sz$12 (\dummy_trap_op__sv_pred_sz$33 ),
.trap_op__sv_saturate(dummy_trap_op__sv_saturate),
- .\trap_op__sv_saturate$14 (\dummy_trap_op__sv_saturate$34 ),
+ .\trap_op__sv_saturate$14 (\dummy_trap_op__sv_saturate$35 ),
.trap_op__svstate(dummy_trap_op__svstate),
- .\trap_op__svstate$7 (\dummy_trap_op__svstate$27 ),
+ .\trap_op__svstate$7 (\dummy_trap_op__svstate$28 ),
.trap_op__trapaddr(dummy_trap_op__trapaddr),
- .\trap_op__trapaddr$10 (\dummy_trap_op__trapaddr$30 ),
+ .\trap_op__trapaddr$10 (\dummy_trap_op__trapaddr$31 ),
.trap_op__traptype(dummy_trap_op__traptype),
- .\trap_op__traptype$9 (\dummy_trap_op__traptype$29 )
+ .\trap_op__traptype$9 (\dummy_trap_op__traptype$30 )
);
\n$34 n (
.n_ready_i(n_ready_i),
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \muxid$next = \muxid$44 ;
+ \muxid$next = \muxid$46 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \muxid$next = \muxid$44 ;
+ \muxid$next = \muxid$46 ;
endcase
end
always @* begin
\trap_op__sv_pred_sz$next = trap_op__sv_pred_sz;
\trap_op__sv_pred_dz$next = trap_op__sv_pred_dz;
\trap_op__sv_saturate$next = trap_op__sv_saturate;
+ \trap_op__sv_ldstmode$next = trap_op__sv_ldstmode;
\trap_op__SV_Ptype$next = trap_op__SV_Ptype;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \trap_op__SV_Ptype$next , \trap_op__sv_saturate$next , \trap_op__sv_pred_dz$next , \trap_op__sv_pred_sz$next , \trap_op__ldst_exc$next , \trap_op__trapaddr$next , \trap_op__traptype$next , \trap_op__is_32bit$next , \trap_op__svstate$next , \trap_op__cia$next , \trap_op__msr$next , \trap_op__insn$next , \trap_op__fn_unit$next , \trap_op__insn_type$next } = { \trap_op__SV_Ptype$58 , \trap_op__sv_saturate$57 , \trap_op__sv_pred_dz$56 , \trap_op__sv_pred_sz$55 , \trap_op__ldst_exc$54 , \trap_op__trapaddr$53 , \trap_op__traptype$52 , \trap_op__is_32bit$51 , \trap_op__svstate$50 , \trap_op__cia$49 , \trap_op__msr$48 , \trap_op__insn$47 , \trap_op__fn_unit$46 , \trap_op__insn_type$45 };
+ { \trap_op__SV_Ptype$next , \trap_op__sv_ldstmode$next , \trap_op__sv_saturate$next , \trap_op__sv_pred_dz$next , \trap_op__sv_pred_sz$next , \trap_op__ldst_exc$next , \trap_op__trapaddr$next , \trap_op__traptype$next , \trap_op__is_32bit$next , \trap_op__svstate$next , \trap_op__cia$next , \trap_op__msr$next , \trap_op__insn$next , \trap_op__fn_unit$next , \trap_op__insn_type$next } = { \trap_op__SV_Ptype$61 , \trap_op__sv_ldstmode$60 , \trap_op__sv_saturate$59 , \trap_op__sv_pred_dz$58 , \trap_op__sv_pred_sz$57 , \trap_op__ldst_exc$56 , \trap_op__trapaddr$55 , \trap_op__traptype$54 , \trap_op__is_32bit$53 , \trap_op__svstate$52 , \trap_op__cia$51 , \trap_op__msr$50 , \trap_op__insn$49 , \trap_op__fn_unit$48 , \trap_op__insn_type$47 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \trap_op__SV_Ptype$next , \trap_op__sv_saturate$next , \trap_op__sv_pred_dz$next , \trap_op__sv_pred_sz$next , \trap_op__ldst_exc$next , \trap_op__trapaddr$next , \trap_op__traptype$next , \trap_op__is_32bit$next , \trap_op__svstate$next , \trap_op__cia$next , \trap_op__msr$next , \trap_op__insn$next , \trap_op__fn_unit$next , \trap_op__insn_type$next } = { \trap_op__SV_Ptype$58 , \trap_op__sv_saturate$57 , \trap_op__sv_pred_dz$56 , \trap_op__sv_pred_sz$55 , \trap_op__ldst_exc$54 , \trap_op__trapaddr$53 , \trap_op__traptype$52 , \trap_op__is_32bit$51 , \trap_op__svstate$50 , \trap_op__cia$49 , \trap_op__msr$48 , \trap_op__insn$47 , \trap_op__fn_unit$46 , \trap_op__insn_type$45 };
+ { \trap_op__SV_Ptype$next , \trap_op__sv_ldstmode$next , \trap_op__sv_saturate$next , \trap_op__sv_pred_dz$next , \trap_op__sv_pred_sz$next , \trap_op__ldst_exc$next , \trap_op__trapaddr$next , \trap_op__traptype$next , \trap_op__is_32bit$next , \trap_op__svstate$next , \trap_op__cia$next , \trap_op__msr$next , \trap_op__insn$next , \trap_op__fn_unit$next , \trap_op__insn_type$next } = { \trap_op__SV_Ptype$61 , \trap_op__sv_ldstmode$60 , \trap_op__sv_saturate$59 , \trap_op__sv_pred_dz$58 , \trap_op__sv_pred_sz$57 , \trap_op__ldst_exc$56 , \trap_op__trapaddr$55 , \trap_op__traptype$54 , \trap_op__is_32bit$53 , \trap_op__svstate$52 , \trap_op__cia$51 , \trap_op__msr$50 , \trap_op__insn$49 , \trap_op__fn_unit$48 , \trap_op__insn_type$47 };
endcase
end
always @* begin
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \ra$next = \ra$59 ;
+ \ra$next = \ra$62 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \ra$next = \ra$59 ;
+ \ra$next = \ra$62 ;
endcase
end
always @* begin
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \rb$next = \rb$60 ;
+ \rb$next = \rb$63 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \rb$next = \rb$60 ;
+ \rb$next = \rb$63 ;
endcase
end
always @* begin
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \fast1$next = \fast1$61 ;
+ \fast1$next = \fast1$64 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \fast1$next = \fast1$61 ;
+ \fast1$next = \fast1$64 ;
endcase
end
always @* begin
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \fast2$next = \fast2$62 ;
+ \fast2$next = \fast2$65 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \fast2$next = \fast2$62 ;
+ \fast2$next = \fast2$65 ;
endcase
end
always @* begin
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \fast3$next = \fast3$63 ;
+ \fast3$next = \fast3$66 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \fast3$next = \fast3$63 ;
+ \fast3$next = \fast3$66 ;
endcase
end
assign p_ready_o = n_i_rdy_data;
assign n_valid_o = r_busy;
- assign \fast3$63 = \dummy_fast3$40 ;
- assign \fast2$62 = \dummy_fast2$39 ;
- assign \fast1$61 = \dummy_fast1$38 ;
- assign \rb$60 = \dummy_rb$37 ;
- assign \ra$59 = \dummy_ra$36 ;
- assign { \trap_op__SV_Ptype$58 , \trap_op__sv_saturate$57 , \trap_op__sv_pred_dz$56 , \trap_op__sv_pred_sz$55 , \trap_op__ldst_exc$54 , \trap_op__trapaddr$53 , \trap_op__traptype$52 , \trap_op__is_32bit$51 , \trap_op__svstate$50 , \trap_op__cia$49 , \trap_op__msr$48 , \trap_op__insn$47 , \trap_op__fn_unit$46 , \trap_op__insn_type$45 } = { \dummy_trap_op__SV_Ptype$35 , \dummy_trap_op__sv_saturate$34 , \dummy_trap_op__sv_pred_dz$33 , \dummy_trap_op__sv_pred_sz$32 , \dummy_trap_op__ldst_exc$31 , \dummy_trap_op__trapaddr$30 , \dummy_trap_op__traptype$29 , \dummy_trap_op__is_32bit$28 , \dummy_trap_op__svstate$27 , \dummy_trap_op__cia$26 , \dummy_trap_op__msr$25 , \dummy_trap_op__insn$24 , \dummy_trap_op__fn_unit$23 , \dummy_trap_op__insn_type$22 };
- assign \muxid$44 = \dummy_muxid$21 ;
- assign p_valid_i_p_ready_o = \$42 ;
+ assign \fast3$66 = \dummy_fast3$42 ;
+ assign \fast2$65 = \dummy_fast2$41 ;
+ assign \fast1$64 = \dummy_fast1$40 ;
+ assign \rb$63 = \dummy_rb$39 ;
+ assign \ra$62 = \dummy_ra$38 ;
+ assign { \trap_op__SV_Ptype$61 , \trap_op__sv_ldstmode$60 , \trap_op__sv_saturate$59 , \trap_op__sv_pred_dz$58 , \trap_op__sv_pred_sz$57 , \trap_op__ldst_exc$56 , \trap_op__trapaddr$55 , \trap_op__traptype$54 , \trap_op__is_32bit$53 , \trap_op__svstate$52 , \trap_op__cia$51 , \trap_op__msr$50 , \trap_op__insn$49 , \trap_op__fn_unit$48 , \trap_op__insn_type$47 } = { \dummy_trap_op__SV_Ptype$37 , \dummy_trap_op__sv_ldstmode$36 , \dummy_trap_op__sv_saturate$35 , \dummy_trap_op__sv_pred_dz$34 , \dummy_trap_op__sv_pred_sz$33 , \dummy_trap_op__ldst_exc$32 , \dummy_trap_op__trapaddr$31 , \dummy_trap_op__traptype$30 , \dummy_trap_op__is_32bit$29 , \dummy_trap_op__svstate$28 , \dummy_trap_op__cia$27 , \dummy_trap_op__msr$26 , \dummy_trap_op__insn$25 , \dummy_trap_op__fn_unit$24 , \dummy_trap_op__insn_type$23 };
+ assign \muxid$46 = \dummy_muxid$22 ;
+ assign p_valid_i_p_ready_o = \$44 ;
assign n_i_rdy_data = n_ready_i;
- assign \p_valid_i$41 = p_valid_i;
- assign dummy_fast3 = \fast3$20 ;
- assign dummy_fast2 = \fast2$19 ;
- assign dummy_fast1 = \fast1$18 ;
- assign dummy_rb = \rb$17 ;
- assign dummy_ra = \ra$16 ;
- assign { dummy_trap_op__SV_Ptype, dummy_trap_op__sv_saturate, dummy_trap_op__sv_pred_dz, dummy_trap_op__sv_pred_sz, dummy_trap_op__ldst_exc, dummy_trap_op__trapaddr, dummy_trap_op__traptype, dummy_trap_op__is_32bit, dummy_trap_op__svstate, dummy_trap_op__cia, dummy_trap_op__msr, dummy_trap_op__insn, dummy_trap_op__fn_unit, dummy_trap_op__insn_type } = { \trap_op__SV_Ptype$15 , \trap_op__sv_saturate$14 , \trap_op__sv_pred_dz$13 , \trap_op__sv_pred_sz$12 , \trap_op__ldst_exc$11 , \trap_op__trapaddr$10 , \trap_op__traptype$9 , \trap_op__is_32bit$8 , \trap_op__svstate$7 , \trap_op__cia$6 , \trap_op__msr$5 , \trap_op__insn$4 , \trap_op__fn_unit$3 , \trap_op__insn_type$2 };
+ assign \p_valid_i$43 = p_valid_i;
+ assign dummy_fast3 = \fast3$21 ;
+ assign dummy_fast2 = \fast2$20 ;
+ assign dummy_fast1 = \fast1$19 ;
+ assign dummy_rb = \rb$18 ;
+ assign dummy_ra = \ra$17 ;
+ assign { dummy_trap_op__SV_Ptype, dummy_trap_op__sv_ldstmode, dummy_trap_op__sv_saturate, dummy_trap_op__sv_pred_dz, dummy_trap_op__sv_pred_sz, dummy_trap_op__ldst_exc, dummy_trap_op__trapaddr, dummy_trap_op__traptype, dummy_trap_op__is_32bit, dummy_trap_op__svstate, dummy_trap_op__cia, dummy_trap_op__msr, dummy_trap_op__insn, dummy_trap_op__fn_unit, dummy_trap_op__insn_type } = { \trap_op__SV_Ptype$16 , \trap_op__sv_ldstmode$15 , \trap_op__sv_saturate$14 , \trap_op__sv_pred_dz$13 , \trap_op__sv_pred_sz$12 , \trap_op__ldst_exc$11 , \trap_op__trapaddr$10 , \trap_op__traptype$9 , \trap_op__is_32bit$8 , \trap_op__svstate$7 , \trap_op__cia$6 , \trap_op__msr$5 , \trap_op__insn$4 , \trap_op__fn_unit$3 , \trap_op__insn_type$2 };
assign dummy_muxid = \muxid$1 ;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2" *)
(* generator = "nMigen" *)
-module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, alu_op__sv_pred_sz, alu_op__sv_pred_dz, alu_op__sv_saturate, alu_op__SV_Ptype, o, o_ok, cr_a, cr_a_ok, xer_ca, xer_ca_ok, xer_ov, xer_ov_ok, xer_so, xer_so_ok, n_valid_o, n_ready_i, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , \alu_op__sv_pred_sz$20 , \alu_op__sv_pred_dz$21 , \alu_op__sv_saturate$22 , \alu_op__SV_Ptype$23 , \o$24 , \o_ok$25 , \cr_a$26 , \cr_a_ok$27 , \xer_ca$28 , \xer_ca_ok$29 , \xer_ov$30 , \xer_ov_ok$31 , \xer_so$32 , \xer_so_ok$33 , coresync_clk);
+module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, alu_op__sv_pred_sz, alu_op__sv_pred_dz, alu_op__sv_saturate, alu_op__sv_ldstmode, alu_op__SV_Ptype, o, o_ok, cr_a, cr_a_ok, xer_ca, xer_ca_ok, xer_ov, xer_ov_ok, xer_so, xer_so_ok, n_valid_o, n_ready_i, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , \alu_op__sv_pred_sz$20 , \alu_op__sv_pred_dz$21 , \alu_op__sv_saturate$22 , \alu_op__sv_ldstmode$23 , \alu_op__SV_Ptype$24 , \o$25 , \o_ok$26 , \cr_a$27 , \cr_a_ok$28 , \xer_ca$29 , \xer_ca_ok$30 , \xer_ov$31 , \xer_ov_ok$32 , \xer_so$33 , \xer_so_ok$34 , coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
- wire \$68 ;
+ wire \$70 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \alu_op__SV_Ptype$23 ;
- reg [1:0] \alu_op__SV_Ptype$23 = 2'h0;
+ output [1:0] \alu_op__SV_Ptype$24 ;
+ reg [1:0] \alu_op__SV_Ptype$24 = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [1:0] \alu_op__SV_Ptype$23$next ;
+ reg [1:0] \alu_op__SV_Ptype$24$next ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \alu_op__SV_Ptype$92 ;
+ wire [1:0] \alu_op__SV_Ptype$95 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [3:0] alu_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [3:0] \alu_op__data_len$18$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [3:0] \alu_op__data_len$87 ;
+ wire [3:0] \alu_op__data_len$89 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \alu_op__fn_unit$72 ;
+ wire [14:0] \alu_op__fn_unit$74 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] alu_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [63:0] \alu_op__imm_data__data$4$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \alu_op__imm_data__data$73 ;
+ wire [63:0] \alu_op__imm_data__data$75 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_op__imm_data__ok$5$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__imm_data__ok$74 ;
+ wire \alu_op__imm_data__ok$76 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \alu_op__input_carry$83 ;
+ wire [1:0] \alu_op__input_carry$85 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] alu_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [31:0] \alu_op__insn$19$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \alu_op__insn$88 ;
+ wire [31:0] \alu_op__insn$90 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \alu_op__insn_type$71 ;
+ wire [6:0] \alu_op__insn_type$73 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_op__invert_in$10$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__invert_in$79 ;
+ wire \alu_op__invert_in$81 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__invert_out;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_op__invert_out$12$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__invert_out$81 ;
+ wire \alu_op__invert_out$83 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_op__is_32bit$16$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__is_32bit$85 ;
+ wire \alu_op__is_32bit$87 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_op__is_signed$17$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__is_signed$86 ;
+ wire \alu_op__is_signed$88 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__oe__oe$77 ;
+ wire \alu_op__oe__oe$79 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \alu_op__oe__oe$8 ;
reg \alu_op__oe__oe$8 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__oe__ok$78 ;
+ wire \alu_op__oe__ok$80 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \alu_op__oe__ok$9 ;
reg \alu_op__oe__ok$9 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_op__output_carry$15$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__output_carry$84 ;
+ wire \alu_op__output_carry$86 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_op__rc__ok$7$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__rc__ok$76 ;
+ wire \alu_op__rc__ok$78 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_op__rc__rc$6$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__rc__rc$75 ;
+ wire \alu_op__rc__rc$77 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] alu_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \alu_op__sv_ldstmode$23 ;
+ reg [1:0] \alu_op__sv_ldstmode$23 = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \alu_op__sv_ldstmode$23$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \alu_op__sv_ldstmode$94 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_op__sv_pred_dz$21$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__sv_pred_dz$90 ;
+ wire \alu_op__sv_pred_dz$92 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_op__sv_pred_sz$20$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__sv_pred_sz$89 ;
+ wire \alu_op__sv_pred_sz$91 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \alu_op__sv_saturate$91 ;
+ wire [1:0] \alu_op__sv_saturate$93 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_op__write_cr0$13$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__write_cr0$82 ;
+ wire \alu_op__write_cr0$84 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input alu_op__zero_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_op__zero_a$11$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \alu_op__zero_a$80 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ wire \alu_op__zero_a$82 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input [3:0] cr_a;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [3:0] \cr_a$26 ;
- reg [3:0] \cr_a$26 = 4'h0;
+ output [3:0] \cr_a$27 ;
+ reg [3:0] \cr_a$27 = 4'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg [3:0] \cr_a$26$next ;
+ reg [3:0] \cr_a$27$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [3:0] \cr_a$95 ;
+ wire [3:0] \cr_a$98 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input cr_a_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \cr_a_ok$27 ;
- reg \cr_a_ok$27 = 1'h0;
+ output \cr_a_ok$28 ;
+ reg \cr_a_ok$28 = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg \cr_a_ok$27$next ;
+ reg \cr_a_ok$28$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \cr_a_ok$63 ;
+ wire \cr_a_ok$65 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \cr_a_ok$96 ;
+ wire \cr_a_ok$99 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
input [1:0] muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
reg [1:0] \muxid$1$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \muxid$70 ;
+ wire [1:0] \muxid$72 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
wire n_i_rdy_data;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input [63:0] o;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [63:0] \o$24 ;
- reg [63:0] \o$24 = 64'h0000000000000000;
+ output [63:0] \o$25 ;
+ reg [63:0] \o$25 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg [63:0] \o$24$next ;
+ reg [63:0] \o$25$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \o$93 ;
+ wire [63:0] \o$96 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input o_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \o_ok$25 ;
- reg \o_ok$25 = 1'h0;
+ output \o_ok$26 ;
+ reg \o_ok$26 = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg \o_ok$25$next ;
+ reg \o_ok$26$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \o_ok$94 ;
+ wire \o_ok$97 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \output_alu_op__SV_Ptype$56 ;
+ wire [1:0] \output_alu_op__SV_Ptype$58 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [3:0] output_alu_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [3:0] \output_alu_op__data_len$51 ;
+ wire [3:0] \output_alu_op__data_len$52 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \output_alu_op__fn_unit$36 ;
+ wire [14:0] \output_alu_op__fn_unit$37 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] output_alu_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \output_alu_op__imm_data__data$37 ;
+ wire [63:0] \output_alu_op__imm_data__data$38 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_alu_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_alu_op__imm_data__ok$38 ;
+ wire \output_alu_op__imm_data__ok$39 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \output_alu_op__input_carry$47 ;
+ wire [1:0] \output_alu_op__input_carry$48 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] output_alu_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \output_alu_op__insn$52 ;
+ wire [31:0] \output_alu_op__insn$53 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \output_alu_op__insn_type$35 ;
+ wire [6:0] \output_alu_op__insn_type$36 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_alu_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_alu_op__invert_in$43 ;
+ wire \output_alu_op__invert_in$44 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_alu_op__invert_out;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_alu_op__invert_out$45 ;
+ wire \output_alu_op__invert_out$46 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_alu_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_alu_op__is_32bit$49 ;
+ wire \output_alu_op__is_32bit$50 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_alu_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_alu_op__is_signed$50 ;
+ wire \output_alu_op__is_signed$51 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_alu_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_alu_op__oe__oe$41 ;
+ wire \output_alu_op__oe__oe$42 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_alu_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_alu_op__oe__ok$42 ;
+ wire \output_alu_op__oe__ok$43 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_alu_op__output_carry;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_alu_op__output_carry$48 ;
+ wire \output_alu_op__output_carry$49 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_alu_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_alu_op__rc__ok$40 ;
+ wire \output_alu_op__rc__ok$41 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_alu_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_alu_op__rc__rc$39 ;
+ wire \output_alu_op__rc__rc$40 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] output_alu_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \output_alu_op__sv_ldstmode$57 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_alu_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_alu_op__sv_pred_dz$54 ;
+ wire \output_alu_op__sv_pred_dz$55 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_alu_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_alu_op__sv_pred_sz$53 ;
+ wire \output_alu_op__sv_pred_sz$54 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \output_alu_op__sv_saturate$55 ;
+ wire [1:0] \output_alu_op__sv_saturate$56 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_alu_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_alu_op__write_cr0$46 ;
+ wire \output_alu_op__write_cr0$47 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_alu_op__zero_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_alu_op__zero_a$44 ;
+ wire \output_alu_op__zero_a$45 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [3:0] output_cr_a;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [3:0] \output_cr_a$59 ;
+ wire [3:0] \output_cr_a$61 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire output_cr_a_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] output_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \output_muxid$34 ;
+ wire [1:0] \output_muxid$35 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [63:0] output_o;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \output_o$57 ;
+ wire [63:0] \output_o$59 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire output_o_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \output_o_ok$58 ;
+ wire \output_o_ok$60 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [1:0] output_xer_ca;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [1:0] \output_xer_ca$60 ;
+ wire [1:0] \output_xer_ca$62 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire output_xer_ca_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [1:0] output_xer_ov;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [1:0] \output_xer_ov$61 ;
+ wire [1:0] \output_xer_ov$63 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire output_xer_ov_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire output_xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \output_xer_so$62 ;
+ wire \output_xer_so$64 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire output_xer_so_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
input p_valid_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
- wire \p_valid_i$67 ;
+ wire \p_valid_i$69 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
wire p_valid_i_p_ready_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input [1:0] xer_ca;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [1:0] \xer_ca$28 ;
- reg [1:0] \xer_ca$28 = 2'h0;
+ wire [1:0] \xer_ca$100 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg [1:0] \xer_ca$28$next ;
+ output [1:0] \xer_ca$29 ;
+ reg [1:0] \xer_ca$29 = 2'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [1:0] \xer_ca$97 ;
+ reg [1:0] \xer_ca$29$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input xer_ca_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \xer_ca_ok$29 ;
- reg \xer_ca_ok$29 = 1'h0;
+ wire \xer_ca_ok$101 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg \xer_ca_ok$29$next ;
+ output \xer_ca_ok$30 ;
+ reg \xer_ca_ok$30 = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_ca_ok$64 ;
+ reg \xer_ca_ok$30$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_ca_ok$98 ;
+ wire \xer_ca_ok$66 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input [1:0] xer_ov;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [1:0] \xer_ov$30 ;
- reg [1:0] \xer_ov$30 = 2'h0;
+ wire [1:0] \xer_ov$102 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg [1:0] \xer_ov$30$next ;
+ output [1:0] \xer_ov$31 ;
+ reg [1:0] \xer_ov$31 = 2'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [1:0] \xer_ov$99 ;
+ reg [1:0] \xer_ov$31$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input xer_ov_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_ov_ok$100 ;
+ wire \xer_ov_ok$103 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \xer_ov_ok$31 ;
- reg \xer_ov_ok$31 = 1'h0;
+ output \xer_ov_ok$32 ;
+ reg \xer_ov_ok$32 = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg \xer_ov_ok$31$next ;
+ reg \xer_ov_ok$32$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_ov_ok$65 ;
+ wire \xer_ov_ok$67 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_so$101 ;
+ wire \xer_so$104 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \xer_so$32 ;
- reg \xer_so$32 = 1'h0;
+ output \xer_so$33 ;
+ reg \xer_so$33 = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg \xer_so$32$next ;
+ reg \xer_so$33$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input xer_so_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_so_ok$102 ;
+ wire \xer_so_ok$105 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \xer_so_ok$33 ;
- reg \xer_so_ok$33 = 1'h0;
+ output \xer_so_ok$34 ;
+ reg \xer_so_ok$34 = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg \xer_so_ok$33$next ;
+ reg \xer_so_ok$34$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_so_ok$66 ;
- assign \$68 = \p_valid_i$67 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
+ wire \xer_so_ok$68 ;
+ assign \$70 = \p_valid_i$69 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
always @(posedge coresync_clk)
- \xer_so$32 <= \xer_so$32$next ;
+ \xer_so$33 <= \xer_so$33$next ;
always @(posedge coresync_clk)
- \xer_so_ok$33 <= \xer_so_ok$33$next ;
+ \xer_so_ok$34 <= \xer_so_ok$34$next ;
always @(posedge coresync_clk)
- \xer_ov$30 <= \xer_ov$30$next ;
+ \xer_ov$31 <= \xer_ov$31$next ;
always @(posedge coresync_clk)
- \xer_ov_ok$31 <= \xer_ov_ok$31$next ;
+ \xer_ov_ok$32 <= \xer_ov_ok$32$next ;
always @(posedge coresync_clk)
- \xer_ca$28 <= \xer_ca$28$next ;
+ \xer_ca$29 <= \xer_ca$29$next ;
always @(posedge coresync_clk)
- \xer_ca_ok$29 <= \xer_ca_ok$29$next ;
+ \xer_ca_ok$30 <= \xer_ca_ok$30$next ;
always @(posedge coresync_clk)
- \cr_a$26 <= \cr_a$26$next ;
+ \cr_a$27 <= \cr_a$27$next ;
always @(posedge coresync_clk)
- \cr_a_ok$27 <= \cr_a_ok$27$next ;
+ \cr_a_ok$28 <= \cr_a_ok$28$next ;
always @(posedge coresync_clk)
- \o$24 <= \o$24$next ;
+ \o$25 <= \o$25$next ;
always @(posedge coresync_clk)
- \o_ok$25 <= \o_ok$25$next ;
+ \o_ok$26 <= \o_ok$26$next ;
always @(posedge coresync_clk)
\alu_op__insn_type$2 <= \alu_op__insn_type$2$next ;
always @(posedge coresync_clk)
always @(posedge coresync_clk)
\alu_op__sv_saturate$22 <= \alu_op__sv_saturate$22$next ;
always @(posedge coresync_clk)
- \alu_op__SV_Ptype$23 <= \alu_op__SV_Ptype$23$next ;
+ \alu_op__sv_ldstmode$23 <= \alu_op__sv_ldstmode$23$next ;
+ always @(posedge coresync_clk)
+ \alu_op__SV_Ptype$24 <= \alu_op__SV_Ptype$24$next ;
always @(posedge coresync_clk)
\muxid$1 <= \muxid$1$next ;
always @(posedge coresync_clk)
);
\output \output (
.alu_op__SV_Ptype(output_alu_op__SV_Ptype),
- .\alu_op__SV_Ptype$23 (\output_alu_op__SV_Ptype$56 ),
+ .\alu_op__SV_Ptype$24 (\output_alu_op__SV_Ptype$58 ),
.alu_op__data_len(output_alu_op__data_len),
- .\alu_op__data_len$18 (\output_alu_op__data_len$51 ),
+ .\alu_op__data_len$18 (\output_alu_op__data_len$52 ),
.alu_op__fn_unit(output_alu_op__fn_unit),
- .\alu_op__fn_unit$3 (\output_alu_op__fn_unit$36 ),
+ .\alu_op__fn_unit$3 (\output_alu_op__fn_unit$37 ),
.alu_op__imm_data__data(output_alu_op__imm_data__data),
- .\alu_op__imm_data__data$4 (\output_alu_op__imm_data__data$37 ),
+ .\alu_op__imm_data__data$4 (\output_alu_op__imm_data__data$38 ),
.alu_op__imm_data__ok(output_alu_op__imm_data__ok),
- .\alu_op__imm_data__ok$5 (\output_alu_op__imm_data__ok$38 ),
+ .\alu_op__imm_data__ok$5 (\output_alu_op__imm_data__ok$39 ),
.alu_op__input_carry(output_alu_op__input_carry),
- .\alu_op__input_carry$14 (\output_alu_op__input_carry$47 ),
+ .\alu_op__input_carry$14 (\output_alu_op__input_carry$48 ),
.alu_op__insn(output_alu_op__insn),
- .\alu_op__insn$19 (\output_alu_op__insn$52 ),
+ .\alu_op__insn$19 (\output_alu_op__insn$53 ),
.alu_op__insn_type(output_alu_op__insn_type),
- .\alu_op__insn_type$2 (\output_alu_op__insn_type$35 ),
+ .\alu_op__insn_type$2 (\output_alu_op__insn_type$36 ),
.alu_op__invert_in(output_alu_op__invert_in),
- .\alu_op__invert_in$10 (\output_alu_op__invert_in$43 ),
+ .\alu_op__invert_in$10 (\output_alu_op__invert_in$44 ),
.alu_op__invert_out(output_alu_op__invert_out),
- .\alu_op__invert_out$12 (\output_alu_op__invert_out$45 ),
+ .\alu_op__invert_out$12 (\output_alu_op__invert_out$46 ),
.alu_op__is_32bit(output_alu_op__is_32bit),
- .\alu_op__is_32bit$16 (\output_alu_op__is_32bit$49 ),
+ .\alu_op__is_32bit$16 (\output_alu_op__is_32bit$50 ),
.alu_op__is_signed(output_alu_op__is_signed),
- .\alu_op__is_signed$17 (\output_alu_op__is_signed$50 ),
+ .\alu_op__is_signed$17 (\output_alu_op__is_signed$51 ),
.alu_op__oe__oe(output_alu_op__oe__oe),
- .\alu_op__oe__oe$8 (\output_alu_op__oe__oe$41 ),
+ .\alu_op__oe__oe$8 (\output_alu_op__oe__oe$42 ),
.alu_op__oe__ok(output_alu_op__oe__ok),
- .\alu_op__oe__ok$9 (\output_alu_op__oe__ok$42 ),
+ .\alu_op__oe__ok$9 (\output_alu_op__oe__ok$43 ),
.alu_op__output_carry(output_alu_op__output_carry),
- .\alu_op__output_carry$15 (\output_alu_op__output_carry$48 ),
+ .\alu_op__output_carry$15 (\output_alu_op__output_carry$49 ),
.alu_op__rc__ok(output_alu_op__rc__ok),
- .\alu_op__rc__ok$7 (\output_alu_op__rc__ok$40 ),
+ .\alu_op__rc__ok$7 (\output_alu_op__rc__ok$41 ),
.alu_op__rc__rc(output_alu_op__rc__rc),
- .\alu_op__rc__rc$6 (\output_alu_op__rc__rc$39 ),
+ .\alu_op__rc__rc$6 (\output_alu_op__rc__rc$40 ),
+ .alu_op__sv_ldstmode(output_alu_op__sv_ldstmode),
+ .\alu_op__sv_ldstmode$23 (\output_alu_op__sv_ldstmode$57 ),
.alu_op__sv_pred_dz(output_alu_op__sv_pred_dz),
- .\alu_op__sv_pred_dz$21 (\output_alu_op__sv_pred_dz$54 ),
+ .\alu_op__sv_pred_dz$21 (\output_alu_op__sv_pred_dz$55 ),
.alu_op__sv_pred_sz(output_alu_op__sv_pred_sz),
- .\alu_op__sv_pred_sz$20 (\output_alu_op__sv_pred_sz$53 ),
+ .\alu_op__sv_pred_sz$20 (\output_alu_op__sv_pred_sz$54 ),
.alu_op__sv_saturate(output_alu_op__sv_saturate),
- .\alu_op__sv_saturate$22 (\output_alu_op__sv_saturate$55 ),
+ .\alu_op__sv_saturate$22 (\output_alu_op__sv_saturate$56 ),
.alu_op__write_cr0(output_alu_op__write_cr0),
- .\alu_op__write_cr0$13 (\output_alu_op__write_cr0$46 ),
+ .\alu_op__write_cr0$13 (\output_alu_op__write_cr0$47 ),
.alu_op__zero_a(output_alu_op__zero_a),
- .\alu_op__zero_a$11 (\output_alu_op__zero_a$44 ),
+ .\alu_op__zero_a$11 (\output_alu_op__zero_a$45 ),
.cr_a(output_cr_a),
- .\cr_a$26 (\output_cr_a$59 ),
+ .\cr_a$27 (\output_cr_a$61 ),
.cr_a_ok(output_cr_a_ok),
.muxid(output_muxid),
- .\muxid$1 (\output_muxid$34 ),
+ .\muxid$1 (\output_muxid$35 ),
.o(output_o),
- .\o$24 (\output_o$57 ),
+ .\o$25 (\output_o$59 ),
.o_ok(output_o_ok),
- .\o_ok$25 (\output_o_ok$58 ),
+ .\o_ok$26 (\output_o_ok$60 ),
.xer_ca(output_xer_ca),
- .\xer_ca$27 (\output_xer_ca$60 ),
+ .\xer_ca$28 (\output_xer_ca$62 ),
.xer_ca_ok(output_xer_ca_ok),
.xer_ov(output_xer_ov),
- .\xer_ov$28 (\output_xer_ov$61 ),
+ .\xer_ov$29 (\output_xer_ov$63 ),
.xer_ov_ok(output_xer_ov_ok),
.xer_so(output_xer_so),
- .\xer_so$29 (\output_xer_so$62 ),
+ .\xer_so$30 (\output_xer_so$64 ),
.xer_so_ok(output_xer_so_ok)
);
\p$3 p (
);
always @* begin
if (\initial ) begin end
- \xer_so$32$next = \xer_so$32 ;
- \xer_so_ok$33$next = \xer_so_ok$33 ;
+ \xer_ca$29$next = \xer_ca$29 ;
+ \xer_ca_ok$30$next = \xer_ca_ok$30 ;
+ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
+ casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
+ /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
+ 2'b?1:
+ { \xer_ca_ok$30$next , \xer_ca$29$next } = { \xer_ca_ok$101 , \xer_ca$100 };
+ /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
+ 2'b1?:
+ { \xer_ca_ok$30$next , \xer_ca$29$next } = { \xer_ca_ok$101 , \xer_ca$100 };
+ endcase
+ (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
+ casez (coresync_rst)
+ 1'h1:
+ \xer_ca_ok$30$next = 1'h0;
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ \xer_ov$31$next = \xer_ov$31 ;
+ \xer_ov_ok$32$next = \xer_ov_ok$32 ;
+ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
+ casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
+ /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
+ 2'b?1:
+ { \xer_ov_ok$32$next , \xer_ov$31$next } = { \xer_ov_ok$103 , \xer_ov$102 };
+ /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
+ 2'b1?:
+ { \xer_ov_ok$32$next , \xer_ov$31$next } = { \xer_ov_ok$103 , \xer_ov$102 };
+ endcase
+ (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
+ casez (coresync_rst)
+ 1'h1:
+ \xer_ov_ok$32$next = 1'h0;
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ \xer_so$33$next = \xer_so$33 ;
+ \xer_so_ok$34$next = \xer_so_ok$34 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \xer_so_ok$33$next , \xer_so$32$next } = { \xer_so_ok$102 , \xer_so$101 };
+ { \xer_so_ok$34$next , \xer_so$33$next } = { \xer_so_ok$105 , \xer_so$104 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \xer_so_ok$33$next , \xer_so$32$next } = { \xer_so_ok$102 , \xer_so$101 };
+ { \xer_so_ok$34$next , \xer_so$33$next } = { \xer_so_ok$105 , \xer_so$104 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
1'h1:
- \xer_so_ok$33$next = 1'h0;
+ \xer_so_ok$34$next = 1'h0;
endcase
end
always @* begin
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \muxid$1$next = \muxid$70 ;
+ \muxid$1$next = \muxid$72 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \muxid$1$next = \muxid$70 ;
+ \muxid$1$next = \muxid$72 ;
endcase
end
always @* begin
\alu_op__sv_pred_sz$20$next = \alu_op__sv_pred_sz$20 ;
\alu_op__sv_pred_dz$21$next = \alu_op__sv_pred_dz$21 ;
\alu_op__sv_saturate$22$next = \alu_op__sv_saturate$22 ;
- \alu_op__SV_Ptype$23$next = \alu_op__SV_Ptype$23 ;
+ \alu_op__sv_ldstmode$23$next = \alu_op__sv_ldstmode$23 ;
+ \alu_op__SV_Ptype$24$next = \alu_op__SV_Ptype$24 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \alu_op__SV_Ptype$23$next , \alu_op__sv_saturate$22$next , \alu_op__sv_pred_dz$21$next , \alu_op__sv_pred_sz$20$next , \alu_op__insn$19$next , \alu_op__data_len$18$next , \alu_op__is_signed$17$next , \alu_op__is_32bit$16$next , \alu_op__output_carry$15$next , \alu_op__input_carry$14$next , \alu_op__write_cr0$13$next , \alu_op__invert_out$12$next , \alu_op__zero_a$11$next , \alu_op__invert_in$10$next , \alu_op__oe__ok$9$next , \alu_op__oe__oe$8$next , \alu_op__rc__ok$7$next , \alu_op__rc__rc$6$next , \alu_op__imm_data__ok$5$next , \alu_op__imm_data__data$4$next , \alu_op__fn_unit$3$next , \alu_op__insn_type$2$next } = { \alu_op__SV_Ptype$92 , \alu_op__sv_saturate$91 , \alu_op__sv_pred_dz$90 , \alu_op__sv_pred_sz$89 , \alu_op__insn$88 , \alu_op__data_len$87 , \alu_op__is_signed$86 , \alu_op__is_32bit$85 , \alu_op__output_carry$84 , \alu_op__input_carry$83 , \alu_op__write_cr0$82 , \alu_op__invert_out$81 , \alu_op__zero_a$80 , \alu_op__invert_in$79 , \alu_op__oe__ok$78 , \alu_op__oe__oe$77 , \alu_op__rc__ok$76 , \alu_op__rc__rc$75 , \alu_op__imm_data__ok$74 , \alu_op__imm_data__data$73 , \alu_op__fn_unit$72 , \alu_op__insn_type$71 };
+ { \alu_op__SV_Ptype$24$next , \alu_op__sv_ldstmode$23$next , \alu_op__sv_saturate$22$next , \alu_op__sv_pred_dz$21$next , \alu_op__sv_pred_sz$20$next , \alu_op__insn$19$next , \alu_op__data_len$18$next , \alu_op__is_signed$17$next , \alu_op__is_32bit$16$next , \alu_op__output_carry$15$next , \alu_op__input_carry$14$next , \alu_op__write_cr0$13$next , \alu_op__invert_out$12$next , \alu_op__zero_a$11$next , \alu_op__invert_in$10$next , \alu_op__oe__ok$9$next , \alu_op__oe__oe$8$next , \alu_op__rc__ok$7$next , \alu_op__rc__rc$6$next , \alu_op__imm_data__ok$5$next , \alu_op__imm_data__data$4$next , \alu_op__fn_unit$3$next , \alu_op__insn_type$2$next } = { \alu_op__SV_Ptype$95 , \alu_op__sv_ldstmode$94 , \alu_op__sv_saturate$93 , \alu_op__sv_pred_dz$92 , \alu_op__sv_pred_sz$91 , \alu_op__insn$90 , \alu_op__data_len$89 , \alu_op__is_signed$88 , \alu_op__is_32bit$87 , \alu_op__output_carry$86 , \alu_op__input_carry$85 , \alu_op__write_cr0$84 , \alu_op__invert_out$83 , \alu_op__zero_a$82 , \alu_op__invert_in$81 , \alu_op__oe__ok$80 , \alu_op__oe__oe$79 , \alu_op__rc__ok$78 , \alu_op__rc__rc$77 , \alu_op__imm_data__ok$76 , \alu_op__imm_data__data$75 , \alu_op__fn_unit$74 , \alu_op__insn_type$73 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \alu_op__SV_Ptype$23$next , \alu_op__sv_saturate$22$next , \alu_op__sv_pred_dz$21$next , \alu_op__sv_pred_sz$20$next , \alu_op__insn$19$next , \alu_op__data_len$18$next , \alu_op__is_signed$17$next , \alu_op__is_32bit$16$next , \alu_op__output_carry$15$next , \alu_op__input_carry$14$next , \alu_op__write_cr0$13$next , \alu_op__invert_out$12$next , \alu_op__zero_a$11$next , \alu_op__invert_in$10$next , \alu_op__oe__ok$9$next , \alu_op__oe__oe$8$next , \alu_op__rc__ok$7$next , \alu_op__rc__rc$6$next , \alu_op__imm_data__ok$5$next , \alu_op__imm_data__data$4$next , \alu_op__fn_unit$3$next , \alu_op__insn_type$2$next } = { \alu_op__SV_Ptype$92 , \alu_op__sv_saturate$91 , \alu_op__sv_pred_dz$90 , \alu_op__sv_pred_sz$89 , \alu_op__insn$88 , \alu_op__data_len$87 , \alu_op__is_signed$86 , \alu_op__is_32bit$85 , \alu_op__output_carry$84 , \alu_op__input_carry$83 , \alu_op__write_cr0$82 , \alu_op__invert_out$81 , \alu_op__zero_a$80 , \alu_op__invert_in$79 , \alu_op__oe__ok$78 , \alu_op__oe__oe$77 , \alu_op__rc__ok$76 , \alu_op__rc__rc$75 , \alu_op__imm_data__ok$74 , \alu_op__imm_data__data$73 , \alu_op__fn_unit$72 , \alu_op__insn_type$71 };
+ { \alu_op__SV_Ptype$24$next , \alu_op__sv_ldstmode$23$next , \alu_op__sv_saturate$22$next , \alu_op__sv_pred_dz$21$next , \alu_op__sv_pred_sz$20$next , \alu_op__insn$19$next , \alu_op__data_len$18$next , \alu_op__is_signed$17$next , \alu_op__is_32bit$16$next , \alu_op__output_carry$15$next , \alu_op__input_carry$14$next , \alu_op__write_cr0$13$next , \alu_op__invert_out$12$next , \alu_op__zero_a$11$next , \alu_op__invert_in$10$next , \alu_op__oe__ok$9$next , \alu_op__oe__oe$8$next , \alu_op__rc__ok$7$next , \alu_op__rc__rc$6$next , \alu_op__imm_data__ok$5$next , \alu_op__imm_data__data$4$next , \alu_op__fn_unit$3$next , \alu_op__insn_type$2$next } = { \alu_op__SV_Ptype$95 , \alu_op__sv_ldstmode$94 , \alu_op__sv_saturate$93 , \alu_op__sv_pred_dz$92 , \alu_op__sv_pred_sz$91 , \alu_op__insn$90 , \alu_op__data_len$89 , \alu_op__is_signed$88 , \alu_op__is_32bit$87 , \alu_op__output_carry$86 , \alu_op__input_carry$85 , \alu_op__write_cr0$84 , \alu_op__invert_out$83 , \alu_op__zero_a$82 , \alu_op__invert_in$81 , \alu_op__oe__ok$80 , \alu_op__oe__oe$79 , \alu_op__rc__ok$78 , \alu_op__rc__rc$77 , \alu_op__imm_data__ok$76 , \alu_op__imm_data__data$75 , \alu_op__fn_unit$74 , \alu_op__insn_type$73 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
end
always @* begin
if (\initial ) begin end
- \o$24$next = \o$24 ;
- \o_ok$25$next = \o_ok$25 ;
- (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
- casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
- /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
- 2'b?1:
- { \o_ok$25$next , \o$24$next } = { \o_ok$94 , \o$93 };
- /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
- 2'b1?:
- { \o_ok$25$next , \o$24$next } = { \o_ok$94 , \o$93 };
- endcase
- (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (coresync_rst)
- 1'h1:
- \o_ok$25$next = 1'h0;
- endcase
- end
- always @* begin
- if (\initial ) begin end
- \cr_a$26$next = \cr_a$26 ;
- \cr_a_ok$27$next = \cr_a_ok$27 ;
- (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
- casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
- /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
- 2'b?1:
- { \cr_a_ok$27$next , \cr_a$26$next } = { \cr_a_ok$96 , \cr_a$95 };
- /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
- 2'b1?:
- { \cr_a_ok$27$next , \cr_a$26$next } = { \cr_a_ok$96 , \cr_a$95 };
- endcase
- (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (coresync_rst)
- 1'h1:
- \cr_a_ok$27$next = 1'h0;
- endcase
- end
- always @* begin
- if (\initial ) begin end
- \xer_ca$28$next = \xer_ca$28 ;
- \xer_ca_ok$29$next = \xer_ca_ok$29 ;
+ \o$25$next = \o$25 ;
+ \o_ok$26$next = \o_ok$26 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \xer_ca_ok$29$next , \xer_ca$28$next } = { \xer_ca_ok$98 , \xer_ca$97 };
+ { \o_ok$26$next , \o$25$next } = { \o_ok$97 , \o$96 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \xer_ca_ok$29$next , \xer_ca$28$next } = { \xer_ca_ok$98 , \xer_ca$97 };
+ { \o_ok$26$next , \o$25$next } = { \o_ok$97 , \o$96 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
1'h1:
- \xer_ca_ok$29$next = 1'h0;
+ \o_ok$26$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
- \xer_ov$30$next = \xer_ov$30 ;
- \xer_ov_ok$31$next = \xer_ov_ok$31 ;
+ \cr_a$27$next = \cr_a$27 ;
+ \cr_a_ok$28$next = \cr_a_ok$28 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \xer_ov_ok$31$next , \xer_ov$30$next } = { \xer_ov_ok$100 , \xer_ov$99 };
+ { \cr_a_ok$28$next , \cr_a$27$next } = { \cr_a_ok$99 , \cr_a$98 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \xer_ov_ok$31$next , \xer_ov$30$next } = { \xer_ov_ok$100 , \xer_ov$99 };
+ { \cr_a_ok$28$next , \cr_a$27$next } = { \cr_a_ok$99 , \cr_a$98 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
1'h1:
- \xer_ov_ok$31$next = 1'h0;
+ \cr_a_ok$28$next = 1'h0;
endcase
end
assign p_ready_o = n_i_rdy_data;
assign n_valid_o = r_busy;
- assign { \xer_so_ok$102 , \xer_so$101 } = { output_xer_so_ok, \output_xer_so$62 };
- assign { \xer_ov_ok$100 , \xer_ov$99 } = { output_xer_ov_ok, \output_xer_ov$61 };
- assign { \xer_ca_ok$98 , \xer_ca$97 } = { output_xer_ca_ok, \output_xer_ca$60 };
- assign { \cr_a_ok$96 , \cr_a$95 } = { output_cr_a_ok, \output_cr_a$59 };
- assign { \o_ok$94 , \o$93 } = { \output_o_ok$58 , \output_o$57 };
- assign { \alu_op__SV_Ptype$92 , \alu_op__sv_saturate$91 , \alu_op__sv_pred_dz$90 , \alu_op__sv_pred_sz$89 , \alu_op__insn$88 , \alu_op__data_len$87 , \alu_op__is_signed$86 , \alu_op__is_32bit$85 , \alu_op__output_carry$84 , \alu_op__input_carry$83 , \alu_op__write_cr0$82 , \alu_op__invert_out$81 , \alu_op__zero_a$80 , \alu_op__invert_in$79 , \alu_op__oe__ok$78 , \alu_op__oe__oe$77 , \alu_op__rc__ok$76 , \alu_op__rc__rc$75 , \alu_op__imm_data__ok$74 , \alu_op__imm_data__data$73 , \alu_op__fn_unit$72 , \alu_op__insn_type$71 } = { \output_alu_op__SV_Ptype$56 , \output_alu_op__sv_saturate$55 , \output_alu_op__sv_pred_dz$54 , \output_alu_op__sv_pred_sz$53 , \output_alu_op__insn$52 , \output_alu_op__data_len$51 , \output_alu_op__is_signed$50 , \output_alu_op__is_32bit$49 , \output_alu_op__output_carry$48 , \output_alu_op__input_carry$47 , \output_alu_op__write_cr0$46 , \output_alu_op__invert_out$45 , \output_alu_op__zero_a$44 , \output_alu_op__invert_in$43 , \output_alu_op__oe__ok$42 , \output_alu_op__oe__oe$41 , \output_alu_op__rc__ok$40 , \output_alu_op__rc__rc$39 , \output_alu_op__imm_data__ok$38 , \output_alu_op__imm_data__data$37 , \output_alu_op__fn_unit$36 , \output_alu_op__insn_type$35 };
- assign \muxid$70 = \output_muxid$34 ;
- assign p_valid_i_p_ready_o = \$68 ;
+ assign { \xer_so_ok$105 , \xer_so$104 } = { output_xer_so_ok, \output_xer_so$64 };
+ assign { \xer_ov_ok$103 , \xer_ov$102 } = { output_xer_ov_ok, \output_xer_ov$63 };
+ assign { \xer_ca_ok$101 , \xer_ca$100 } = { output_xer_ca_ok, \output_xer_ca$62 };
+ assign { \cr_a_ok$99 , \cr_a$98 } = { output_cr_a_ok, \output_cr_a$61 };
+ assign { \o_ok$97 , \o$96 } = { \output_o_ok$60 , \output_o$59 };
+ assign { \alu_op__SV_Ptype$95 , \alu_op__sv_ldstmode$94 , \alu_op__sv_saturate$93 , \alu_op__sv_pred_dz$92 , \alu_op__sv_pred_sz$91 , \alu_op__insn$90 , \alu_op__data_len$89 , \alu_op__is_signed$88 , \alu_op__is_32bit$87 , \alu_op__output_carry$86 , \alu_op__input_carry$85 , \alu_op__write_cr0$84 , \alu_op__invert_out$83 , \alu_op__zero_a$82 , \alu_op__invert_in$81 , \alu_op__oe__ok$80 , \alu_op__oe__oe$79 , \alu_op__rc__ok$78 , \alu_op__rc__rc$77 , \alu_op__imm_data__ok$76 , \alu_op__imm_data__data$75 , \alu_op__fn_unit$74 , \alu_op__insn_type$73 } = { \output_alu_op__SV_Ptype$58 , \output_alu_op__sv_ldstmode$57 , \output_alu_op__sv_saturate$56 , \output_alu_op__sv_pred_dz$55 , \output_alu_op__sv_pred_sz$54 , \output_alu_op__insn$53 , \output_alu_op__data_len$52 , \output_alu_op__is_signed$51 , \output_alu_op__is_32bit$50 , \output_alu_op__output_carry$49 , \output_alu_op__input_carry$48 , \output_alu_op__write_cr0$47 , \output_alu_op__invert_out$46 , \output_alu_op__zero_a$45 , \output_alu_op__invert_in$44 , \output_alu_op__oe__ok$43 , \output_alu_op__oe__oe$42 , \output_alu_op__rc__ok$41 , \output_alu_op__rc__rc$40 , \output_alu_op__imm_data__ok$39 , \output_alu_op__imm_data__data$38 , \output_alu_op__fn_unit$37 , \output_alu_op__insn_type$36 };
+ assign \muxid$72 = \output_muxid$35 ;
+ assign p_valid_i_p_ready_o = \$70 ;
assign n_i_rdy_data = n_ready_i;
- assign \p_valid_i$67 = p_valid_i;
- assign { \xer_so_ok$66 , output_xer_so } = { xer_so_ok, xer_so };
- assign { \xer_ov_ok$65 , output_xer_ov } = { xer_ov_ok, xer_ov };
- assign { \xer_ca_ok$64 , output_xer_ca } = { xer_ca_ok, xer_ca };
- assign { \cr_a_ok$63 , output_cr_a } = { cr_a_ok, cr_a };
+ assign \p_valid_i$69 = p_valid_i;
+ assign { \xer_so_ok$68 , output_xer_so } = { xer_so_ok, xer_so };
+ assign { \xer_ov_ok$67 , output_xer_ov } = { xer_ov_ok, xer_ov };
+ assign { \xer_ca_ok$66 , output_xer_ca } = { xer_ca_ok, xer_ca };
+ assign { \cr_a_ok$65 , output_cr_a } = { cr_a_ok, cr_a };
assign { output_o_ok, output_o } = { o_ok, o };
- assign { output_alu_op__SV_Ptype, output_alu_op__sv_saturate, output_alu_op__sv_pred_dz, output_alu_op__sv_pred_sz, output_alu_op__insn, output_alu_op__data_len, output_alu_op__is_signed, output_alu_op__is_32bit, output_alu_op__output_carry, output_alu_op__input_carry, output_alu_op__write_cr0, output_alu_op__invert_out, output_alu_op__zero_a, output_alu_op__invert_in, output_alu_op__oe__ok, output_alu_op__oe__oe, output_alu_op__rc__ok, output_alu_op__rc__rc, output_alu_op__imm_data__ok, output_alu_op__imm_data__data, output_alu_op__fn_unit, output_alu_op__insn_type } = { alu_op__SV_Ptype, alu_op__sv_saturate, alu_op__sv_pred_dz, alu_op__sv_pred_sz, alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type };
+ assign { output_alu_op__SV_Ptype, output_alu_op__sv_ldstmode, output_alu_op__sv_saturate, output_alu_op__sv_pred_dz, output_alu_op__sv_pred_sz, output_alu_op__insn, output_alu_op__data_len, output_alu_op__is_signed, output_alu_op__is_32bit, output_alu_op__output_carry, output_alu_op__input_carry, output_alu_op__write_cr0, output_alu_op__invert_out, output_alu_op__zero_a, output_alu_op__invert_in, output_alu_op__oe__ok, output_alu_op__oe__oe, output_alu_op__rc__ok, output_alu_op__rc__rc, output_alu_op__imm_data__ok, output_alu_op__imm_data__data, output_alu_op__fn_unit, output_alu_op__insn_type } = { alu_op__SV_Ptype, alu_op__sv_ldstmode, alu_op__sv_saturate, alu_op__sv_pred_dz, alu_op__sv_pred_sz, alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type };
assign output_muxid = muxid;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2" *)
(* generator = "nMigen" *)
-module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, sr_op__sv_pred_sz, sr_op__sv_pred_dz, sr_op__sv_saturate, sr_op__SV_Ptype, o, o_ok, cr_a, cr_a_ok, xer_so, xer_so_ok, xer_ca, xer_ca_ok, n_valid_o, n_ready_i, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , \sr_op__sv_pred_sz$19 , \sr_op__sv_pred_dz$20 , \sr_op__sv_saturate$21 , \sr_op__SV_Ptype$22 , \o$23 , \o_ok$24 , \cr_a$25 , \cr_a_ok$26 , \xer_ca$27 , \xer_ca_ok$28 , coresync_clk);
+module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, sr_op__sv_pred_sz, sr_op__sv_pred_dz, sr_op__sv_saturate, sr_op__sv_ldstmode, sr_op__SV_Ptype, o, o_ok, cr_a, cr_a_ok, xer_so, xer_so_ok, xer_ca, xer_ca_ok, n_valid_o, n_ready_i, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , \sr_op__sv_pred_sz$19 , \sr_op__sv_pred_dz$20 , \sr_op__sv_saturate$21 , \sr_op__sv_ldstmode$22 , \sr_op__SV_Ptype$23 , \o$24 , \o_ok$25 , \cr_a$26 , \cr_a_ok$27 , \xer_ca$28 , \xer_ca_ok$29 , coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
- wire \$59 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ wire \$61 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input [3:0] cr_a;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [3:0] \cr_a$25 ;
- reg [3:0] \cr_a$25 = 4'h0;
+ output [3:0] \cr_a$26 ;
+ reg [3:0] \cr_a$26 = 4'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg [3:0] \cr_a$25$next ;
+ reg [3:0] \cr_a$26$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [3:0] \cr_a$85 ;
+ wire [3:0] \cr_a$88 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input cr_a_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \cr_a_ok$26 ;
- reg \cr_a_ok$26 = 1'h0;
+ output \cr_a_ok$27 ;
+ reg \cr_a_ok$27 = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg \cr_a_ok$26$next ;
+ reg \cr_a_ok$27$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \cr_a_ok$55 ;
+ wire \cr_a_ok$57 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \cr_a_ok$86 ;
+ wire \cr_a_ok$89 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
input [1:0] muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
reg [1:0] \muxid$1$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \muxid$61 ;
+ wire [1:0] \muxid$63 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
wire n_i_rdy_data;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input [63:0] o;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [63:0] \o$23 ;
- reg [63:0] \o$23 = 64'h0000000000000000;
+ output [63:0] \o$24 ;
+ reg [63:0] \o$24 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg [63:0] \o$23$next ;
+ reg [63:0] \o$24$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \o$83 ;
+ wire [63:0] \o$86 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input o_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \o_ok$24 ;
- reg \o_ok$24 = 1'h0;
+ output \o_ok$25 ;
+ reg \o_ok$25 = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg \o_ok$24$next ;
+ reg \o_ok$25$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \o_ok$84 ;
+ wire \o_ok$87 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [3:0] output_cr_a;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [3:0] \output_cr_a$53 ;
+ wire [3:0] \output_cr_a$55 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire output_cr_a_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] output_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \output_muxid$29 ;
+ wire [1:0] \output_muxid$30 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [63:0] output_o;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \output_o$51 ;
+ wire [63:0] \output_o$53 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire output_o_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \output_o_ok$52 ;
+ wire \output_o_ok$54 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \output_sr_op__SV_Ptype$50 ;
+ wire [1:0] \output_sr_op__SV_Ptype$52 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \output_sr_op__fn_unit$31 ;
+ wire [14:0] \output_sr_op__fn_unit$32 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] output_sr_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \output_sr_op__imm_data__data$32 ;
+ wire [63:0] \output_sr_op__imm_data__data$33 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_sr_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_sr_op__imm_data__ok$33 ;
+ wire \output_sr_op__imm_data__ok$34 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \output_sr_op__input_carry$40 ;
+ wire [1:0] \output_sr_op__input_carry$41 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_sr_op__input_cr;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_sr_op__input_cr$42 ;
+ wire \output_sr_op__input_cr$43 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] output_sr_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \output_sr_op__insn$46 ;
+ wire [31:0] \output_sr_op__insn$47 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \output_sr_op__insn_type$30 ;
+ wire [6:0] \output_sr_op__insn_type$31 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_sr_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_sr_op__invert_in$39 ;
+ wire \output_sr_op__invert_in$40 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_sr_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_sr_op__is_32bit$44 ;
+ wire \output_sr_op__is_32bit$45 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_sr_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_sr_op__is_signed$45 ;
+ wire \output_sr_op__is_signed$46 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_sr_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_sr_op__oe__oe$36 ;
+ wire \output_sr_op__oe__oe$37 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_sr_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_sr_op__oe__ok$37 ;
+ wire \output_sr_op__oe__ok$38 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_sr_op__output_carry;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_sr_op__output_carry$41 ;
+ wire \output_sr_op__output_carry$42 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_sr_op__output_cr;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_sr_op__output_cr$43 ;
+ wire \output_sr_op__output_cr$44 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_sr_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_sr_op__rc__ok$35 ;
+ wire \output_sr_op__rc__ok$36 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_sr_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_sr_op__rc__rc$34 ;
+ wire \output_sr_op__rc__rc$35 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] output_sr_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \output_sr_op__sv_ldstmode$51 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_sr_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_sr_op__sv_pred_dz$48 ;
+ wire \output_sr_op__sv_pred_dz$49 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_sr_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_sr_op__sv_pred_sz$47 ;
+ wire \output_sr_op__sv_pred_sz$48 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \output_sr_op__sv_saturate$49 ;
+ wire [1:0] \output_sr_op__sv_saturate$50 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_sr_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_sr_op__write_cr0$38 ;
+ wire \output_sr_op__write_cr0$39 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [1:0] output_xer_ca;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [1:0] \output_xer_ca$54 ;
+ wire [1:0] \output_xer_ca$56 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire output_xer_ca_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
input p_valid_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
- wire \p_valid_i$58 ;
+ wire \p_valid_i$60 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
wire p_valid_i_p_ready_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \sr_op__SV_Ptype$22 ;
- reg [1:0] \sr_op__SV_Ptype$22 = 2'h0;
+ output [1:0] \sr_op__SV_Ptype$23 ;
+ reg [1:0] \sr_op__SV_Ptype$23 = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [1:0] \sr_op__SV_Ptype$22$next ;
+ reg [1:0] \sr_op__SV_Ptype$23$next ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \sr_op__SV_Ptype$82 ;
+ wire [1:0] \sr_op__SV_Ptype$85 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \sr_op__fn_unit$63 ;
+ wire [14:0] \sr_op__fn_unit$65 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] sr_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [63:0] \sr_op__imm_data__data$4$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \sr_op__imm_data__data$64 ;
+ wire [63:0] \sr_op__imm_data__data$66 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \sr_op__imm_data__ok$5$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__imm_data__ok$65 ;
+ wire \sr_op__imm_data__ok$67 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \sr_op__input_carry$72 ;
+ wire [1:0] \sr_op__input_carry$74 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__input_cr;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \sr_op__input_cr$14$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__input_cr$74 ;
+ wire \sr_op__input_cr$76 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] sr_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [31:0] \sr_op__insn$18$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \sr_op__insn$78 ;
+ wire [31:0] \sr_op__insn$80 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \sr_op__insn_type$62 ;
+ wire [6:0] \sr_op__insn_type$64 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \sr_op__invert_in$11$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__invert_in$71 ;
+ wire \sr_op__invert_in$73 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \sr_op__is_32bit$16$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__is_32bit$76 ;
+ wire \sr_op__is_32bit$78 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \sr_op__is_signed$17$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__is_signed$77 ;
+ wire \sr_op__is_signed$79 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__oe__oe$68 ;
+ wire \sr_op__oe__oe$70 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \sr_op__oe__oe$8 ;
reg \sr_op__oe__oe$8 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__oe__ok$69 ;
+ wire \sr_op__oe__ok$71 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \sr_op__oe__ok$9 ;
reg \sr_op__oe__ok$9 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \sr_op__output_carry$13$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__output_carry$73 ;
+ wire \sr_op__output_carry$75 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__output_cr;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \sr_op__output_cr$15$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__output_cr$75 ;
+ wire \sr_op__output_cr$77 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__rc__ok$67 ;
+ wire \sr_op__rc__ok$69 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \sr_op__rc__ok$7 ;
reg \sr_op__rc__ok$7 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \sr_op__rc__rc$6$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__rc__rc$66 ;
+ wire \sr_op__rc__rc$68 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] sr_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \sr_op__sv_ldstmode$22 ;
+ reg [1:0] \sr_op__sv_ldstmode$22 = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \sr_op__sv_ldstmode$22$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \sr_op__sv_ldstmode$84 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \sr_op__sv_pred_dz$20$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__sv_pred_dz$80 ;
+ wire \sr_op__sv_pred_dz$82 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \sr_op__sv_pred_sz$19$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__sv_pred_sz$79 ;
+ wire \sr_op__sv_pred_sz$81 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \sr_op__sv_saturate$81 ;
+ wire [1:0] \sr_op__sv_saturate$83 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input sr_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \sr_op__write_cr0$10$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \sr_op__write_cr0$70 ;
+ wire \sr_op__write_cr0$72 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input [1:0] xer_ca;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [1:0] \xer_ca$27 ;
- reg [1:0] \xer_ca$27 = 2'h0;
+ output [1:0] \xer_ca$28 ;
+ reg [1:0] \xer_ca$28 = 2'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg [1:0] \xer_ca$27$next ;
+ reg [1:0] \xer_ca$28$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [1:0] \xer_ca$87 ;
+ wire [1:0] \xer_ca$90 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input xer_ca_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \xer_ca_ok$28 ;
- reg \xer_ca_ok$28 = 1'h0;
+ output \xer_ca_ok$29 ;
+ reg \xer_ca_ok$29 = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg \xer_ca_ok$28$next ;
+ reg \xer_ca_ok$29$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_ca_ok$57 ;
+ wire \xer_ca_ok$59 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_ca_ok$88 ;
+ wire \xer_ca_ok$91 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input xer_so_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_so_ok$56 ;
- assign \$59 = \p_valid_i$58 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
+ wire \xer_so_ok$58 ;
+ assign \$61 = \p_valid_i$60 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
always @(posedge coresync_clk)
- \xer_ca$27 <= \xer_ca$27$next ;
+ \xer_ca$28 <= \xer_ca$28$next ;
always @(posedge coresync_clk)
- \xer_ca_ok$28 <= \xer_ca_ok$28$next ;
+ \xer_ca_ok$29 <= \xer_ca_ok$29$next ;
always @(posedge coresync_clk)
- \cr_a$25 <= \cr_a$25$next ;
+ \cr_a$26 <= \cr_a$26$next ;
always @(posedge coresync_clk)
- \cr_a_ok$26 <= \cr_a_ok$26$next ;
+ \cr_a_ok$27 <= \cr_a_ok$27$next ;
always @(posedge coresync_clk)
- \o$23 <= \o$23$next ;
+ \o$24 <= \o$24$next ;
always @(posedge coresync_clk)
- \o_ok$24 <= \o_ok$24$next ;
+ \o_ok$25 <= \o_ok$25$next ;
always @(posedge coresync_clk)
\sr_op__insn_type$2 <= \sr_op__insn_type$2$next ;
always @(posedge coresync_clk)
always @(posedge coresync_clk)
\sr_op__sv_saturate$21 <= \sr_op__sv_saturate$21$next ;
always @(posedge coresync_clk)
- \sr_op__SV_Ptype$22 <= \sr_op__SV_Ptype$22$next ;
+ \sr_op__sv_ldstmode$22 <= \sr_op__sv_ldstmode$22$next ;
+ always @(posedge coresync_clk)
+ \sr_op__SV_Ptype$23 <= \sr_op__SV_Ptype$23$next ;
always @(posedge coresync_clk)
\muxid$1 <= \muxid$1$next ;
always @(posedge coresync_clk)
);
\output$118 \output (
.cr_a(output_cr_a),
- .\cr_a$25 (\output_cr_a$53 ),
+ .\cr_a$26 (\output_cr_a$55 ),
.cr_a_ok(output_cr_a_ok),
.muxid(output_muxid),
- .\muxid$1 (\output_muxid$29 ),
+ .\muxid$1 (\output_muxid$30 ),
.o(output_o),
- .\o$23 (\output_o$51 ),
+ .\o$24 (\output_o$53 ),
.o_ok(output_o_ok),
- .\o_ok$24 (\output_o_ok$52 ),
+ .\o_ok$25 (\output_o_ok$54 ),
.sr_op__SV_Ptype(output_sr_op__SV_Ptype),
- .\sr_op__SV_Ptype$22 (\output_sr_op__SV_Ptype$50 ),
+ .\sr_op__SV_Ptype$23 (\output_sr_op__SV_Ptype$52 ),
.sr_op__fn_unit(output_sr_op__fn_unit),
- .\sr_op__fn_unit$3 (\output_sr_op__fn_unit$31 ),
+ .\sr_op__fn_unit$3 (\output_sr_op__fn_unit$32 ),
.sr_op__imm_data__data(output_sr_op__imm_data__data),
- .\sr_op__imm_data__data$4 (\output_sr_op__imm_data__data$32 ),
+ .\sr_op__imm_data__data$4 (\output_sr_op__imm_data__data$33 ),
.sr_op__imm_data__ok(output_sr_op__imm_data__ok),
- .\sr_op__imm_data__ok$5 (\output_sr_op__imm_data__ok$33 ),
+ .\sr_op__imm_data__ok$5 (\output_sr_op__imm_data__ok$34 ),
.sr_op__input_carry(output_sr_op__input_carry),
- .\sr_op__input_carry$12 (\output_sr_op__input_carry$40 ),
+ .\sr_op__input_carry$12 (\output_sr_op__input_carry$41 ),
.sr_op__input_cr(output_sr_op__input_cr),
- .\sr_op__input_cr$14 (\output_sr_op__input_cr$42 ),
+ .\sr_op__input_cr$14 (\output_sr_op__input_cr$43 ),
.sr_op__insn(output_sr_op__insn),
- .\sr_op__insn$18 (\output_sr_op__insn$46 ),
+ .\sr_op__insn$18 (\output_sr_op__insn$47 ),
.sr_op__insn_type(output_sr_op__insn_type),
- .\sr_op__insn_type$2 (\output_sr_op__insn_type$30 ),
+ .\sr_op__insn_type$2 (\output_sr_op__insn_type$31 ),
.sr_op__invert_in(output_sr_op__invert_in),
- .\sr_op__invert_in$11 (\output_sr_op__invert_in$39 ),
+ .\sr_op__invert_in$11 (\output_sr_op__invert_in$40 ),
.sr_op__is_32bit(output_sr_op__is_32bit),
- .\sr_op__is_32bit$16 (\output_sr_op__is_32bit$44 ),
+ .\sr_op__is_32bit$16 (\output_sr_op__is_32bit$45 ),
.sr_op__is_signed(output_sr_op__is_signed),
- .\sr_op__is_signed$17 (\output_sr_op__is_signed$45 ),
+ .\sr_op__is_signed$17 (\output_sr_op__is_signed$46 ),
.sr_op__oe__oe(output_sr_op__oe__oe),
- .\sr_op__oe__oe$8 (\output_sr_op__oe__oe$36 ),
+ .\sr_op__oe__oe$8 (\output_sr_op__oe__oe$37 ),
.sr_op__oe__ok(output_sr_op__oe__ok),
- .\sr_op__oe__ok$9 (\output_sr_op__oe__ok$37 ),
+ .\sr_op__oe__ok$9 (\output_sr_op__oe__ok$38 ),
.sr_op__output_carry(output_sr_op__output_carry),
- .\sr_op__output_carry$13 (\output_sr_op__output_carry$41 ),
+ .\sr_op__output_carry$13 (\output_sr_op__output_carry$42 ),
.sr_op__output_cr(output_sr_op__output_cr),
- .\sr_op__output_cr$15 (\output_sr_op__output_cr$43 ),
+ .\sr_op__output_cr$15 (\output_sr_op__output_cr$44 ),
.sr_op__rc__ok(output_sr_op__rc__ok),
- .\sr_op__rc__ok$7 (\output_sr_op__rc__ok$35 ),
+ .\sr_op__rc__ok$7 (\output_sr_op__rc__ok$36 ),
.sr_op__rc__rc(output_sr_op__rc__rc),
- .\sr_op__rc__rc$6 (\output_sr_op__rc__rc$34 ),
+ .\sr_op__rc__rc$6 (\output_sr_op__rc__rc$35 ),
+ .sr_op__sv_ldstmode(output_sr_op__sv_ldstmode),
+ .\sr_op__sv_ldstmode$22 (\output_sr_op__sv_ldstmode$51 ),
.sr_op__sv_pred_dz(output_sr_op__sv_pred_dz),
- .\sr_op__sv_pred_dz$20 (\output_sr_op__sv_pred_dz$48 ),
+ .\sr_op__sv_pred_dz$20 (\output_sr_op__sv_pred_dz$49 ),
.sr_op__sv_pred_sz(output_sr_op__sv_pred_sz),
- .\sr_op__sv_pred_sz$19 (\output_sr_op__sv_pred_sz$47 ),
+ .\sr_op__sv_pred_sz$19 (\output_sr_op__sv_pred_sz$48 ),
.sr_op__sv_saturate(output_sr_op__sv_saturate),
- .\sr_op__sv_saturate$21 (\output_sr_op__sv_saturate$49 ),
+ .\sr_op__sv_saturate$21 (\output_sr_op__sv_saturate$50 ),
.sr_op__write_cr0(output_sr_op__write_cr0),
- .\sr_op__write_cr0$10 (\output_sr_op__write_cr0$38 ),
+ .\sr_op__write_cr0$10 (\output_sr_op__write_cr0$39 ),
.xer_ca(output_xer_ca),
- .\xer_ca$26 (\output_xer_ca$54 ),
+ .\xer_ca$27 (\output_xer_ca$56 ),
.xer_ca_ok(output_xer_ca_ok),
.xer_so(output_xer_so)
);
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \muxid$1$next = \muxid$61 ;
+ \muxid$1$next = \muxid$63 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \muxid$1$next = \muxid$61 ;
+ \muxid$1$next = \muxid$63 ;
endcase
end
always @* begin
\sr_op__sv_pred_sz$19$next = \sr_op__sv_pred_sz$19 ;
\sr_op__sv_pred_dz$20$next = \sr_op__sv_pred_dz$20 ;
\sr_op__sv_saturate$21$next = \sr_op__sv_saturate$21 ;
- \sr_op__SV_Ptype$22$next = \sr_op__SV_Ptype$22 ;
+ \sr_op__sv_ldstmode$22$next = \sr_op__sv_ldstmode$22 ;
+ \sr_op__SV_Ptype$23$next = \sr_op__SV_Ptype$23 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \sr_op__SV_Ptype$22$next , \sr_op__sv_saturate$21$next , \sr_op__sv_pred_dz$20$next , \sr_op__sv_pred_sz$19$next , \sr_op__insn$18$next , \sr_op__is_signed$17$next , \sr_op__is_32bit$16$next , \sr_op__output_cr$15$next , \sr_op__input_cr$14$next , \sr_op__output_carry$13$next , \sr_op__input_carry$12$next , \sr_op__invert_in$11$next , \sr_op__write_cr0$10$next , \sr_op__oe__ok$9$next , \sr_op__oe__oe$8$next , \sr_op__rc__ok$7$next , \sr_op__rc__rc$6$next , \sr_op__imm_data__ok$5$next , \sr_op__imm_data__data$4$next , \sr_op__fn_unit$3$next , \sr_op__insn_type$2$next } = { \sr_op__SV_Ptype$82 , \sr_op__sv_saturate$81 , \sr_op__sv_pred_dz$80 , \sr_op__sv_pred_sz$79 , \sr_op__insn$78 , \sr_op__is_signed$77 , \sr_op__is_32bit$76 , \sr_op__output_cr$75 , \sr_op__input_cr$74 , \sr_op__output_carry$73 , \sr_op__input_carry$72 , \sr_op__invert_in$71 , \sr_op__write_cr0$70 , \sr_op__oe__ok$69 , \sr_op__oe__oe$68 , \sr_op__rc__ok$67 , \sr_op__rc__rc$66 , \sr_op__imm_data__ok$65 , \sr_op__imm_data__data$64 , \sr_op__fn_unit$63 , \sr_op__insn_type$62 };
+ { \sr_op__SV_Ptype$23$next , \sr_op__sv_ldstmode$22$next , \sr_op__sv_saturate$21$next , \sr_op__sv_pred_dz$20$next , \sr_op__sv_pred_sz$19$next , \sr_op__insn$18$next , \sr_op__is_signed$17$next , \sr_op__is_32bit$16$next , \sr_op__output_cr$15$next , \sr_op__input_cr$14$next , \sr_op__output_carry$13$next , \sr_op__input_carry$12$next , \sr_op__invert_in$11$next , \sr_op__write_cr0$10$next , \sr_op__oe__ok$9$next , \sr_op__oe__oe$8$next , \sr_op__rc__ok$7$next , \sr_op__rc__rc$6$next , \sr_op__imm_data__ok$5$next , \sr_op__imm_data__data$4$next , \sr_op__fn_unit$3$next , \sr_op__insn_type$2$next } = { \sr_op__SV_Ptype$85 , \sr_op__sv_ldstmode$84 , \sr_op__sv_saturate$83 , \sr_op__sv_pred_dz$82 , \sr_op__sv_pred_sz$81 , \sr_op__insn$80 , \sr_op__is_signed$79 , \sr_op__is_32bit$78 , \sr_op__output_cr$77 , \sr_op__input_cr$76 , \sr_op__output_carry$75 , \sr_op__input_carry$74 , \sr_op__invert_in$73 , \sr_op__write_cr0$72 , \sr_op__oe__ok$71 , \sr_op__oe__oe$70 , \sr_op__rc__ok$69 , \sr_op__rc__rc$68 , \sr_op__imm_data__ok$67 , \sr_op__imm_data__data$66 , \sr_op__fn_unit$65 , \sr_op__insn_type$64 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \sr_op__SV_Ptype$22$next , \sr_op__sv_saturate$21$next , \sr_op__sv_pred_dz$20$next , \sr_op__sv_pred_sz$19$next , \sr_op__insn$18$next , \sr_op__is_signed$17$next , \sr_op__is_32bit$16$next , \sr_op__output_cr$15$next , \sr_op__input_cr$14$next , \sr_op__output_carry$13$next , \sr_op__input_carry$12$next , \sr_op__invert_in$11$next , \sr_op__write_cr0$10$next , \sr_op__oe__ok$9$next , \sr_op__oe__oe$8$next , \sr_op__rc__ok$7$next , \sr_op__rc__rc$6$next , \sr_op__imm_data__ok$5$next , \sr_op__imm_data__data$4$next , \sr_op__fn_unit$3$next , \sr_op__insn_type$2$next } = { \sr_op__SV_Ptype$82 , \sr_op__sv_saturate$81 , \sr_op__sv_pred_dz$80 , \sr_op__sv_pred_sz$79 , \sr_op__insn$78 , \sr_op__is_signed$77 , \sr_op__is_32bit$76 , \sr_op__output_cr$75 , \sr_op__input_cr$74 , \sr_op__output_carry$73 , \sr_op__input_carry$72 , \sr_op__invert_in$71 , \sr_op__write_cr0$70 , \sr_op__oe__ok$69 , \sr_op__oe__oe$68 , \sr_op__rc__ok$67 , \sr_op__rc__rc$66 , \sr_op__imm_data__ok$65 , \sr_op__imm_data__data$64 , \sr_op__fn_unit$63 , \sr_op__insn_type$62 };
+ { \sr_op__SV_Ptype$23$next , \sr_op__sv_ldstmode$22$next , \sr_op__sv_saturate$21$next , \sr_op__sv_pred_dz$20$next , \sr_op__sv_pred_sz$19$next , \sr_op__insn$18$next , \sr_op__is_signed$17$next , \sr_op__is_32bit$16$next , \sr_op__output_cr$15$next , \sr_op__input_cr$14$next , \sr_op__output_carry$13$next , \sr_op__input_carry$12$next , \sr_op__invert_in$11$next , \sr_op__write_cr0$10$next , \sr_op__oe__ok$9$next , \sr_op__oe__oe$8$next , \sr_op__rc__ok$7$next , \sr_op__rc__rc$6$next , \sr_op__imm_data__ok$5$next , \sr_op__imm_data__data$4$next , \sr_op__fn_unit$3$next , \sr_op__insn_type$2$next } = { \sr_op__SV_Ptype$85 , \sr_op__sv_ldstmode$84 , \sr_op__sv_saturate$83 , \sr_op__sv_pred_dz$82 , \sr_op__sv_pred_sz$81 , \sr_op__insn$80 , \sr_op__is_signed$79 , \sr_op__is_32bit$78 , \sr_op__output_cr$77 , \sr_op__input_cr$76 , \sr_op__output_carry$75 , \sr_op__input_carry$74 , \sr_op__invert_in$73 , \sr_op__write_cr0$72 , \sr_op__oe__ok$71 , \sr_op__oe__oe$70 , \sr_op__rc__ok$69 , \sr_op__rc__rc$68 , \sr_op__imm_data__ok$67 , \sr_op__imm_data__data$66 , \sr_op__fn_unit$65 , \sr_op__insn_type$64 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
end
always @* begin
if (\initial ) begin end
- \o$23$next = \o$23 ;
- \o_ok$24$next = \o_ok$24 ;
+ \o$24$next = \o$24 ;
+ \o_ok$25$next = \o_ok$25 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \o_ok$24$next , \o$23$next } = { \o_ok$84 , \o$83 };
+ { \o_ok$25$next , \o$24$next } = { \o_ok$87 , \o$86 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \o_ok$24$next , \o$23$next } = { \o_ok$84 , \o$83 };
+ { \o_ok$25$next , \o$24$next } = { \o_ok$87 , \o$86 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
1'h1:
- \o_ok$24$next = 1'h0;
+ \o_ok$25$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
- \cr_a$25$next = \cr_a$25 ;
- \cr_a_ok$26$next = \cr_a_ok$26 ;
+ \cr_a$26$next = \cr_a$26 ;
+ \cr_a_ok$27$next = \cr_a_ok$27 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \cr_a_ok$26$next , \cr_a$25$next } = { \cr_a_ok$86 , \cr_a$85 };
+ { \cr_a_ok$27$next , \cr_a$26$next } = { \cr_a_ok$89 , \cr_a$88 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \cr_a_ok$26$next , \cr_a$25$next } = { \cr_a_ok$86 , \cr_a$85 };
+ { \cr_a_ok$27$next , \cr_a$26$next } = { \cr_a_ok$89 , \cr_a$88 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
1'h1:
- \cr_a_ok$26$next = 1'h0;
+ \cr_a_ok$27$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
- \xer_ca$27$next = \xer_ca$27 ;
- \xer_ca_ok$28$next = \xer_ca_ok$28 ;
+ \xer_ca$28$next = \xer_ca$28 ;
+ \xer_ca_ok$29$next = \xer_ca_ok$29 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \xer_ca_ok$28$next , \xer_ca$27$next } = { \xer_ca_ok$88 , \xer_ca$87 };
+ { \xer_ca_ok$29$next , \xer_ca$28$next } = { \xer_ca_ok$91 , \xer_ca$90 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \xer_ca_ok$28$next , \xer_ca$27$next } = { \xer_ca_ok$88 , \xer_ca$87 };
+ { \xer_ca_ok$29$next , \xer_ca$28$next } = { \xer_ca_ok$91 , \xer_ca$90 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
1'h1:
- \xer_ca_ok$28$next = 1'h0;
+ \xer_ca_ok$29$next = 1'h0;
endcase
end
assign p_ready_o = n_i_rdy_data;
assign n_valid_o = r_busy;
- assign { \xer_ca_ok$88 , \xer_ca$87 } = { output_xer_ca_ok, \output_xer_ca$54 };
- assign { \cr_a_ok$86 , \cr_a$85 } = { output_cr_a_ok, \output_cr_a$53 };
- assign { \o_ok$84 , \o$83 } = { \output_o_ok$52 , \output_o$51 };
- assign { \sr_op__SV_Ptype$82 , \sr_op__sv_saturate$81 , \sr_op__sv_pred_dz$80 , \sr_op__sv_pred_sz$79 , \sr_op__insn$78 , \sr_op__is_signed$77 , \sr_op__is_32bit$76 , \sr_op__output_cr$75 , \sr_op__input_cr$74 , \sr_op__output_carry$73 , \sr_op__input_carry$72 , \sr_op__invert_in$71 , \sr_op__write_cr0$70 , \sr_op__oe__ok$69 , \sr_op__oe__oe$68 , \sr_op__rc__ok$67 , \sr_op__rc__rc$66 , \sr_op__imm_data__ok$65 , \sr_op__imm_data__data$64 , \sr_op__fn_unit$63 , \sr_op__insn_type$62 } = { \output_sr_op__SV_Ptype$50 , \output_sr_op__sv_saturate$49 , \output_sr_op__sv_pred_dz$48 , \output_sr_op__sv_pred_sz$47 , \output_sr_op__insn$46 , \output_sr_op__is_signed$45 , \output_sr_op__is_32bit$44 , \output_sr_op__output_cr$43 , \output_sr_op__input_cr$42 , \output_sr_op__output_carry$41 , \output_sr_op__input_carry$40 , \output_sr_op__invert_in$39 , \output_sr_op__write_cr0$38 , \output_sr_op__oe__ok$37 , \output_sr_op__oe__oe$36 , \output_sr_op__rc__ok$35 , \output_sr_op__rc__rc$34 , \output_sr_op__imm_data__ok$33 , \output_sr_op__imm_data__data$32 , \output_sr_op__fn_unit$31 , \output_sr_op__insn_type$30 };
- assign \muxid$61 = \output_muxid$29 ;
- assign p_valid_i_p_ready_o = \$59 ;
+ assign { \xer_ca_ok$91 , \xer_ca$90 } = { output_xer_ca_ok, \output_xer_ca$56 };
+ assign { \cr_a_ok$89 , \cr_a$88 } = { output_cr_a_ok, \output_cr_a$55 };
+ assign { \o_ok$87 , \o$86 } = { \output_o_ok$54 , \output_o$53 };
+ assign { \sr_op__SV_Ptype$85 , \sr_op__sv_ldstmode$84 , \sr_op__sv_saturate$83 , \sr_op__sv_pred_dz$82 , \sr_op__sv_pred_sz$81 , \sr_op__insn$80 , \sr_op__is_signed$79 , \sr_op__is_32bit$78 , \sr_op__output_cr$77 , \sr_op__input_cr$76 , \sr_op__output_carry$75 , \sr_op__input_carry$74 , \sr_op__invert_in$73 , \sr_op__write_cr0$72 , \sr_op__oe__ok$71 , \sr_op__oe__oe$70 , \sr_op__rc__ok$69 , \sr_op__rc__rc$68 , \sr_op__imm_data__ok$67 , \sr_op__imm_data__data$66 , \sr_op__fn_unit$65 , \sr_op__insn_type$64 } = { \output_sr_op__SV_Ptype$52 , \output_sr_op__sv_ldstmode$51 , \output_sr_op__sv_saturate$50 , \output_sr_op__sv_pred_dz$49 , \output_sr_op__sv_pred_sz$48 , \output_sr_op__insn$47 , \output_sr_op__is_signed$46 , \output_sr_op__is_32bit$45 , \output_sr_op__output_cr$44 , \output_sr_op__input_cr$43 , \output_sr_op__output_carry$42 , \output_sr_op__input_carry$41 , \output_sr_op__invert_in$40 , \output_sr_op__write_cr0$39 , \output_sr_op__oe__ok$38 , \output_sr_op__oe__oe$37 , \output_sr_op__rc__ok$36 , \output_sr_op__rc__rc$35 , \output_sr_op__imm_data__ok$34 , \output_sr_op__imm_data__data$33 , \output_sr_op__fn_unit$32 , \output_sr_op__insn_type$31 };
+ assign \muxid$63 = \output_muxid$30 ;
+ assign p_valid_i_p_ready_o = \$61 ;
assign n_i_rdy_data = n_ready_i;
- assign \p_valid_i$58 = p_valid_i;
- assign { \xer_ca_ok$57 , output_xer_ca } = { xer_ca_ok, xer_ca };
- assign { \xer_so_ok$56 , output_xer_so } = { xer_so_ok, xer_so };
- assign { \cr_a_ok$55 , output_cr_a } = { cr_a_ok, cr_a };
+ assign \p_valid_i$60 = p_valid_i;
+ assign { \xer_ca_ok$59 , output_xer_ca } = { xer_ca_ok, xer_ca };
+ assign { \xer_so_ok$58 , output_xer_so } = { xer_so_ok, xer_so };
+ assign { \cr_a_ok$57 , output_cr_a } = { cr_a_ok, cr_a };
assign { output_o_ok, output_o } = { o_ok, o };
- assign { output_sr_op__SV_Ptype, output_sr_op__sv_saturate, output_sr_op__sv_pred_dz, output_sr_op__sv_pred_sz, output_sr_op__insn, output_sr_op__is_signed, output_sr_op__is_32bit, output_sr_op__output_cr, output_sr_op__input_cr, output_sr_op__output_carry, output_sr_op__input_carry, output_sr_op__invert_in, output_sr_op__write_cr0, output_sr_op__oe__ok, output_sr_op__oe__oe, output_sr_op__rc__ok, output_sr_op__rc__rc, output_sr_op__imm_data__ok, output_sr_op__imm_data__data, output_sr_op__fn_unit, output_sr_op__insn_type } = { sr_op__SV_Ptype, sr_op__sv_saturate, sr_op__sv_pred_dz, sr_op__sv_pred_sz, sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type };
+ assign { output_sr_op__SV_Ptype, output_sr_op__sv_ldstmode, output_sr_op__sv_saturate, output_sr_op__sv_pred_dz, output_sr_op__sv_pred_sz, output_sr_op__insn, output_sr_op__is_signed, output_sr_op__is_32bit, output_sr_op__output_cr, output_sr_op__input_cr, output_sr_op__output_carry, output_sr_op__input_carry, output_sr_op__invert_in, output_sr_op__write_cr0, output_sr_op__oe__ok, output_sr_op__oe__oe, output_sr_op__rc__ok, output_sr_op__rc__rc, output_sr_op__imm_data__ok, output_sr_op__imm_data__data, output_sr_op__fn_unit, output_sr_op__insn_type } = { sr_op__SV_Ptype, sr_op__sv_ldstmode, sr_op__sv_saturate, sr_op__sv_pred_dz, sr_op__sv_pred_sz, sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type };
assign output_muxid = muxid;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2" *)
(* generator = "nMigen" *)
-module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__svstate, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, trap_op__sv_pred_sz, trap_op__sv_pred_dz, trap_op__sv_saturate, trap_op__SV_Ptype, ra, rb, fast1, fast2, fast3, n_valid_o, n_ready_i, \muxid$1 , \trap_op__insn_type$2 , \trap_op__fn_unit$3 , \trap_op__insn$4 , \trap_op__msr$5 , \trap_op__cia$6 , \trap_op__svstate$7 , \trap_op__is_32bit$8 , \trap_op__traptype$9 , \trap_op__trapaddr$10 , \trap_op__ldst_exc$11 , \trap_op__sv_pred_sz$12 , \trap_op__sv_pred_dz$13 , \trap_op__sv_saturate$14 , \trap_op__SV_Ptype$15 , o, o_ok, \fast1$16 , fast1_ok, \fast2$17 , fast2_ok, \fast3$18 , fast3_ok, nia, nia_ok, msr, msr_ok, svstate, svstate_ok, coresync_clk);
+module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__svstate, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, trap_op__sv_pred_sz, trap_op__sv_pred_dz, trap_op__sv_saturate, trap_op__sv_ldstmode, trap_op__SV_Ptype, ra, rb, fast1, fast2, fast3, n_valid_o, n_ready_i, \muxid$1 , \trap_op__insn_type$2 , \trap_op__fn_unit$3 , \trap_op__insn$4 , \trap_op__msr$5 , \trap_op__cia$6 , \trap_op__svstate$7 , \trap_op__is_32bit$8 , \trap_op__traptype$9 , \trap_op__trapaddr$10 , \trap_op__ldst_exc$11 , \trap_op__sv_pred_sz$12 , \trap_op__sv_pred_dz$13 , \trap_op__sv_saturate$14 , \trap_op__sv_ldstmode$15 , \trap_op__SV_Ptype$16 , o, o_ok, \fast1$17 , fast1_ok, \fast2$18 , fast2_ok, \fast3$19 , fast3_ok, nia, nia_ok, msr, msr_ok, svstate, svstate_ok, coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
- wire \$38 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ wire \$40 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] fast1;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [63:0] \fast1$16 ;
- reg [63:0] \fast1$16 = 64'h0000000000000000;
+ output [63:0] \fast1$17 ;
+ reg [63:0] \fast1$17 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg [63:0] \fast1$16$next ;
+ reg [63:0] \fast1$17$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \fast1$57 ;
+ wire [63:0] \fast1$60 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output fast1_ok;
reg fast1_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \fast1_ok$58 ;
+ wire \fast1_ok$61 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \fast1_ok$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] fast2;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [63:0] \fast2$17 ;
- reg [63:0] \fast2$17 = 64'h0000000000000000;
+ output [63:0] \fast2$18 ;
+ reg [63:0] \fast2$18 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg [63:0] \fast2$17$next ;
+ reg [63:0] \fast2$18$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \fast2$59 ;
+ wire [63:0] \fast2$62 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output fast2_ok;
reg fast2_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \fast2_ok$60 ;
+ wire \fast2_ok$63 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \fast2_ok$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] fast3;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [63:0] \fast3$18 ;
- reg [63:0] \fast3$18 = 64'h0000000000000000;
+ output [63:0] \fast3$19 ;
+ reg [63:0] \fast3$19 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg [63:0] \fast3$18$next ;
+ reg [63:0] \fast3$19$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \fast3$36 ;
+ wire [63:0] \fast3$38 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \fast3$61 ;
+ wire [63:0] \fast3$64 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output fast3_ok;
reg fast3_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \fast3_ok$62 ;
+ wire \fast3_ok$65 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \fast3_ok$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] main_fast1;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \main_fast1$34 ;
+ wire [63:0] \main_fast1$36 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire main_fast1_ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] main_fast2;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \main_fast2$35 ;
+ wire [63:0] \main_fast2$37 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire main_fast2_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] main_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \main_muxid$19 ;
+ wire [1:0] \main_muxid$20 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [63:0] main_nia;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \main_trap_op__SV_Ptype$33 ;
+ wire [1:0] \main_trap_op__SV_Ptype$35 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] main_trap_op__cia;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \main_trap_op__cia$24 ;
+ wire [63:0] \main_trap_op__cia$25 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \main_trap_op__fn_unit$21 ;
+ wire [14:0] \main_trap_op__fn_unit$22 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] main_trap_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \main_trap_op__insn$22 ;
+ wire [31:0] \main_trap_op__insn$23 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \main_trap_op__insn_type$20 ;
+ wire [6:0] \main_trap_op__insn_type$21 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_trap_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_trap_op__is_32bit$26 ;
+ wire \main_trap_op__is_32bit$27 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [7:0] main_trap_op__ldst_exc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [7:0] \main_trap_op__ldst_exc$29 ;
+ wire [7:0] \main_trap_op__ldst_exc$30 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] main_trap_op__msr;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \main_trap_op__msr$23 ;
+ wire [63:0] \main_trap_op__msr$24 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] main_trap_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \main_trap_op__sv_ldstmode$34 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_trap_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_trap_op__sv_pred_dz$31 ;
+ wire \main_trap_op__sv_pred_dz$32 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire main_trap_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \main_trap_op__sv_pred_sz$30 ;
+ wire \main_trap_op__sv_pred_sz$31 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \main_trap_op__sv_saturate$32 ;
+ wire [1:0] \main_trap_op__sv_saturate$33 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] main_trap_op__svstate;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \main_trap_op__svstate$25 ;
+ wire [31:0] \main_trap_op__svstate$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [12:0] main_trap_op__trapaddr;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [12:0] \main_trap_op__trapaddr$28 ;
+ wire [12:0] \main_trap_op__trapaddr$29 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [7:0] main_trap_op__traptype;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [7:0] \main_trap_op__traptype$27 ;
+ wire [7:0] \main_trap_op__traptype$28 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output [63:0] msr;
reg [63:0] msr = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \msr$65 ;
+ wire [63:0] \msr$68 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg [63:0] \msr$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output msr_ok;
reg msr_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \msr_ok$66 ;
+ wire \msr_ok$69 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \msr_ok$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
reg [1:0] \muxid$1$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \muxid$40 ;
+ wire [1:0] \muxid$42 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
wire n_i_rdy_data;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
output [63:0] nia;
reg [63:0] nia = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \nia$63 ;
+ wire [63:0] \nia$66 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg [63:0] \nia$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output nia_ok;
reg nia_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \nia_ok$64 ;
+ wire \nia_ok$67 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \nia_ok$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output [63:0] o;
reg [63:0] o = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \o$55 ;
+ wire [63:0] \o$58 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg [63:0] \o$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output o_ok;
reg o_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \o_ok$56 ;
+ wire \o_ok$59 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \o_ok$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
input p_valid_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
- wire \p_valid_i$37 ;
+ wire \p_valid_i$39 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
wire p_valid_i_p_ready_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
output [31:0] svstate;
reg [31:0] svstate = 32'd0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [31:0] \svstate$67 ;
+ wire [31:0] \svstate$70 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg [31:0] \svstate$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output svstate_ok;
reg svstate_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \svstate_ok$68 ;
+ wire \svstate_ok$71 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \svstate_ok$next ;
(* enum_base_type = "SVPtype" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \trap_op__SV_Ptype$15 ;
- reg [1:0] \trap_op__SV_Ptype$15 = 2'h0;
+ output [1:0] \trap_op__SV_Ptype$16 ;
+ reg [1:0] \trap_op__SV_Ptype$16 = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [1:0] \trap_op__SV_Ptype$15$next ;
+ reg [1:0] \trap_op__SV_Ptype$16$next ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \trap_op__SV_Ptype$54 ;
+ wire [1:0] \trap_op__SV_Ptype$57 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] trap_op__cia;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \trap_op__cia$45 ;
+ wire [63:0] \trap_op__cia$47 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output [63:0] \trap_op__cia$6 ;
reg [63:0] \trap_op__cia$6 = 64'h0000000000000000;
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \trap_op__fn_unit$42 ;
+ wire [14:0] \trap_op__fn_unit$44 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] trap_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [31:0] \trap_op__insn$4$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \trap_op__insn$43 ;
+ wire [31:0] \trap_op__insn$45 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \trap_op__insn_type$41 ;
+ wire [6:0] \trap_op__insn_type$43 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input trap_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \trap_op__is_32bit$47 ;
+ wire \trap_op__is_32bit$49 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \trap_op__is_32bit$8 ;
reg \trap_op__is_32bit$8 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [7:0] \trap_op__ldst_exc$11$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [7:0] \trap_op__ldst_exc$50 ;
+ wire [7:0] \trap_op__ldst_exc$52 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] trap_op__msr;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \trap_op__msr$44 ;
+ wire [63:0] \trap_op__msr$46 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output [63:0] \trap_op__msr$5 ;
reg [63:0] \trap_op__msr$5 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [63:0] \trap_op__msr$5$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] trap_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \trap_op__sv_ldstmode$15 ;
+ reg [1:0] \trap_op__sv_ldstmode$15 = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \trap_op__sv_ldstmode$15$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \trap_op__sv_ldstmode$56 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input trap_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \trap_op__sv_pred_dz$13$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \trap_op__sv_pred_dz$52 ;
+ wire \trap_op__sv_pred_dz$54 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input trap_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \trap_op__sv_pred_sz$12$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \trap_op__sv_pred_sz$51 ;
+ wire \trap_op__sv_pred_sz$53 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \trap_op__sv_saturate$53 ;
+ wire [1:0] \trap_op__sv_saturate$55 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] trap_op__svstate;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \trap_op__svstate$46 ;
+ wire [31:0] \trap_op__svstate$48 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output [31:0] \trap_op__svstate$7 ;
reg [31:0] \trap_op__svstate$7 = 32'd0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [12:0] \trap_op__trapaddr$10$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [12:0] \trap_op__trapaddr$49 ;
+ wire [12:0] \trap_op__trapaddr$51 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [7:0] trap_op__traptype;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [7:0] \trap_op__traptype$48 ;
+ wire [7:0] \trap_op__traptype$50 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output [7:0] \trap_op__traptype$9 ;
reg [7:0] \trap_op__traptype$9 = 8'h00;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [7:0] \trap_op__traptype$9$next ;
- assign \$38 = \p_valid_i$37 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
+ assign \$40 = \p_valid_i$39 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
always @(posedge coresync_clk)
svstate <= \svstate$next ;
always @(posedge coresync_clk)
always @(posedge coresync_clk)
nia_ok <= \nia_ok$next ;
always @(posedge coresync_clk)
- \fast3$18 <= \fast3$18$next ;
+ \fast3$19 <= \fast3$19$next ;
always @(posedge coresync_clk)
fast3_ok <= \fast3_ok$next ;
always @(posedge coresync_clk)
- \fast2$17 <= \fast2$17$next ;
+ \fast2$18 <= \fast2$18$next ;
always @(posedge coresync_clk)
fast2_ok <= \fast2_ok$next ;
always @(posedge coresync_clk)
- \fast1$16 <= \fast1$16$next ;
+ \fast1$17 <= \fast1$17$next ;
always @(posedge coresync_clk)
fast1_ok <= \fast1_ok$next ;
always @(posedge coresync_clk)
always @(posedge coresync_clk)
\trap_op__sv_saturate$14 <= \trap_op__sv_saturate$14$next ;
always @(posedge coresync_clk)
- \trap_op__SV_Ptype$15 <= \trap_op__SV_Ptype$15$next ;
+ \trap_op__sv_ldstmode$15 <= \trap_op__sv_ldstmode$15$next ;
+ always @(posedge coresync_clk)
+ \trap_op__SV_Ptype$16 <= \trap_op__SV_Ptype$16$next ;
always @(posedge coresync_clk)
\muxid$1 <= \muxid$1$next ;
always @(posedge coresync_clk)
r_busy <= \r_busy$next ;
\main$38 main (
.fast1(main_fast1),
- .\fast1$16 (\main_fast1$34 ),
+ .\fast1$17 (\main_fast1$36 ),
.fast1_ok(main_fast1_ok),
.fast2(main_fast2),
- .\fast2$17 (\main_fast2$35 ),
+ .\fast2$18 (\main_fast2$37 ),
.fast2_ok(main_fast2_ok),
.fast3(main_fast3),
.fast3_ok(main_fast3_ok),
.msr(main_msr),
.msr_ok(main_msr_ok),
.muxid(main_muxid),
- .\muxid$1 (\main_muxid$19 ),
+ .\muxid$1 (\main_muxid$20 ),
.nia(main_nia),
.nia_ok(main_nia_ok),
.o(main_o),
.svstate(main_svstate),
.svstate_ok(main_svstate_ok),
.trap_op__SV_Ptype(main_trap_op__SV_Ptype),
- .\trap_op__SV_Ptype$15 (\main_trap_op__SV_Ptype$33 ),
+ .\trap_op__SV_Ptype$16 (\main_trap_op__SV_Ptype$35 ),
.trap_op__cia(main_trap_op__cia),
- .\trap_op__cia$6 (\main_trap_op__cia$24 ),
+ .\trap_op__cia$6 (\main_trap_op__cia$25 ),
.trap_op__fn_unit(main_trap_op__fn_unit),
- .\trap_op__fn_unit$3 (\main_trap_op__fn_unit$21 ),
+ .\trap_op__fn_unit$3 (\main_trap_op__fn_unit$22 ),
.trap_op__insn(main_trap_op__insn),
- .\trap_op__insn$4 (\main_trap_op__insn$22 ),
+ .\trap_op__insn$4 (\main_trap_op__insn$23 ),
.trap_op__insn_type(main_trap_op__insn_type),
- .\trap_op__insn_type$2 (\main_trap_op__insn_type$20 ),
+ .\trap_op__insn_type$2 (\main_trap_op__insn_type$21 ),
.trap_op__is_32bit(main_trap_op__is_32bit),
- .\trap_op__is_32bit$8 (\main_trap_op__is_32bit$26 ),
+ .\trap_op__is_32bit$8 (\main_trap_op__is_32bit$27 ),
.trap_op__ldst_exc(main_trap_op__ldst_exc),
- .\trap_op__ldst_exc$11 (\main_trap_op__ldst_exc$29 ),
+ .\trap_op__ldst_exc$11 (\main_trap_op__ldst_exc$30 ),
.trap_op__msr(main_trap_op__msr),
- .\trap_op__msr$5 (\main_trap_op__msr$23 ),
+ .\trap_op__msr$5 (\main_trap_op__msr$24 ),
+ .trap_op__sv_ldstmode(main_trap_op__sv_ldstmode),
+ .\trap_op__sv_ldstmode$15 (\main_trap_op__sv_ldstmode$34 ),
.trap_op__sv_pred_dz(main_trap_op__sv_pred_dz),
- .\trap_op__sv_pred_dz$13 (\main_trap_op__sv_pred_dz$31 ),
+ .\trap_op__sv_pred_dz$13 (\main_trap_op__sv_pred_dz$32 ),
.trap_op__sv_pred_sz(main_trap_op__sv_pred_sz),
- .\trap_op__sv_pred_sz$12 (\main_trap_op__sv_pred_sz$30 ),
+ .\trap_op__sv_pred_sz$12 (\main_trap_op__sv_pred_sz$31 ),
.trap_op__sv_saturate(main_trap_op__sv_saturate),
- .\trap_op__sv_saturate$14 (\main_trap_op__sv_saturate$32 ),
+ .\trap_op__sv_saturate$14 (\main_trap_op__sv_saturate$33 ),
.trap_op__svstate(main_trap_op__svstate),
- .\trap_op__svstate$7 (\main_trap_op__svstate$25 ),
+ .\trap_op__svstate$7 (\main_trap_op__svstate$26 ),
.trap_op__trapaddr(main_trap_op__trapaddr),
- .\trap_op__trapaddr$10 (\main_trap_op__trapaddr$28 ),
+ .\trap_op__trapaddr$10 (\main_trap_op__trapaddr$29 ),
.trap_op__traptype(main_trap_op__traptype),
- .\trap_op__traptype$9 (\main_trap_op__traptype$27 )
+ .\trap_op__traptype$9 (\main_trap_op__traptype$28 )
);
\n$37 n (
.n_ready_i(n_ready_i),
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \muxid$1$next = \muxid$40 ;
+ \muxid$1$next = \muxid$42 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \muxid$1$next = \muxid$40 ;
+ \muxid$1$next = \muxid$42 ;
endcase
end
always @* begin
\trap_op__sv_pred_sz$12$next = \trap_op__sv_pred_sz$12 ;
\trap_op__sv_pred_dz$13$next = \trap_op__sv_pred_dz$13 ;
\trap_op__sv_saturate$14$next = \trap_op__sv_saturate$14 ;
- \trap_op__SV_Ptype$15$next = \trap_op__SV_Ptype$15 ;
+ \trap_op__sv_ldstmode$15$next = \trap_op__sv_ldstmode$15 ;
+ \trap_op__SV_Ptype$16$next = \trap_op__SV_Ptype$16 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \trap_op__SV_Ptype$15$next , \trap_op__sv_saturate$14$next , \trap_op__sv_pred_dz$13$next , \trap_op__sv_pred_sz$12$next , \trap_op__ldst_exc$11$next , \trap_op__trapaddr$10$next , \trap_op__traptype$9$next , \trap_op__is_32bit$8$next , \trap_op__svstate$7$next , \trap_op__cia$6$next , \trap_op__msr$5$next , \trap_op__insn$4$next , \trap_op__fn_unit$3$next , \trap_op__insn_type$2$next } = { \trap_op__SV_Ptype$54 , \trap_op__sv_saturate$53 , \trap_op__sv_pred_dz$52 , \trap_op__sv_pred_sz$51 , \trap_op__ldst_exc$50 , \trap_op__trapaddr$49 , \trap_op__traptype$48 , \trap_op__is_32bit$47 , \trap_op__svstate$46 , \trap_op__cia$45 , \trap_op__msr$44 , \trap_op__insn$43 , \trap_op__fn_unit$42 , \trap_op__insn_type$41 };
+ { \trap_op__SV_Ptype$16$next , \trap_op__sv_ldstmode$15$next , \trap_op__sv_saturate$14$next , \trap_op__sv_pred_dz$13$next , \trap_op__sv_pred_sz$12$next , \trap_op__ldst_exc$11$next , \trap_op__trapaddr$10$next , \trap_op__traptype$9$next , \trap_op__is_32bit$8$next , \trap_op__svstate$7$next , \trap_op__cia$6$next , \trap_op__msr$5$next , \trap_op__insn$4$next , \trap_op__fn_unit$3$next , \trap_op__insn_type$2$next } = { \trap_op__SV_Ptype$57 , \trap_op__sv_ldstmode$56 , \trap_op__sv_saturate$55 , \trap_op__sv_pred_dz$54 , \trap_op__sv_pred_sz$53 , \trap_op__ldst_exc$52 , \trap_op__trapaddr$51 , \trap_op__traptype$50 , \trap_op__is_32bit$49 , \trap_op__svstate$48 , \trap_op__cia$47 , \trap_op__msr$46 , \trap_op__insn$45 , \trap_op__fn_unit$44 , \trap_op__insn_type$43 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \trap_op__SV_Ptype$15$next , \trap_op__sv_saturate$14$next , \trap_op__sv_pred_dz$13$next , \trap_op__sv_pred_sz$12$next , \trap_op__ldst_exc$11$next , \trap_op__trapaddr$10$next , \trap_op__traptype$9$next , \trap_op__is_32bit$8$next , \trap_op__svstate$7$next , \trap_op__cia$6$next , \trap_op__msr$5$next , \trap_op__insn$4$next , \trap_op__fn_unit$3$next , \trap_op__insn_type$2$next } = { \trap_op__SV_Ptype$54 , \trap_op__sv_saturate$53 , \trap_op__sv_pred_dz$52 , \trap_op__sv_pred_sz$51 , \trap_op__ldst_exc$50 , \trap_op__trapaddr$49 , \trap_op__traptype$48 , \trap_op__is_32bit$47 , \trap_op__svstate$46 , \trap_op__cia$45 , \trap_op__msr$44 , \trap_op__insn$43 , \trap_op__fn_unit$42 , \trap_op__insn_type$41 };
+ { \trap_op__SV_Ptype$16$next , \trap_op__sv_ldstmode$15$next , \trap_op__sv_saturate$14$next , \trap_op__sv_pred_dz$13$next , \trap_op__sv_pred_sz$12$next , \trap_op__ldst_exc$11$next , \trap_op__trapaddr$10$next , \trap_op__traptype$9$next , \trap_op__is_32bit$8$next , \trap_op__svstate$7$next , \trap_op__cia$6$next , \trap_op__msr$5$next , \trap_op__insn$4$next , \trap_op__fn_unit$3$next , \trap_op__insn_type$2$next } = { \trap_op__SV_Ptype$57 , \trap_op__sv_ldstmode$56 , \trap_op__sv_saturate$55 , \trap_op__sv_pred_dz$54 , \trap_op__sv_pred_sz$53 , \trap_op__ldst_exc$52 , \trap_op__trapaddr$51 , \trap_op__traptype$50 , \trap_op__is_32bit$49 , \trap_op__svstate$48 , \trap_op__cia$47 , \trap_op__msr$46 , \trap_op__insn$45 , \trap_op__fn_unit$44 , \trap_op__insn_type$43 };
endcase
end
always @* begin
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \o_ok$next , \o$next } = { \o_ok$56 , \o$55 };
+ { \o_ok$next , \o$next } = { \o_ok$59 , \o$58 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \o_ok$next , \o$next } = { \o_ok$56 , \o$55 };
+ { \o_ok$next , \o$next } = { \o_ok$59 , \o$58 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
end
always @* begin
if (\initial ) begin end
- \fast1$16$next = \fast1$16 ;
+ \fast1$17$next = \fast1$17 ;
\fast1_ok$next = fast1_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \fast1_ok$next , \fast1$16$next } = { \fast1_ok$58 , \fast1$57 };
+ { \fast1_ok$next , \fast1$17$next } = { \fast1_ok$61 , \fast1$60 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \fast1_ok$next , \fast1$16$next } = { \fast1_ok$58 , \fast1$57 };
+ { \fast1_ok$next , \fast1$17$next } = { \fast1_ok$61 , \fast1$60 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
end
always @* begin
if (\initial ) begin end
- \fast2$17$next = \fast2$17 ;
+ \fast2$18$next = \fast2$18 ;
\fast2_ok$next = fast2_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \fast2_ok$next , \fast2$17$next } = { \fast2_ok$60 , \fast2$59 };
+ { \fast2_ok$next , \fast2$18$next } = { \fast2_ok$63 , \fast2$62 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \fast2_ok$next , \fast2$17$next } = { \fast2_ok$60 , \fast2$59 };
+ { \fast2_ok$next , \fast2$18$next } = { \fast2_ok$63 , \fast2$62 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
end
always @* begin
if (\initial ) begin end
- \fast3$18$next = \fast3$18 ;
+ \fast3$19$next = \fast3$19 ;
\fast3_ok$next = fast3_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \fast3_ok$next , \fast3$18$next } = { \fast3_ok$62 , \fast3$61 };
+ { \fast3_ok$next , \fast3$19$next } = { \fast3_ok$65 , \fast3$64 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \fast3_ok$next , \fast3$18$next } = { \fast3_ok$62 , \fast3$61 };
+ { \fast3_ok$next , \fast3$19$next } = { \fast3_ok$65 , \fast3$64 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \nia_ok$next , \nia$next } = { \nia_ok$64 , \nia$63 };
+ { \nia_ok$next , \nia$next } = { \nia_ok$67 , \nia$66 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \nia_ok$next , \nia$next } = { \nia_ok$64 , \nia$63 };
+ { \nia_ok$next , \nia$next } = { \nia_ok$67 , \nia$66 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \msr_ok$next , \msr$next } = { \msr_ok$66 , \msr$65 };
+ { \msr_ok$next , \msr$next } = { \msr_ok$69 , \msr$68 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \msr_ok$next , \msr$next } = { \msr_ok$66 , \msr$65 };
+ { \msr_ok$next , \msr$next } = { \msr_ok$69 , \msr$68 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \svstate_ok$next , \svstate$next } = { \svstate_ok$68 , \svstate$67 };
+ { \svstate_ok$next , \svstate$next } = { \svstate_ok$71 , \svstate$70 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \svstate_ok$next , \svstate$next } = { \svstate_ok$68 , \svstate$67 };
+ { \svstate_ok$next , \svstate$next } = { \svstate_ok$71 , \svstate$70 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
end
assign p_ready_o = n_i_rdy_data;
assign n_valid_o = r_busy;
- assign { \svstate_ok$68 , \svstate$67 } = { main_svstate_ok, main_svstate };
- assign { \msr_ok$66 , \msr$65 } = { main_msr_ok, main_msr };
- assign { \nia_ok$64 , \nia$63 } = { main_nia_ok, main_nia };
- assign { \fast3_ok$62 , \fast3$61 } = { main_fast3_ok, main_fast3 };
- assign { \fast2_ok$60 , \fast2$59 } = { main_fast2_ok, \main_fast2$35 };
- assign { \fast1_ok$58 , \fast1$57 } = { main_fast1_ok, \main_fast1$34 };
- assign { \o_ok$56 , \o$55 } = { main_o_ok, main_o };
- assign { \trap_op__SV_Ptype$54 , \trap_op__sv_saturate$53 , \trap_op__sv_pred_dz$52 , \trap_op__sv_pred_sz$51 , \trap_op__ldst_exc$50 , \trap_op__trapaddr$49 , \trap_op__traptype$48 , \trap_op__is_32bit$47 , \trap_op__svstate$46 , \trap_op__cia$45 , \trap_op__msr$44 , \trap_op__insn$43 , \trap_op__fn_unit$42 , \trap_op__insn_type$41 } = { \main_trap_op__SV_Ptype$33 , \main_trap_op__sv_saturate$32 , \main_trap_op__sv_pred_dz$31 , \main_trap_op__sv_pred_sz$30 , \main_trap_op__ldst_exc$29 , \main_trap_op__trapaddr$28 , \main_trap_op__traptype$27 , \main_trap_op__is_32bit$26 , \main_trap_op__svstate$25 , \main_trap_op__cia$24 , \main_trap_op__msr$23 , \main_trap_op__insn$22 , \main_trap_op__fn_unit$21 , \main_trap_op__insn_type$20 };
- assign \muxid$40 = \main_muxid$19 ;
- assign p_valid_i_p_ready_o = \$38 ;
+ assign { \svstate_ok$71 , \svstate$70 } = { main_svstate_ok, main_svstate };
+ assign { \msr_ok$69 , \msr$68 } = { main_msr_ok, main_msr };
+ assign { \nia_ok$67 , \nia$66 } = { main_nia_ok, main_nia };
+ assign { \fast3_ok$65 , \fast3$64 } = { main_fast3_ok, main_fast3 };
+ assign { \fast2_ok$63 , \fast2$62 } = { main_fast2_ok, \main_fast2$37 };
+ assign { \fast1_ok$61 , \fast1$60 } = { main_fast1_ok, \main_fast1$36 };
+ assign { \o_ok$59 , \o$58 } = { main_o_ok, main_o };
+ assign { \trap_op__SV_Ptype$57 , \trap_op__sv_ldstmode$56 , \trap_op__sv_saturate$55 , \trap_op__sv_pred_dz$54 , \trap_op__sv_pred_sz$53 , \trap_op__ldst_exc$52 , \trap_op__trapaddr$51 , \trap_op__traptype$50 , \trap_op__is_32bit$49 , \trap_op__svstate$48 , \trap_op__cia$47 , \trap_op__msr$46 , \trap_op__insn$45 , \trap_op__fn_unit$44 , \trap_op__insn_type$43 } = { \main_trap_op__SV_Ptype$35 , \main_trap_op__sv_ldstmode$34 , \main_trap_op__sv_saturate$33 , \main_trap_op__sv_pred_dz$32 , \main_trap_op__sv_pred_sz$31 , \main_trap_op__ldst_exc$30 , \main_trap_op__trapaddr$29 , \main_trap_op__traptype$28 , \main_trap_op__is_32bit$27 , \main_trap_op__svstate$26 , \main_trap_op__cia$25 , \main_trap_op__msr$24 , \main_trap_op__insn$23 , \main_trap_op__fn_unit$22 , \main_trap_op__insn_type$21 };
+ assign \muxid$42 = \main_muxid$20 ;
+ assign p_valid_i_p_ready_o = \$40 ;
assign n_i_rdy_data = n_ready_i;
- assign \p_valid_i$37 = p_valid_i;
- assign \fast3$36 = fast3;
+ assign \p_valid_i$39 = p_valid_i;
+ assign \fast3$38 = fast3;
assign main_fast2 = fast2;
assign main_fast1 = fast1;
assign main_rb = rb;
assign main_ra = ra;
- assign { main_trap_op__SV_Ptype, main_trap_op__sv_saturate, main_trap_op__sv_pred_dz, main_trap_op__sv_pred_sz, main_trap_op__ldst_exc, main_trap_op__trapaddr, main_trap_op__traptype, main_trap_op__is_32bit, main_trap_op__svstate, main_trap_op__cia, main_trap_op__msr, main_trap_op__insn, main_trap_op__fn_unit, main_trap_op__insn_type } = { trap_op__SV_Ptype, trap_op__sv_saturate, trap_op__sv_pred_dz, trap_op__sv_pred_sz, trap_op__ldst_exc, trap_op__trapaddr, trap_op__traptype, trap_op__is_32bit, trap_op__svstate, trap_op__cia, trap_op__msr, trap_op__insn, trap_op__fn_unit, trap_op__insn_type };
+ assign { main_trap_op__SV_Ptype, main_trap_op__sv_ldstmode, main_trap_op__sv_saturate, main_trap_op__sv_pred_dz, main_trap_op__sv_pred_sz, main_trap_op__ldst_exc, main_trap_op__trapaddr, main_trap_op__traptype, main_trap_op__is_32bit, main_trap_op__svstate, main_trap_op__cia, main_trap_op__msr, main_trap_op__insn, main_trap_op__fn_unit, main_trap_op__insn_type } = { trap_op__SV_Ptype, trap_op__sv_ldstmode, trap_op__sv_saturate, trap_op__sv_pred_dz, trap_op__sv_pred_sz, trap_op__ldst_exc, trap_op__trapaddr, trap_op__traptype, trap_op__is_32bit, trap_op__svstate, trap_op__cia, trap_op__msr, trap_op__insn, trap_op__fn_unit, trap_op__insn_type };
assign main_muxid = muxid;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_end" *)
(* generator = "nMigen" *)
-module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, ra, rb, xer_so, divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, quotient_root, remainder, n_valid_o, n_ready_i, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__SV_Ptype$23 , o, o_ok, cr_a, cr_a_ok, xer_ov, xer_ov_ok, \xer_so$24 , xer_so_ok, coresync_clk);
+module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__sv_ldstmode, logical_op__SV_Ptype, ra, rb, xer_so, divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, quotient_root, remainder, n_valid_o, n_ready_i, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__sv_ldstmode$23 , \logical_op__SV_Ptype$24 , o, o_ok, cr_a, cr_a_ok, xer_ov, xer_ov_ok, \xer_so$25 , xer_so_ok, coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
- wire \$86 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ wire \$89 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output [3:0] cr_a;
reg [3:0] cr_a = 4'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [3:0] \cr_a$113 ;
+ wire [3:0] \cr_a$117 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [3:0] \cr_a$80 ;
+ wire [3:0] \cr_a$83 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg [3:0] \cr_a$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output cr_a_ok;
reg cr_a_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \cr_a_ok$114 ;
+ wire \cr_a_ok$118 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \cr_a_ok$79 ;
+ wire \cr_a_ok$82 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \cr_a_ok$81 ;
+ wire \cr_a_ok$84 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \cr_a_ok$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \logical_op__SV_Ptype$110 ;
+ wire [1:0] \logical_op__SV_Ptype$114 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \logical_op__SV_Ptype$23 ;
- reg [1:0] \logical_op__SV_Ptype$23 = 2'h0;
+ output [1:0] \logical_op__SV_Ptype$24 ;
+ reg [1:0] \logical_op__SV_Ptype$24 = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [1:0] \logical_op__SV_Ptype$23$next ;
+ reg [1:0] \logical_op__SV_Ptype$24$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [3:0] logical_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [3:0] \logical_op__data_len$105 ;
+ wire [3:0] \logical_op__data_len$108 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output [3:0] \logical_op__data_len$18 ;
reg [3:0] \logical_op__data_len$18 = 4'h0;
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \logical_op__fn_unit$90 ;
+ wire [14:0] \logical_op__fn_unit$93 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] logical_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [63:0] \logical_op__imm_data__data$4$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \logical_op__imm_data__data$91 ;
+ wire [63:0] \logical_op__imm_data__data$94 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__imm_data__ok$5$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__imm_data__ok$92 ;
+ wire \logical_op__imm_data__ok$95 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \logical_op__input_carry$12 ;
- reg [1:0] \logical_op__input_carry$12 = 2'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [1:0] \logical_op__input_carry$12$next ;
+ wire [1:0] \logical_op__input_carry$102 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \logical_op__input_carry$99 ;
+ output [1:0] \logical_op__input_carry$12 ;
+ reg [1:0] \logical_op__input_carry$12 = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \logical_op__input_carry$12$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] logical_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \logical_op__insn$106 ;
+ wire [31:0] \logical_op__insn$109 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output [31:0] \logical_op__insn$19 ;
reg [31:0] \logical_op__insn$19 = 32'd0;
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \logical_op__insn_type$89 ;
+ wire [6:0] \logical_op__insn_type$92 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__invert_in$10$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__invert_in$97 ;
+ wire \logical_op__invert_in$100 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__invert_out;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__invert_out$100 ;
+ wire \logical_op__invert_out$103 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__invert_out$13 ;
reg \logical_op__invert_out$13 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__is_32bit$103 ;
+ wire \logical_op__is_32bit$106 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__is_32bit$16 ;
reg \logical_op__is_32bit$16 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__is_signed$104 ;
+ wire \logical_op__is_signed$107 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__is_signed$17 ;
reg \logical_op__is_signed$17 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__oe__oe$8$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__oe__oe$95 ;
+ wire \logical_op__oe__oe$98 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__oe__ok$9$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__oe__ok$96 ;
+ wire \logical_op__oe__ok$99 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__output_carry;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__output_carry$102 ;
+ wire \logical_op__output_carry$105 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__output_carry$15 ;
reg \logical_op__output_carry$15 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__rc__ok$7$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__rc__ok$94 ;
+ wire \logical_op__rc__ok$97 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__rc__rc$6$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__rc__rc$93 ;
+ wire \logical_op__rc__rc$96 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] logical_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \logical_op__sv_ldstmode$113 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \logical_op__sv_ldstmode$23 ;
+ reg [1:0] \logical_op__sv_ldstmode$23 = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \logical_op__sv_ldstmode$23$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__sv_pred_dz$108 ;
+ wire \logical_op__sv_pred_dz$111 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__sv_pred_dz$21 ;
reg \logical_op__sv_pred_dz$21 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__sv_pred_sz$107 ;
+ wire \logical_op__sv_pred_sz$110 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__sv_pred_sz$20 ;
reg \logical_op__sv_pred_sz$20 = 1'h0;
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \logical_op__sv_saturate$109 ;
+ wire [1:0] \logical_op__sv_saturate$112 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__write_cr0$101 ;
+ wire \logical_op__write_cr0$104 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__write_cr0$14 ;
reg \logical_op__write_cr0$14 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__zero_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire \logical_op__zero_a$101 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__zero_a$11 ;
reg \logical_op__zero_a$11 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__zero_a$11$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__zero_a$98 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
input [1:0] muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
reg [1:0] \muxid$1$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \muxid$88 ;
+ wire [1:0] \muxid$91 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
wire n_i_rdy_data;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
output [63:0] o;
reg [63:0] o = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \o$111 ;
+ wire [63:0] \o$115 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg [63:0] \o$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output o_ok;
reg o_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \o_ok$112 ;
+ wire \o_ok$116 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \o_ok$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [3:0] output_cr_a;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [3:0] \output_cr_a$74 ;
+ wire [3:0] \output_cr_a$77 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire output_cr_a_ok;
(* enum_base_type = "SVPtype" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \output_logical_op__SV_Ptype$71 ;
+ wire [1:0] \output_logical_op__SV_Ptype$74 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [3:0] output_logical_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [3:0] \output_logical_op__data_len$66 ;
+ wire [3:0] \output_logical_op__data_len$68 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \output_logical_op__fn_unit$51 ;
+ wire [14:0] \output_logical_op__fn_unit$53 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] output_logical_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \output_logical_op__imm_data__data$52 ;
+ wire [63:0] \output_logical_op__imm_data__data$54 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__imm_data__ok$53 ;
+ wire \output_logical_op__imm_data__ok$55 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \output_logical_op__input_carry$60 ;
+ wire [1:0] \output_logical_op__input_carry$62 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] output_logical_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \output_logical_op__insn$67 ;
+ wire [31:0] \output_logical_op__insn$69 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \output_logical_op__insn_type$50 ;
+ wire [6:0] \output_logical_op__insn_type$52 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__invert_in$58 ;
+ wire \output_logical_op__invert_in$60 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__invert_out;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__invert_out$61 ;
+ wire \output_logical_op__invert_out$63 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__is_32bit$64 ;
+ wire \output_logical_op__is_32bit$66 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__is_signed$65 ;
+ wire \output_logical_op__is_signed$67 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__oe__oe$56 ;
+ wire \output_logical_op__oe__oe$58 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__oe__ok$57 ;
+ wire \output_logical_op__oe__ok$59 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__output_carry;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__output_carry$63 ;
+ wire \output_logical_op__output_carry$65 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__rc__ok$55 ;
+ wire \output_logical_op__rc__ok$57 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__rc__rc$54 ;
+ wire \output_logical_op__rc__rc$56 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] output_logical_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \output_logical_op__sv_ldstmode$73 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__sv_pred_dz$69 ;
+ wire \output_logical_op__sv_pred_dz$71 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__sv_pred_sz$68 ;
+ wire \output_logical_op__sv_pred_sz$70 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \output_logical_op__sv_saturate$70 ;
+ wire [1:0] \output_logical_op__sv_saturate$72 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__write_cr0$62 ;
+ wire \output_logical_op__write_cr0$64 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_logical_op__zero_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_logical_op__zero_a$59 ;
+ wire \output_logical_op__zero_a$61 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] output_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \output_muxid$49 ;
+ wire [1:0] \output_muxid$51 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [63:0] output_o;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [63:0] \output_o$72 ;
+ wire [63:0] \output_o$75 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire output_o_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \output_o_ok$73 ;
+ wire \output_o_ok$76 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
wire output_stage_div_by_zero;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \output_stage_logical_op__SV_Ptype$47 ;
+ wire [1:0] \output_stage_logical_op__SV_Ptype$49 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [3:0] output_stage_logical_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [3:0] \output_stage_logical_op__data_len$42 ;
+ wire [3:0] \output_stage_logical_op__data_len$43 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \output_stage_logical_op__fn_unit$27 ;
+ wire [14:0] \output_stage_logical_op__fn_unit$28 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] output_stage_logical_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \output_stage_logical_op__imm_data__data$28 ;
+ wire [63:0] \output_stage_logical_op__imm_data__data$29 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_stage_logical_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_stage_logical_op__imm_data__ok$29 ;
+ wire \output_stage_logical_op__imm_data__ok$30 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \output_stage_logical_op__input_carry$36 ;
+ wire [1:0] \output_stage_logical_op__input_carry$37 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] output_stage_logical_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \output_stage_logical_op__insn$43 ;
+ wire [31:0] \output_stage_logical_op__insn$44 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \output_stage_logical_op__insn_type$26 ;
+ wire [6:0] \output_stage_logical_op__insn_type$27 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_stage_logical_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_stage_logical_op__invert_in$34 ;
+ wire \output_stage_logical_op__invert_in$35 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_stage_logical_op__invert_out;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_stage_logical_op__invert_out$37 ;
+ wire \output_stage_logical_op__invert_out$38 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_stage_logical_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_stage_logical_op__is_32bit$40 ;
+ wire \output_stage_logical_op__is_32bit$41 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_stage_logical_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_stage_logical_op__is_signed$41 ;
+ wire \output_stage_logical_op__is_signed$42 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_stage_logical_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_stage_logical_op__oe__oe$32 ;
+ wire \output_stage_logical_op__oe__oe$33 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_stage_logical_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_stage_logical_op__oe__ok$33 ;
+ wire \output_stage_logical_op__oe__ok$34 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_stage_logical_op__output_carry;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_stage_logical_op__output_carry$39 ;
+ wire \output_stage_logical_op__output_carry$40 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_stage_logical_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_stage_logical_op__rc__ok$31 ;
+ wire \output_stage_logical_op__rc__ok$32 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_stage_logical_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_stage_logical_op__rc__rc$30 ;
+ wire \output_stage_logical_op__rc__rc$31 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] output_stage_logical_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \output_stage_logical_op__sv_ldstmode$48 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_stage_logical_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_stage_logical_op__sv_pred_dz$45 ;
+ wire \output_stage_logical_op__sv_pred_dz$46 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_stage_logical_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_stage_logical_op__sv_pred_sz$44 ;
+ wire \output_stage_logical_op__sv_pred_sz$45 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \output_stage_logical_op__sv_saturate$46 ;
+ wire [1:0] \output_stage_logical_op__sv_saturate$47 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_stage_logical_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_stage_logical_op__write_cr0$38 ;
+ wire \output_stage_logical_op__write_cr0$39 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire output_stage_logical_op__zero_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \output_stage_logical_op__zero_a$35 ;
+ wire \output_stage_logical_op__zero_a$36 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] output_stage_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \output_stage_muxid$25 ;
+ wire [1:0] \output_stage_muxid$26 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [63:0] output_stage_o;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire output_stage_xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \output_stage_xer_so$48 ;
+ wire \output_stage_xer_so$50 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire [1:0] output_xer_ov;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [1:0] \output_xer_ov$75 ;
+ wire [1:0] \output_xer_ov$78 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire output_xer_ov_ok;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire output_xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \output_xer_so$76 ;
+ wire \output_xer_so$79 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire output_xer_so_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
input p_valid_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
- wire \p_valid_i$85 ;
+ wire \p_valid_i$88 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
wire p_valid_i_p_ready_o;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] ra;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \ra$77 ;
+ wire [63:0] \ra$80 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] rb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \rb$78 ;
+ wire [63:0] \rb$81 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" *)
input [191:0] remainder;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output [1:0] xer_ov;
reg [1:0] xer_ov = 2'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire [1:0] \xer_ov$115 ;
+ wire [1:0] \xer_ov$119 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg [1:0] \xer_ov$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_ov_ok;
reg xer_ov_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_ov_ok$116 ;
+ wire \xer_ov_ok$120 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_ov_ok$82 ;
+ wire \xer_ov_ok$85 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \xer_ov_ok$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_so$117 ;
+ wire \xer_so$121 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \xer_so$24 ;
- reg \xer_so$24 = 1'h0;
+ output \xer_so$25 ;
+ reg \xer_so$25 = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- reg \xer_so$24$next ;
+ reg \xer_so$25$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_so_ok;
reg xer_so_ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_so_ok$118 ;
+ wire \xer_so_ok$122 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_so_ok$83 ;
+ wire \xer_so_ok$86 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- wire \xer_so_ok$84 ;
+ wire \xer_so_ok$87 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg \xer_so_ok$next ;
- assign \$86 = \p_valid_i$85 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
+ assign \$89 = \p_valid_i$88 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
always @(posedge coresync_clk)
- \xer_so$24 <= \xer_so$24$next ;
+ \xer_so$25 <= \xer_so$25$next ;
always @(posedge coresync_clk)
xer_so_ok <= \xer_so_ok$next ;
always @(posedge coresync_clk)
always @(posedge coresync_clk)
\logical_op__sv_saturate$22 <= \logical_op__sv_saturate$22$next ;
always @(posedge coresync_clk)
- \logical_op__SV_Ptype$23 <= \logical_op__SV_Ptype$23$next ;
+ \logical_op__sv_ldstmode$23 <= \logical_op__sv_ldstmode$23$next ;
+ always @(posedge coresync_clk)
+ \logical_op__SV_Ptype$24 <= \logical_op__SV_Ptype$24$next ;
always @(posedge coresync_clk)
\muxid$1 <= \muxid$1$next ;
always @(posedge coresync_clk)
);
\output$83 \output (
.cr_a(output_cr_a),
- .\cr_a$26 (\output_cr_a$74 ),
+ .\cr_a$27 (\output_cr_a$77 ),
.cr_a_ok(output_cr_a_ok),
.logical_op__SV_Ptype(output_logical_op__SV_Ptype),
- .\logical_op__SV_Ptype$23 (\output_logical_op__SV_Ptype$71 ),
+ .\logical_op__SV_Ptype$24 (\output_logical_op__SV_Ptype$74 ),
.logical_op__data_len(output_logical_op__data_len),
- .\logical_op__data_len$18 (\output_logical_op__data_len$66 ),
+ .\logical_op__data_len$18 (\output_logical_op__data_len$68 ),
.logical_op__fn_unit(output_logical_op__fn_unit),
- .\logical_op__fn_unit$3 (\output_logical_op__fn_unit$51 ),
+ .\logical_op__fn_unit$3 (\output_logical_op__fn_unit$53 ),
.logical_op__imm_data__data(output_logical_op__imm_data__data),
- .\logical_op__imm_data__data$4 (\output_logical_op__imm_data__data$52 ),
+ .\logical_op__imm_data__data$4 (\output_logical_op__imm_data__data$54 ),
.logical_op__imm_data__ok(output_logical_op__imm_data__ok),
- .\logical_op__imm_data__ok$5 (\output_logical_op__imm_data__ok$53 ),
+ .\logical_op__imm_data__ok$5 (\output_logical_op__imm_data__ok$55 ),
.logical_op__input_carry(output_logical_op__input_carry),
- .\logical_op__input_carry$12 (\output_logical_op__input_carry$60 ),
+ .\logical_op__input_carry$12 (\output_logical_op__input_carry$62 ),
.logical_op__insn(output_logical_op__insn),
- .\logical_op__insn$19 (\output_logical_op__insn$67 ),
+ .\logical_op__insn$19 (\output_logical_op__insn$69 ),
.logical_op__insn_type(output_logical_op__insn_type),
- .\logical_op__insn_type$2 (\output_logical_op__insn_type$50 ),
+ .\logical_op__insn_type$2 (\output_logical_op__insn_type$52 ),
.logical_op__invert_in(output_logical_op__invert_in),
- .\logical_op__invert_in$10 (\output_logical_op__invert_in$58 ),
+ .\logical_op__invert_in$10 (\output_logical_op__invert_in$60 ),
.logical_op__invert_out(output_logical_op__invert_out),
- .\logical_op__invert_out$13 (\output_logical_op__invert_out$61 ),
+ .\logical_op__invert_out$13 (\output_logical_op__invert_out$63 ),
.logical_op__is_32bit(output_logical_op__is_32bit),
- .\logical_op__is_32bit$16 (\output_logical_op__is_32bit$64 ),
+ .\logical_op__is_32bit$16 (\output_logical_op__is_32bit$66 ),
.logical_op__is_signed(output_logical_op__is_signed),
- .\logical_op__is_signed$17 (\output_logical_op__is_signed$65 ),
+ .\logical_op__is_signed$17 (\output_logical_op__is_signed$67 ),
.logical_op__oe__oe(output_logical_op__oe__oe),
- .\logical_op__oe__oe$8 (\output_logical_op__oe__oe$56 ),
+ .\logical_op__oe__oe$8 (\output_logical_op__oe__oe$58 ),
.logical_op__oe__ok(output_logical_op__oe__ok),
- .\logical_op__oe__ok$9 (\output_logical_op__oe__ok$57 ),
+ .\logical_op__oe__ok$9 (\output_logical_op__oe__ok$59 ),
.logical_op__output_carry(output_logical_op__output_carry),
- .\logical_op__output_carry$15 (\output_logical_op__output_carry$63 ),
+ .\logical_op__output_carry$15 (\output_logical_op__output_carry$65 ),
.logical_op__rc__ok(output_logical_op__rc__ok),
- .\logical_op__rc__ok$7 (\output_logical_op__rc__ok$55 ),
+ .\logical_op__rc__ok$7 (\output_logical_op__rc__ok$57 ),
.logical_op__rc__rc(output_logical_op__rc__rc),
- .\logical_op__rc__rc$6 (\output_logical_op__rc__rc$54 ),
+ .\logical_op__rc__rc$6 (\output_logical_op__rc__rc$56 ),
+ .logical_op__sv_ldstmode(output_logical_op__sv_ldstmode),
+ .\logical_op__sv_ldstmode$23 (\output_logical_op__sv_ldstmode$73 ),
.logical_op__sv_pred_dz(output_logical_op__sv_pred_dz),
- .\logical_op__sv_pred_dz$21 (\output_logical_op__sv_pred_dz$69 ),
+ .\logical_op__sv_pred_dz$21 (\output_logical_op__sv_pred_dz$71 ),
.logical_op__sv_pred_sz(output_logical_op__sv_pred_sz),
- .\logical_op__sv_pred_sz$20 (\output_logical_op__sv_pred_sz$68 ),
+ .\logical_op__sv_pred_sz$20 (\output_logical_op__sv_pred_sz$70 ),
.logical_op__sv_saturate(output_logical_op__sv_saturate),
- .\logical_op__sv_saturate$22 (\output_logical_op__sv_saturate$70 ),
+ .\logical_op__sv_saturate$22 (\output_logical_op__sv_saturate$72 ),
.logical_op__write_cr0(output_logical_op__write_cr0),
- .\logical_op__write_cr0$14 (\output_logical_op__write_cr0$62 ),
+ .\logical_op__write_cr0$14 (\output_logical_op__write_cr0$64 ),
.logical_op__zero_a(output_logical_op__zero_a),
- .\logical_op__zero_a$11 (\output_logical_op__zero_a$59 ),
+ .\logical_op__zero_a$11 (\output_logical_op__zero_a$61 ),
.muxid(output_muxid),
- .\muxid$1 (\output_muxid$49 ),
+ .\muxid$1 (\output_muxid$51 ),
.o(output_o),
- .\o$24 (\output_o$72 ),
+ .\o$25 (\output_o$75 ),
.o_ok(output_o_ok),
- .\o_ok$25 (\output_o_ok$73 ),
+ .\o_ok$26 (\output_o_ok$76 ),
.xer_ov(output_xer_ov),
- .\xer_ov$27 (\output_xer_ov$75 ),
+ .\xer_ov$28 (\output_xer_ov$78 ),
.xer_ov_ok(output_xer_ov_ok),
.xer_so(output_xer_so),
- .\xer_so$28 (\output_xer_so$76 ),
+ .\xer_so$29 (\output_xer_so$79 ),
.xer_so_ok(output_xer_so_ok)
);
output_stage output_stage (
.dividend_neg(output_stage_dividend_neg),
.divisor_neg(output_stage_divisor_neg),
.logical_op__SV_Ptype(output_stage_logical_op__SV_Ptype),
- .\logical_op__SV_Ptype$23 (\output_stage_logical_op__SV_Ptype$47 ),
+ .\logical_op__SV_Ptype$24 (\output_stage_logical_op__SV_Ptype$49 ),
.logical_op__data_len(output_stage_logical_op__data_len),
- .\logical_op__data_len$18 (\output_stage_logical_op__data_len$42 ),
+ .\logical_op__data_len$18 (\output_stage_logical_op__data_len$43 ),
.logical_op__fn_unit(output_stage_logical_op__fn_unit),
- .\logical_op__fn_unit$3 (\output_stage_logical_op__fn_unit$27 ),
+ .\logical_op__fn_unit$3 (\output_stage_logical_op__fn_unit$28 ),
.logical_op__imm_data__data(output_stage_logical_op__imm_data__data),
- .\logical_op__imm_data__data$4 (\output_stage_logical_op__imm_data__data$28 ),
+ .\logical_op__imm_data__data$4 (\output_stage_logical_op__imm_data__data$29 ),
.logical_op__imm_data__ok(output_stage_logical_op__imm_data__ok),
- .\logical_op__imm_data__ok$5 (\output_stage_logical_op__imm_data__ok$29 ),
+ .\logical_op__imm_data__ok$5 (\output_stage_logical_op__imm_data__ok$30 ),
.logical_op__input_carry(output_stage_logical_op__input_carry),
- .\logical_op__input_carry$12 (\output_stage_logical_op__input_carry$36 ),
+ .\logical_op__input_carry$12 (\output_stage_logical_op__input_carry$37 ),
.logical_op__insn(output_stage_logical_op__insn),
- .\logical_op__insn$19 (\output_stage_logical_op__insn$43 ),
+ .\logical_op__insn$19 (\output_stage_logical_op__insn$44 ),
.logical_op__insn_type(output_stage_logical_op__insn_type),
- .\logical_op__insn_type$2 (\output_stage_logical_op__insn_type$26 ),
+ .\logical_op__insn_type$2 (\output_stage_logical_op__insn_type$27 ),
.logical_op__invert_in(output_stage_logical_op__invert_in),
- .\logical_op__invert_in$10 (\output_stage_logical_op__invert_in$34 ),
+ .\logical_op__invert_in$10 (\output_stage_logical_op__invert_in$35 ),
.logical_op__invert_out(output_stage_logical_op__invert_out),
- .\logical_op__invert_out$13 (\output_stage_logical_op__invert_out$37 ),
+ .\logical_op__invert_out$13 (\output_stage_logical_op__invert_out$38 ),
.logical_op__is_32bit(output_stage_logical_op__is_32bit),
- .\logical_op__is_32bit$16 (\output_stage_logical_op__is_32bit$40 ),
+ .\logical_op__is_32bit$16 (\output_stage_logical_op__is_32bit$41 ),
.logical_op__is_signed(output_stage_logical_op__is_signed),
- .\logical_op__is_signed$17 (\output_stage_logical_op__is_signed$41 ),
+ .\logical_op__is_signed$17 (\output_stage_logical_op__is_signed$42 ),
.logical_op__oe__oe(output_stage_logical_op__oe__oe),
- .\logical_op__oe__oe$8 (\output_stage_logical_op__oe__oe$32 ),
+ .\logical_op__oe__oe$8 (\output_stage_logical_op__oe__oe$33 ),
.logical_op__oe__ok(output_stage_logical_op__oe__ok),
- .\logical_op__oe__ok$9 (\output_stage_logical_op__oe__ok$33 ),
+ .\logical_op__oe__ok$9 (\output_stage_logical_op__oe__ok$34 ),
.logical_op__output_carry(output_stage_logical_op__output_carry),
- .\logical_op__output_carry$15 (\output_stage_logical_op__output_carry$39 ),
+ .\logical_op__output_carry$15 (\output_stage_logical_op__output_carry$40 ),
.logical_op__rc__ok(output_stage_logical_op__rc__ok),
- .\logical_op__rc__ok$7 (\output_stage_logical_op__rc__ok$31 ),
+ .\logical_op__rc__ok$7 (\output_stage_logical_op__rc__ok$32 ),
.logical_op__rc__rc(output_stage_logical_op__rc__rc),
- .\logical_op__rc__rc$6 (\output_stage_logical_op__rc__rc$30 ),
+ .\logical_op__rc__rc$6 (\output_stage_logical_op__rc__rc$31 ),
+ .logical_op__sv_ldstmode(output_stage_logical_op__sv_ldstmode),
+ .\logical_op__sv_ldstmode$23 (\output_stage_logical_op__sv_ldstmode$48 ),
.logical_op__sv_pred_dz(output_stage_logical_op__sv_pred_dz),
- .\logical_op__sv_pred_dz$21 (\output_stage_logical_op__sv_pred_dz$45 ),
+ .\logical_op__sv_pred_dz$21 (\output_stage_logical_op__sv_pred_dz$46 ),
.logical_op__sv_pred_sz(output_stage_logical_op__sv_pred_sz),
- .\logical_op__sv_pred_sz$20 (\output_stage_logical_op__sv_pred_sz$44 ),
+ .\logical_op__sv_pred_sz$20 (\output_stage_logical_op__sv_pred_sz$45 ),
.logical_op__sv_saturate(output_stage_logical_op__sv_saturate),
- .\logical_op__sv_saturate$22 (\output_stage_logical_op__sv_saturate$46 ),
+ .\logical_op__sv_saturate$22 (\output_stage_logical_op__sv_saturate$47 ),
.logical_op__write_cr0(output_stage_logical_op__write_cr0),
- .\logical_op__write_cr0$14 (\output_stage_logical_op__write_cr0$38 ),
+ .\logical_op__write_cr0$14 (\output_stage_logical_op__write_cr0$39 ),
.logical_op__zero_a(output_stage_logical_op__zero_a),
- .\logical_op__zero_a$11 (\output_stage_logical_op__zero_a$35 ),
+ .\logical_op__zero_a$11 (\output_stage_logical_op__zero_a$36 ),
.muxid(output_stage_muxid),
- .\muxid$1 (\output_stage_muxid$25 ),
+ .\muxid$1 (\output_stage_muxid$26 ),
.o(output_stage_o),
.o_ok(output_stage_o_ok),
.quotient_root(output_stage_quotient_root),
.xer_ov(output_stage_xer_ov),
.xer_ov_ok(output_stage_xer_ov_ok),
.xer_so(output_stage_xer_so),
- .\xer_so$24 (\output_stage_xer_so$48 )
+ .\xer_so$25 (\output_stage_xer_so$50 )
);
\p$81 p (
.p_ready_o(p_ready_o),
.p_valid_i(p_valid_i)
);
+ always @* begin
+ if (\initial ) begin end
+ \r_busy$next = r_busy;
+ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
+ casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
+ /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
+ 2'b?1:
+ \r_busy$next = 1'h1;
+ /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
+ 2'b1?:
+ \r_busy$next = 1'h0;
+ endcase
+ (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
+ casez (coresync_rst)
+ 1'h1:
+ \r_busy$next = 1'h0;
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ \muxid$1$next = \muxid$1 ;
+ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
+ casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
+ /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
+ 2'b?1:
+ \muxid$1$next = \muxid$91 ;
+ /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
+ 2'b1?:
+ \muxid$1$next = \muxid$91 ;
+ endcase
+ end
always @* begin
if (\initial ) begin end
\logical_op__insn_type$2$next = \logical_op__insn_type$2 ;
\logical_op__sv_pred_sz$20$next = \logical_op__sv_pred_sz$20 ;
\logical_op__sv_pred_dz$21$next = \logical_op__sv_pred_dz$21 ;
\logical_op__sv_saturate$22$next = \logical_op__sv_saturate$22 ;
- \logical_op__SV_Ptype$23$next = \logical_op__SV_Ptype$23 ;
+ \logical_op__sv_ldstmode$23$next = \logical_op__sv_ldstmode$23 ;
+ \logical_op__SV_Ptype$24$next = \logical_op__SV_Ptype$24 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \logical_op__SV_Ptype$23$next , \logical_op__sv_saturate$22$next , \logical_op__sv_pred_dz$21$next , \logical_op__sv_pred_sz$20$next , \logical_op__insn$19$next , \logical_op__data_len$18$next , \logical_op__is_signed$17$next , \logical_op__is_32bit$16$next , \logical_op__output_carry$15$next , \logical_op__write_cr0$14$next , \logical_op__invert_out$13$next , \logical_op__input_carry$12$next , \logical_op__zero_a$11$next , \logical_op__invert_in$10$next , \logical_op__oe__ok$9$next , \logical_op__oe__oe$8$next , \logical_op__rc__ok$7$next , \logical_op__rc__rc$6$next , \logical_op__imm_data__ok$5$next , \logical_op__imm_data__data$4$next , \logical_op__fn_unit$3$next , \logical_op__insn_type$2$next } = { \logical_op__SV_Ptype$110 , \logical_op__sv_saturate$109 , \logical_op__sv_pred_dz$108 , \logical_op__sv_pred_sz$107 , \logical_op__insn$106 , \logical_op__data_len$105 , \logical_op__is_signed$104 , \logical_op__is_32bit$103 , \logical_op__output_carry$102 , \logical_op__write_cr0$101 , \logical_op__invert_out$100 , \logical_op__input_carry$99 , \logical_op__zero_a$98 , \logical_op__invert_in$97 , \logical_op__oe__ok$96 , \logical_op__oe__oe$95 , \logical_op__rc__ok$94 , \logical_op__rc__rc$93 , \logical_op__imm_data__ok$92 , \logical_op__imm_data__data$91 , \logical_op__fn_unit$90 , \logical_op__insn_type$89 };
+ { \logical_op__SV_Ptype$24$next , \logical_op__sv_ldstmode$23$next , \logical_op__sv_saturate$22$next , \logical_op__sv_pred_dz$21$next , \logical_op__sv_pred_sz$20$next , \logical_op__insn$19$next , \logical_op__data_len$18$next , \logical_op__is_signed$17$next , \logical_op__is_32bit$16$next , \logical_op__output_carry$15$next , \logical_op__write_cr0$14$next , \logical_op__invert_out$13$next , \logical_op__input_carry$12$next , \logical_op__zero_a$11$next , \logical_op__invert_in$10$next , \logical_op__oe__ok$9$next , \logical_op__oe__oe$8$next , \logical_op__rc__ok$7$next , \logical_op__rc__rc$6$next , \logical_op__imm_data__ok$5$next , \logical_op__imm_data__data$4$next , \logical_op__fn_unit$3$next , \logical_op__insn_type$2$next } = { \logical_op__SV_Ptype$114 , \logical_op__sv_ldstmode$113 , \logical_op__sv_saturate$112 , \logical_op__sv_pred_dz$111 , \logical_op__sv_pred_sz$110 , \logical_op__insn$109 , \logical_op__data_len$108 , \logical_op__is_signed$107 , \logical_op__is_32bit$106 , \logical_op__output_carry$105 , \logical_op__write_cr0$104 , \logical_op__invert_out$103 , \logical_op__input_carry$102 , \logical_op__zero_a$101 , \logical_op__invert_in$100 , \logical_op__oe__ok$99 , \logical_op__oe__oe$98 , \logical_op__rc__ok$97 , \logical_op__rc__rc$96 , \logical_op__imm_data__ok$95 , \logical_op__imm_data__data$94 , \logical_op__fn_unit$93 , \logical_op__insn_type$92 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \logical_op__SV_Ptype$23$next , \logical_op__sv_saturate$22$next , \logical_op__sv_pred_dz$21$next , \logical_op__sv_pred_sz$20$next , \logical_op__insn$19$next , \logical_op__data_len$18$next , \logical_op__is_signed$17$next , \logical_op__is_32bit$16$next , \logical_op__output_carry$15$next , \logical_op__write_cr0$14$next , \logical_op__invert_out$13$next , \logical_op__input_carry$12$next , \logical_op__zero_a$11$next , \logical_op__invert_in$10$next , \logical_op__oe__ok$9$next , \logical_op__oe__oe$8$next , \logical_op__rc__ok$7$next , \logical_op__rc__rc$6$next , \logical_op__imm_data__ok$5$next , \logical_op__imm_data__data$4$next , \logical_op__fn_unit$3$next , \logical_op__insn_type$2$next } = { \logical_op__SV_Ptype$110 , \logical_op__sv_saturate$109 , \logical_op__sv_pred_dz$108 , \logical_op__sv_pred_sz$107 , \logical_op__insn$106 , \logical_op__data_len$105 , \logical_op__is_signed$104 , \logical_op__is_32bit$103 , \logical_op__output_carry$102 , \logical_op__write_cr0$101 , \logical_op__invert_out$100 , \logical_op__input_carry$99 , \logical_op__zero_a$98 , \logical_op__invert_in$97 , \logical_op__oe__ok$96 , \logical_op__oe__oe$95 , \logical_op__rc__ok$94 , \logical_op__rc__rc$93 , \logical_op__imm_data__ok$92 , \logical_op__imm_data__data$91 , \logical_op__fn_unit$90 , \logical_op__insn_type$89 };
+ { \logical_op__SV_Ptype$24$next , \logical_op__sv_ldstmode$23$next , \logical_op__sv_saturate$22$next , \logical_op__sv_pred_dz$21$next , \logical_op__sv_pred_sz$20$next , \logical_op__insn$19$next , \logical_op__data_len$18$next , \logical_op__is_signed$17$next , \logical_op__is_32bit$16$next , \logical_op__output_carry$15$next , \logical_op__write_cr0$14$next , \logical_op__invert_out$13$next , \logical_op__input_carry$12$next , \logical_op__zero_a$11$next , \logical_op__invert_in$10$next , \logical_op__oe__ok$9$next , \logical_op__oe__oe$8$next , \logical_op__rc__ok$7$next , \logical_op__rc__rc$6$next , \logical_op__imm_data__ok$5$next , \logical_op__imm_data__data$4$next , \logical_op__fn_unit$3$next , \logical_op__insn_type$2$next } = { \logical_op__SV_Ptype$114 , \logical_op__sv_ldstmode$113 , \logical_op__sv_saturate$112 , \logical_op__sv_pred_dz$111 , \logical_op__sv_pred_sz$110 , \logical_op__insn$109 , \logical_op__data_len$108 , \logical_op__is_signed$107 , \logical_op__is_32bit$106 , \logical_op__output_carry$105 , \logical_op__write_cr0$104 , \logical_op__invert_out$103 , \logical_op__input_carry$102 , \logical_op__zero_a$101 , \logical_op__invert_in$100 , \logical_op__oe__ok$99 , \logical_op__oe__oe$98 , \logical_op__rc__ok$97 , \logical_op__rc__rc$96 , \logical_op__imm_data__ok$95 , \logical_op__imm_data__data$94 , \logical_op__fn_unit$93 , \logical_op__insn_type$92 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \o_ok$next , \o$next } = { \o_ok$112 , \o$111 };
+ { \o_ok$next , \o$next } = { \o_ok$116 , \o$115 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \o_ok$next , \o$next } = { \o_ok$112 , \o$111 };
+ { \o_ok$next , \o$next } = { \o_ok$116 , \o$115 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$114 , \cr_a$113 };
+ { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$118 , \cr_a$117 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$114 , \cr_a$113 };
+ { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$118 , \cr_a$117 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$116 , \xer_ov$115 };
+ { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$120 , \xer_ov$119 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$116 , \xer_ov$115 };
+ { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$120 , \xer_ov$119 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
end
always @* begin
if (\initial ) begin end
- \xer_so$24$next = \xer_so$24 ;
+ \xer_so$25$next = \xer_so$25 ;
\xer_so_ok$next = xer_so_ok;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \xer_so_ok$next , \xer_so$24$next } = { \xer_so_ok$118 , \xer_so$117 };
+ { \xer_so_ok$next , \xer_so$25$next } = { \xer_so_ok$122 , \xer_so$121 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \xer_so_ok$next , \xer_so$24$next } = { \xer_so_ok$118 , \xer_so$117 };
+ { \xer_so_ok$next , \xer_so$25$next } = { \xer_so_ok$122 , \xer_so$121 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
\xer_so_ok$next = 1'h0;
endcase
end
- always @* begin
- if (\initial ) begin end
- \r_busy$next = r_busy;
- (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
- casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
- /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
- 2'b?1:
- \r_busy$next = 1'h1;
- /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
- 2'b1?:
- \r_busy$next = 1'h0;
- endcase
- (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (coresync_rst)
- 1'h1:
- \r_busy$next = 1'h0;
- endcase
- end
- always @* begin
- if (\initial ) begin end
- \muxid$1$next = \muxid$1 ;
- (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
- casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
- /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
- 2'b?1:
- \muxid$1$next = \muxid$88 ;
- /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
- 2'b1?:
- \muxid$1$next = \muxid$88 ;
- endcase
- end
- assign \cr_a$80 = 4'h0;
- assign \cr_a_ok$81 = 1'h0;
- assign \xer_so_ok$84 = 1'h0;
+ assign \cr_a$83 = 4'h0;
+ assign \cr_a_ok$84 = 1'h0;
+ assign \xer_so_ok$87 = 1'h0;
assign p_ready_o = n_i_rdy_data;
assign n_valid_o = r_busy;
- assign { \xer_so_ok$118 , \xer_so$117 } = { output_xer_so_ok, \output_xer_so$76 };
- assign { \xer_ov_ok$116 , \xer_ov$115 } = { output_xer_ov_ok, \output_xer_ov$75 };
- assign { \cr_a_ok$114 , \cr_a$113 } = { output_cr_a_ok, \output_cr_a$74 };
- assign { \o_ok$112 , \o$111 } = { \output_o_ok$73 , \output_o$72 };
- assign { \logical_op__SV_Ptype$110 , \logical_op__sv_saturate$109 , \logical_op__sv_pred_dz$108 , \logical_op__sv_pred_sz$107 , \logical_op__insn$106 , \logical_op__data_len$105 , \logical_op__is_signed$104 , \logical_op__is_32bit$103 , \logical_op__output_carry$102 , \logical_op__write_cr0$101 , \logical_op__invert_out$100 , \logical_op__input_carry$99 , \logical_op__zero_a$98 , \logical_op__invert_in$97 , \logical_op__oe__ok$96 , \logical_op__oe__oe$95 , \logical_op__rc__ok$94 , \logical_op__rc__rc$93 , \logical_op__imm_data__ok$92 , \logical_op__imm_data__data$91 , \logical_op__fn_unit$90 , \logical_op__insn_type$89 } = { \output_logical_op__SV_Ptype$71 , \output_logical_op__sv_saturate$70 , \output_logical_op__sv_pred_dz$69 , \output_logical_op__sv_pred_sz$68 , \output_logical_op__insn$67 , \output_logical_op__data_len$66 , \output_logical_op__is_signed$65 , \output_logical_op__is_32bit$64 , \output_logical_op__output_carry$63 , \output_logical_op__write_cr0$62 , \output_logical_op__invert_out$61 , \output_logical_op__input_carry$60 , \output_logical_op__zero_a$59 , \output_logical_op__invert_in$58 , \output_logical_op__oe__ok$57 , \output_logical_op__oe__oe$56 , \output_logical_op__rc__ok$55 , \output_logical_op__rc__rc$54 , \output_logical_op__imm_data__ok$53 , \output_logical_op__imm_data__data$52 , \output_logical_op__fn_unit$51 , \output_logical_op__insn_type$50 };
- assign \muxid$88 = \output_muxid$49 ;
- assign p_valid_i_p_ready_o = \$86 ;
+ assign { \xer_so_ok$122 , \xer_so$121 } = { output_xer_so_ok, \output_xer_so$79 };
+ assign { \xer_ov_ok$120 , \xer_ov$119 } = { output_xer_ov_ok, \output_xer_ov$78 };
+ assign { \cr_a_ok$118 , \cr_a$117 } = { output_cr_a_ok, \output_cr_a$77 };
+ assign { \o_ok$116 , \o$115 } = { \output_o_ok$76 , \output_o$75 };
+ assign { \logical_op__SV_Ptype$114 , \logical_op__sv_ldstmode$113 , \logical_op__sv_saturate$112 , \logical_op__sv_pred_dz$111 , \logical_op__sv_pred_sz$110 , \logical_op__insn$109 , \logical_op__data_len$108 , \logical_op__is_signed$107 , \logical_op__is_32bit$106 , \logical_op__output_carry$105 , \logical_op__write_cr0$104 , \logical_op__invert_out$103 , \logical_op__input_carry$102 , \logical_op__zero_a$101 , \logical_op__invert_in$100 , \logical_op__oe__ok$99 , \logical_op__oe__oe$98 , \logical_op__rc__ok$97 , \logical_op__rc__rc$96 , \logical_op__imm_data__ok$95 , \logical_op__imm_data__data$94 , \logical_op__fn_unit$93 , \logical_op__insn_type$92 } = { \output_logical_op__SV_Ptype$74 , \output_logical_op__sv_ldstmode$73 , \output_logical_op__sv_saturate$72 , \output_logical_op__sv_pred_dz$71 , \output_logical_op__sv_pred_sz$70 , \output_logical_op__insn$69 , \output_logical_op__data_len$68 , \output_logical_op__is_signed$67 , \output_logical_op__is_32bit$66 , \output_logical_op__output_carry$65 , \output_logical_op__write_cr0$64 , \output_logical_op__invert_out$63 , \output_logical_op__input_carry$62 , \output_logical_op__zero_a$61 , \output_logical_op__invert_in$60 , \output_logical_op__oe__ok$59 , \output_logical_op__oe__oe$58 , \output_logical_op__rc__ok$57 , \output_logical_op__rc__rc$56 , \output_logical_op__imm_data__ok$55 , \output_logical_op__imm_data__data$54 , \output_logical_op__fn_unit$53 , \output_logical_op__insn_type$52 };
+ assign \muxid$91 = \output_muxid$51 ;
+ assign p_valid_i_p_ready_o = \$89 ;
assign n_i_rdy_data = n_ready_i;
- assign \p_valid_i$85 = p_valid_i;
- assign { \xer_so_ok$83 , output_xer_so } = { 1'h0, \output_stage_xer_so$48 };
- assign { \xer_ov_ok$82 , output_xer_ov } = { output_stage_xer_ov_ok, output_stage_xer_ov };
- assign { \cr_a_ok$79 , output_cr_a } = 5'h00;
+ assign \p_valid_i$88 = p_valid_i;
+ assign { \xer_so_ok$86 , output_xer_so } = { 1'h0, \output_stage_xer_so$50 };
+ assign { \xer_ov_ok$85 , output_xer_ov } = { output_stage_xer_ov_ok, output_stage_xer_ov };
+ assign { \cr_a_ok$82 , output_cr_a } = 5'h00;
assign { output_o_ok, output_o } = { output_stage_o_ok, output_stage_o };
- assign { output_logical_op__SV_Ptype, output_logical_op__sv_saturate, output_logical_op__sv_pred_dz, output_logical_op__sv_pred_sz, output_logical_op__insn, output_logical_op__data_len, output_logical_op__is_signed, output_logical_op__is_32bit, output_logical_op__output_carry, output_logical_op__write_cr0, output_logical_op__invert_out, output_logical_op__input_carry, output_logical_op__zero_a, output_logical_op__invert_in, output_logical_op__oe__ok, output_logical_op__oe__oe, output_logical_op__rc__ok, output_logical_op__rc__rc, output_logical_op__imm_data__ok, output_logical_op__imm_data__data, output_logical_op__fn_unit, output_logical_op__insn_type } = { \output_stage_logical_op__SV_Ptype$47 , \output_stage_logical_op__sv_saturate$46 , \output_stage_logical_op__sv_pred_dz$45 , \output_stage_logical_op__sv_pred_sz$44 , \output_stage_logical_op__insn$43 , \output_stage_logical_op__data_len$42 , \output_stage_logical_op__is_signed$41 , \output_stage_logical_op__is_32bit$40 , \output_stage_logical_op__output_carry$39 , \output_stage_logical_op__write_cr0$38 , \output_stage_logical_op__invert_out$37 , \output_stage_logical_op__input_carry$36 , \output_stage_logical_op__zero_a$35 , \output_stage_logical_op__invert_in$34 , \output_stage_logical_op__oe__ok$33 , \output_stage_logical_op__oe__oe$32 , \output_stage_logical_op__rc__ok$31 , \output_stage_logical_op__rc__rc$30 , \output_stage_logical_op__imm_data__ok$29 , \output_stage_logical_op__imm_data__data$28 , \output_stage_logical_op__fn_unit$27 , \output_stage_logical_op__insn_type$26 };
- assign output_muxid = \output_stage_muxid$25 ;
+ assign { output_logical_op__SV_Ptype, output_logical_op__sv_ldstmode, output_logical_op__sv_saturate, output_logical_op__sv_pred_dz, output_logical_op__sv_pred_sz, output_logical_op__insn, output_logical_op__data_len, output_logical_op__is_signed, output_logical_op__is_32bit, output_logical_op__output_carry, output_logical_op__write_cr0, output_logical_op__invert_out, output_logical_op__input_carry, output_logical_op__zero_a, output_logical_op__invert_in, output_logical_op__oe__ok, output_logical_op__oe__oe, output_logical_op__rc__ok, output_logical_op__rc__rc, output_logical_op__imm_data__ok, output_logical_op__imm_data__data, output_logical_op__fn_unit, output_logical_op__insn_type } = { \output_stage_logical_op__SV_Ptype$49 , \output_stage_logical_op__sv_ldstmode$48 , \output_stage_logical_op__sv_saturate$47 , \output_stage_logical_op__sv_pred_dz$46 , \output_stage_logical_op__sv_pred_sz$45 , \output_stage_logical_op__insn$44 , \output_stage_logical_op__data_len$43 , \output_stage_logical_op__is_signed$42 , \output_stage_logical_op__is_32bit$41 , \output_stage_logical_op__output_carry$40 , \output_stage_logical_op__write_cr0$39 , \output_stage_logical_op__invert_out$38 , \output_stage_logical_op__input_carry$37 , \output_stage_logical_op__zero_a$36 , \output_stage_logical_op__invert_in$35 , \output_stage_logical_op__oe__ok$34 , \output_stage_logical_op__oe__oe$33 , \output_stage_logical_op__rc__ok$32 , \output_stage_logical_op__rc__rc$31 , \output_stage_logical_op__imm_data__ok$30 , \output_stage_logical_op__imm_data__data$29 , \output_stage_logical_op__fn_unit$28 , \output_stage_logical_op__insn_type$27 };
+ assign output_muxid = \output_stage_muxid$26 ;
assign output_stage_remainder = remainder;
assign output_stage_quotient_root = quotient_root;
assign output_stage_div_by_zero = div_by_zero;
assign output_stage_dividend_neg = dividend_neg;
assign output_stage_divisor_neg = divisor_neg;
assign output_stage_xer_so = xer_so;
- assign \rb$78 = rb;
- assign \ra$77 = ra;
- assign { output_stage_logical_op__SV_Ptype, output_stage_logical_op__sv_saturate, output_stage_logical_op__sv_pred_dz, output_stage_logical_op__sv_pred_sz, output_stage_logical_op__insn, output_stage_logical_op__data_len, output_stage_logical_op__is_signed, output_stage_logical_op__is_32bit, output_stage_logical_op__output_carry, output_stage_logical_op__write_cr0, output_stage_logical_op__invert_out, output_stage_logical_op__input_carry, output_stage_logical_op__zero_a, output_stage_logical_op__invert_in, output_stage_logical_op__oe__ok, output_stage_logical_op__oe__oe, output_stage_logical_op__rc__ok, output_stage_logical_op__rc__rc, output_stage_logical_op__imm_data__ok, output_stage_logical_op__imm_data__data, output_stage_logical_op__fn_unit, output_stage_logical_op__insn_type } = { logical_op__SV_Ptype, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
+ assign \rb$81 = rb;
+ assign \ra$80 = ra;
+ assign { output_stage_logical_op__SV_Ptype, output_stage_logical_op__sv_ldstmode, output_stage_logical_op__sv_saturate, output_stage_logical_op__sv_pred_dz, output_stage_logical_op__sv_pred_sz, output_stage_logical_op__insn, output_stage_logical_op__data_len, output_stage_logical_op__is_signed, output_stage_logical_op__is_32bit, output_stage_logical_op__output_carry, output_stage_logical_op__write_cr0, output_stage_logical_op__invert_out, output_stage_logical_op__input_carry, output_stage_logical_op__zero_a, output_stage_logical_op__invert_in, output_stage_logical_op__oe__ok, output_stage_logical_op__oe__oe, output_stage_logical_op__rc__ok, output_stage_logical_op__rc__rc, output_stage_logical_op__imm_data__ok, output_stage_logical_op__imm_data__data, output_stage_logical_op__fn_unit, output_stage_logical_op__insn_type } = { logical_op__SV_Ptype, logical_op__sv_ldstmode, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
assign output_stage_muxid = muxid;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0" *)
(* generator = "nMigen" *)
-module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, ra, rb, xer_so, divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, dividend, divisor_radicand, operation, n_valid_o, n_ready_i, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__SV_Ptype$23 , \ra$24 , \rb$25 , \xer_so$26 , \divisor_neg$27 , \dividend_neg$28 , \dive_abs_ov32$29 , \dive_abs_ov64$30 , \div_by_zero$31 , quotient_root, remainder, coresync_clk);
+module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__sv_ldstmode, logical_op__SV_Ptype, ra, rb, xer_so, divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, dividend, divisor_radicand, operation, n_valid_o, n_ready_i, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__sv_ldstmode$23 , \logical_op__SV_Ptype$24 , \ra$25 , \rb$26 , \xer_so$27 , \divisor_neg$28 , \dividend_neg$29 , \dive_abs_ov32$30 , \dive_abs_ov64$31 , \div_by_zero$32 , quotient_root, remainder, coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" *)
- wire [191:0] \$63 ;
+ wire [191:0] \$65 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" *)
- wire [190:0] \$64 ;
+ wire [190:0] \$66 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" *)
- wire \$67 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" *)
wire \$69 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" *)
wire \$71 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" *)
+ wire \$73 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" *)
- wire \$74 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ wire \$76 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
input div_by_zero;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
- output \div_by_zero$31 ;
+ output \div_by_zero$32 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
- reg \div_by_zero$62 = 1'h0;
+ reg \div_by_zero$64 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
- reg \div_by_zero$62$next ;
+ reg \div_by_zero$64$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:89" *)
wire [127:0] div_state_init_dividend;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
input dive_abs_ov32;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
- output \dive_abs_ov32$29 ;
+ output \dive_abs_ov32$30 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
- reg \dive_abs_ov32$60 = 1'h0;
+ reg \dive_abs_ov32$62 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
- reg \dive_abs_ov32$60$next ;
+ reg \dive_abs_ov32$62$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *)
input dive_abs_ov64;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *)
- output \dive_abs_ov64$30 ;
+ output \dive_abs_ov64$31 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *)
- reg \dive_abs_ov64$61 = 1'h0;
+ reg \dive_abs_ov64$63 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *)
- reg \dive_abs_ov64$61$next ;
+ reg \dive_abs_ov64$63$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *)
input [127:0] dividend;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *)
- reg [127:0] \dividend$76 = 128'h00000000000000000000000000000000;
+ reg [127:0] \dividend$78 = 128'h00000000000000000000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *)
- reg [127:0] \dividend$76$next ;
+ reg [127:0] \dividend$78$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *)
input dividend_neg;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *)
- output \dividend_neg$28 ;
+ output \dividend_neg$29 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *)
- reg \dividend_neg$59 = 1'h0;
+ reg \dividend_neg$61 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *)
- reg \dividend_neg$59$next ;
+ reg \dividend_neg$61$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *)
input divisor_neg;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *)
- output \divisor_neg$27 ;
+ output \divisor_neg$28 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *)
- reg \divisor_neg$58 = 1'h0;
+ reg \divisor_neg$60 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *)
- reg \divisor_neg$58$next ;
+ reg \divisor_neg$60$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *)
input [63:0] divisor_radicand;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *)
- reg [63:0] \divisor_radicand$73 = 64'h0000000000000000;
+ reg [63:0] \divisor_radicand$75 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *)
- reg [63:0] \divisor_radicand$73$next ;
+ reg [63:0] \divisor_radicand$75$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" *)
reg empty = 1'h1;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \logical_op__SV_Ptype$23 ;
+ output [1:0] \logical_op__SV_Ptype$24 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [1:0] \logical_op__SV_Ptype$54 = 2'h0;
+ reg [1:0] \logical_op__SV_Ptype$56 = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [1:0] \logical_op__SV_Ptype$54$next ;
+ reg [1:0] \logical_op__SV_Ptype$56$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [3:0] logical_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output [3:0] \logical_op__data_len$18 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [3:0] \logical_op__data_len$49 = 4'h0;
+ reg [3:0] \logical_op__data_len$50 = 4'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [3:0] \logical_op__data_len$49$next ;
+ reg [3:0] \logical_op__data_len$50$next ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [14:0] \logical_op__fn_unit$34 = 15'h0000;
+ reg [14:0] \logical_op__fn_unit$35 = 15'h0000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [14:0] \logical_op__fn_unit$34$next ;
+ reg [14:0] \logical_op__fn_unit$35$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] logical_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [63:0] \logical_op__imm_data__data$35 = 64'h0000000000000000;
+ reg [63:0] \logical_op__imm_data__data$36 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [63:0] \logical_op__imm_data__data$35$next ;
+ reg [63:0] \logical_op__imm_data__data$36$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output [63:0] \logical_op__imm_data__data$4 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__imm_data__ok$36 = 1'h0;
+ reg \logical_op__imm_data__ok$37 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__imm_data__ok$36$next ;
+ reg \logical_op__imm_data__ok$37$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__imm_data__ok$5 ;
(* enum_base_type = "CryIn" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [1:0] \logical_op__input_carry$43 = 2'h0;
+ reg [1:0] \logical_op__input_carry$44 = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [1:0] \logical_op__input_carry$43$next ;
+ reg [1:0] \logical_op__input_carry$44$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [31:0] logical_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output [31:0] \logical_op__insn$19 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [31:0] \logical_op__insn$50 = 32'd0;
+ reg [31:0] \logical_op__insn$51 = 32'd0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [31:0] \logical_op__insn$50$next ;
+ reg [31:0] \logical_op__insn$51$next ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [6:0] \logical_op__insn_type$33 = 7'h00;
+ reg [6:0] \logical_op__insn_type$34 = 7'h00;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [6:0] \logical_op__insn_type$33$next ;
+ reg [6:0] \logical_op__insn_type$34$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__invert_in$10 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__invert_in$41 = 1'h0;
+ reg \logical_op__invert_in$42 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__invert_in$41$next ;
+ reg \logical_op__invert_in$42$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__invert_out;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__invert_out$13 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__invert_out$44 = 1'h0;
+ reg \logical_op__invert_out$45 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__invert_out$44$next ;
+ reg \logical_op__invert_out$45$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__is_32bit$16 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__is_32bit$47 = 1'h0;
+ reg \logical_op__is_32bit$48 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__is_32bit$47$next ;
+ reg \logical_op__is_32bit$48$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__is_signed$17 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__is_signed$48 = 1'h0;
+ reg \logical_op__is_signed$49 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__is_signed$48$next ;
+ reg \logical_op__is_signed$49$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__oe__oe$39 = 1'h0;
+ reg \logical_op__oe__oe$40 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__oe__oe$39$next ;
+ reg \logical_op__oe__oe$40$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__oe__oe$8 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__oe__ok$40 = 1'h0;
+ reg \logical_op__oe__ok$41 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__oe__ok$40$next ;
+ reg \logical_op__oe__ok$41$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__oe__ok$9 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__output_carry$15 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__output_carry$46 = 1'h0;
+ reg \logical_op__output_carry$47 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__output_carry$46$next ;
+ reg \logical_op__output_carry$47$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__rc__ok$38 = 1'h0;
+ reg \logical_op__rc__ok$39 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__rc__ok$38$next ;
+ reg \logical_op__rc__ok$39$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__rc__ok$7 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__rc__rc$37 = 1'h0;
+ reg \logical_op__rc__rc$38 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__rc__rc$37$next ;
+ reg \logical_op__rc__rc$38$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__rc__rc$6 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] logical_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \logical_op__sv_ldstmode$23 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \logical_op__sv_ldstmode$55 = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \logical_op__sv_ldstmode$55$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__sv_pred_dz$21 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__sv_pred_dz$52 = 1'h0;
+ reg \logical_op__sv_pred_dz$53 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__sv_pred_dz$52$next ;
+ reg \logical_op__sv_pred_dz$53$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__sv_pred_sz$20 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__sv_pred_sz$51 = 1'h0;
+ reg \logical_op__sv_pred_sz$52 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__sv_pred_sz$51$next ;
+ reg \logical_op__sv_pred_sz$52$next ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [1:0] \logical_op__sv_saturate$53 = 2'h0;
+ reg [1:0] \logical_op__sv_saturate$54 = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg [1:0] \logical_op__sv_saturate$53$next ;
+ reg [1:0] \logical_op__sv_saturate$54$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__write_cr0$14 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__write_cr0$45 = 1'h0;
+ reg \logical_op__write_cr0$46 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__write_cr0$45$next ;
+ reg \logical_op__write_cr0$46$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__zero_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__zero_a$11 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__zero_a$42 = 1'h0;
+ reg \logical_op__zero_a$43 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- reg \logical_op__zero_a$42$next ;
+ reg \logical_op__zero_a$43$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
input [1:0] muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
output [1:0] \muxid$1 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- reg [1:0] \muxid$32 = 2'h0;
+ reg [1:0] \muxid$33 = 2'h0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- reg [1:0] \muxid$32$next ;
+ reg [1:0] \muxid$33$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
input n_ready_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *)
input [1:0] operation;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *)
- reg [1:0] \operation$77 = 2'h0;
+ reg [1:0] \operation$79 = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *)
- reg [1:0] \operation$77$next ;
+ reg [1:0] \operation$79$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
output p_ready_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] ra;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output [63:0] \ra$24 ;
+ output [63:0] \ra$25 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- reg [63:0] \ra$55 = 64'h0000000000000000;
+ reg [63:0] \ra$57 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- reg [63:0] \ra$55$next ;
+ reg [63:0] \ra$57$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] rb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output [63:0] \rb$25 ;
+ output [63:0] \rb$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- reg [63:0] \rb$56 = 64'h0000000000000000;
+ reg [63:0] \rb$58 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- reg [63:0] \rb$56$next ;
+ reg [63:0] \rb$58$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" *)
output [191:0] remainder;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input xer_so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output \xer_so$26 ;
+ output \xer_so$27 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- reg \xer_so$57 = 1'h0;
+ reg \xer_so$59 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- reg \xer_so$57$next ;
- assign \$64 = div_state_next_o_dividend_quotient[127:64] <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" *) 7'h40;
- assign \$63 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" *) \$64 ;
- assign \$67 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" *) empty;
- assign \$69 = saved_state_q_bits_known >= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" *) 6'h3f;
- assign \$71 = \$67 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" *) \$69 ;
- assign \$74 = n_ready_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" *) n_valid_o;
+ reg \xer_so$59$next ;
+ assign \$66 = div_state_next_o_dividend_quotient[127:64] <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" *) 7'h40;
+ assign \$65 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" *) \$66 ;
+ assign \$69 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" *) empty;
+ assign \$71 = saved_state_q_bits_known >= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" *) 6'h3f;
+ assign \$73 = \$69 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" *) \$71 ;
+ assign \$76 = n_ready_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" *) n_valid_o;
always @(posedge coresync_clk)
- \operation$77 <= \operation$77$next ;
+ \operation$79 <= \operation$79$next ;
always @(posedge coresync_clk)
- \divisor_radicand$73 <= \divisor_radicand$73$next ;
+ \divisor_radicand$75 <= \divisor_radicand$75$next ;
always @(posedge coresync_clk)
- \dividend$76 <= \dividend$76$next ;
+ \dividend$78 <= \dividend$78$next ;
always @(posedge coresync_clk)
- \div_by_zero$62 <= \div_by_zero$62$next ;
+ \div_by_zero$64 <= \div_by_zero$64$next ;
always @(posedge coresync_clk)
- \dive_abs_ov64$61 <= \dive_abs_ov64$61$next ;
+ \dive_abs_ov64$63 <= \dive_abs_ov64$63$next ;
always @(posedge coresync_clk)
- \dive_abs_ov32$60 <= \dive_abs_ov32$60$next ;
+ \dive_abs_ov32$62 <= \dive_abs_ov32$62$next ;
always @(posedge coresync_clk)
- \dividend_neg$59 <= \dividend_neg$59$next ;
+ \dividend_neg$61 <= \dividend_neg$61$next ;
always @(posedge coresync_clk)
- \divisor_neg$58 <= \divisor_neg$58$next ;
+ \divisor_neg$60 <= \divisor_neg$60$next ;
always @(posedge coresync_clk)
- \xer_so$57 <= \xer_so$57$next ;
+ \xer_so$59 <= \xer_so$59$next ;
always @(posedge coresync_clk)
- \rb$56 <= \rb$56$next ;
+ \rb$58 <= \rb$58$next ;
always @(posedge coresync_clk)
- \ra$55 <= \ra$55$next ;
+ \ra$57 <= \ra$57$next ;
always @(posedge coresync_clk)
- \logical_op__insn_type$33 <= \logical_op__insn_type$33$next ;
+ \logical_op__insn_type$34 <= \logical_op__insn_type$34$next ;
always @(posedge coresync_clk)
- \logical_op__fn_unit$34 <= \logical_op__fn_unit$34$next ;
+ \logical_op__fn_unit$35 <= \logical_op__fn_unit$35$next ;
always @(posedge coresync_clk)
- \logical_op__imm_data__data$35 <= \logical_op__imm_data__data$35$next ;
+ \logical_op__imm_data__data$36 <= \logical_op__imm_data__data$36$next ;
always @(posedge coresync_clk)
- \logical_op__imm_data__ok$36 <= \logical_op__imm_data__ok$36$next ;
+ \logical_op__imm_data__ok$37 <= \logical_op__imm_data__ok$37$next ;
always @(posedge coresync_clk)
- \logical_op__rc__rc$37 <= \logical_op__rc__rc$37$next ;
+ \logical_op__rc__rc$38 <= \logical_op__rc__rc$38$next ;
always @(posedge coresync_clk)
- \logical_op__rc__ok$38 <= \logical_op__rc__ok$38$next ;
+ \logical_op__rc__ok$39 <= \logical_op__rc__ok$39$next ;
always @(posedge coresync_clk)
- \logical_op__oe__oe$39 <= \logical_op__oe__oe$39$next ;
+ \logical_op__oe__oe$40 <= \logical_op__oe__oe$40$next ;
always @(posedge coresync_clk)
- \logical_op__oe__ok$40 <= \logical_op__oe__ok$40$next ;
+ \logical_op__oe__ok$41 <= \logical_op__oe__ok$41$next ;
always @(posedge coresync_clk)
- \logical_op__invert_in$41 <= \logical_op__invert_in$41$next ;
+ \logical_op__invert_in$42 <= \logical_op__invert_in$42$next ;
always @(posedge coresync_clk)
- \logical_op__zero_a$42 <= \logical_op__zero_a$42$next ;
+ \logical_op__zero_a$43 <= \logical_op__zero_a$43$next ;
always @(posedge coresync_clk)
- \logical_op__input_carry$43 <= \logical_op__input_carry$43$next ;
+ \logical_op__input_carry$44 <= \logical_op__input_carry$44$next ;
always @(posedge coresync_clk)
- \logical_op__invert_out$44 <= \logical_op__invert_out$44$next ;
+ \logical_op__invert_out$45 <= \logical_op__invert_out$45$next ;
always @(posedge coresync_clk)
- \logical_op__write_cr0$45 <= \logical_op__write_cr0$45$next ;
+ \logical_op__write_cr0$46 <= \logical_op__write_cr0$46$next ;
always @(posedge coresync_clk)
- \logical_op__output_carry$46 <= \logical_op__output_carry$46$next ;
+ \logical_op__output_carry$47 <= \logical_op__output_carry$47$next ;
always @(posedge coresync_clk)
- \logical_op__is_32bit$47 <= \logical_op__is_32bit$47$next ;
+ \logical_op__is_32bit$48 <= \logical_op__is_32bit$48$next ;
always @(posedge coresync_clk)
- \logical_op__is_signed$48 <= \logical_op__is_signed$48$next ;
+ \logical_op__is_signed$49 <= \logical_op__is_signed$49$next ;
always @(posedge coresync_clk)
- \logical_op__data_len$49 <= \logical_op__data_len$49$next ;
+ \logical_op__data_len$50 <= \logical_op__data_len$50$next ;
always @(posedge coresync_clk)
- \logical_op__insn$50 <= \logical_op__insn$50$next ;
+ \logical_op__insn$51 <= \logical_op__insn$51$next ;
always @(posedge coresync_clk)
- \logical_op__sv_pred_sz$51 <= \logical_op__sv_pred_sz$51$next ;
+ \logical_op__sv_pred_sz$52 <= \logical_op__sv_pred_sz$52$next ;
always @(posedge coresync_clk)
- \logical_op__sv_pred_dz$52 <= \logical_op__sv_pred_dz$52$next ;
+ \logical_op__sv_pred_dz$53 <= \logical_op__sv_pred_dz$53$next ;
always @(posedge coresync_clk)
- \logical_op__sv_saturate$53 <= \logical_op__sv_saturate$53$next ;
+ \logical_op__sv_saturate$54 <= \logical_op__sv_saturate$54$next ;
always @(posedge coresync_clk)
- \logical_op__SV_Ptype$54 <= \logical_op__SV_Ptype$54$next ;
+ \logical_op__sv_ldstmode$55 <= \logical_op__sv_ldstmode$55$next ;
always @(posedge coresync_clk)
- \muxid$32 <= \muxid$32$next ;
+ \logical_op__SV_Ptype$56 <= \logical_op__SV_Ptype$56$next ;
+ always @(posedge coresync_clk)
+ \muxid$33 <= \muxid$33$next ;
always @(posedge coresync_clk)
empty <= \empty$next ;
always @(posedge coresync_clk)
div_state_next_divisor = divisor_radicand;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:181" */
default:
- div_state_next_divisor = \divisor_radicand$73 ;
+ div_state_next_divisor = \divisor_radicand$75 ;
endcase
end
always @* begin
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:181" */
default:
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" *)
- casez (\$74 )
+ casez (\$76 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" */
1'h1:
\empty$next = 1'h1;
end
always @* begin
if (\initial ) begin end
- \muxid$32$next = \muxid$32 ;
+ \muxid$33$next = \muxid$33 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
casez (empty)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */
casez (p_valid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */
1'h1:
- \muxid$32$next = muxid;
- endcase
- endcase
- end
- always @* begin
- if (\initial ) begin end
- \logical_op__insn_type$33$next = \logical_op__insn_type$33 ;
- \logical_op__fn_unit$34$next = \logical_op__fn_unit$34 ;
- \logical_op__imm_data__data$35$next = \logical_op__imm_data__data$35 ;
- \logical_op__imm_data__ok$36$next = \logical_op__imm_data__ok$36 ;
- \logical_op__rc__rc$37$next = \logical_op__rc__rc$37 ;
- \logical_op__rc__ok$38$next = \logical_op__rc__ok$38 ;
- \logical_op__oe__oe$39$next = \logical_op__oe__oe$39 ;
- \logical_op__oe__ok$40$next = \logical_op__oe__ok$40 ;
- \logical_op__invert_in$41$next = \logical_op__invert_in$41 ;
- \logical_op__zero_a$42$next = \logical_op__zero_a$42 ;
- \logical_op__input_carry$43$next = \logical_op__input_carry$43 ;
- \logical_op__invert_out$44$next = \logical_op__invert_out$44 ;
- \logical_op__write_cr0$45$next = \logical_op__write_cr0$45 ;
- \logical_op__output_carry$46$next = \logical_op__output_carry$46 ;
- \logical_op__is_32bit$47$next = \logical_op__is_32bit$47 ;
- \logical_op__is_signed$48$next = \logical_op__is_signed$48 ;
- \logical_op__data_len$49$next = \logical_op__data_len$49 ;
- \logical_op__insn$50$next = \logical_op__insn$50 ;
- \logical_op__sv_pred_sz$51$next = \logical_op__sv_pred_sz$51 ;
- \logical_op__sv_pred_dz$52$next = \logical_op__sv_pred_dz$52 ;
- \logical_op__sv_saturate$53$next = \logical_op__sv_saturate$53 ;
- \logical_op__SV_Ptype$54$next = \logical_op__SV_Ptype$54 ;
+ \muxid$33$next = muxid;
+ endcase
+ endcase
+ end
+ always @* begin
+ if (\initial ) begin end
+ \logical_op__insn_type$34$next = \logical_op__insn_type$34 ;
+ \logical_op__fn_unit$35$next = \logical_op__fn_unit$35 ;
+ \logical_op__imm_data__data$36$next = \logical_op__imm_data__data$36 ;
+ \logical_op__imm_data__ok$37$next = \logical_op__imm_data__ok$37 ;
+ \logical_op__rc__rc$38$next = \logical_op__rc__rc$38 ;
+ \logical_op__rc__ok$39$next = \logical_op__rc__ok$39 ;
+ \logical_op__oe__oe$40$next = \logical_op__oe__oe$40 ;
+ \logical_op__oe__ok$41$next = \logical_op__oe__ok$41 ;
+ \logical_op__invert_in$42$next = \logical_op__invert_in$42 ;
+ \logical_op__zero_a$43$next = \logical_op__zero_a$43 ;
+ \logical_op__input_carry$44$next = \logical_op__input_carry$44 ;
+ \logical_op__invert_out$45$next = \logical_op__invert_out$45 ;
+ \logical_op__write_cr0$46$next = \logical_op__write_cr0$46 ;
+ \logical_op__output_carry$47$next = \logical_op__output_carry$47 ;
+ \logical_op__is_32bit$48$next = \logical_op__is_32bit$48 ;
+ \logical_op__is_signed$49$next = \logical_op__is_signed$49 ;
+ \logical_op__data_len$50$next = \logical_op__data_len$50 ;
+ \logical_op__insn$51$next = \logical_op__insn$51 ;
+ \logical_op__sv_pred_sz$52$next = \logical_op__sv_pred_sz$52 ;
+ \logical_op__sv_pred_dz$53$next = \logical_op__sv_pred_dz$53 ;
+ \logical_op__sv_saturate$54$next = \logical_op__sv_saturate$54 ;
+ \logical_op__sv_ldstmode$55$next = \logical_op__sv_ldstmode$55 ;
+ \logical_op__SV_Ptype$56$next = \logical_op__SV_Ptype$56 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
casez (empty)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */
casez (p_valid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */
1'h1:
- { \logical_op__SV_Ptype$54$next , \logical_op__sv_saturate$53$next , \logical_op__sv_pred_dz$52$next , \logical_op__sv_pred_sz$51$next , \logical_op__insn$50$next , \logical_op__data_len$49$next , \logical_op__is_signed$48$next , \logical_op__is_32bit$47$next , \logical_op__output_carry$46$next , \logical_op__write_cr0$45$next , \logical_op__invert_out$44$next , \logical_op__input_carry$43$next , \logical_op__zero_a$42$next , \logical_op__invert_in$41$next , \logical_op__oe__ok$40$next , \logical_op__oe__oe$39$next , \logical_op__rc__ok$38$next , \logical_op__rc__rc$37$next , \logical_op__imm_data__ok$36$next , \logical_op__imm_data__data$35$next , \logical_op__fn_unit$34$next , \logical_op__insn_type$33$next } = { logical_op__SV_Ptype, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
+ { \logical_op__SV_Ptype$56$next , \logical_op__sv_ldstmode$55$next , \logical_op__sv_saturate$54$next , \logical_op__sv_pred_dz$53$next , \logical_op__sv_pred_sz$52$next , \logical_op__insn$51$next , \logical_op__data_len$50$next , \logical_op__is_signed$49$next , \logical_op__is_32bit$48$next , \logical_op__output_carry$47$next , \logical_op__write_cr0$46$next , \logical_op__invert_out$45$next , \logical_op__input_carry$44$next , \logical_op__zero_a$43$next , \logical_op__invert_in$42$next , \logical_op__oe__ok$41$next , \logical_op__oe__oe$40$next , \logical_op__rc__ok$39$next , \logical_op__rc__rc$38$next , \logical_op__imm_data__ok$37$next , \logical_op__imm_data__data$36$next , \logical_op__fn_unit$35$next , \logical_op__insn_type$34$next } = { logical_op__SV_Ptype, logical_op__sv_ldstmode, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
endcase
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
1'h1:
begin
- \logical_op__imm_data__data$35$next = 64'h0000000000000000;
- \logical_op__imm_data__ok$36$next = 1'h0;
- \logical_op__rc__rc$37$next = 1'h0;
- \logical_op__rc__ok$38$next = 1'h0;
- \logical_op__oe__oe$39$next = 1'h0;
- \logical_op__oe__ok$40$next = 1'h0;
+ \logical_op__imm_data__data$36$next = 64'h0000000000000000;
+ \logical_op__imm_data__ok$37$next = 1'h0;
+ \logical_op__rc__rc$38$next = 1'h0;
+ \logical_op__rc__ok$39$next = 1'h0;
+ \logical_op__oe__oe$40$next = 1'h0;
+ \logical_op__oe__ok$41$next = 1'h0;
end
endcase
end
always @* begin
if (\initial ) begin end
- \ra$55$next = \ra$55 ;
+ \ra$57$next = \ra$57 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
casez (empty)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */
casez (p_valid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */
1'h1:
- \ra$55$next = ra;
+ \ra$57$next = ra;
endcase
endcase
end
always @* begin
if (\initial ) begin end
- \rb$56$next = \rb$56 ;
+ \rb$58$next = \rb$58 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
casez (empty)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */
casez (p_valid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */
1'h1:
- \rb$56$next = rb;
+ \rb$58$next = rb;
endcase
endcase
end
always @* begin
if (\initial ) begin end
- \xer_so$57$next = \xer_so$57 ;
+ \xer_so$59$next = \xer_so$59 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
casez (empty)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */
casez (p_valid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */
1'h1:
- \xer_so$57$next = xer_so;
+ \xer_so$59$next = xer_so;
endcase
endcase
end
always @* begin
if (\initial ) begin end
- \divisor_neg$58$next = \divisor_neg$58 ;
+ \divisor_neg$60$next = \divisor_neg$60 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
casez (empty)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */
casez (p_valid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */
1'h1:
- \divisor_neg$58$next = divisor_neg;
+ \divisor_neg$60$next = divisor_neg;
endcase
endcase
end
always @* begin
if (\initial ) begin end
- \dividend_neg$59$next = \dividend_neg$59 ;
+ \dividend_neg$61$next = \dividend_neg$61 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
casez (empty)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */
casez (p_valid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */
1'h1:
- \dividend_neg$59$next = dividend_neg;
+ \dividend_neg$61$next = dividend_neg;
endcase
endcase
end
always @* begin
if (\initial ) begin end
- \dive_abs_ov32$60$next = \dive_abs_ov32$60 ;
+ \dive_abs_ov32$62$next = \dive_abs_ov32$62 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
casez (empty)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */
casez (p_valid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */
1'h1:
- \dive_abs_ov32$60$next = dive_abs_ov32;
+ \dive_abs_ov32$62$next = dive_abs_ov32;
endcase
endcase
end
always @* begin
if (\initial ) begin end
- \dive_abs_ov64$61$next = \dive_abs_ov64$61 ;
+ \dive_abs_ov64$63$next = \dive_abs_ov64$63 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
casez (empty)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */
casez (p_valid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */
1'h1:
- \dive_abs_ov64$61$next = dive_abs_ov64;
+ \dive_abs_ov64$63$next = dive_abs_ov64;
endcase
endcase
end
always @* begin
if (\initial ) begin end
- \div_by_zero$62$next = \div_by_zero$62 ;
+ \div_by_zero$64$next = \div_by_zero$64 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
casez (empty)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */
casez (p_valid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */
1'h1:
- \div_by_zero$62$next = div_by_zero;
+ \div_by_zero$64$next = div_by_zero;
endcase
endcase
end
always @* begin
if (\initial ) begin end
- \dividend$76$next = \dividend$76 ;
+ \dividend$78$next = \dividend$78 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
casez (empty)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */
casez (p_valid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */
1'h1:
- \dividend$76$next = dividend;
+ \dividend$78$next = dividend;
endcase
endcase
end
always @* begin
if (\initial ) begin end
- \divisor_radicand$73$next = \divisor_radicand$73 ;
+ \divisor_radicand$75$next = \divisor_radicand$75 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
casez (empty)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */
casez (p_valid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */
1'h1:
- \divisor_radicand$73$next = divisor_radicand;
+ \divisor_radicand$75$next = divisor_radicand;
endcase
endcase
end
always @* begin
if (\initial ) begin end
- \operation$77$next = \operation$77 ;
+ \operation$79$next = \operation$79 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
casez (empty)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */
casez (p_valid_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */
1'h1:
- \operation$77$next = operation;
+ \operation$79$next = operation;
endcase
endcase
end
assign p_ready_o = empty;
- assign n_valid_o = \$71 ;
- assign remainder = \$63 ;
+ assign n_valid_o = \$73 ;
+ assign remainder = \$65 ;
assign quotient_root = div_state_next_o_dividend_quotient[63:0];
- assign \div_by_zero$31 = \div_by_zero$62 ;
- assign \dive_abs_ov64$30 = \dive_abs_ov64$61 ;
- assign \dive_abs_ov32$29 = \dive_abs_ov32$60 ;
- assign \dividend_neg$28 = \dividend_neg$59 ;
- assign \divisor_neg$27 = \divisor_neg$58 ;
- assign \xer_so$26 = \xer_so$57 ;
- assign \rb$25 = \rb$56 ;
- assign \ra$24 = \ra$55 ;
- assign { \logical_op__SV_Ptype$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { \logical_op__SV_Ptype$54 , \logical_op__sv_saturate$53 , \logical_op__sv_pred_dz$52 , \logical_op__sv_pred_sz$51 , \logical_op__insn$50 , \logical_op__data_len$49 , \logical_op__is_signed$48 , \logical_op__is_32bit$47 , \logical_op__output_carry$46 , \logical_op__write_cr0$45 , \logical_op__invert_out$44 , \logical_op__input_carry$43 , \logical_op__zero_a$42 , \logical_op__invert_in$41 , \logical_op__oe__ok$40 , \logical_op__oe__oe$39 , \logical_op__rc__ok$38 , \logical_op__rc__rc$37 , \logical_op__imm_data__ok$36 , \logical_op__imm_data__data$35 , \logical_op__fn_unit$34 , \logical_op__insn_type$33 };
- assign \muxid$1 = \muxid$32 ;
+ assign \div_by_zero$32 = \div_by_zero$64 ;
+ assign \dive_abs_ov64$31 = \dive_abs_ov64$63 ;
+ assign \dive_abs_ov32$30 = \dive_abs_ov32$62 ;
+ assign \dividend_neg$29 = \dividend_neg$61 ;
+ assign \divisor_neg$28 = \divisor_neg$60 ;
+ assign \xer_so$27 = \xer_so$59 ;
+ assign \rb$26 = \rb$58 ;
+ assign \ra$25 = \ra$57 ;
+ assign { \logical_op__SV_Ptype$24 , \logical_op__sv_ldstmode$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { \logical_op__SV_Ptype$56 , \logical_op__sv_ldstmode$55 , \logical_op__sv_saturate$54 , \logical_op__sv_pred_dz$53 , \logical_op__sv_pred_sz$52 , \logical_op__insn$51 , \logical_op__data_len$50 , \logical_op__is_signed$49 , \logical_op__is_32bit$48 , \logical_op__output_carry$47 , \logical_op__write_cr0$46 , \logical_op__invert_out$45 , \logical_op__input_carry$44 , \logical_op__zero_a$43 , \logical_op__invert_in$42 , \logical_op__oe__ok$41 , \logical_op__oe__oe$40 , \logical_op__rc__ok$39 , \logical_op__rc__rc$38 , \logical_op__imm_data__ok$37 , \logical_op__imm_data__data$36 , \logical_op__fn_unit$35 , \logical_op__insn_type$34 };
+ assign \muxid$1 = \muxid$33 ;
assign div_state_init_dividend = dividend;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_start" *)
(* generator = "nMigen" *)
-module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, ra, rb, xer_so, divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, dividend, divisor_radicand, operation, p_valid_i, p_ready_o, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__SV_Ptype$23 , \ra$24 , \rb$25 , \xer_so$26 , coresync_clk);
+module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__sv_ldstmode, logical_op__SV_Ptype, ra, rb, xer_so, divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, dividend, divisor_radicand, operation, p_valid_i, p_ready_o, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__sv_ldstmode$23 , \logical_op__SV_Ptype$24 , \ra$25 , \rb$26 , \xer_so$27 , coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
- wire \$78 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ wire \$81 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
output div_by_zero;
reg div_by_zero = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
- wire \div_by_zero$112 ;
+ wire \div_by_zero$116 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
reg \div_by_zero$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
output dive_abs_ov32;
reg dive_abs_ov32 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
- wire \dive_abs_ov32$110 ;
+ wire \dive_abs_ov32$114 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
reg \dive_abs_ov32$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *)
output dive_abs_ov64;
reg dive_abs_ov64 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *)
- wire \dive_abs_ov64$111 ;
+ wire \dive_abs_ov64$115 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *)
reg \dive_abs_ov64$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *)
output [127:0] dividend;
reg [127:0] dividend = 128'h00000000000000000000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *)
- wire [127:0] \dividend$113 ;
+ wire [127:0] \dividend$117 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *)
reg [127:0] \dividend$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *)
output dividend_neg;
reg dividend_neg = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *)
- wire \dividend_neg$109 ;
+ wire \dividend_neg$113 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *)
reg \dividend_neg$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *)
output divisor_neg;
reg divisor_neg = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *)
- wire \divisor_neg$108 ;
+ wire \divisor_neg$112 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *)
reg \divisor_neg$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *)
output [63:0] divisor_radicand;
reg [63:0] divisor_radicand = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *)
- wire [63:0] \divisor_radicand$114 ;
+ wire [63:0] \divisor_radicand$118 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *)
reg [63:0] \divisor_radicand$next ;
(* enum_base_type = "SVPtype" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \input_logical_op__SV_Ptype$49 ;
+ wire [1:0] \input_logical_op__SV_Ptype$51 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [3:0] input_logical_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [3:0] \input_logical_op__data_len$44 ;
+ wire [3:0] \input_logical_op__data_len$45 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \input_logical_op__fn_unit$29 ;
+ wire [14:0] \input_logical_op__fn_unit$30 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] input_logical_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \input_logical_op__imm_data__data$30 ;
+ wire [63:0] \input_logical_op__imm_data__data$31 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__imm_data__ok$31 ;
+ wire \input_logical_op__imm_data__ok$32 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \input_logical_op__input_carry$38 ;
+ wire [1:0] \input_logical_op__input_carry$39 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] input_logical_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \input_logical_op__insn$45 ;
+ wire [31:0] \input_logical_op__insn$46 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \input_logical_op__insn_type$28 ;
+ wire [6:0] \input_logical_op__insn_type$29 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__invert_in$36 ;
+ wire \input_logical_op__invert_in$37 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__invert_out;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__invert_out$39 ;
+ wire \input_logical_op__invert_out$40 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__is_32bit$42 ;
+ wire \input_logical_op__is_32bit$43 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__is_signed$43 ;
+ wire \input_logical_op__is_signed$44 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__oe__oe$34 ;
+ wire \input_logical_op__oe__oe$35 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__oe__ok$35 ;
+ wire \input_logical_op__oe__ok$36 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__output_carry;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__output_carry$41 ;
+ wire \input_logical_op__output_carry$42 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__rc__ok$33 ;
+ wire \input_logical_op__rc__ok$34 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__rc__rc$32 ;
+ wire \input_logical_op__rc__rc$33 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] input_logical_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \input_logical_op__sv_ldstmode$50 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__sv_pred_dz$47 ;
+ wire \input_logical_op__sv_pred_dz$48 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__sv_pred_sz$46 ;
+ wire \input_logical_op__sv_pred_sz$47 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \input_logical_op__sv_saturate$48 ;
+ wire [1:0] \input_logical_op__sv_saturate$49 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__write_cr0$40 ;
+ wire \input_logical_op__write_cr0$41 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire input_logical_op__zero_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \input_logical_op__zero_a$37 ;
+ wire \input_logical_op__zero_a$38 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] input_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \input_muxid$27 ;
+ wire [1:0] \input_muxid$28 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] input_ra;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \input_ra$50 ;
+ wire [63:0] \input_ra$52 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire [63:0] input_rb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \input_rb$51 ;
+ wire [63:0] \input_rb$53 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire input_xer_so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire \input_xer_so$52 ;
+ wire \input_xer_so$54 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \logical_op__SV_Ptype$102 ;
+ wire [1:0] \logical_op__SV_Ptype$106 ;
(* enum_base_type = "SVPtype" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- input [1:0] \logical_op__SV_Ptype$23 ;
+ input [1:0] \logical_op__SV_Ptype$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [1:0] \logical_op__SV_Ptype$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output [3:0] logical_op__data_len;
reg [3:0] logical_op__data_len = 4'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- input [3:0] \logical_op__data_len$18 ;
+ wire [3:0] \logical_op__data_len$100 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [3:0] \logical_op__data_len$97 ;
+ input [3:0] \logical_op__data_len$18 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [3:0] \logical_op__data_len$next ;
(* enum_base_type = "Function" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \logical_op__fn_unit$82 ;
+ wire [14:0] \logical_op__fn_unit$85 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [14:0] \logical_op__fn_unit$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] \logical_op__imm_data__data$4 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \logical_op__imm_data__data$83 ;
+ wire [63:0] \logical_op__imm_data__data$86 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [63:0] \logical_op__imm_data__data$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \logical_op__imm_data__ok$5 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__imm_data__ok$84 ;
+ wire \logical_op__imm_data__ok$87 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__imm_data__ok$next ;
(* enum_base_type = "CryIn" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \logical_op__input_carry$91 ;
+ wire [1:0] \logical_op__input_carry$94 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [1:0] \logical_op__input_carry$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output [31:0] logical_op__insn;
reg [31:0] logical_op__insn = 32'd0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- input [31:0] \logical_op__insn$19 ;
+ wire [31:0] \logical_op__insn$101 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \logical_op__insn$98 ;
+ input [31:0] \logical_op__insn$19 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [31:0] \logical_op__insn$next ;
(* enum_base_type = "MicrOp" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \logical_op__insn_type$81 ;
+ wire [6:0] \logical_op__insn_type$84 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [6:0] \logical_op__insn_type$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \logical_op__invert_in$10 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__invert_in$89 ;
+ wire \logical_op__invert_in$92 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__invert_in$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \logical_op__invert_out$13 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__invert_out$92 ;
+ wire \logical_op__invert_out$95 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__invert_out$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \logical_op__is_32bit$16 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__is_32bit$95 ;
+ wire \logical_op__is_32bit$98 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__is_32bit$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \logical_op__is_signed$17 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__is_signed$96 ;
+ wire \logical_op__is_signed$99 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__is_signed$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \logical_op__oe__oe$8 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__oe__oe$87 ;
+ wire \logical_op__oe__oe$90 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__oe__oe$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output logical_op__oe__ok;
reg logical_op__oe__ok = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__oe__ok$88 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \logical_op__oe__ok$9 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire \logical_op__oe__ok$91 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__oe__ok$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output logical_op__output_carry;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \logical_op__output_carry$15 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__output_carry$94 ;
+ wire \logical_op__output_carry$97 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__output_carry$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \logical_op__rc__ok$7 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__rc__ok$86 ;
+ wire \logical_op__rc__ok$89 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__rc__ok$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \logical_op__rc__rc$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__rc__rc$85 ;
+ wire \logical_op__rc__rc$88 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__rc__rc$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] logical_op__sv_ldstmode;
+ reg [1:0] logical_op__sv_ldstmode = 2'h0;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \logical_op__sv_ldstmode$105 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] \logical_op__sv_ldstmode$23 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \logical_op__sv_ldstmode$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output logical_op__sv_pred_dz;
reg logical_op__sv_pred_dz = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__sv_pred_dz$100 ;
+ wire \logical_op__sv_pred_dz$103 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \logical_op__sv_pred_dz$21 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output logical_op__sv_pred_sz;
reg logical_op__sv_pred_sz = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- input \logical_op__sv_pred_sz$20 ;
+ wire \logical_op__sv_pred_sz$102 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__sv_pred_sz$99 ;
+ input \logical_op__sv_pred_sz$20 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__sv_pred_sz$next ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \logical_op__sv_saturate$101 ;
+ wire [1:0] \logical_op__sv_saturate$104 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \logical_op__write_cr0$14 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__write_cr0$93 ;
+ wire \logical_op__write_cr0$96 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__write_cr0$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input \logical_op__zero_a$11 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \logical_op__zero_a$90 ;
+ wire \logical_op__zero_a$93 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \logical_op__zero_a$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
input [1:0] \muxid$1 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \muxid$80 ;
+ wire [1:0] \muxid$83 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
reg [1:0] \muxid$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
output [1:0] operation;
reg [1:0] operation = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *)
- wire [1:0] \operation$115 ;
+ wire [1:0] \operation$119 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *)
reg [1:0] \operation$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
input p_valid_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
- wire \p_valid_i$77 ;
+ wire \p_valid_i$80 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
wire p_valid_i_p_ready_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
output [63:0] ra;
reg [63:0] ra = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \ra$103 ;
+ wire [63:0] \ra$107 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \ra$104 ;
+ wire [63:0] \ra$108 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- input [63:0] \ra$24 ;
+ input [63:0] \ra$25 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
reg [63:0] \ra$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
output [63:0] rb;
reg [63:0] rb = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \rb$105 ;
+ wire [63:0] \rb$109 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [63:0] \rb$106 ;
+ wire [63:0] \rb$110 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- input [63:0] \rb$25 ;
+ input [63:0] \rb$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
reg [63:0] \rb$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \setup_stage_logical_op__SV_Ptype$75 ;
+ wire [1:0] \setup_stage_logical_op__SV_Ptype$78 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [3:0] setup_stage_logical_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [3:0] \setup_stage_logical_op__data_len$70 ;
+ wire [3:0] \setup_stage_logical_op__data_len$72 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
(* enum_value_010000000000000 = "VL" *)
(* enum_value_100000000000000 = "FPU" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [14:0] \setup_stage_logical_op__fn_unit$55 ;
+ wire [14:0] \setup_stage_logical_op__fn_unit$57 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [63:0] setup_stage_logical_op__imm_data__data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [63:0] \setup_stage_logical_op__imm_data__data$56 ;
+ wire [63:0] \setup_stage_logical_op__imm_data__data$58 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire setup_stage_logical_op__imm_data__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \setup_stage_logical_op__imm_data__ok$57 ;
+ wire \setup_stage_logical_op__imm_data__ok$59 ;
(* enum_base_type = "CryIn" *)
(* enum_value_00 = "ZERO" *)
(* enum_value_01 = "ONE" *)
(* enum_value_01 = "ONE" *)
(* enum_value_10 = "CA" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \setup_stage_logical_op__input_carry$64 ;
+ wire [1:0] \setup_stage_logical_op__input_carry$66 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire [31:0] setup_stage_logical_op__insn;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [31:0] \setup_stage_logical_op__insn$71 ;
+ wire [31:0] \setup_stage_logical_op__insn$73 ;
(* enum_base_type = "MicrOp" *)
(* enum_value_0000000 = "OP_ILLEGAL" *)
(* enum_value_0000001 = "OP_NOP" *)
(* enum_value_1001101 = "OP_FPOP" *)
(* enum_value_1001110 = "OP_FPOP_I" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [6:0] \setup_stage_logical_op__insn_type$54 ;
+ wire [6:0] \setup_stage_logical_op__insn_type$56 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire setup_stage_logical_op__invert_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \setup_stage_logical_op__invert_in$62 ;
+ wire \setup_stage_logical_op__invert_in$64 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire setup_stage_logical_op__invert_out;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \setup_stage_logical_op__invert_out$65 ;
+ wire \setup_stage_logical_op__invert_out$67 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire setup_stage_logical_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \setup_stage_logical_op__is_32bit$68 ;
+ wire \setup_stage_logical_op__is_32bit$70 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire setup_stage_logical_op__is_signed;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \setup_stage_logical_op__is_signed$69 ;
+ wire \setup_stage_logical_op__is_signed$71 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire setup_stage_logical_op__oe__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \setup_stage_logical_op__oe__oe$60 ;
+ wire \setup_stage_logical_op__oe__oe$62 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire setup_stage_logical_op__oe__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \setup_stage_logical_op__oe__ok$61 ;
+ wire \setup_stage_logical_op__oe__ok$63 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire setup_stage_logical_op__output_carry;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \setup_stage_logical_op__output_carry$67 ;
+ wire \setup_stage_logical_op__output_carry$69 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire setup_stage_logical_op__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \setup_stage_logical_op__rc__ok$59 ;
+ wire \setup_stage_logical_op__rc__ok$61 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire setup_stage_logical_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \setup_stage_logical_op__rc__rc$58 ;
+ wire \setup_stage_logical_op__rc__rc$60 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] setup_stage_logical_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ wire [1:0] \setup_stage_logical_op__sv_ldstmode$77 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire setup_stage_logical_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \setup_stage_logical_op__sv_pred_dz$73 ;
+ wire \setup_stage_logical_op__sv_pred_dz$75 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire setup_stage_logical_op__sv_pred_sz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \setup_stage_logical_op__sv_pred_sz$72 ;
+ wire \setup_stage_logical_op__sv_pred_sz$74 ;
(* enum_base_type = "SVP64sat" *)
(* enum_value_00 = "NONE" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_01 = "SIGNED" *)
(* enum_value_10 = "UNSIGNED" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire [1:0] \setup_stage_logical_op__sv_saturate$74 ;
+ wire [1:0] \setup_stage_logical_op__sv_saturate$76 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire setup_stage_logical_op__write_cr0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \setup_stage_logical_op__write_cr0$66 ;
+ wire \setup_stage_logical_op__write_cr0$68 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
wire setup_stage_logical_op__zero_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- wire \setup_stage_logical_op__zero_a$63 ;
+ wire \setup_stage_logical_op__zero_a$65 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
wire [1:0] setup_stage_muxid;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
- wire [1:0] \setup_stage_muxid$53 ;
+ wire [1:0] \setup_stage_muxid$55 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *)
wire [1:0] setup_stage_operation;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
wire setup_stage_xer_so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire \setup_stage_xer_so$76 ;
+ wire \setup_stage_xer_so$79 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
output xer_so;
reg xer_so = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire \xer_so$107 ;
+ wire \xer_so$111 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- input \xer_so$26 ;
+ input \xer_so$27 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
reg \xer_so$next ;
- assign \$78 = \p_valid_i$77 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
+ assign \$81 = \p_valid_i$80 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
always @(posedge coresync_clk)
operation <= \operation$next ;
always @(posedge coresync_clk)
logical_op__sv_pred_dz <= \logical_op__sv_pred_dz$next ;
always @(posedge coresync_clk)
logical_op__sv_saturate <= \logical_op__sv_saturate$next ;
+ always @(posedge coresync_clk)
+ logical_op__sv_ldstmode <= \logical_op__sv_ldstmode$next ;
always @(posedge coresync_clk)
logical_op__SV_Ptype <= \logical_op__SV_Ptype$next ;
always @(posedge coresync_clk)
r_busy <= \r_busy$next ;
\input$78 \input (
.logical_op__SV_Ptype(input_logical_op__SV_Ptype),
- .\logical_op__SV_Ptype$23 (\input_logical_op__SV_Ptype$49 ),
+ .\logical_op__SV_Ptype$24 (\input_logical_op__SV_Ptype$51 ),
.logical_op__data_len(input_logical_op__data_len),
- .\logical_op__data_len$18 (\input_logical_op__data_len$44 ),
+ .\logical_op__data_len$18 (\input_logical_op__data_len$45 ),
.logical_op__fn_unit(input_logical_op__fn_unit),
- .\logical_op__fn_unit$3 (\input_logical_op__fn_unit$29 ),
+ .\logical_op__fn_unit$3 (\input_logical_op__fn_unit$30 ),
.logical_op__imm_data__data(input_logical_op__imm_data__data),
- .\logical_op__imm_data__data$4 (\input_logical_op__imm_data__data$30 ),
+ .\logical_op__imm_data__data$4 (\input_logical_op__imm_data__data$31 ),
.logical_op__imm_data__ok(input_logical_op__imm_data__ok),
- .\logical_op__imm_data__ok$5 (\input_logical_op__imm_data__ok$31 ),
+ .\logical_op__imm_data__ok$5 (\input_logical_op__imm_data__ok$32 ),
.logical_op__input_carry(input_logical_op__input_carry),
- .\logical_op__input_carry$12 (\input_logical_op__input_carry$38 ),
+ .\logical_op__input_carry$12 (\input_logical_op__input_carry$39 ),
.logical_op__insn(input_logical_op__insn),
- .\logical_op__insn$19 (\input_logical_op__insn$45 ),
+ .\logical_op__insn$19 (\input_logical_op__insn$46 ),
.logical_op__insn_type(input_logical_op__insn_type),
- .\logical_op__insn_type$2 (\input_logical_op__insn_type$28 ),
+ .\logical_op__insn_type$2 (\input_logical_op__insn_type$29 ),
.logical_op__invert_in(input_logical_op__invert_in),
- .\logical_op__invert_in$10 (\input_logical_op__invert_in$36 ),
+ .\logical_op__invert_in$10 (\input_logical_op__invert_in$37 ),
.logical_op__invert_out(input_logical_op__invert_out),
- .\logical_op__invert_out$13 (\input_logical_op__invert_out$39 ),
+ .\logical_op__invert_out$13 (\input_logical_op__invert_out$40 ),
.logical_op__is_32bit(input_logical_op__is_32bit),
- .\logical_op__is_32bit$16 (\input_logical_op__is_32bit$42 ),
+ .\logical_op__is_32bit$16 (\input_logical_op__is_32bit$43 ),
.logical_op__is_signed(input_logical_op__is_signed),
- .\logical_op__is_signed$17 (\input_logical_op__is_signed$43 ),
+ .\logical_op__is_signed$17 (\input_logical_op__is_signed$44 ),
.logical_op__oe__oe(input_logical_op__oe__oe),
- .\logical_op__oe__oe$8 (\input_logical_op__oe__oe$34 ),
+ .\logical_op__oe__oe$8 (\input_logical_op__oe__oe$35 ),
.logical_op__oe__ok(input_logical_op__oe__ok),
- .\logical_op__oe__ok$9 (\input_logical_op__oe__ok$35 ),
+ .\logical_op__oe__ok$9 (\input_logical_op__oe__ok$36 ),
.logical_op__output_carry(input_logical_op__output_carry),
- .\logical_op__output_carry$15 (\input_logical_op__output_carry$41 ),
+ .\logical_op__output_carry$15 (\input_logical_op__output_carry$42 ),
.logical_op__rc__ok(input_logical_op__rc__ok),
- .\logical_op__rc__ok$7 (\input_logical_op__rc__ok$33 ),
+ .\logical_op__rc__ok$7 (\input_logical_op__rc__ok$34 ),
.logical_op__rc__rc(input_logical_op__rc__rc),
- .\logical_op__rc__rc$6 (\input_logical_op__rc__rc$32 ),
+ .\logical_op__rc__rc$6 (\input_logical_op__rc__rc$33 ),
+ .logical_op__sv_ldstmode(input_logical_op__sv_ldstmode),
+ .\logical_op__sv_ldstmode$23 (\input_logical_op__sv_ldstmode$50 ),
.logical_op__sv_pred_dz(input_logical_op__sv_pred_dz),
- .\logical_op__sv_pred_dz$21 (\input_logical_op__sv_pred_dz$47 ),
+ .\logical_op__sv_pred_dz$21 (\input_logical_op__sv_pred_dz$48 ),
.logical_op__sv_pred_sz(input_logical_op__sv_pred_sz),
- .\logical_op__sv_pred_sz$20 (\input_logical_op__sv_pred_sz$46 ),
+ .\logical_op__sv_pred_sz$20 (\input_logical_op__sv_pred_sz$47 ),
.logical_op__sv_saturate(input_logical_op__sv_saturate),
- .\logical_op__sv_saturate$22 (\input_logical_op__sv_saturate$48 ),
+ .\logical_op__sv_saturate$22 (\input_logical_op__sv_saturate$49 ),
.logical_op__write_cr0(input_logical_op__write_cr0),
- .\logical_op__write_cr0$14 (\input_logical_op__write_cr0$40 ),
+ .\logical_op__write_cr0$14 (\input_logical_op__write_cr0$41 ),
.logical_op__zero_a(input_logical_op__zero_a),
- .\logical_op__zero_a$11 (\input_logical_op__zero_a$37 ),
+ .\logical_op__zero_a$11 (\input_logical_op__zero_a$38 ),
.muxid(input_muxid),
- .\muxid$1 (\input_muxid$27 ),
+ .\muxid$1 (\input_muxid$28 ),
.ra(input_ra),
- .\ra$24 (\input_ra$50 ),
+ .\ra$25 (\input_ra$52 ),
.rb(input_rb),
- .\rb$25 (\input_rb$51 ),
+ .\rb$26 (\input_rb$53 ),
.xer_so(input_xer_so),
- .\xer_so$26 (\input_xer_so$52 )
+ .\xer_so$27 (\input_xer_so$54 )
);
\n$77 n (
.n_ready_i(n_ready_i),
.divisor_neg(setup_stage_divisor_neg),
.divisor_radicand(setup_stage_divisor_radicand),
.logical_op__SV_Ptype(setup_stage_logical_op__SV_Ptype),
- .\logical_op__SV_Ptype$23 (\setup_stage_logical_op__SV_Ptype$75 ),
+ .\logical_op__SV_Ptype$24 (\setup_stage_logical_op__SV_Ptype$78 ),
.logical_op__data_len(setup_stage_logical_op__data_len),
- .\logical_op__data_len$18 (\setup_stage_logical_op__data_len$70 ),
+ .\logical_op__data_len$18 (\setup_stage_logical_op__data_len$72 ),
.logical_op__fn_unit(setup_stage_logical_op__fn_unit),
- .\logical_op__fn_unit$3 (\setup_stage_logical_op__fn_unit$55 ),
+ .\logical_op__fn_unit$3 (\setup_stage_logical_op__fn_unit$57 ),
.logical_op__imm_data__data(setup_stage_logical_op__imm_data__data),
- .\logical_op__imm_data__data$4 (\setup_stage_logical_op__imm_data__data$56 ),
+ .\logical_op__imm_data__data$4 (\setup_stage_logical_op__imm_data__data$58 ),
.logical_op__imm_data__ok(setup_stage_logical_op__imm_data__ok),
- .\logical_op__imm_data__ok$5 (\setup_stage_logical_op__imm_data__ok$57 ),
+ .\logical_op__imm_data__ok$5 (\setup_stage_logical_op__imm_data__ok$59 ),
.logical_op__input_carry(setup_stage_logical_op__input_carry),
- .\logical_op__input_carry$12 (\setup_stage_logical_op__input_carry$64 ),
+ .\logical_op__input_carry$12 (\setup_stage_logical_op__input_carry$66 ),
.logical_op__insn(setup_stage_logical_op__insn),
- .\logical_op__insn$19 (\setup_stage_logical_op__insn$71 ),
+ .\logical_op__insn$19 (\setup_stage_logical_op__insn$73 ),
.logical_op__insn_type(setup_stage_logical_op__insn_type),
- .\logical_op__insn_type$2 (\setup_stage_logical_op__insn_type$54 ),
+ .\logical_op__insn_type$2 (\setup_stage_logical_op__insn_type$56 ),
.logical_op__invert_in(setup_stage_logical_op__invert_in),
- .\logical_op__invert_in$10 (\setup_stage_logical_op__invert_in$62 ),
+ .\logical_op__invert_in$10 (\setup_stage_logical_op__invert_in$64 ),
.logical_op__invert_out(setup_stage_logical_op__invert_out),
- .\logical_op__invert_out$13 (\setup_stage_logical_op__invert_out$65 ),
+ .\logical_op__invert_out$13 (\setup_stage_logical_op__invert_out$67 ),
.logical_op__is_32bit(setup_stage_logical_op__is_32bit),
- .\logical_op__is_32bit$16 (\setup_stage_logical_op__is_32bit$68 ),
+ .\logical_op__is_32bit$16 (\setup_stage_logical_op__is_32bit$70 ),
.logical_op__is_signed(setup_stage_logical_op__is_signed),
- .\logical_op__is_signed$17 (\setup_stage_logical_op__is_signed$69 ),
+ .\logical_op__is_signed$17 (\setup_stage_logical_op__is_signed$71 ),
.logical_op__oe__oe(setup_stage_logical_op__oe__oe),
- .\logical_op__oe__oe$8 (\setup_stage_logical_op__oe__oe$60 ),
+ .\logical_op__oe__oe$8 (\setup_stage_logical_op__oe__oe$62 ),
.logical_op__oe__ok(setup_stage_logical_op__oe__ok),
- .\logical_op__oe__ok$9 (\setup_stage_logical_op__oe__ok$61 ),
+ .\logical_op__oe__ok$9 (\setup_stage_logical_op__oe__ok$63 ),
.logical_op__output_carry(setup_stage_logical_op__output_carry),
- .\logical_op__output_carry$15 (\setup_stage_logical_op__output_carry$67 ),
+ .\logical_op__output_carry$15 (\setup_stage_logical_op__output_carry$69 ),
.logical_op__rc__ok(setup_stage_logical_op__rc__ok),
- .\logical_op__rc__ok$7 (\setup_stage_logical_op__rc__ok$59 ),
+ .\logical_op__rc__ok$7 (\setup_stage_logical_op__rc__ok$61 ),
.logical_op__rc__rc(setup_stage_logical_op__rc__rc),
- .\logical_op__rc__rc$6 (\setup_stage_logical_op__rc__rc$58 ),
+ .\logical_op__rc__rc$6 (\setup_stage_logical_op__rc__rc$60 ),
+ .logical_op__sv_ldstmode(setup_stage_logical_op__sv_ldstmode),
+ .\logical_op__sv_ldstmode$23 (\setup_stage_logical_op__sv_ldstmode$77 ),
.logical_op__sv_pred_dz(setup_stage_logical_op__sv_pred_dz),
- .\logical_op__sv_pred_dz$21 (\setup_stage_logical_op__sv_pred_dz$73 ),
+ .\logical_op__sv_pred_dz$21 (\setup_stage_logical_op__sv_pred_dz$75 ),
.logical_op__sv_pred_sz(setup_stage_logical_op__sv_pred_sz),
- .\logical_op__sv_pred_sz$20 (\setup_stage_logical_op__sv_pred_sz$72 ),
+ .\logical_op__sv_pred_sz$20 (\setup_stage_logical_op__sv_pred_sz$74 ),
.logical_op__sv_saturate(setup_stage_logical_op__sv_saturate),
- .\logical_op__sv_saturate$22 (\setup_stage_logical_op__sv_saturate$74 ),
+ .\logical_op__sv_saturate$22 (\setup_stage_logical_op__sv_saturate$76 ),
.logical_op__write_cr0(setup_stage_logical_op__write_cr0),
- .\logical_op__write_cr0$14 (\setup_stage_logical_op__write_cr0$66 ),
+ .\logical_op__write_cr0$14 (\setup_stage_logical_op__write_cr0$68 ),
.logical_op__zero_a(setup_stage_logical_op__zero_a),
- .\logical_op__zero_a$11 (\setup_stage_logical_op__zero_a$63 ),
+ .\logical_op__zero_a$11 (\setup_stage_logical_op__zero_a$65 ),
.muxid(setup_stage_muxid),
- .\muxid$1 (\setup_stage_muxid$53 ),
+ .\muxid$1 (\setup_stage_muxid$55 ),
.operation(setup_stage_operation),
.ra(setup_stage_ra),
.rb(setup_stage_rb),
.xer_so(setup_stage_xer_so),
- .\xer_so$24 (\setup_stage_xer_so$76 )
+ .\xer_so$25 (\setup_stage_xer_so$79 )
);
always @* begin
if (\initial ) begin end
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \ra$next = \ra$103 ;
+ \ra$next = \ra$107 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \ra$next = \ra$103 ;
+ \ra$next = \ra$107 ;
endcase
end
always @* begin
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \rb$next = \rb$105 ;
+ \rb$next = \rb$109 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \rb$next = \rb$105 ;
+ \rb$next = \rb$109 ;
endcase
end
always @* begin
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \xer_so$next = \xer_so$107 ;
+ \xer_so$next = \xer_so$111 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \xer_so$next = \xer_so$107 ;
+ \xer_so$next = \xer_so$111 ;
endcase
end
always @* begin
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \divisor_neg$next = \divisor_neg$108 ;
+ \divisor_neg$next = \divisor_neg$112 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \divisor_neg$next = \divisor_neg$108 ;
+ \divisor_neg$next = \divisor_neg$112 ;
endcase
end
always @* begin
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \dividend_neg$next = \dividend_neg$109 ;
+ \dividend_neg$next = \dividend_neg$113 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \dividend_neg$next = \dividend_neg$109 ;
+ \dividend_neg$next = \dividend_neg$113 ;
endcase
end
always @* begin
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \dive_abs_ov32$next = \dive_abs_ov32$110 ;
+ \dive_abs_ov32$next = \dive_abs_ov32$114 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \dive_abs_ov32$next = \dive_abs_ov32$110 ;
+ \dive_abs_ov32$next = \dive_abs_ov32$114 ;
endcase
end
always @* begin
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \dive_abs_ov64$next = \dive_abs_ov64$111 ;
+ \dive_abs_ov64$next = \dive_abs_ov64$115 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \dive_abs_ov64$next = \dive_abs_ov64$111 ;
+ \dive_abs_ov64$next = \dive_abs_ov64$115 ;
endcase
end
always @* begin
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \div_by_zero$next = \div_by_zero$112 ;
+ \div_by_zero$next = \div_by_zero$116 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \div_by_zero$next = \div_by_zero$112 ;
+ \div_by_zero$next = \div_by_zero$116 ;
endcase
end
always @* begin
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \dividend$next = \dividend$113 ;
+ \dividend$next = \dividend$117 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \dividend$next = \dividend$113 ;
+ \dividend$next = \dividend$117 ;
endcase
end
always @* begin
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \divisor_radicand$next = \divisor_radicand$114 ;
+ \divisor_radicand$next = \divisor_radicand$118 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \divisor_radicand$next = \divisor_radicand$114 ;
+ \divisor_radicand$next = \divisor_radicand$118 ;
endcase
end
always @* begin
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \operation$next = \operation$115 ;
+ \operation$next = \operation$119 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \operation$next = \operation$115 ;
+ \operation$next = \operation$119 ;
endcase
end
always @* begin
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- \muxid$next = \muxid$80 ;
+ \muxid$next = \muxid$83 ;
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- \muxid$next = \muxid$80 ;
+ \muxid$next = \muxid$83 ;
endcase
end
always @* begin
\logical_op__sv_pred_sz$next = logical_op__sv_pred_sz;
\logical_op__sv_pred_dz$next = logical_op__sv_pred_dz;
\logical_op__sv_saturate$next = logical_op__sv_saturate;
+ \logical_op__sv_ldstmode$next = logical_op__sv_ldstmode;
\logical_op__SV_Ptype$next = logical_op__SV_Ptype;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */
2'b?1:
- { \logical_op__SV_Ptype$next , \logical_op__sv_saturate$next , \logical_op__sv_pred_dz$next , \logical_op__sv_pred_sz$next , \logical_op__insn$next , \logical_op__data_len$next , \logical_op__is_signed$next , \logical_op__is_32bit$next , \logical_op__output_carry$next , \logical_op__write_cr0$next , \logical_op__invert_out$next , \logical_op__input_carry$next , \logical_op__zero_a$next , \logical_op__invert_in$next , \logical_op__oe__ok$next , \logical_op__oe__oe$next , \logical_op__rc__ok$next , \logical_op__rc__rc$next , \logical_op__imm_data__ok$next , \logical_op__imm_data__data$next , \logical_op__fn_unit$next , \logical_op__insn_type$next } = { \logical_op__SV_Ptype$102 , \logical_op__sv_saturate$101 , \logical_op__sv_pred_dz$100 , \logical_op__sv_pred_sz$99 , \logical_op__insn$98 , \logical_op__data_len$97 , \logical_op__is_signed$96 , \logical_op__is_32bit$95 , \logical_op__output_carry$94 , \logical_op__write_cr0$93 , \logical_op__invert_out$92 , \logical_op__input_carry$91 , \logical_op__zero_a$90 , \logical_op__invert_in$89 , \logical_op__oe__ok$88 , \logical_op__oe__oe$87 , \logical_op__rc__ok$86 , \logical_op__rc__rc$85 , \logical_op__imm_data__ok$84 , \logical_op__imm_data__data$83 , \logical_op__fn_unit$82 , \logical_op__insn_type$81 };
+ { \logical_op__SV_Ptype$next , \logical_op__sv_ldstmode$next , \logical_op__sv_saturate$next , \logical_op__sv_pred_dz$next , \logical_op__sv_pred_sz$next , \logical_op__insn$next , \logical_op__data_len$next , \logical_op__is_signed$next , \logical_op__is_32bit$next , \logical_op__output_carry$next , \logical_op__write_cr0$next , \logical_op__invert_out$next , \logical_op__input_carry$next , \logical_op__zero_a$next , \logical_op__invert_in$next , \logical_op__oe__ok$next , \logical_op__oe__oe$next , \logical_op__rc__ok$next , \logical_op__rc__rc$next , \logical_op__imm_data__ok$next , \logical_op__imm_data__data$next , \logical_op__fn_unit$next , \logical_op__insn_type$next } = { \logical_op__SV_Ptype$106 , \logical_op__sv_ldstmode$105 , \logical_op__sv_saturate$104 , \logical_op__sv_pred_dz$103 , \logical_op__sv_pred_sz$102 , \logical_op__insn$101 , \logical_op__data_len$100 , \logical_op__is_signed$99 , \logical_op__is_32bit$98 , \logical_op__output_carry$97 , \logical_op__write_cr0$96 , \logical_op__invert_out$95 , \logical_op__input_carry$94 , \logical_op__zero_a$93 , \logical_op__invert_in$92 , \logical_op__oe__ok$91 , \logical_op__oe__oe$90 , \logical_op__rc__ok$89 , \logical_op__rc__rc$88 , \logical_op__imm_data__ok$87 , \logical_op__imm_data__data$86 , \logical_op__fn_unit$85 , \logical_op__insn_type$84 };
/* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */
2'b1?:
- { \logical_op__SV_Ptype$next , \logical_op__sv_saturate$next , \logical_op__sv_pred_dz$next , \logical_op__sv_pred_sz$next , \logical_op__insn$next , \logical_op__data_len$next , \logical_op__is_signed$next , \logical_op__is_32bit$next , \logical_op__output_carry$next , \logical_op__write_cr0$next , \logical_op__invert_out$next , \logical_op__input_carry$next , \logical_op__zero_a$next , \logical_op__invert_in$next , \logical_op__oe__ok$next , \logical_op__oe__oe$next , \logical_op__rc__ok$next , \logical_op__rc__rc$next , \logical_op__imm_data__ok$next , \logical_op__imm_data__data$next , \logical_op__fn_unit$next , \logical_op__insn_type$next } = { \logical_op__SV_Ptype$102 , \logical_op__sv_saturate$101 , \logical_op__sv_pred_dz$100 , \logical_op__sv_pred_sz$99 , \logical_op__insn$98 , \logical_op__data_len$97 , \logical_op__is_signed$96 , \logical_op__is_32bit$95 , \logical_op__output_carry$94 , \logical_op__write_cr0$93 , \logical_op__invert_out$92 , \logical_op__input_carry$91 , \logical_op__zero_a$90 , \logical_op__invert_in$89 , \logical_op__oe__ok$88 , \logical_op__oe__oe$87 , \logical_op__rc__ok$86 , \logical_op__rc__rc$85 , \logical_op__imm_data__ok$84 , \logical_op__imm_data__data$83 , \logical_op__fn_unit$82 , \logical_op__insn_type$81 };
+ { \logical_op__SV_Ptype$next , \logical_op__sv_ldstmode$next , \logical_op__sv_saturate$next , \logical_op__sv_pred_dz$next , \logical_op__sv_pred_sz$next , \logical_op__insn$next , \logical_op__data_len$next , \logical_op__is_signed$next , \logical_op__is_32bit$next , \logical_op__output_carry$next , \logical_op__write_cr0$next , \logical_op__invert_out$next , \logical_op__input_carry$next , \logical_op__zero_a$next , \logical_op__invert_in$next , \logical_op__oe__ok$next , \logical_op__oe__oe$next , \logical_op__rc__ok$next , \logical_op__rc__rc$next , \logical_op__imm_data__ok$next , \logical_op__imm_data__data$next , \logical_op__fn_unit$next , \logical_op__insn_type$next } = { \logical_op__SV_Ptype$106 , \logical_op__sv_ldstmode$105 , \logical_op__sv_saturate$104 , \logical_op__sv_pred_dz$103 , \logical_op__sv_pred_sz$102 , \logical_op__insn$101 , \logical_op__data_len$100 , \logical_op__is_signed$99 , \logical_op__is_32bit$98 , \logical_op__output_carry$97 , \logical_op__write_cr0$96 , \logical_op__invert_out$95 , \logical_op__input_carry$94 , \logical_op__zero_a$93 , \logical_op__invert_in$92 , \logical_op__oe__ok$91 , \logical_op__oe__oe$90 , \logical_op__rc__ok$89 , \logical_op__rc__rc$88 , \logical_op__imm_data__ok$87 , \logical_op__imm_data__data$86 , \logical_op__fn_unit$85 , \logical_op__insn_type$84 };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
end
endcase
end
- assign \ra$104 = 64'h0000000000000000;
- assign \rb$106 = 64'h0000000000000000;
+ assign \ra$108 = 64'h0000000000000000;
+ assign \rb$110 = 64'h0000000000000000;
assign p_ready_o = n_i_rdy_data;
assign n_valid_o = r_busy;
- assign \operation$115 = setup_stage_operation;
- assign \divisor_radicand$114 = setup_stage_divisor_radicand;
- assign \dividend$113 = setup_stage_dividend;
- assign \div_by_zero$112 = setup_stage_div_by_zero;
- assign \dive_abs_ov64$111 = setup_stage_dive_abs_ov64;
- assign \dive_abs_ov32$110 = setup_stage_dive_abs_ov32;
- assign \dividend_neg$109 = setup_stage_dividend_neg;
- assign \divisor_neg$108 = setup_stage_divisor_neg;
- assign \xer_so$107 = \setup_stage_xer_so$76 ;
- assign \rb$105 = 64'h0000000000000000;
- assign \ra$103 = 64'h0000000000000000;
- assign { \logical_op__SV_Ptype$102 , \logical_op__sv_saturate$101 , \logical_op__sv_pred_dz$100 , \logical_op__sv_pred_sz$99 , \logical_op__insn$98 , \logical_op__data_len$97 , \logical_op__is_signed$96 , \logical_op__is_32bit$95 , \logical_op__output_carry$94 , \logical_op__write_cr0$93 , \logical_op__invert_out$92 , \logical_op__input_carry$91 , \logical_op__zero_a$90 , \logical_op__invert_in$89 , \logical_op__oe__ok$88 , \logical_op__oe__oe$87 , \logical_op__rc__ok$86 , \logical_op__rc__rc$85 , \logical_op__imm_data__ok$84 , \logical_op__imm_data__data$83 , \logical_op__fn_unit$82 , \logical_op__insn_type$81 } = { \setup_stage_logical_op__SV_Ptype$75 , \setup_stage_logical_op__sv_saturate$74 , \setup_stage_logical_op__sv_pred_dz$73 , \setup_stage_logical_op__sv_pred_sz$72 , \setup_stage_logical_op__insn$71 , \setup_stage_logical_op__data_len$70 , \setup_stage_logical_op__is_signed$69 , \setup_stage_logical_op__is_32bit$68 , \setup_stage_logical_op__output_carry$67 , \setup_stage_logical_op__write_cr0$66 , \setup_stage_logical_op__invert_out$65 , \setup_stage_logical_op__input_carry$64 , \setup_stage_logical_op__zero_a$63 , \setup_stage_logical_op__invert_in$62 , \setup_stage_logical_op__oe__ok$61 , \setup_stage_logical_op__oe__oe$60 , \setup_stage_logical_op__rc__ok$59 , \setup_stage_logical_op__rc__rc$58 , \setup_stage_logical_op__imm_data__ok$57 , \setup_stage_logical_op__imm_data__data$56 , \setup_stage_logical_op__fn_unit$55 , \setup_stage_logical_op__insn_type$54 };
- assign \muxid$80 = \setup_stage_muxid$53 ;
- assign p_valid_i_p_ready_o = \$78 ;
+ assign \operation$119 = setup_stage_operation;
+ assign \divisor_radicand$118 = setup_stage_divisor_radicand;
+ assign \dividend$117 = setup_stage_dividend;
+ assign \div_by_zero$116 = setup_stage_div_by_zero;
+ assign \dive_abs_ov64$115 = setup_stage_dive_abs_ov64;
+ assign \dive_abs_ov32$114 = setup_stage_dive_abs_ov32;
+ assign \dividend_neg$113 = setup_stage_dividend_neg;
+ assign \divisor_neg$112 = setup_stage_divisor_neg;
+ assign \xer_so$111 = \setup_stage_xer_so$79 ;
+ assign \rb$109 = 64'h0000000000000000;
+ assign \ra$107 = 64'h0000000000000000;
+ assign { \logical_op__SV_Ptype$106 , \logical_op__sv_ldstmode$105 , \logical_op__sv_saturate$104 , \logical_op__sv_pred_dz$103 , \logical_op__sv_pred_sz$102 , \logical_op__insn$101 , \logical_op__data_len$100 , \logical_op__is_signed$99 , \logical_op__is_32bit$98 , \logical_op__output_carry$97 , \logical_op__write_cr0$96 , \logical_op__invert_out$95 , \logical_op__input_carry$94 , \logical_op__zero_a$93 , \logical_op__invert_in$92 , \logical_op__oe__ok$91 , \logical_op__oe__oe$90 , \logical_op__rc__ok$89 , \logical_op__rc__rc$88 , \logical_op__imm_data__ok$87 , \logical_op__imm_data__data$86 , \logical_op__fn_unit$85 , \logical_op__insn_type$84 } = { \setup_stage_logical_op__SV_Ptype$78 , \setup_stage_logical_op__sv_ldstmode$77 , \setup_stage_logical_op__sv_saturate$76 , \setup_stage_logical_op__sv_pred_dz$75 , \setup_stage_logical_op__sv_pred_sz$74 , \setup_stage_logical_op__insn$73 , \setup_stage_logical_op__data_len$72 , \setup_stage_logical_op__is_signed$71 , \setup_stage_logical_op__is_32bit$70 , \setup_stage_logical_op__output_carry$69 , \setup_stage_logical_op__write_cr0$68 , \setup_stage_logical_op__invert_out$67 , \setup_stage_logical_op__input_carry$66 , \setup_stage_logical_op__zero_a$65 , \setup_stage_logical_op__invert_in$64 , \setup_stage_logical_op__oe__ok$63 , \setup_stage_logical_op__oe__oe$62 , \setup_stage_logical_op__rc__ok$61 , \setup_stage_logical_op__rc__rc$60 , \setup_stage_logical_op__imm_data__ok$59 , \setup_stage_logical_op__imm_data__data$58 , \setup_stage_logical_op__fn_unit$57 , \setup_stage_logical_op__insn_type$56 };
+ assign \muxid$83 = \setup_stage_muxid$55 ;
+ assign p_valid_i_p_ready_o = \$81 ;
assign n_i_rdy_data = n_ready_i;
- assign \p_valid_i$77 = p_valid_i;
- assign setup_stage_xer_so = \input_xer_so$52 ;
- assign setup_stage_rb = \input_rb$51 ;
- assign setup_stage_ra = \input_ra$50 ;
- assign { setup_stage_logical_op__SV_Ptype, setup_stage_logical_op__sv_saturate, setup_stage_logical_op__sv_pred_dz, setup_stage_logical_op__sv_pred_sz, setup_stage_logical_op__insn, setup_stage_logical_op__data_len, setup_stage_logical_op__is_signed, setup_stage_logical_op__is_32bit, setup_stage_logical_op__output_carry, setup_stage_logical_op__write_cr0, setup_stage_logical_op__invert_out, setup_stage_logical_op__input_carry, setup_stage_logical_op__zero_a, setup_stage_logical_op__invert_in, setup_stage_logical_op__oe__ok, setup_stage_logical_op__oe__oe, setup_stage_logical_op__rc__ok, setup_stage_logical_op__rc__rc, setup_stage_logical_op__imm_data__ok, setup_stage_logical_op__imm_data__data, setup_stage_logical_op__fn_unit, setup_stage_logical_op__insn_type } = { \input_logical_op__SV_Ptype$49 , \input_logical_op__sv_saturate$48 , \input_logical_op__sv_pred_dz$47 , \input_logical_op__sv_pred_sz$46 , \input_logical_op__insn$45 , \input_logical_op__data_len$44 , \input_logical_op__is_signed$43 , \input_logical_op__is_32bit$42 , \input_logical_op__output_carry$41 , \input_logical_op__write_cr0$40 , \input_logical_op__invert_out$39 , \input_logical_op__input_carry$38 , \input_logical_op__zero_a$37 , \input_logical_op__invert_in$36 , \input_logical_op__oe__ok$35 , \input_logical_op__oe__oe$34 , \input_logical_op__rc__ok$33 , \input_logical_op__rc__rc$32 , \input_logical_op__imm_data__ok$31 , \input_logical_op__imm_data__data$30 , \input_logical_op__fn_unit$29 , \input_logical_op__insn_type$28 };
- assign setup_stage_muxid = \input_muxid$27 ;
- assign input_xer_so = \xer_so$26 ;
- assign input_rb = \rb$25 ;
- assign input_ra = \ra$24 ;
- assign { input_logical_op__SV_Ptype, input_logical_op__sv_saturate, input_logical_op__sv_pred_dz, input_logical_op__sv_pred_sz, input_logical_op__insn, input_logical_op__data_len, input_logical_op__is_signed, input_logical_op__is_32bit, input_logical_op__output_carry, input_logical_op__write_cr0, input_logical_op__invert_out, input_logical_op__input_carry, input_logical_op__zero_a, input_logical_op__invert_in, input_logical_op__oe__ok, input_logical_op__oe__oe, input_logical_op__rc__ok, input_logical_op__rc__rc, input_logical_op__imm_data__ok, input_logical_op__imm_data__data, input_logical_op__fn_unit, input_logical_op__insn_type } = { \logical_op__SV_Ptype$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 };
+ assign \p_valid_i$80 = p_valid_i;
+ assign setup_stage_xer_so = \input_xer_so$54 ;
+ assign setup_stage_rb = \input_rb$53 ;
+ assign setup_stage_ra = \input_ra$52 ;
+ assign { setup_stage_logical_op__SV_Ptype, setup_stage_logical_op__sv_ldstmode, setup_stage_logical_op__sv_saturate, setup_stage_logical_op__sv_pred_dz, setup_stage_logical_op__sv_pred_sz, setup_stage_logical_op__insn, setup_stage_logical_op__data_len, setup_stage_logical_op__is_signed, setup_stage_logical_op__is_32bit, setup_stage_logical_op__output_carry, setup_stage_logical_op__write_cr0, setup_stage_logical_op__invert_out, setup_stage_logical_op__input_carry, setup_stage_logical_op__zero_a, setup_stage_logical_op__invert_in, setup_stage_logical_op__oe__ok, setup_stage_logical_op__oe__oe, setup_stage_logical_op__rc__ok, setup_stage_logical_op__rc__rc, setup_stage_logical_op__imm_data__ok, setup_stage_logical_op__imm_data__data, setup_stage_logical_op__fn_unit, setup_stage_logical_op__insn_type } = { \input_logical_op__SV_Ptype$51 , \input_logical_op__sv_ldstmode$50 , \input_logical_op__sv_saturate$49 , \input_logical_op__sv_pred_dz$48 , \input_logical_op__sv_pred_sz$47 , \input_logical_op__insn$46 , \input_logical_op__data_len$45 , \input_logical_op__is_signed$44 , \input_logical_op__is_32bit$43 , \input_logical_op__output_carry$42 , \input_logical_op__write_cr0$41 , \input_logical_op__invert_out$40 , \input_logical_op__input_carry$39 , \input_logical_op__zero_a$38 , \input_logical_op__invert_in$37 , \input_logical_op__oe__ok$36 , \input_logical_op__oe__oe$35 , \input_logical_op__rc__ok$34 , \input_logical_op__rc__rc$33 , \input_logical_op__imm_data__ok$32 , \input_logical_op__imm_data__data$31 , \input_logical_op__fn_unit$30 , \input_logical_op__insn_type$29 };
+ assign setup_stage_muxid = \input_muxid$28 ;
+ assign input_xer_so = \xer_so$27 ;
+ assign input_rb = \rb$26 ;
+ assign input_ra = \ra$25 ;
+ assign { input_logical_op__SV_Ptype, input_logical_op__sv_ldstmode, input_logical_op__sv_saturate, input_logical_op__sv_pred_dz, input_logical_op__sv_pred_sz, input_logical_op__insn, input_logical_op__data_len, input_logical_op__is_signed, input_logical_op__is_32bit, input_logical_op__output_carry, input_logical_op__write_cr0, input_logical_op__invert_out, input_logical_op__input_carry, input_logical_op__zero_a, input_logical_op__invert_in, input_logical_op__oe__ok, input_logical_op__oe__oe, input_logical_op__rc__ok, input_logical_op__rc__rc, input_logical_op__imm_data__ok, input_logical_op__imm_data__data, input_logical_op__fn_unit, input_logical_op__insn_type } = { \logical_op__SV_Ptype$24 , \logical_op__sv_ldstmode$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 };
assign input_muxid = \muxid$1 ;
endmodule
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] dest10__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [1:0] dest10__data_i;
reg [63:0] \cia0__data_o$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input cia0__ren;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [63:0] d_wr10__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] dest11__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [1:0] dest11__data_i;
reg [63:0] \cia1__data_o$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input cia1__ren;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [63:0] d_wr11__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] dest12__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [1:0] dest12__data_i;
reg [63:0] \cia2__data_o$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input cia2__ren;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [63:0] d_wr12__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] dest13__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] dest14__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] dest15__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] dest16__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] dest17__data_i;
wire [4:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [4:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [4:0] q_int = 5'h00;
wire [3:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [3:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [3:0] q_int = 4'h0;
wire [2:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [2:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [2:0] q_int = 3'h0;
wire [2:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [2:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [2:0] q_int = 3'h0;
wire [2:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [2:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [2:0] q_int = 3'h0;
wire [6:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [6:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [6:0] q_int = 7'h00;
wire [1:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [1:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [1:0] q_int = 2'h0;
wire [5:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [5:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [5:0] q_int = 6'h00;
wire [3:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [3:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [3:0] q_int = 4'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.setup_stage" *)
(* generator = "nMigen" *)
-module setup_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, ra, rb, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__SV_Ptype$23 , \xer_so$24 , divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, dividend, divisor_radicand, operation, muxid);
+module setup_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__sv_ldstmode, logical_op__SV_Ptype, ra, rb, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__sv_ldstmode$23 , \logical_op__SV_Ptype$24 , \xer_so$25 , divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, dividend, divisor_radicand, operation, muxid);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" *)
- wire \$25 ;
+ wire \$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" *)
- wire \$27 ;
+ wire \$28 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" *)
- wire \$29 ;
+ wire \$30 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" *)
- wire \$31 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *)
- wire [64:0] \$33 ;
+ wire \$32 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *)
wire [64:0] \$34 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *)
+ wire [64:0] \$35 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [64:0] \$36 ;
+ wire [64:0] \$37 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *)
- wire [64:0] \$38 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *)
- wire [64:0] \$40 ;
+ wire [64:0] \$39 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *)
wire [64:0] \$41 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *)
+ wire [64:0] \$42 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- wire [64:0] \$43 ;
+ wire [64:0] \$44 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *)
- wire [64:0] \$45 ;
+ wire [64:0] \$46 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" *)
- wire \$47 ;
+ wire \$48 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" *)
- wire \$49 ;
+ wire \$50 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" *)
- wire \$51 ;
+ wire \$52 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" *)
- wire \$53 ;
+ wire \$54 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" *)
- wire \$55 ;
+ wire \$56 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" *)
- wire \$57 ;
+ wire \$58 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *)
- wire [31:0] \$59 ;
+ wire [31:0] \$60 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" *)
- wire \$61 ;
+ wire \$62 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *)
- wire [31:0] \$63 ;
+ wire [31:0] \$64 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" *)
- wire [127:0] \$65 ;
+ wire [127:0] \$66 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" *)
- wire [94:0] \$66 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" *)
- wire [190:0] \$69 ;
+ wire [94:0] \$67 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" *)
wire [190:0] \$70 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" *)
+ wire [190:0] \$71 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:52" *)
wire [63:0] abs_dend;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:51" *)
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \logical_op__SV_Ptype$23 ;
+ output [1:0] \logical_op__SV_Ptype$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [3:0] logical_op__data_len;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__rc__rc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \logical_op__rc__rc$6 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] logical_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \logical_op__sv_ldstmode$23 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input logical_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input xer_so;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
- output \xer_so$24 ;
- assign \$25 = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" *) ra[31] : ra[63];
- assign \$27 = \$25 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" *) logical_op__is_signed;
- assign \$29 = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" *) rb[31] : rb[63];
- assign \$31 = \$29 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" *) logical_op__is_signed;
- assign \$34 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *) rb;
- assign \$36 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) rb;
- assign \$38 = divisor_neg ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *) \$34 : \$36 ;
- assign \$41 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *) ra;
- assign \$43 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) ra;
- assign \$45 = dividend_neg ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *) \$41 : \$43 ;
- assign \$47 = abs_dend >= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" *) abs_dor;
- assign \$49 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" *) 7'h1e;
- assign \$51 = \$47 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" *) \$49 ;
- assign \$53 = abs_dend[31:0] >= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" *) abs_dor[31:0];
- assign \$55 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" *) 7'h1e;
- assign \$57 = \$53 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" *) \$55 ;
- assign \$59 = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) 32'd0 : abs_dor[63:32];
- assign \$61 = divisor_radicand == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" *) 1'h0;
- assign \$63 = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) 32'd0 : abs_dend[63:32];
- assign \$66 = abs_dend[31:0] <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" *) 6'h20;
- assign \$65 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" *) \$66 ;
- assign \$70 = abs_dend <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" *) 7'h40;
+ output \xer_so$25 ;
+ assign \$26 = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" *) ra[31] : ra[63];
+ assign \$28 = \$26 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" *) logical_op__is_signed;
+ assign \$30 = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" *) rb[31] : rb[63];
+ assign \$32 = \$30 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" *) logical_op__is_signed;
+ assign \$35 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *) rb;
+ assign \$37 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) rb;
+ assign \$39 = divisor_neg ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *) \$35 : \$37 ;
+ assign \$42 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *) ra;
+ assign \$44 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) ra;
+ assign \$46 = dividend_neg ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *) \$42 : \$44 ;
+ assign \$48 = abs_dend >= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" *) abs_dor;
+ assign \$50 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" *) 7'h1e;
+ assign \$52 = \$48 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" *) \$50 ;
+ assign \$54 = abs_dend[31:0] >= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" *) abs_dor[31:0];
+ assign \$56 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" *) 7'h1e;
+ assign \$58 = \$54 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" *) \$56 ;
+ assign \$60 = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) 32'd0 : abs_dor[63:32];
+ assign \$62 = divisor_radicand == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" *) 1'h0;
+ assign \$64 = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) 32'd0 : abs_dend[63:32];
+ assign \$67 = abs_dend[31:0] <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" *) 6'h20;
+ assign \$66 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" *) \$67 ;
+ assign \$71 = abs_dend <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" *) 7'h40;
always @* begin
if (\initial ) begin end
dividend = 128'h00000000000000000000000000000000;
7'h1d, 7'h2f:
begin
dividend[31:0] = abs_dend[31:0];
- dividend[63:32] = \$63 ;
+ dividend[63:32] = \$64 ;
end
/* \nmigen.decoding = "OP_DIVE/30" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:77" */
casez (logical_op__is_32bit)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:78" */
1'h1:
- dividend = \$65 ;
+ dividend = \$66 ;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:80" */
default:
- dividend = \$69 [127:0];
+ dividend = \$70 [127:0];
endcase
endcase
end
- assign \$33 = \$38 ;
- assign \$40 = \$45 ;
- assign \$69 = \$70 ;
- assign { \logical_op__SV_Ptype$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__SV_Ptype, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
+ assign \$34 = \$39 ;
+ assign \$41 = \$46 ;
+ assign \$70 = \$71 ;
+ assign { \logical_op__SV_Ptype$24 , \logical_op__sv_ldstmode$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__SV_Ptype, logical_op__sv_ldstmode, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
assign \muxid$1 = muxid;
- assign \xer_so$24 = xer_so;
- assign div_by_zero = \$61 ;
- assign divisor_radicand[63:32] = \$59 ;
+ assign \xer_so$25 = xer_so;
+ assign div_by_zero = \$62 ;
+ assign divisor_radicand[63:32] = \$60 ;
assign divisor_radicand[31:0] = abs_dor[31:0];
- assign dive_abs_ov32 = \$57 ;
- assign dive_abs_ov64 = \$51 ;
- assign abs_dend = \$45 [63:0];
- assign abs_dor = \$38 [63:0];
- assign divisor_neg = \$31 ;
- assign dividend_neg = \$27 ;
+ assign dive_abs_ov32 = \$58 ;
+ assign dive_abs_ov64 = \$52 ;
+ assign abs_dend = \$46 [63:0];
+ assign abs_dor = \$39 [63:0];
+ assign divisor_neg = \$32 ;
+ assign dividend_neg = \$28 ;
assign operation = 2'h1;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0" *)
(* generator = "nMigen" *)
-module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__insn, oper_i_alu_shift_rot0__sv_pred_sz, oper_i_alu_shift_rot0__sv_pred_dz, oper_i_alu_shift_rot0__sv_saturate, oper_i_alu_shift_rot0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src3_i, src1_i, src4_i, src5_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, xer_ca_ok, dest3_o, coresync_clk);
+module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__insn, oper_i_alu_shift_rot0__sv_pred_sz, oper_i_alu_shift_rot0__sv_pred_dz, oper_i_alu_shift_rot0__sv_saturate, oper_i_alu_shift_rot0__sv_ldstmode, oper_i_alu_shift_rot0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src3_i, src1_i, src4_i, src5_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, xer_ca_ok, dest3_o, coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
wire \$10 ;
reg alu_shift_rot0_sr_op__rc__rc = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_shift_rot0_sr_op__rc__rc$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] alu_shift_rot0_sr_op__sv_ldstmode = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \alu_shift_rot0_sr_op__sv_ldstmode$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg alu_shift_rot0_sr_op__sv_pred_dz = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output cr_a_ok;
input oper_i_alu_shift_rot0__rc__ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_shift_rot0__rc__rc;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] oper_i_alu_shift_rot0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_shift_rot0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
alu_shift_rot0_sr_op__sv_pred_dz <= \alu_shift_rot0_sr_op__sv_pred_dz$next ;
always @(posedge coresync_clk)
alu_shift_rot0_sr_op__sv_saturate <= \alu_shift_rot0_sr_op__sv_saturate$next ;
+ always @(posedge coresync_clk)
+ alu_shift_rot0_sr_op__sv_ldstmode <= \alu_shift_rot0_sr_op__sv_ldstmode$next ;
always @(posedge coresync_clk)
alu_shift_rot0_sr_op__SV_Ptype <= \alu_shift_rot0_sr_op__SV_Ptype$next ;
always @(posedge coresync_clk)
.sr_op__output_cr(alu_shift_rot0_sr_op__output_cr),
.sr_op__rc__ok(alu_shift_rot0_sr_op__rc__ok),
.sr_op__rc__rc(alu_shift_rot0_sr_op__rc__rc),
+ .sr_op__sv_ldstmode(alu_shift_rot0_sr_op__sv_ldstmode),
.sr_op__sv_pred_dz(alu_shift_rot0_sr_op__sv_pred_dz),
.sr_op__sv_pred_sz(alu_shift_rot0_sr_op__sv_pred_sz),
.sr_op__sv_saturate(alu_shift_rot0_sr_op__sv_saturate),
\alu_shift_rot0_sr_op__sv_pred_sz$next = alu_shift_rot0_sr_op__sv_pred_sz;
\alu_shift_rot0_sr_op__sv_pred_dz$next = alu_shift_rot0_sr_op__sv_pred_dz;
\alu_shift_rot0_sr_op__sv_saturate$next = alu_shift_rot0_sr_op__sv_saturate;
+ \alu_shift_rot0_sr_op__sv_ldstmode$next = alu_shift_rot0_sr_op__sv_ldstmode;
\alu_shift_rot0_sr_op__SV_Ptype$next = alu_shift_rot0_sr_op__SV_Ptype;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *)
casez (cu_issue_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */
1'h1:
- { \alu_shift_rot0_sr_op__SV_Ptype$next , \alu_shift_rot0_sr_op__sv_saturate$next , \alu_shift_rot0_sr_op__sv_pred_dz$next , \alu_shift_rot0_sr_op__sv_pred_sz$next , \alu_shift_rot0_sr_op__insn$next , \alu_shift_rot0_sr_op__is_signed$next , \alu_shift_rot0_sr_op__is_32bit$next , \alu_shift_rot0_sr_op__output_cr$next , \alu_shift_rot0_sr_op__input_cr$next , \alu_shift_rot0_sr_op__output_carry$next , \alu_shift_rot0_sr_op__input_carry$next , \alu_shift_rot0_sr_op__invert_in$next , \alu_shift_rot0_sr_op__write_cr0$next , \alu_shift_rot0_sr_op__oe__ok$next , \alu_shift_rot0_sr_op__oe__oe$next , \alu_shift_rot0_sr_op__rc__ok$next , \alu_shift_rot0_sr_op__rc__rc$next , \alu_shift_rot0_sr_op__imm_data__ok$next , \alu_shift_rot0_sr_op__imm_data__data$next , \alu_shift_rot0_sr_op__fn_unit$next , \alu_shift_rot0_sr_op__insn_type$next } = { oper_i_alu_shift_rot0__SV_Ptype, oper_i_alu_shift_rot0__sv_saturate, oper_i_alu_shift_rot0__sv_pred_dz, oper_i_alu_shift_rot0__sv_pred_sz, oper_i_alu_shift_rot0__insn, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__insn_type };
+ { \alu_shift_rot0_sr_op__SV_Ptype$next , \alu_shift_rot0_sr_op__sv_ldstmode$next , \alu_shift_rot0_sr_op__sv_saturate$next , \alu_shift_rot0_sr_op__sv_pred_dz$next , \alu_shift_rot0_sr_op__sv_pred_sz$next , \alu_shift_rot0_sr_op__insn$next , \alu_shift_rot0_sr_op__is_signed$next , \alu_shift_rot0_sr_op__is_32bit$next , \alu_shift_rot0_sr_op__output_cr$next , \alu_shift_rot0_sr_op__input_cr$next , \alu_shift_rot0_sr_op__output_carry$next , \alu_shift_rot0_sr_op__input_carry$next , \alu_shift_rot0_sr_op__invert_in$next , \alu_shift_rot0_sr_op__write_cr0$next , \alu_shift_rot0_sr_op__oe__ok$next , \alu_shift_rot0_sr_op__oe__oe$next , \alu_shift_rot0_sr_op__rc__ok$next , \alu_shift_rot0_sr_op__rc__rc$next , \alu_shift_rot0_sr_op__imm_data__ok$next , \alu_shift_rot0_sr_op__imm_data__data$next , \alu_shift_rot0_sr_op__fn_unit$next , \alu_shift_rot0_sr_op__insn_type$next } = { oper_i_alu_shift_rot0__SV_Ptype, oper_i_alu_shift_rot0__sv_ldstmode, oper_i_alu_shift_rot0__sv_saturate, oper_i_alu_shift_rot0__sv_pred_dz, oper_i_alu_shift_rot0__sv_pred_sz, oper_i_alu_shift_rot0__insn, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__insn_type };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (coresync_rst)
(* generator = "nMigen" *)
module spr(coresync_rst, spr1__data_o, spr1__addr, spr1__ren, spr1__data_i, \spr1__addr$1 , spr1__wen, coresync_clk);
reg \initial = 0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211" *)
wire [3:0] memory_r_addr;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0" *)
(* generator = "nMigen" *)
-module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, oper_i_alu_spr0__insn, oper_i_alu_spr0__is_32bit, oper_i_alu_spr0__sv_pred_sz, oper_i_alu_spr0__sv_pred_dz, oper_i_alu_spr0__sv_saturate, oper_i_alu_spr0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src1_i, src4_i, src6_i, src5_i, src3_i, src2_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, xer_ca_ok, dest6_o, xer_ov_ok, dest5_o, xer_so_ok, dest4_o, fast1_ok, dest3_o, spr1_ok, dest2_o, coresync_clk);
+module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, oper_i_alu_spr0__insn, oper_i_alu_spr0__is_32bit, oper_i_alu_spr0__sv_pred_sz, oper_i_alu_spr0__sv_pred_dz, oper_i_alu_spr0__sv_saturate, oper_i_alu_spr0__sv_ldstmode, oper_i_alu_spr0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src1_i, src4_i, src6_i, src5_i, src3_i, src2_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, xer_ca_ok, dest6_o, xer_ov_ok, dest5_o, xer_so_ok, dest4_o, fast1_ok, dest3_o, spr1_ok, dest2_o, coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *)
wire \$100 ;
reg alu_spr0_spr_op__is_32bit = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alu_spr0_spr_op__is_32bit$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] alu_spr0_spr_op__sv_ldstmode = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \alu_spr0_spr_op__sv_ldstmode$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg alu_spr0_spr_op__sv_pred_dz = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
output cu_busy_o;
input [6:0] oper_i_alu_spr0__insn_type;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_spr0__is_32bit;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] oper_i_alu_spr0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_spr0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
alu_spr0_spr_op__sv_pred_dz <= \alu_spr0_spr_op__sv_pred_dz$next ;
always @(posedge coresync_clk)
alu_spr0_spr_op__sv_saturate <= \alu_spr0_spr_op__sv_saturate$next ;
+ always @(posedge coresync_clk)
+ alu_spr0_spr_op__sv_ldstmode <= \alu_spr0_spr_op__sv_ldstmode$next ;
always @(posedge coresync_clk)
alu_spr0_spr_op__SV_Ptype <= \alu_spr0_spr_op__SV_Ptype$next ;
always @(posedge coresync_clk)
.spr_op__insn(alu_spr0_spr_op__insn),
.spr_op__insn_type(alu_spr0_spr_op__insn_type),
.spr_op__is_32bit(alu_spr0_spr_op__is_32bit),
+ .spr_op__sv_ldstmode(alu_spr0_spr_op__sv_ldstmode),
.spr_op__sv_pred_dz(alu_spr0_spr_op__sv_pred_dz),
.spr_op__sv_pred_sz(alu_spr0_spr_op__sv_pred_sz),
.spr_op__sv_saturate(alu_spr0_spr_op__sv_saturate),
\alu_spr0_spr_op__sv_pred_sz$next = alu_spr0_spr_op__sv_pred_sz;
\alu_spr0_spr_op__sv_pred_dz$next = alu_spr0_spr_op__sv_pred_dz;
\alu_spr0_spr_op__sv_saturate$next = alu_spr0_spr_op__sv_saturate;
+ \alu_spr0_spr_op__sv_ldstmode$next = alu_spr0_spr_op__sv_ldstmode;
\alu_spr0_spr_op__SV_Ptype$next = alu_spr0_spr_op__SV_Ptype;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *)
casez (cu_issue_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */
1'h1:
- { \alu_spr0_spr_op__SV_Ptype$next , \alu_spr0_spr_op__sv_saturate$next , \alu_spr0_spr_op__sv_pred_dz$next , \alu_spr0_spr_op__sv_pred_sz$next , \alu_spr0_spr_op__is_32bit$next , \alu_spr0_spr_op__insn$next , \alu_spr0_spr_op__fn_unit$next , \alu_spr0_spr_op__insn_type$next } = { oper_i_alu_spr0__SV_Ptype, oper_i_alu_spr0__sv_saturate, oper_i_alu_spr0__sv_pred_dz, oper_i_alu_spr0__sv_pred_sz, oper_i_alu_spr0__is_32bit, oper_i_alu_spr0__insn, oper_i_alu_spr0__fn_unit, oper_i_alu_spr0__insn_type };
+ { \alu_spr0_spr_op__SV_Ptype$next , \alu_spr0_spr_op__sv_ldstmode$next , \alu_spr0_spr_op__sv_saturate$next , \alu_spr0_spr_op__sv_pred_dz$next , \alu_spr0_spr_op__sv_pred_sz$next , \alu_spr0_spr_op__is_32bit$next , \alu_spr0_spr_op__insn$next , \alu_spr0_spr_op__fn_unit$next , \alu_spr0_spr_op__insn_type$next } = { oper_i_alu_spr0__SV_Ptype, oper_i_alu_spr0__sv_ldstmode, oper_i_alu_spr0__sv_saturate, oper_i_alu_spr0__sv_pred_dz, oper_i_alu_spr0__sv_pred_sz, oper_i_alu_spr0__is_32bit, oper_i_alu_spr0__insn, oper_i_alu_spr0__fn_unit, oper_i_alu_spr0__insn_type };
endcase
end
always @* begin
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.spr_main" *)
(* generator = "nMigen" *)
-module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32bit, spr_op__sv_pred_sz, spr_op__sv_pred_dz, spr_op__sv_saturate, spr_op__SV_Ptype, ra, spr1, fast1, xer_so, xer_ov, xer_ca, \muxid$1 , \spr_op__insn_type$2 , \spr_op__fn_unit$3 , \spr_op__insn$4 , \spr_op__is_32bit$5 , \spr_op__sv_pred_sz$6 , \spr_op__sv_pred_dz$7 , \spr_op__sv_saturate$8 , \spr_op__SV_Ptype$9 , o, o_ok, \spr1$10 , spr1_ok, \fast1$11 , fast1_ok, \xer_so$12 , xer_so_ok, \xer_ov$13 , xer_ov_ok, \xer_ca$14 , xer_ca_ok, muxid);
+module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32bit, spr_op__sv_pred_sz, spr_op__sv_pred_dz, spr_op__sv_saturate, spr_op__sv_ldstmode, spr_op__SV_Ptype, ra, spr1, fast1, xer_so, xer_ov, xer_ca, \muxid$1 , \spr_op__insn_type$2 , \spr_op__fn_unit$3 , \spr_op__insn$4 , \spr_op__is_32bit$5 , \spr_op__sv_pred_sz$6 , \spr_op__sv_pred_dz$7 , \spr_op__sv_saturate$8 , \spr_op__sv_ldstmode$9 , \spr_op__SV_Ptype$10 , o, o_ok, \spr1$11 , spr1_ok, \fast1$12 , fast1_ok, \xer_so$13 , xer_so_ok, \xer_ov$14 , xer_ov_ok, \xer_ca$15 , xer_ca_ok, muxid);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *)
- wire \$15 ;
+ wire \$16 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *)
- wire \$17 ;
+ wire \$18 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *)
- wire \$19 ;
+ wire \$20 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *)
- wire \$21 ;
+ wire \$22 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *)
- wire \$23 ;
+ wire \$24 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *)
- wire \$25 ;
+ wire \$26 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90" *)
- wire \$27 ;
+ wire \$28 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] fast1;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [63:0] \fast1$11 ;
- reg [63:0] \fast1$11 ;
+ output [63:0] \fast1$12 ;
+ reg [63:0] \fast1$12 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output fast1_ok;
reg fast1_ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [63:0] spr1;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [63:0] \spr1$10 ;
- reg [63:0] \spr1$10 ;
+ output [63:0] \spr1$11 ;
+ reg [63:0] \spr1$11 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output spr1_ok;
reg spr1_ok;
(* enum_value_01 = "P1" *)
(* enum_value_10 = "P2" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
- output [1:0] \spr_op__SV_Ptype$9 ;
+ output [1:0] \spr_op__SV_Ptype$10 ;
(* enum_base_type = "Function" *)
(* enum_value_000000000000000 = "NONE" *)
(* enum_value_000000000000010 = "ALU" *)
input spr_op__is_32bit;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
output \spr_op__is_32bit$5 ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] spr_op__sv_ldstmode;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ output [1:0] \spr_op__sv_ldstmode$9 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input spr_op__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [1:0] xer_ca;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [1:0] \xer_ca$14 ;
- reg [1:0] \xer_ca$14 ;
+ output [1:0] \xer_ca$15 ;
+ reg [1:0] \xer_ca$15 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_ca_ok;
reg xer_ca_ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input [1:0] xer_ov;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output [1:0] \xer_ov$13 ;
- reg [1:0] \xer_ov$13 ;
+ output [1:0] \xer_ov$14 ;
+ reg [1:0] \xer_ov$14 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_ov_ok;
reg xer_ov_ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *)
input xer_so;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
- output \xer_so$12 ;
- reg \xer_so$12 ;
+ output \xer_so$13 ;
+ reg \xer_so$13 ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
output xer_so_ok;
reg xer_so_ok;
- assign \$15 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001;
- assign \$17 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001;
- assign \$19 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001;
- assign \$21 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001;
- assign \$23 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001;
- assign \$25 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001;
- assign \$27 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90" *) 10'h001;
+ assign \$16 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001;
+ assign \$18 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001;
+ assign \$20 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001;
+ assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001;
+ assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001;
+ assign \$26 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001;
+ assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90" *) 10'h001;
always @* begin
if (\initial ) begin end
- \fast1$11 = 64'h0000000000000000;
+ \fast1$12 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *)
casez (spr_op__insn_type)
/* \nmigen.decoding = "OP_MTSPR/49" */
casez (spr)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:60" */
10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016:
- \fast1$11 = ra;
+ \fast1$12 = ra;
endcase
endcase
end
begin
o = fast1;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90" *)
- casez (\$27 )
+ casez (\$28 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90" */
1'h1:
begin
end
always @* begin
if (\initial ) begin end
- \xer_so$12 = 1'h0;
+ \xer_so$13 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *)
casez (spr_op__insn_type)
/* \nmigen.decoding = "OP_MTSPR/49" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:60" */
10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016:
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *)
- casez (\$15 )
+ casez (\$16 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" */
1'h1:
- \xer_so$12 = ra[31];
+ \xer_so$13 = ra[31];
endcase
endcase
endcase
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:60" */
10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016:
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *)
- casez (\$17 )
+ casez (\$18 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" */
1'h1:
xer_so_ok = 1'h1;
end
always @* begin
if (\initial ) begin end
- \xer_ov$13 = 2'h0;
+ \xer_ov$14 = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *)
casez (spr_op__insn_type)
/* \nmigen.decoding = "OP_MTSPR/49" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:60" */
10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016:
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *)
- casez (\$19 )
+ casez (\$20 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" */
1'h1:
begin
- \xer_ov$13 [0] = ra[30];
- \xer_ov$13 [1] = ra[19];
+ \xer_ov$14 [0] = ra[30];
+ \xer_ov$14 [1] = ra[19];
end
endcase
endcase
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:60" */
10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016:
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *)
- casez (\$21 )
+ casez (\$22 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" */
1'h1:
xer_ov_ok = 1'h1;
end
always @* begin
if (\initial ) begin end
- \xer_ca$14 = 2'h0;
+ \xer_ca$15 = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *)
casez (spr_op__insn_type)
/* \nmigen.decoding = "OP_MTSPR/49" */
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:60" */
10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016:
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *)
- casez (\$23 )
+ casez (\$24 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" */
1'h1:
begin
- \xer_ca$14 [0] = ra[29];
- \xer_ca$14 [1] = ra[18];
+ \xer_ca$15 [0] = ra[29];
+ \xer_ca$15 [1] = ra[18];
end
endcase
endcase
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:60" */
10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016:
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *)
- casez (\$25 )
+ casez (\$26 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" */
1'h1:
xer_ca_ok = 1'h1;
end
always @* begin
if (\initial ) begin end
- \spr1$10 = 64'h0000000000000000;
+ \spr1$11 = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *)
casez (spr_op__insn_type)
/* \nmigen.decoding = "OP_MTSPR/49" */
/* empty */;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:78" */
default:
- \spr1$10 = ra;
+ \spr1$11 = ra;
endcase
endcase
end
- assign { \spr_op__SV_Ptype$9 , \spr_op__sv_saturate$8 , \spr_op__sv_pred_dz$7 , \spr_op__sv_pred_sz$6 , \spr_op__is_32bit$5 , \spr_op__insn$4 , \spr_op__fn_unit$3 , \spr_op__insn_type$2 } = { spr_op__SV_Ptype, spr_op__sv_saturate, spr_op__sv_pred_dz, spr_op__sv_pred_sz, spr_op__is_32bit, spr_op__insn, spr_op__fn_unit, spr_op__insn_type };
+ assign { \spr_op__SV_Ptype$10 , \spr_op__sv_ldstmode$9 , \spr_op__sv_saturate$8 , \spr_op__sv_pred_dz$7 , \spr_op__sv_pred_sz$6 , \spr_op__is_32bit$5 , \spr_op__insn$4 , \spr_op__fn_unit$3 , \spr_op__insn_type$2 } = { spr_op__SV_Ptype, spr_op__sv_ldstmode, spr_op__sv_saturate, spr_op__sv_pred_dz, spr_op__sv_pred_sz, spr_op__is_32bit, spr_op__insn, spr_op__fn_unit, spr_op__insn_type };
assign \muxid$1 = muxid;
assign spr = { spr_op__insn[15:11], spr_op__insn[20:16] };
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.sram4k_0" *)
(* generator = "nMigen" *)
-module sram4k_0(rst, enable, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__ack, sram4k_0_wb__adr, sram4k_0_wb__dat_r, sram4k_0_wb__dat_w, sram4k_0_wb__we, sram4k_0_wb__sel, clk);
+module sram4k_0(enable, coresync_rst, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__ack, sram4k_0_wb__adr, sram4k_0_wb__dat_r, sram4k_0_wb__dat_w, sram4k_0_wb__we, sram4k_0_wb__sel, coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *)
wire \$1 ;
wire \$5 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:44" *)
reg [8:0] a;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
- input clk;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
+ input coresync_clk;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
+ input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:47" *)
reg [63:0] d;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:20" *)
input enable;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:46" *)
wire [63:0] q;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
- input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
output sram4k_0_wb__ack;
reg sram4k_0_wb__ack = 1'h0;
assign \$1 = sram4k_0_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *) sram4k_0_wb__stb;
assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:65" *) sram4k_0_wb__ack;
assign \$5 = wb_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:65" *) \$3 ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
sram4k_0_wb__ack <= \sram4k_0_wb__ack$next ;
spblock_512w64b8w spblock_512w64b8w_0 (
.a(a),
- .clk(clk),
+ .clk(coresync_clk),
.d(d),
.q(q),
.we(we)
\sram4k_0_wb__ack$next = \$5 ;
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (rst)
+ casez (coresync_rst)
1'h1:
\sram4k_0_wb__ack$next = 1'h0;
endcase
(* \nmigen.hierarchy = "test_issuer.ti.sram4k_1" *)
(* generator = "nMigen" *)
-module sram4k_1(rst, enable, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__ack, sram4k_1_wb__adr, sram4k_1_wb__dat_r, sram4k_1_wb__dat_w, sram4k_1_wb__we, sram4k_1_wb__sel, clk);
+module sram4k_1(enable, coresync_rst, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__ack, sram4k_1_wb__adr, sram4k_1_wb__dat_r, sram4k_1_wb__dat_w, sram4k_1_wb__we, sram4k_1_wb__sel, coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *)
wire \$1 ;
wire \$5 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:44" *)
reg [8:0] a;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
- input clk;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
+ input coresync_clk;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
+ input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:47" *)
reg [63:0] d;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:20" *)
input enable;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:46" *)
wire [63:0] q;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
- input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
output sram4k_1_wb__ack;
reg sram4k_1_wb__ack = 1'h0;
assign \$1 = sram4k_1_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *) sram4k_1_wb__stb;
assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:65" *) sram4k_1_wb__ack;
assign \$5 = wb_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:65" *) \$3 ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
sram4k_1_wb__ack <= \sram4k_1_wb__ack$next ;
spblock_512w64b8w spblock_512w64b8w_1 (
.a(a),
- .clk(clk),
+ .clk(coresync_clk),
.d(d),
.q(q),
.we(we)
\sram4k_1_wb__ack$next = \$5 ;
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (rst)
+ casez (coresync_rst)
1'h1:
\sram4k_1_wb__ack$next = 1'h0;
endcase
(* \nmigen.hierarchy = "test_issuer.ti.sram4k_2" *)
(* generator = "nMigen" *)
-module sram4k_2(rst, enable, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__ack, sram4k_2_wb__adr, sram4k_2_wb__dat_r, sram4k_2_wb__dat_w, sram4k_2_wb__we, sram4k_2_wb__sel, clk);
+module sram4k_2(enable, coresync_rst, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__ack, sram4k_2_wb__adr, sram4k_2_wb__dat_r, sram4k_2_wb__dat_w, sram4k_2_wb__we, sram4k_2_wb__sel, coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *)
wire \$1 ;
wire \$5 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:44" *)
reg [8:0] a;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
- input clk;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
+ input coresync_clk;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
+ input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:47" *)
reg [63:0] d;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:20" *)
input enable;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:46" *)
wire [63:0] q;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
- input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
output sram4k_2_wb__ack;
reg sram4k_2_wb__ack = 1'h0;
assign \$1 = sram4k_2_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *) sram4k_2_wb__stb;
assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:65" *) sram4k_2_wb__ack;
assign \$5 = wb_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:65" *) \$3 ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
sram4k_2_wb__ack <= \sram4k_2_wb__ack$next ;
spblock_512w64b8w spblock_512w64b8w_2 (
.a(a),
- .clk(clk),
+ .clk(coresync_clk),
.d(d),
.q(q),
.we(we)
\sram4k_2_wb__ack$next = \$5 ;
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (rst)
+ casez (coresync_rst)
1'h1:
\sram4k_2_wb__ack$next = 1'h0;
endcase
(* \nmigen.hierarchy = "test_issuer.ti.sram4k_3" *)
(* generator = "nMigen" *)
-module sram4k_3(rst, enable, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__ack, sram4k_3_wb__adr, sram4k_3_wb__dat_r, sram4k_3_wb__dat_w, sram4k_3_wb__we, sram4k_3_wb__sel, clk);
+module sram4k_3(enable, coresync_rst, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__ack, sram4k_3_wb__adr, sram4k_3_wb__dat_r, sram4k_3_wb__dat_w, sram4k_3_wb__we, sram4k_3_wb__sel, coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *)
wire \$1 ;
wire \$5 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:44" *)
reg [8:0] a;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
- input clk;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
+ input coresync_clk;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
+ input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:47" *)
reg [63:0] d;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:20" *)
input enable;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:46" *)
wire [63:0] q;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
- input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
output sram4k_3_wb__ack;
reg sram4k_3_wb__ack = 1'h0;
assign \$1 = sram4k_3_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *) sram4k_3_wb__stb;
assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:65" *) sram4k_3_wb__ack;
assign \$5 = wb_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:65" *) \$3 ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
sram4k_3_wb__ack <= \sram4k_3_wb__ack$next ;
spblock_512w64b8w spblock_512w64b8w_3 (
.a(a),
- .clk(clk),
+ .clk(coresync_clk),
.d(d),
.q(q),
.we(we)
\sram4k_3_wb__ack$next = \$5 ;
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (rst)
+ casez (coresync_rst)
1'h1:
\sram4k_3_wb__ack$next = 1'h0;
endcase
wire [3:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [3:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [3:0] q_int = 4'h0;
wire [5:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [5:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [5:0] q_int = 6'h00;
wire [2:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [2:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [2:0] q_int = 3'h0;
wire [4:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [4:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [4:0] q_int = 5'h00;
wire [2:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [2:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [2:0] q_int = 3'h0;
wire [2:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [2:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [2:0] q_int = 3'h0;
wire [4:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [4:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [4:0] q_int = 5'h00;
wire [2:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [2:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [2:0] q_int = 3'h0;
wire [5:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [5:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [5:0] q_int = 6'h00;
wire [2:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [2:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [2:0] q_int = 3'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
reg [63:0] cia__data_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [2:0] cia__ren;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [63:0] data_i;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
(* top = 1 *)
(* generator = "nMigen" *)
module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__tdo, TAP_bus__tdi, TAP_bus__tms, TAP_bus__tck, jtag_wb__adr, jtag_wb__dat_w, jtag_wb__dat_r, jtag_wb__sel, jtag_wb__cyc, jtag_wb__stb, jtag_wb__we, jtag_wb__ack, jtag_wb__err, mspi0_clk__core__o, mspi0_clk__pad__o, mspi0_cs_n__core__o, mspi0_cs_n__pad__o, mspi0_mosi__core__o, mspi0_mosi__pad__o, mspi0_miso__core__i, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_0__pad__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_1__pad__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_2__pad__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_3__pad__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_4__pad__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_5__pad__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_6__pad__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_dq_7__pad__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__core__o, sdr_a_0__pad__o, sdr_a_1__core__o, sdr_a_1__pad__o, sdr_a_2__core__o, sdr_a_2__pad__o, sdr_a_3__core__o, sdr_a_3__pad__o, sdr_a_4__core__o, sdr_a_4__pad__o, sdr_a_5__core__o, sdr_a_5__pad__o, sdr_a_6__core__o, sdr_a_6__pad__o, sdr_a_7__core__o, sdr_a_7__pad__o, sdr_a_8__core__o, sdr_a_8__pad__o, sdr_a_9__core__o, sdr_a_9__pad__o, sdr_ba_0__core__o, sdr_ba_0__pad__o, sdr_ba_1__core__o, sdr_ba_1__pad__o, sdr_clock__core__o, sdr_clock__pad__o, sdr_cke__core__o, sdr_cke__pad__o, sdr_ras_n__core__o, sdr_ras_n__pad__o, sdr_cas_n__core__o, sdr_cas_n__pad__o, sdr_we_n__core__o, sdr_we_n__pad__o, sdr_cs_n__core__o, sdr_cs_n__pad__o, sdr_a_10__core__o, sdr_a_10__pad__o, sdr_a_11__core__o, sdr_a_11__pad__o, sdr_a_12__core__o, sdr_a_12__pad__o, sdr_dm_1__core__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_8__pad__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_9__pad__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_10__pad__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_11__pad__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_12__pad__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_13__pad__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_14__pad__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, sdr_dq_15__pad__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e8__pad__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e9__pad__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e10__pad__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e11__pad__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e12__pad__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e13__pad__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e14__pad__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_e15__pad__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s0__pad__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s1__pad__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s2__pad__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s3__pad__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s4__pad__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s5__pad__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s6__pad__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__core__o, gpio_s7__core__oe, gpio_s7__pad__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_sda__pad__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__core__o, mtwi_scl__pad__o, eint_0__core__i, eint_0__pad__i, eint_1__core__i, eint_1__pad__i, eint_2__core__i, eint_2__pad__i, ibus__adr, ibus__dat_w, ibus__dat_r, ibus__sel, ibus__cyc, ibus__stb, ibus__ack, ibus__we, ibus__err, ibus__cti, ibus__bte, dbus__adr, dbus__dat_w, dbus__dat_r, dbus__sel, dbus__cyc, dbus__stb, dbus__ack, dbus__we, dbus__err, dbus__cti, dbus__bte, sram4k_0_wb__adr, sram4k_0_wb__dat_w, sram4k_0_wb__dat_r, sram4k_0_wb__sel, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__we, sram4k_0_wb__ack, sram4k_1_wb__adr, sram4k_1_wb__dat_w, sram4k_1_wb__dat_r, sram4k_1_wb__sel, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__we, sram4k_1_wb__ack, sram4k_2_wb__adr, sram4k_2_wb__dat_w, sram4k_2_wb__dat_r, sram4k_2_wb__sel, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__we, sram4k_2_wb__ack, sram4k_3_wb__adr, sram4k_3_wb__dat_w, sram4k_3_wb__dat_r, sram4k_3_wb__sel, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__we, sram4k_3_wb__ack, icp_wb__adr, icp_wb__dat_w, icp_wb__dat_r, icp_wb__sel, icp_wb__cyc, icp_wb__stb, icp_wb__ack, icp_wb__we, icp_wb__err, ics_wb__adr, ics_wb__dat_w, ics_wb__dat_r, ics_wb__sel, ics_wb__cyc, ics_wb__stb, ics_wb__ack, ics_wb__we, ics_wb__err, int_level_i, clk, rst, clk_sel_i, pll_test_o, pll_vco_o, pc_i);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:68" *)
input TAP_bus__tck;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:68" *)
input TAP_bus__tdi;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:68" *)
output TAP_bus__tdo;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:68" *)
input TAP_bus__tms;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" *)
output busy_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *)
input clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1238" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1255" *)
input [1:0] clk_sel_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:240" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" *)
input core_bigendian_i;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
input dbus__ack;
output dbus__stb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
output dbus__we;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output eint_0__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input eint_0__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output eint_1__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input eint_1__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output eint_2__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input eint_2__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e10__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e10__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e10__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e10__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e10__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e10__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e11__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e11__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e11__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e11__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e11__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e11__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e12__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e12__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e12__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e12__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e12__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e12__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e13__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e13__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e13__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e13__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e13__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e13__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e14__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e14__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e14__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e14__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e14__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e14__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e15__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e15__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e15__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e15__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e15__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e15__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e8__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e8__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e8__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e8__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e8__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e8__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e9__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e9__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e9__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e9__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e9__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e9__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s0__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s0__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s0__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s0__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s0__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s0__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s1__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s1__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s1__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s1__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s1__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s1__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s2__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s2__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s2__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s2__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s2__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s2__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s3__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s3__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s3__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s3__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s3__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s3__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s4__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s4__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s4__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s4__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s4__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s4__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s5__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s5__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s5__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s5__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s5__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s5__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s6__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s6__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s6__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s6__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s6__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s6__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s7__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s7__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s7__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s7__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s7__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s7__pad__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
input ibus__ack;
output jtag_wb__stb;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *)
output jtag_wb__we;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:242" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:246" *)
input memerr_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input mspi0_clk__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output mspi0_clk__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input mspi0_cs_n__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output mspi0_cs_n__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output mspi0_miso__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input mspi0_miso__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input mspi0_mosi__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output mspi0_mosi__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input mtwi_scl__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output mtwi_scl__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output mtwi_sda__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input mtwi_sda__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input mtwi_sda__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input mtwi_sda__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output mtwi_sda__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output mtwi_sda__pad__oe;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input [63:0] pc_i;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input pc_i_ok;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:237" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" *)
output [63:0] pc_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1236" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1253" *)
output pll_test_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1237" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1254" *)
output pll_vco_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1253" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1270" *)
wire pllclk_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1253" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1270" *)
wire pllclk_rst;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *)
input rst;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_0__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_0__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_10__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_10__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_11__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_11__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_12__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_12__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_1__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_1__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_2__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_2__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_3__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_3__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_4__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_4__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_5__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_5__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_6__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_6__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_7__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_7__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_8__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_8__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_9__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_9__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_ba_0__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_ba_0__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_ba_1__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_ba_1__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_cas_n__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_cas_n__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_cke__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_cke__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_clock__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_clock__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_cs_n__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_cs_n__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dm_0__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dm_0__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dm_1__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dm_1__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_0__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_0__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_0__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_0__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_0__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_0__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_10__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_10__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_10__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_10__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_10__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_10__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_11__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_11__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_11__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_11__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_11__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_11__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_12__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_12__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_12__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_12__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_12__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_12__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_13__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_13__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_13__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_13__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_13__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_13__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_14__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_14__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_14__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_14__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_14__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_14__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_15__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_15__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_15__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_15__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_15__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_15__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_1__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_1__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_1__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_1__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_1__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_1__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_2__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_2__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_2__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_2__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_2__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_2__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_3__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_3__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_3__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_3__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_3__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_3__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_4__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_4__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_4__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_4__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_4__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_4__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_5__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_5__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_5__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_5__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_5__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_5__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_6__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_6__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_6__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_6__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_6__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_6__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_7__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_7__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_7__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_7__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_7__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_7__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_8__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_8__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_8__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_8__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_8__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_8__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_9__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_9__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_9__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_9__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_9__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_9__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_ras_n__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_ras_n__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_we_n__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_we_n__pad__o;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
output sram4k_0_wb__ack;
input sram4k_3_wb__stb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
input sram4k_3_wb__we;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
wire ti_coresync_clk;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" *)
wire wrappll_clk_24_i;
.pll_test_o(wrappll_pll_test_o),
.pll_vco_o(wrappll_pll_vco_o)
);
- assign ti_coresync_clk = pllclk_clk;
+ assign ti_coresync_clk = clk;
assign pllclk_rst = rst;
assign wrappll_clk_sel_i = clk_sel_i;
assign pll_vco_o = wrappll_pll_vco_o;
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *)
wire [6:0] \$101 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$104 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$106 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$108 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:951" *)
wire \$11 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$110 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$112 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$114 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" *)
wire \$116 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" *)
wire \$118 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" *)
wire \$120 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:595" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" *)
wire [7:0] \$122 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:595" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" *)
wire [7:0] \$123 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:596" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:600" *)
wire [7:0] \$125 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:596" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:600" *)
wire [7:0] \$126 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" *)
wire \$128 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:938" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:952" *)
wire [2:0] \$13 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$130 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$132 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$134 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$136 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$138 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:938" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:952" *)
wire [2:0] \$14 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$140 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" *)
wire \$142 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" *)
wire \$144 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:670" *)
wire \$146 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$148 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$150 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$152 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" *)
wire \$154 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" *)
wire \$156 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" *)
wire \$158 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:957" *)
wire \$16 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$160 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$162 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$164 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$166 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$168 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$170 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$172 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$174 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$176 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$178 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:957" *)
wire \$18 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$180 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$182 ;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
wire \$184 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:874" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:878" *)
wire [2:0] \$185 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$188 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$190 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$192 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$194 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$196 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$198 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:957" *)
wire \$20 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" *)
wire \$200 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" *)
wire \$202 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" *)
wire \$204 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$206 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$208 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$210 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$212 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$214 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$216 ;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
wire \$218 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *)
wire [2:0] \$219 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$22 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" *)
wire \$222 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" *)
wire \$224 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:880" *)
wire \$226 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$228 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$230 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$232 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$234 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$236 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$238 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$24 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *)
wire \$240 ;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *)
wire [63:0] \$242 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:869" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873" *)
wire \$244 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:880" *)
wire \$246 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:880" *)
wire \$248 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
wire [63:0] \$250 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
wire [63:0] \$252 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1158" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1176" *)
wire [64:0] \$254 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1158" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1176" *)
wire [64:0] \$255 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1174" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1192" *)
wire [64:0] \$257 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1174" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1192" *)
wire [64:0] \$258 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *)
wire \$26 ;
wire [63:0] \$40 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *)
wire \$42 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$44 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$46 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$48 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" *)
wire \$50 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" *)
wire \$52 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$54 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$56 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$58 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" *)
wire \$60 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" *)
wire \$62 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" *)
wire \$64 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$66 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$68 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
wire \$70 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" *)
wire \$72 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" *)
wire \$74 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$76 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$78 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
wire \$80 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" *)
wire \$82 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" *)
wire \$84 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" *)
wire \$86 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:323" *)
wire \$88 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:323" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" *)
wire [64:0] \$90 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" *)
wire [64:0] \$91 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:57" *)
wire [31:0] \$93 ;
wire [6:0] \$94 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:57" *)
wire [31:0] \$97 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:370" *)
wire [64:0] \$98 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:370" *)
wire [64:0] \$99 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:68" *)
input TAP_bus__tck;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:68" *)
input TAP_bus__tdi;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:68" *)
output TAP_bus__tdo;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:68" *)
input TAP_bus__tms;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" *)
output busy_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *)
input clk;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:105" *)
reg [7:0] core_asmcode = 8'h00;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:105" *)
reg [7:0] \core_asmcode$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:240" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" *)
input core_bigendian_i;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" *)
reg \core_bigendian_i$3 = 1'h0;
reg [1:0] core_core_core__SV_Ptype = 2'h0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
reg [1:0] \core_core_core__SV_Ptype$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
+ reg [1:0] core_core_core__sv_ldstmode = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
+ reg [1:0] \core_core_core__sv_ldstmode$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
reg core_core_core__sv_pred_dz = 1'h0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
reg [2:0] \core_core_xer_in$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:120" *)
wire core_corebusy_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
wire core_coresync_rst;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
reg core_cr_out_ok = 1'h0;
wire [63:0] core_sv__data_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
reg [2:0] core_sv__ren;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:99" *)
wire core_wb_dcache_en;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
reg [2:0] core_wen;
reg core_xer_out = 1'h0;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:116" *)
reg \core_xer_out$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
reg cu_st__rel_o_dly = 1'h0;
wire \cu_st__rel_o_dly$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
wire cu_st__rel_o_rise;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1113" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1131" *)
reg d_cr_delay = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1113" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1131" *)
reg \d_cr_delay$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1103" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1121" *)
reg d_reg_delay = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1103" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1121" *)
reg \d_reg_delay$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1123" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1141" *)
reg d_xer_delay = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1123" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1141" *)
reg \d_xer_delay$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:28" *)
wire [6:0] dbg_core_dbg_core_dbg_dststep;
wire [9:0] dec2_spro;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
wire dec2_spro_ok;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
+ wire [1:0] dec2_sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
wire dec2_sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
wire [2:0] dec2_xer_in;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:116" *)
wire dec2_xer_out;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:950" *)
reg [1:0] delay = 2'h3;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:950" *)
reg [1:0] \delay$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output eint_0__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input eint_0__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output eint_1__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input eint_1__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output eint_2__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input eint_2__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
wire exc_happened;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *)
reg exec_fsm_state = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *)
reg \exec_fsm_state$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1033" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1051" *)
reg exec_insn_ready_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1032" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1050" *)
reg exec_insn_valid_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1037" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1055" *)
reg exec_pc_ready_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1036" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1054" *)
reg exec_pc_valid_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *)
reg [1:0] fetch_fsm_state = 2'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *)
reg [1:0] \fetch_fsm_state$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1021" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1039" *)
reg fetch_insn_ready_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1020" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1038" *)
reg fetch_insn_valid_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1017" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1035" *)
reg fetch_pc_ready_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1016" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1034" *)
reg fetch_pc_valid_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1164" *)
reg [1:0] fsm_state = 2'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1164" *)
reg [1:0] \fsm_state$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e10__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e10__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e10__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e10__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e10__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e10__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e11__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e11__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e11__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e11__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e11__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e11__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e12__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e12__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e12__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e12__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e12__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e12__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e13__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e13__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e13__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e13__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e13__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e13__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e14__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e14__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e14__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e14__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e14__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e14__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e15__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e15__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e15__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e15__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e15__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e15__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e8__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e8__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e8__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e8__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e8__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e8__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e9__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e9__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e9__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_e9__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e9__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_e9__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s0__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s0__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s0__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s0__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s0__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s0__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s1__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s1__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s1__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s1__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s1__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s1__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s2__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s2__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s2__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s2__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s2__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s2__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s3__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s3__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s3__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s3__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s3__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s3__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s4__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s4__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s4__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s4__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s4__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s4__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s5__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s5__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s5__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s5__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s5__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s5__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s6__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s6__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s6__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s6__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s6__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s6__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s7__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s7__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s7__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input gpio_s7__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s7__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output gpio_s7__pad__oe;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
input ibus__ack;
wire [63:0] imem_f_instr_o;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" *)
reg imem_f_valid_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:98" *)
wire imem_wb_icache_en;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:270" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274" *)
reg insn_done;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" *)
input [15:0] int_level_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:775" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *)
reg is_last;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1009" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1027" *)
wire is_svp64_mode;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *)
reg [2:0] issue_fsm_state = 3'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *)
reg [2:0] \issue_fsm_state$next ;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *)
reg jtag_dmi0__ack_o = 1'h0;
output jtag_wb__stb;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *)
output jtag_wb__we;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:100" *)
wire jtag_wb_sram_en;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input mspi0_clk__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output mspi0_clk__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input mspi0_cs_n__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output mspi0_cs_n__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output mspi0_miso__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input mspi0_miso__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input mspi0_mosi__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output mspi0_mosi__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" *)
reg msr_read = 1'h1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" *)
reg \msr_read$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input mtwi_scl__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output mtwi_scl__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output mtwi_sda__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input mtwi_sda__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input mtwi_sda__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input mtwi_sda__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output mtwi_sda__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output mtwi_sda__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1156" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1174" *)
reg [63:0] new_dec;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:28" *)
reg [6:0] new_svstate_dststep;
reg [1:0] new_svstate_svstep;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:30" *)
reg [6:0] new_svstate_vl;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1191" *)
reg [63:0] new_tb;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:594" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" *)
wire [6:0] next_dststep;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:593" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" *)
wire [6:0] next_srcstep;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1016" *)
reg [63:0] nia = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1016" *)
reg [63:0] \nia$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *)
reg [63:0] pc;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:977" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:995" *)
reg pc_changed = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:977" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:995" *)
reg \pc_changed$next ;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input [63:0] pc_i;
(* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *)
input pc_i_ok;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:237" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" *)
output [63:0] pc_o;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *)
reg pc_ok_delay = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *)
reg \pc_ok_delay$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:941" *)
wire por_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1025" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1043" *)
wire pred_insn_ready_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1024" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1042" *)
reg pred_insn_valid_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1029" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1047" *)
reg pred_mask_ready_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1046" *)
wire pred_mask_valid_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *)
input rst;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_0__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_0__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_10__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_10__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_11__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_11__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_12__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_12__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_1__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_1__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_2__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_2__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_3__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_3__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_4__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_4__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_5__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_5__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_6__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_6__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_7__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_7__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_8__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_8__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_a_9__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_a_9__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_ba_0__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_ba_0__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_ba_1__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_ba_1__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_cas_n__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_cas_n__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_cke__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_cke__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_clock__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_clock__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_cs_n__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_cs_n__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dm_0__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dm_0__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dm_1__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dm_1__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_0__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_0__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_0__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_0__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_0__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_0__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_10__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_10__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_10__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_10__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_10__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_10__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_11__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_11__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_11__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_11__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_11__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_11__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_12__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_12__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_12__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_12__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_12__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_12__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_13__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_13__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_13__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_13__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_13__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_13__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_14__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_14__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_14__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_14__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_14__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_14__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_15__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_15__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_15__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_15__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_15__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_15__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_1__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_1__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_1__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_1__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_1__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_1__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_2__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_2__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_2__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_2__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_2__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_2__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_3__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_3__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_3__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_3__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_3__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_3__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_4__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_4__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_4__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_4__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_4__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_4__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_5__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_5__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_5__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_5__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_5__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_5__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_6__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_6__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_6__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_6__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_6__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_6__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_7__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_7__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_7__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_7__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_7__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_7__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_8__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_8__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_8__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_8__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_8__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_8__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_9__core__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_9__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_9__core__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_dq_9__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_9__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_dq_9__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_ras_n__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_ras_n__pad__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
input sdr_we_n__core__o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:76" *)
output sdr_we_n__pad__o;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:20" *)
wire sram4k_0_enable;
input sram4k_3_wb__stb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *)
input sram4k_3_wb__we;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:978" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:996" *)
reg sv_changed = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:978" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:996" *)
reg \sv_changed$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *)
reg [63:0] svstate;
reg svstate_ok_delay = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *)
reg \svstate_ok_delay$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:935" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:949" *)
wire ti_rst;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:586" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:590" *)
reg update_svstate;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" *)
wire xics_icp_core_irq_o;
wire [7:0] xics_ics_icp_o_pri;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" *)
wire [3:0] xics_ics_icp_o_src;
- assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" *) msr_read;
- assign \$99 = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" *) 3'h4;
+ assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:323" *) msr_read;
+ assign \$99 = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:370" *) 3'h4;
assign \$101 = \$98 [2] * (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) 6'h20;
assign \$97 = imem_f_instr_o >> \$101 ;
- assign \$104 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o;
- assign \$106 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst;
- assign \$108 = \$104 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$106 ;
- assign \$110 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o;
- assign \$112 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst;
- assign \$114 = \$110 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$112 ;
- assign \$116 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) sv_changed;
- assign \$118 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) 1'h0;
- assign \$11 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *) 1'h0;
- assign \$120 = \$118 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) is_last;
- assign \$123 = dec2_cur_cur_srcstep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:595" *) 1'h1;
- assign \$126 = dec2_cur_cur_dststep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:596" *) 1'h1;
- assign \$128 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) core_exc_o_happened;
- assign \$130 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o;
- assign \$132 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst;
- assign \$134 = \$130 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$132 ;
- assign \$136 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o;
- assign \$138 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst;
- assign \$140 = \$136 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$138 ;
- assign \$142 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) 1'h0;
- assign \$144 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) \$142 ;
- assign \$146 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" *) is_svp64_mode;
- assign \$148 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o;
- assign \$14 = delay - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:938" *) 1'h1;
- assign \$150 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst;
- assign \$152 = \$148 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$150 ;
- assign \$154 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) sv_changed;
- assign \$156 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) 1'h0;
- assign \$158 = \$156 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) is_last;
- assign \$160 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o;
- assign \$162 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst;
- assign \$164 = \$160 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$162 ;
- assign \$166 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o;
- assign \$168 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst;
- assign \$16 = 1'h0 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *) dbg_core_rst_o;
- assign \$170 = \$166 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$168 ;
- assign \$172 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o;
- assign \$174 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst;
- assign \$176 = \$172 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$174 ;
- assign \$178 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o;
- assign \$180 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst;
- assign \$182 = \$178 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$180 ;
- assign \$185 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:874" *) 1'h1;
+ assign \$104 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) dbg_core_stop_o;
+ assign \$106 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) core_coresync_rst;
+ assign \$108 = \$104 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) \$106 ;
+ assign \$110 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) dbg_core_stop_o;
+ assign \$112 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) core_coresync_rst;
+ assign \$114 = \$110 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) \$112 ;
+ assign \$116 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" *) sv_changed;
+ assign \$118 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" *) 1'h0;
+ assign \$11 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:951" *) 1'h0;
+ assign \$120 = \$118 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" *) is_last;
+ assign \$123 = dec2_cur_cur_srcstep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" *) 1'h1;
+ assign \$126 = dec2_cur_cur_dststep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:600" *) 1'h1;
+ assign \$128 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" *) core_exc_o_happened;
+ assign \$130 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) dbg_core_stop_o;
+ assign \$132 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) core_coresync_rst;
+ assign \$134 = \$130 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) \$132 ;
+ assign \$136 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) dbg_core_stop_o;
+ assign \$138 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) core_coresync_rst;
+ assign \$140 = \$136 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) \$138 ;
+ assign \$142 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" *) 1'h0;
+ assign \$144 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" *) \$142 ;
+ assign \$146 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:670" *) is_svp64_mode;
+ assign \$148 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) dbg_core_stop_o;
+ assign \$14 = delay - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:952" *) 1'h1;
+ assign \$150 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) core_coresync_rst;
+ assign \$152 = \$148 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) \$150 ;
+ assign \$154 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" *) sv_changed;
+ assign \$156 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" *) 1'h0;
+ assign \$158 = \$156 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" *) is_last;
+ assign \$160 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) dbg_core_stop_o;
+ assign \$162 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) core_coresync_rst;
+ assign \$164 = \$160 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) \$162 ;
+ assign \$166 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) dbg_core_stop_o;
+ assign \$168 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) core_coresync_rst;
+ assign \$16 = 1'h0 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:957" *) dbg_core_rst_o;
+ assign \$170 = \$166 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) \$168 ;
+ assign \$172 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) dbg_core_stop_o;
+ assign \$174 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) core_coresync_rst;
+ assign \$176 = \$172 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) \$174 ;
+ assign \$178 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) dbg_core_stop_o;
+ assign \$180 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) core_coresync_rst;
+ assign \$182 = \$178 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) \$180 ;
+ assign \$185 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:878" *) 1'h1;
assign \$184 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$185 ;
- assign \$188 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o;
- assign \$18 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *) rst;
- assign \$190 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst;
- assign \$192 = \$188 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$190 ;
- assign \$194 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o;
- assign \$196 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst;
- assign \$198 = \$194 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$196 ;
- assign \$200 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) sv_changed;
- assign \$202 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) 1'h0;
- assign \$204 = \$202 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) is_last;
- assign \$206 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o;
- assign \$208 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst;
- assign \$20 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *) \$18 ;
- assign \$210 = \$206 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$208 ;
- assign \$212 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o;
- assign \$214 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst;
- assign \$216 = \$212 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$214 ;
- assign \$219 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872" *) 3'h4;
+ assign \$188 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) dbg_core_stop_o;
+ assign \$18 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:957" *) rst;
+ assign \$190 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) core_coresync_rst;
+ assign \$192 = \$188 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) \$190 ;
+ assign \$194 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) dbg_core_stop_o;
+ assign \$196 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) core_coresync_rst;
+ assign \$198 = \$194 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) \$196 ;
+ assign \$200 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" *) sv_changed;
+ assign \$202 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" *) 1'h0;
+ assign \$204 = \$202 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" *) is_last;
+ assign \$206 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) dbg_core_stop_o;
+ assign \$208 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) core_coresync_rst;
+ assign \$20 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:957" *) \$18 ;
+ assign \$210 = \$206 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) \$208 ;
+ assign \$212 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) dbg_core_stop_o;
+ assign \$214 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) core_coresync_rst;
+ assign \$216 = \$212 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) \$214 ;
+ assign \$219 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *) 3'h4;
assign \$218 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$219 ;
- assign \$222 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) 1'h0;
- assign \$224 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) \$222 ;
- assign \$226 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *) core_corebusy_o;
- assign \$228 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o;
+ assign \$222 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" *) 1'h0;
+ assign \$224 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" *) \$222 ;
+ assign \$226 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:880" *) core_corebusy_o;
+ assign \$228 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) dbg_core_stop_o;
assign \$22 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) cu_st__rel_o_dly;
- assign \$230 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst;
- assign \$232 = \$228 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$230 ;
- assign \$234 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o;
- assign \$236 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst;
- assign \$238 = \$234 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$236 ;
- assign \$240 = next_srcstep == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" *) dec2_cur_cur_vl;
+ assign \$230 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) core_coresync_rst;
+ assign \$232 = \$228 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) \$230 ;
+ assign \$234 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) dbg_core_stop_o;
+ assign \$236 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) core_coresync_rst;
+ assign \$238 = \$234 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) \$236 ;
+ assign \$240 = next_srcstep == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) dec2_cur_cur_vl;
assign \$242 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *) { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep };
- assign \$244 = core_core_core_insn_type != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:869" *) 7'h01;
- assign \$246 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *) core_corebusy_o;
- assign \$248 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *) core_corebusy_o;
+ assign \$244 = core_core_core_insn_type != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873" *) 7'h01;
+ assign \$246 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:880" *) core_corebusy_o;
+ assign \$248 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:880" *) core_corebusy_o;
assign \$24 = core_cu_st__rel_o & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$22 ;
assign \$250 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd2__data_o;
assign \$252 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd__data_o;
- assign \$255 = core_issue__data_o - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1158" *) 1'h1;
- assign \$258 = core_issue__data_o + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1174" *) 1'h1;
+ assign \$255 = core_issue__data_o - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1176" *) 1'h1;
+ assign \$258 = core_issue__data_o + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1192" *) 1'h1;
assign \$26 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst;
assign \$28 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) pc_i_ok;
assign \$30 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst;
assign \$38 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst;
assign \$40 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:21" *) svstate_i;
assign \$42 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst;
- assign \$44 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o;
- assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst;
- assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$46 ;
- assign \$50 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) 1'h0;
- assign \$52 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) \$50 ;
- assign \$54 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o;
- assign \$56 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst;
- assign \$58 = \$54 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$56 ;
- assign \$60 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) sv_changed;
- assign \$62 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) 1'h0;
- assign \$64 = \$62 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) is_last;
- assign \$66 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o;
- assign \$68 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst;
- assign \$70 = \$66 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$68 ;
- assign \$72 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) 1'h0;
- assign \$74 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) \$72 ;
- assign \$76 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o;
- assign \$78 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst;
- assign \$80 = \$76 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$78 ;
- assign \$82 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) sv_changed;
- assign \$84 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) 1'h0;
- assign \$86 = \$84 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) is_last;
- assign \$88 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" *) msr_read;
- assign \$91 = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" *) 3'h4;
+ assign \$44 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) dbg_core_stop_o;
+ assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) core_coresync_rst;
+ assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) \$46 ;
+ assign \$50 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" *) 1'h0;
+ assign \$52 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" *) \$50 ;
+ assign \$54 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) dbg_core_stop_o;
+ assign \$56 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) core_coresync_rst;
+ assign \$58 = \$54 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) \$56 ;
+ assign \$60 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" *) sv_changed;
+ assign \$62 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" *) 1'h0;
+ assign \$64 = \$62 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" *) is_last;
+ assign \$66 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) dbg_core_stop_o;
+ assign \$68 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) core_coresync_rst;
+ assign \$70 = \$66 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *) \$68 ;
+ assign \$72 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" *) 1'h0;
+ assign \$74 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" *) \$72 ;
+ assign \$76 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) dbg_core_stop_o;
+ assign \$78 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) core_coresync_rst;
+ assign \$80 = \$76 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *) \$78 ;
+ assign \$82 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" *) sv_changed;
+ assign \$84 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" *) 1'h0;
+ assign \$86 = \$84 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" *) is_last;
+ assign \$88 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:323" *) msr_read;
+ assign \$91 = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" *) 3'h4;
assign \$94 = dec2_cur_pc[2] * (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) 6'h20;
assign \$93 = imem_f_instr_o >> \$94 ;
always @(posedge clk)
fsm_state <= \fsm_state$next ;
always @(posedge clk)
core_eint <= \core_eint$next ;
+ always @(posedge clk)
+ dec2_cur_msr <= \dec2_cur_msr$next ;
always @(posedge clk)
dec2_cur_dec <= \dec2_cur_dec$next ;
always @(posedge clk)
jtag_dmi0__dout <= \jtag_dmi0__dout$next ;
always @(posedge clk)
jtag_dmi0__ack_o <= \jtag_dmi0__ack_o$next ;
- always @(posedge clk)
- dbg_dmi_din <= \dbg_dmi_din$next ;
always @(posedge clk)
core_dec <= \core_dec$next ;
+ always @(posedge clk)
+ dbg_dmi_din <= \dbg_dmi_din$next ;
always @(posedge clk)
dbg_dmi_we_i <= \dbg_dmi_we_i$next ;
always @(posedge clk)
always @(posedge clk)
core_core_core__sv_saturate <= \core_core_core__sv_saturate$next ;
always @(posedge clk)
- core_core_core__SV_Ptype <= \core_core_core__SV_Ptype$next ;
+ core_core_core__sv_ldstmode <= \core_core_core__sv_ldstmode$next ;
always @(posedge clk)
- core_core_core_msr <= \core_core_core_msr$next ;
+ core_core_core__SV_Ptype <= \core_core_core__SV_Ptype$next ;
always @(posedge clk)
\core_bigendian_i$3 <= \core_bigendian_i$3$next ;
+ always @(posedge clk)
+ core_core_core_msr <= \core_core_core_msr$next ;
always @(posedge clk)
core_core_core_cia <= \core_core_core_cia$next ;
always @(posedge clk)
core_core_core_rc_ok <= \core_core_core_rc_ok$next ;
always @(posedge clk)
core_core_core_oe <= \core_core_core_oe$next ;
- always @(posedge clk)
- core_core_core_oe_ok <= \core_core_core_oe_ok$next ;
always @(posedge clk)
core_raw_insn_i <= \core_raw_insn_i$next ;
+ always @(posedge clk)
+ core_core_core_oe_ok <= \core_core_core_oe_ok$next ;
always @(posedge clk)
core_core_core_input_carry <= \core_core_core_input_carry$next ;
always @(posedge clk)
core_core_core_exc_rc_error <= \core_core_core_exc_rc_error$next ;
always @(posedge clk)
core_core_core_exc_segment_fault <= \core_core_core_exc_segment_fault$next ;
- always @(posedge clk)
- core_core_core_exc_happened <= \core_core_core_exc_happened$next ;
always @(posedge clk)
core_core_pc <= \core_core_pc$next ;
+ always @(posedge clk)
+ core_core_core_exc_happened <= \core_core_core_exc_happened$next ;
always @(posedge clk)
core_core_core_trapaddr <= \core_core_core_trapaddr$next ;
always @(posedge clk)
pc_changed <= \pc_changed$next ;
always @(posedge clk)
issue_fsm_state <= \issue_fsm_state$next ;
- always @(posedge clk)
- dec2_raw_opcode_in <= \dec2_raw_opcode_in$next ;
always @(posedge clk)
core_core_msr <= \core_core_msr$next ;
+ always @(posedge clk)
+ dec2_raw_opcode_in <= \dec2_raw_opcode_in$next ;
always @(posedge clk)
nia <= \nia$next ;
always @(posedge clk)
dec2_cur_eint <= \dec2_cur_eint$next ;
always @(posedge clk)
dec2_cur_pc <= \dec2_cur_pc$next ;
- always @(posedge clk)
- dec2_cur_msr <= \dec2_cur_msr$next ;
core core (
.bigendian_i(\core_bigendian_i$3 ),
.cia__data_o(core_cia__data_o),
.cia__ren(core_cia__ren),
.core_core__SV_Ptype(core_core_core__SV_Ptype),
+ .core_core__sv_ldstmode(core_core_core__sv_ldstmode),
.core_core__sv_pred_dz(core_core_core__sv_pred_dz),
.core_core__sv_pred_sz(core_core_core__sv_pred_sz),
.core_core__sv_saturate(core_core_core__sv_saturate),
.spr1_ok(dec2_spr1_ok),
.spro(dec2_spro),
.spro_ok(dec2_spro_ok),
+ .sv_ldstmode(dec2_sv_ldstmode),
.sv_pred_dz(dec2_sv_pred_dz),
.sv_pred_sz(dec2_sv_pred_sz),
.sv_saturate(dec2_sv_saturate),
imem imem (
.a_pc_i(imem_a_pc_i),
.a_valid_i(imem_a_valid_i),
- .clk(clk),
+ .coresync_clk(coresync_clk),
+ .coresync_rst(core_coresync_rst),
.f_busy_o(imem_f_busy_o),
.f_instr_o(imem_f_instr_o),
.f_valid_i(imem_f_valid_i),
.ibus__err(ibus__err),
.ibus__sel(ibus__sel),
.ibus__stb(ibus__stb),
- .rst(rst),
.wb_icache_en(imem_wb_icache_en)
);
jtag jtag (
.wb_sram_en(jtag_wb_sram_en)
);
sram4k_0 sram4k_0 (
- .clk(clk),
+ .coresync_clk(coresync_clk),
+ .coresync_rst(core_coresync_rst),
.enable(sram4k_0_enable),
- .rst(rst),
.sram4k_0_wb__ack(sram4k_0_wb__ack),
.sram4k_0_wb__adr(sram4k_0_wb__adr),
.sram4k_0_wb__cyc(sram4k_0_wb__cyc),
.sram4k_0_wb__we(sram4k_0_wb__we)
);
sram4k_1 sram4k_1 (
- .clk(clk),
+ .coresync_clk(coresync_clk),
+ .coresync_rst(core_coresync_rst),
.enable(sram4k_1_enable),
- .rst(rst),
.sram4k_1_wb__ack(sram4k_1_wb__ack),
.sram4k_1_wb__adr(sram4k_1_wb__adr),
.sram4k_1_wb__cyc(sram4k_1_wb__cyc),
.sram4k_1_wb__we(sram4k_1_wb__we)
);
sram4k_2 sram4k_2 (
- .clk(clk),
+ .coresync_clk(coresync_clk),
+ .coresync_rst(core_coresync_rst),
.enable(sram4k_2_enable),
- .rst(rst),
.sram4k_2_wb__ack(sram4k_2_wb__ack),
.sram4k_2_wb__adr(sram4k_2_wb__adr),
.sram4k_2_wb__cyc(sram4k_2_wb__cyc),
.sram4k_2_wb__we(sram4k_2_wb__we)
);
sram4k_3 sram4k_3 (
- .clk(clk),
+ .coresync_clk(coresync_clk),
+ .coresync_rst(core_coresync_rst),
.enable(sram4k_3_enable),
- .rst(rst),
.sram4k_3_wb__ack(sram4k_3_wb__ack),
.sram4k_3_wb__adr(sram4k_3_wb__adr),
.sram4k_3_wb__cyc(sram4k_3_wb__cyc),
.sram4k_3_wb__we(sram4k_3_wb__we)
);
xics_icp xics_icp (
- .clk(clk),
.core_irq_o(xics_icp_core_irq_o),
+ .coresync_clk(coresync_clk),
+ .coresync_rst(core_coresync_rst),
.icp_wb__ack(icp_wb__ack),
.icp_wb__adr(icp_wb__adr),
.icp_wb__cyc(icp_wb__cyc),
.icp_wb__stb(icp_wb__stb),
.icp_wb__we(icp_wb__we),
.ics_i_pri(xics_icp_ics_i_pri),
- .ics_i_src(xics_icp_ics_i_src),
- .rst(rst)
+ .ics_i_src(xics_icp_ics_i_src)
);
xics_ics xics_ics (
- .clk(clk),
+ .coresync_clk(coresync_clk),
+ .coresync_rst(core_coresync_rst),
.icp_o_pri(xics_ics_icp_o_pri),
.icp_o_src(xics_ics_icp_o_src),
.ics_wb__ack(ics_wb__ack),
.ics_wb__dat_w(ics_wb__dat_w),
.ics_wb__stb(ics_wb__stb),
.ics_wb__we(ics_wb__we),
- .int_level_i(int_level_i),
- .rst(rst)
+ .int_level_i(int_level_i)
);
always @* begin
if (\initial ) begin end
always @* begin
if (\initial ) begin end
\delay$next = delay;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:951" *)
casez (\$11 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:951" */
1'h1:
\delay$next = \$13 [1:0];
endcase
\core_core_srcstep$next = core_core_srcstep;
\core_core_vl$next = core_core_vl;
\core_core_maxvl$next = core_core_maxvl;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" */
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:663" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:669" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */
3'h2:
{ \core_core_maxvl$next , \core_core_vl$next , \core_core_srcstep$next , \core_core_dststep$next , \core_core_subvl$next , \core_core_svstep$next , \core_dec$next , \core_eint$next , \core_core_msr$next , \core_core_pc$next } = { dec2_cur_cur_maxvl, dec2_cur_cur_vl, dec2_cur_cur_srcstep, dec2_cur_cur_dststep, dec2_cur_cur_subvl, dec2_cur_cur_svstep, dec2_cur_dec, dec2_cur_eint, dec2_cur_msr, dec2_cur_pc };
endcase
always @* begin
if (\initial ) begin end
\core_raw_insn_i$next = core_raw_insn_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" */
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:663" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:669" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */
3'h2:
\core_raw_insn_i$next = dec2_raw_opcode_in;
endcase
always @* begin
if (\initial ) begin end
\core_bigendian_i$3$next = \core_bigendian_i$3 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" */
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:663" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:669" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */
3'h2:
\core_bigendian_i$3$next = core_bigendian_i;
endcase
always @* begin
if (\initial ) begin end
exec_insn_valid_i = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" */
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:663" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:669" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */
3'h6:
exec_insn_valid_i = 1'h1;
endcase
if (\initial ) begin end
exec_pc_ready_i = 1'h0;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" */
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:663" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:669" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:757" */
3'h7:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
casez (\$232 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" */
1'h1:
exec_pc_ready_i = 1'h1;
endcase
if (\initial ) begin end
is_last = 1'h0;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" */
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:663" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:669" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:757" */
3'h7:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
casez (\$238 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:776" *)
casez (exec_pc_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:776" */
1'h1:
is_last = \$240 ;
endcase
always @* begin
if (\initial ) begin end
\core_wen$4 = 3'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:833" *)
casez (update_svstate)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:833" */
1'h1:
\core_wen$4 = 3'h4;
endcase
always @* begin
if (\initial ) begin end
\core_data_i$5 = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:833" *)
casez (update_svstate)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:833" */
1'h1:
\core_data_i$5 = \$242 ;
endcase
always @* begin
if (\initial ) begin end
exec_insn_ready_o = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *)
casez (exec_fsm_state)
/* \nmigen.decoding = "INSN_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:862" */
1'h0:
exec_insn_ready_o = 1'h1;
endcase
if (\initial ) begin end
core_ivalid_i = 1'h0;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *)
casez (exec_fsm_state)
/* \nmigen.decoding = "INSN_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:862" */
1'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:864" *)
casez (exec_insn_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:864" */
1'h1:
core_ivalid_i = 1'h1;
endcase
/* \nmigen.decoding = "INSN_ACTIVE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:869" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873" *)
casez (\$244 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:869" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873" */
1'h1:
core_ivalid_i = 1'h1;
endcase
always @* begin
if (\initial ) begin end
core_issue_i = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *)
casez (exec_fsm_state)
/* \nmigen.decoding = "INSN_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:862" */
1'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:864" *)
casez (exec_insn_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:864" */
1'h1:
core_issue_i = 1'h1;
endcase
if (\initial ) begin end
\exec_fsm_state$next = exec_fsm_state;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *)
casez (exec_fsm_state)
/* \nmigen.decoding = "INSN_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:862" */
1'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:864" *)
casez (exec_insn_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:864" */
1'h1:
\exec_fsm_state$next = 1'h1;
endcase
/* \nmigen.decoding = "INSN_ACTIVE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:880" *)
casez (\$246 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:880" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:878" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:882" *)
casez (exec_pc_ready_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:878" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:882" */
1'h1:
\exec_fsm_state$next = 1'h0;
endcase
if (\initial ) begin end
exec_pc_valid_o = 1'h0;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *)
casez (exec_fsm_state)
/* \nmigen.decoding = "INSN_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:862" */
1'h0:
/* empty */;
/* \nmigen.decoding = "INSN_ACTIVE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:880" *)
casez (\$248 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:880" */
1'h1:
exec_pc_valid_o = 1'h1;
endcase
always @* begin
if (\initial ) begin end
core_dmi__addr = 5'h00;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1113" *)
casez (dbg_d_gpr_req)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1113" */
1'h1:
core_dmi__addr = dbg_d_gpr_addr[4:0];
endcase
always @* begin
if (\initial ) begin end
core_dmi__ren = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1113" *)
casez (dbg_d_gpr_req)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1113" */
1'h1:
core_dmi__ren = 1'h1;
endcase
always @* begin
if (\initial ) begin end
dbg_d_gpr_data = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1105" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1123" *)
casez (d_reg_delay)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1105" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1123" */
1'h1:
dbg_d_gpr_data = core_dmi__data_o;
endcase
always @* begin
if (\initial ) begin end
dbg_d_gpr_ack = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1105" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1123" *)
casez (d_reg_delay)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1105" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1123" */
1'h1:
dbg_d_gpr_ack = 1'h1;
endcase
always @* begin
if (\initial ) begin end
core_full_rd2__ren = 8'h00;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1111" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1129" *)
casez (dbg_d_cr_req)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1111" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1129" */
1'h1:
core_full_rd2__ren = 8'hff;
endcase
always @* begin
if (\initial ) begin end
dbg_d_cr_data = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1115" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1133" *)
casez (d_cr_delay)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1115" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1133" */
1'h1:
dbg_d_cr_data = \$250 ;
endcase
always @* begin
if (\initial ) begin end
dbg_d_cr_ack = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1115" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1133" *)
casez (d_cr_delay)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1115" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1133" */
1'h1:
dbg_d_cr_ack = 1'h1;
endcase
always @* begin
if (\initial ) begin end
core_full_rd__ren = 3'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1121" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1139" *)
casez (dbg_d_xer_req)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1121" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1139" */
1'h1:
core_full_rd__ren = 3'h7;
endcase
always @* begin
if (\initial ) begin end
dbg_d_xer_data = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1125" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1143" *)
casez (d_xer_delay)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1125" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1143" */
1'h1:
dbg_d_xer_data = \$252 ;
endcase
always @* begin
if (\initial ) begin end
dbg_d_xer_ack = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1125" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1143" *)
casez (d_xer_delay)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1125" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1143" */
1'h1:
dbg_d_xer_ack = 1'h1;
endcase
always @* begin
if (\initial ) begin end
core_issue__addr = 4'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1164" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1167" */
2'h0:
core_issue__addr = 4'h6;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" */
2'h1:
/* empty */;
/* \nmigen.decoding = "TB_READ/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1166" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1184" */
2'h2:
core_issue__addr = 4'h7;
endcase
always @* begin
if (\initial ) begin end
core_issue__ren = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1164" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1167" */
2'h0:
core_issue__ren = 1'h1;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" */
2'h1:
/* empty */;
/* \nmigen.decoding = "TB_READ/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1166" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1184" */
2'h2:
core_issue__ren = 1'h1;
endcase
always @* begin
if (\initial ) begin end
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1164" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1167" */
2'h0:
\fsm_state$next = 2'h1;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" */
2'h1:
\fsm_state$next = 2'h2;
/* \nmigen.decoding = "TB_READ/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1166" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1184" */
2'h2:
\fsm_state$next = 2'h3;
/* \nmigen.decoding = "TB_WRITE/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1172" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1190" */
2'h3:
\fsm_state$next = 2'h0;
endcase
always @* begin
if (\initial ) begin end
new_dec = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1164" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1167" */
2'h0:
/* empty */;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" */
2'h1:
new_dec = \$254 [63:0];
endcase
if (\initial ) begin end
\core_issue__addr$6 = 4'h0;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1164" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1167" */
2'h0:
/* empty */;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" */
2'h1:
\core_issue__addr$6 = 4'h6;
/* \nmigen.decoding = "TB_READ/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1166" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1184" */
2'h2:
/* empty */;
/* \nmigen.decoding = "TB_WRITE/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1172" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1190" */
2'h3:
\core_issue__addr$6 = 4'h7;
endcase
if (\initial ) begin end
core_issue__wen = 1'h0;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1164" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1167" */
2'h0:
/* empty */;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" */
2'h1:
core_issue__wen = 1'h1;
/* \nmigen.decoding = "TB_READ/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1166" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1184" */
2'h2:
/* empty */;
/* \nmigen.decoding = "TB_WRITE/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1172" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1190" */
2'h3:
core_issue__wen = 1'h1;
endcase
if (\initial ) begin end
core_issue__data_i = 64'h0000000000000000;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1164" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1167" */
2'h0:
/* empty */;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" */
2'h1:
core_issue__data_i = new_dec;
/* \nmigen.decoding = "TB_READ/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1166" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1184" */
2'h2:
/* empty */;
/* \nmigen.decoding = "TB_WRITE/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1172" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1190" */
2'h3:
core_issue__data_i = new_tb;
endcase
if (\initial ) begin end
new_tb = 64'h0000000000000000;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1164" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1167" */
2'h0:
/* empty */;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" */
2'h1:
/* empty */;
/* \nmigen.decoding = "TB_READ/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1166" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1184" */
2'h2:
/* empty */;
/* \nmigen.decoding = "TB_WRITE/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1172" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1190" */
2'h3:
new_tb = \$257 [63:0];
endcase
\dec2_cur_cur_vl$next = dec2_cur_cur_vl;
\dec2_cur_cur_maxvl$next = dec2_cur_cur_maxvl;
\dec2_cur_eint$next = xics_icp_core_irq_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:972" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:990" *)
casez (core_coresync_rst)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:972" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:990" */
1'h1:
{ \dec2_cur_cur_maxvl$next , \dec2_cur_cur_vl$next , \dec2_cur_cur_srcstep$next , \dec2_cur_cur_dststep$next , \dec2_cur_cur_subvl$next , \dec2_cur_cur_svstep$next , \dec2_cur_dec$next , \dec2_cur_eint$next , \dec2_cur_msr$next , \dec2_cur_pc$next } = 225'h000000000000000000000000000000000000000000000000000000000;
endcase
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *)
casez (fetch_fsm_state)
/* \nmigen.decoding = "IDLE/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:301" */
2'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303" *)
casez (fetch_pc_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303" */
1'h1:
begin
\dec2_cur_pc$next = pc;
end
endcase
/* \nmigen.decoding = "INSN_READ/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */
2'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:323" *)
casez (\$9 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:323" */
1'h1:
\dec2_cur_msr$next = core_msr__data_o;
endcase
endcase
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:833" *)
casez (update_svstate)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:833" */
1'h1:
{ \dec2_cur_cur_maxvl$next , \dec2_cur_cur_vl$next , \dec2_cur_cur_srcstep$next , \dec2_cur_cur_dststep$next , \dec2_cur_cur_subvl$next , \dec2_cur_cur_svstep$next } = { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep };
endcase
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1164" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1167" */
2'h0:
/* empty */;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" */
2'h1:
\dec2_cur_dec$next = new_dec;
endcase
if (\initial ) begin end
core_wen = 3'h0;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" */
3'h0:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
casez (\$48 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" *)
casez (pc_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" */
1'h1:
core_wen = 3'h1;
endcase
endcase
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" */
3'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:635" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
casez (fetch_insn_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:635" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" *)
casez (\$52 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" */
1'h1:
core_wen = 3'h1;
endcase
endcase
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:663" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:669" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:757" */
3'h7:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
casez (\$58 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:776" *)
casez (exec_pc_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:776" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" *)
casez ({ \$64 , \$60 })
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" */
2'b?1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */
2'b1?:
core_wen = 3'h1;
endcase
endcase
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:816" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:820" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:819" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" *)
casez (pc_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:819" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" */
1'h1:
core_wen = 3'h1;
endcase
if (\initial ) begin end
core_data_i = 64'h0000000000000000;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" */
3'h0:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
casez (\$70 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" *)
casez (pc_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" */
1'h1:
core_data_i = pc_i;
endcase
endcase
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" */
3'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:635" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
casez (fetch_insn_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:635" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" *)
casez (\$74 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" */
1'h1:
core_data_i = nia;
endcase
endcase
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:663" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:669" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:757" */
3'h7:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
casez (\$80 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:776" *)
casez (exec_pc_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:776" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" *)
casez ({ \$86 , \$82 })
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" */
2'b?1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */
2'b1?:
core_data_i = nia;
endcase
endcase
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:816" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:820" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:819" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" *)
casez (pc_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:819" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" */
1'h1:
core_data_i = pc_i;
endcase
always @* begin
if (\initial ) begin end
core_msr__ren = 3'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *)
casez (fetch_fsm_state)
/* \nmigen.decoding = "IDLE/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:301" */
2'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303" *)
casez (fetch_pc_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303" */
1'h1:
core_msr__ren = 3'h2;
endcase
always @* begin
if (\initial ) begin end
fetch_pc_ready_o = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *)
casez (fetch_fsm_state)
/* \nmigen.decoding = "IDLE/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:301" */
2'h0:
fetch_pc_ready_o = 1'h1;
endcase
always @* begin
if (\initial ) begin end
imem_a_pc_i = 48'h000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *)
casez (fetch_fsm_state)
/* \nmigen.decoding = "IDLE/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:301" */
2'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303" *)
casez (fetch_pc_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303" */
1'h1:
imem_a_pc_i = pc[47:0];
endcase
always @* begin
if (\initial ) begin end
imem_a_valid_i = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *)
casez (fetch_fsm_state)
/* \nmigen.decoding = "IDLE/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:301" */
2'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303" *)
casez (fetch_pc_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303" */
1'h1:
imem_a_valid_i = 1'h1;
endcase
/* \nmigen.decoding = "INSN_READ/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */
2'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" *)
casez (imem_f_busy_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" */
1'h1:
imem_a_valid_i = 1'h1;
endcase
/* \nmigen.decoding = "INSN_READ2/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" */
2'h3:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" *)
casez (imem_f_busy_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" */
1'h1:
imem_a_valid_i = 1'h1;
endcase
always @* begin
if (\initial ) begin end
imem_f_valid_i = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *)
casez (fetch_fsm_state)
/* \nmigen.decoding = "IDLE/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:301" */
2'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303" *)
casez (fetch_pc_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303" */
1'h1:
imem_f_valid_i = 1'h1;
endcase
/* \nmigen.decoding = "INSN_READ/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */
2'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" *)
casez (imem_f_busy_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" */
1'h1:
imem_f_valid_i = 1'h1;
endcase
/* \nmigen.decoding = "INSN_READ2/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" */
2'h3:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" *)
casez (imem_f_busy_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" */
1'h1:
imem_f_valid_i = 1'h1;
endcase
always @* begin
if (\initial ) begin end
\msr_read$next = msr_read;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *)
casez (fetch_fsm_state)
/* \nmigen.decoding = "IDLE/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:301" */
2'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303" *)
casez (fetch_pc_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303" */
1'h1:
\msr_read$next = 1'h0;
endcase
/* \nmigen.decoding = "INSN_READ/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */
2'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:323" *)
casez (\$88 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:323" */
1'h1:
\msr_read$next = 1'h1;
endcase
if (\initial ) begin end
\fetch_fsm_state$next = fetch_fsm_state;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *)
casez (fetch_fsm_state)
/* \nmigen.decoding = "IDLE/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:301" */
2'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303" *)
casez (fetch_pc_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303" */
1'h1:
\fetch_fsm_state$next = 2'h1;
endcase
/* \nmigen.decoding = "INSN_READ/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */
2'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" *)
casez (imem_f_busy_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:330" */
default:
\fetch_fsm_state$next = 2'h2;
endcase
/* \nmigen.decoding = "INSN_READ2/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" */
2'h3:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" *)
casez (imem_f_busy_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368" */
default:
\fetch_fsm_state$next = 2'h2;
endcase
/* \nmigen.decoding = "INSN_READY/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:385" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:389" */
2'h2:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:388" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:392" *)
casez (fetch_insn_ready_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:388" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:392" */
1'h1:
\fetch_fsm_state$next = 2'h0;
endcase
always @* begin
if (\initial ) begin end
\nia$next = nia;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *)
casez (fetch_fsm_state)
/* \nmigen.decoding = "IDLE/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:301" */
2'h0:
/* empty */;
/* \nmigen.decoding = "INSN_READ/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */
2'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" *)
casez (imem_f_busy_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:330" */
default:
\nia$next = \$90 [63:0];
endcase
endcase
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1071" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" *)
casez (core_coresync_rst)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1071" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */
1'h1:
\nia$next = 64'h0000000000000000;
endcase
always @* begin
if (\initial ) begin end
\dec2_raw_opcode_in$next = dec2_raw_opcode_in;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *)
casez (fetch_fsm_state)
/* \nmigen.decoding = "IDLE/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:301" */
2'h0:
/* empty */;
/* \nmigen.decoding = "INSN_READ/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */
2'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" *)
casez (imem_f_busy_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:330" */
default:
\dec2_raw_opcode_in$next = \$93 ;
endcase
/* \nmigen.decoding = "INSN_READ2/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" */
2'h3:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" *)
casez (imem_f_busy_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368" */
default:
\dec2_raw_opcode_in$next = \$97 ;
endcase
if (\initial ) begin end
fetch_insn_valid_o = 1'h0;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *)
casez (fetch_fsm_state)
/* \nmigen.decoding = "IDLE/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:301" */
2'h0:
/* empty */;
/* \nmigen.decoding = "INSN_READ/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */
2'h1:
/* empty */;
/* \nmigen.decoding = "INSN_READ2/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" */
2'h3:
/* empty */;
/* \nmigen.decoding = "INSN_READY/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:385" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:389" */
2'h2:
fetch_insn_valid_o = 1'h1;
endcase
if (\initial ) begin end
{ new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep } = { dec2_cur_cur_maxvl, dec2_cur_cur_vl, dec2_cur_cur_srcstep, dec2_cur_cur_dststep, dec2_cur_cur_subvl, dec2_cur_cur_svstep };
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" */
3'h0:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
casez (\$108 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" *)
casez (svstate_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" */
1'h1:
{ new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep } = svstate_i;
endcase
endcase
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:663" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:669" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:757" */
3'h7:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
casez (\$114 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:776" *)
casez (exec_pc_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:776" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" *)
casez ({ \$120 , \$116 })
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" */
2'b?1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */
2'b1?:
begin
new_svstate_srcstep = 7'h00;
new_svstate_dststep = 7'h00;
end
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:809" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:813" */
default:
begin
new_svstate_srcstep = next_srcstep;
end
endcase
endcase
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:816" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:820" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:827" *)
casez (svstate_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:827" */
1'h1:
{ new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep } = svstate_i;
endcase
always @* begin
if (\initial ) begin end
fetch_pc_valid_i = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" */
3'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
casez (\$134 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */
1'h1:
fetch_pc_valid_i = 1'h1;
endcase
if (\initial ) begin end
\issue_fsm_state$next = issue_fsm_state;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" */
3'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
casez (\$140 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:617" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:621" *)
casez (fetch_pc_ready_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:617" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:621" */
1'h1:
\issue_fsm_state$next = 3'h1;
endcase
endcase
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" */
3'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:635" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
casez (fetch_insn_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:635" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" *)
casez (\$144 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" */
1'h1:
\issue_fsm_state$next = 3'h0;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:648" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:652" */
default:
\issue_fsm_state$next = 3'h2;
endcase
endcase
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
3'h3:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:656" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:660" *)
casez (pred_insn_ready_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:656" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:660" */
1'h1:
\issue_fsm_state$next = 3'h4;
endcase
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:663" */
3'h4:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:661" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" *)
casez (pred_mask_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:661" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
1'h1:
\issue_fsm_state$next = 3'h5;
endcase
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:669" */
3'h5:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:670" *)
casez (\$146 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:670" */
1'h1:
\issue_fsm_state$next = 3'h2;
endcase
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */
3'h2:
\issue_fsm_state$next = 3'h6;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */
3'h6:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:750" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:754" *)
casez (exec_insn_ready_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:750" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:754" */
1'h1:
\issue_fsm_state$next = 3'h7;
endcase
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:757" */
3'h7:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
casez (\$152 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:776" *)
casez (exec_pc_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:776" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" *)
casez ({ \$158 , \$154 })
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" */
2'b?1:
\issue_fsm_state$next = 3'h0;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */
2'b1?:
\issue_fsm_state$next = 3'h0;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:809" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:813" */
default:
\issue_fsm_state$next = 3'h5;
endcase
if (\initial ) begin end
dbg_core_stopped_i = 1'h0;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" */
3'h0:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
casez (\$164 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */
default:
dbg_core_stopped_i = 1'h1;
endcase
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:663" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:669" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:757" */
3'h7:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
casez (\$170 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:816" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:820" */
default:
dbg_core_stopped_i = 1'h1;
endcase
if (\initial ) begin end
\pc_changed$next = pc_changed;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" */
3'h0:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
casez (\$176 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" *)
casez (pc_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" */
1'h1:
\pc_changed$next = 1'h1;
endcase
endcase
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:663" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:669" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:757" */
3'h7:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
casez (\$182 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:816" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:820" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:819" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" *)
casez (pc_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:819" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" */
1'h1:
\pc_changed$next = 1'h1;
endcase
endcase
endcase
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *)
casez (exec_fsm_state)
/* \nmigen.decoding = "INSN_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:862" */
1'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:864" *)
casez (exec_insn_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:864" */
1'h1:
\pc_changed$next = 1'h0;
endcase
/* \nmigen.decoding = "INSN_ACTIVE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:874" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:878" *)
casez (\$184 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:874" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:878" */
1'h1:
\pc_changed$next = 1'h1;
endcase
if (\initial ) begin end
update_svstate = 1'h0;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" */
3'h0:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
casez (\$192 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" *)
casez (svstate_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" */
1'h1:
update_svstate = 1'h1;
endcase
endcase
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:663" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:669" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:757" */
3'h7:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
casez (\$198 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:776" *)
casez (exec_pc_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:776" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" *)
casez ({ \$204 , \$200 })
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" */
2'b?1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */
2'b1?:
update_svstate = 1'h1;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:809" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:813" */
default:
update_svstate = 1'h1;
endcase
endcase
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:816" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:820" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:827" *)
casez (svstate_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:827" */
1'h1:
update_svstate = 1'h1;
endcase
if (\initial ) begin end
\sv_changed$next = sv_changed;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" */
3'h0:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" *)
casez (\$210 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" *)
casez (svstate_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" */
1'h1:
\sv_changed$next = 1'h1;
endcase
endcase
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:663" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:669" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:757" */
3'h7:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" *)
casez (\$216 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:760" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:816" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:820" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:827" *)
casez (svstate_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:827" */
1'h1:
\sv_changed$next = 1'h1;
endcase
endcase
endcase
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *)
casez (exec_fsm_state)
/* \nmigen.decoding = "INSN_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:862" */
1'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:864" *)
casez (exec_insn_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:864" */
1'h1:
\sv_changed$next = 1'h0;
endcase
/* \nmigen.decoding = "INSN_ACTIVE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *)
casez (\$218 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" */
1'h1:
\sv_changed$next = 1'h1;
endcase
always @* begin
if (\initial ) begin end
fetch_insn_ready_i = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" */
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" */
3'h1:
fetch_insn_ready_i = 1'h1;
endcase
always @* begin
if (\initial ) begin end
insn_done = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" */
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" */
3'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:635" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *)
casez (fetch_insn_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:635" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" *)
casez (\$224 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:644" */
1'h1:
insn_done = 1'h1;
endcase
endcase
endcase
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *)
casez (exec_fsm_state)
/* \nmigen.decoding = "INSN_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:862" */
1'h0:
/* empty */;
/* \nmigen.decoding = "INSN_ACTIVE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:880" *)
casez (\$226 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:880" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:878" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:882" *)
casez (exec_pc_ready_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:878" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:882" */
1'h1:
insn_done = 1'h1;
endcase
always @* begin
if (\initial ) begin end
pred_insn_valid_i = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" */
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
3'h3:
pred_insn_valid_i = 1'h1;
endcase
always @* begin
if (\initial ) begin end
pred_mask_ready_i = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" */
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:663" */
3'h4:
pred_mask_ready_i = 1'h1;
endcase
\core_core_core__sv_pred_sz$next = core_core_core__sv_pred_sz;
\core_core_core__sv_pred_dz$next = core_core_core__sv_pred_dz;
\core_core_core__sv_saturate$next = core_core_core__sv_saturate;
+ \core_core_core__sv_ldstmode$next = core_core_core__sv_ldstmode;
\core_core_core__SV_Ptype$next = core_core_core__SV_Ptype;
\core_core_core_msr$next = core_core_core_msr;
\core_core_core_cia$next = core_core_core_cia;
\core_core_core_cr_wr$next = core_core_core_cr_wr;
\core_core_cr_wr_ok$next = core_core_cr_wr_ok;
\core_core_core_is_32bit$next = core_core_core_is_32bit;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *)
casez (issue_fsm_state)
/* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" */
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:663" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:669" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */
3'h2:
- { \core_core_core_is_32bit$next , \core_core_cr_wr_ok$next , \core_core_core_cr_wr$next , \core_core_core_cr_rd_ok$next , \core_core_core_cr_rd$next , \core_core_core_trapaddr$next , \core_core_core_exc_happened$next , \core_core_core_exc_segment_fault$next , \core_core_core_exc_rc_error$next , \core_core_core_exc_perm_error$next , \core_core_core_exc_badtree$next , \core_core_core_exc_invalid$next , \core_core_core_exc_instr_fault$next , \core_core_core_exc_alignment$next , \core_core_core_traptype$next , \core_core_core_input_carry$next , \core_core_core_oe_ok$next , \core_core_core_oe$next , \core_core_core_rc_ok$next , \core_core_core_rc$next , \core_core_lk$next , \core_core_core_fn_unit$next , \core_core_core_insn_type$next , \core_core_core_insn$next , \core_core_core_svstate$next , \core_core_core_cia$next , \core_core_core_msr$next , \core_core_core__SV_Ptype$next , \core_core_core__sv_saturate$next , \core_core_core__sv_pred_dz$next , \core_core_core__sv_pred_sz$next , \core_cr_out_ok$next , \core_core_cr_out$next , \core_core_cr_in2_ok$2$next , \core_core_cr_in2$1$next , \core_core_cr_in2_ok$next , \core_core_cr_in2$next , \core_core_cr_in1_ok$next , \core_core_cr_in1$next , \core_fasto3_ok$next , \core_core_fasto3$next , \core_fasto2_ok$next , \core_core_fasto2$next , \core_fasto1_ok$next , \core_core_fasto1$next , \core_core_fast3_ok$next , \core_core_fast3$next , \core_core_fast2_ok$next , \core_core_fast2$next , \core_core_fast1_ok$next , \core_core_fast1$next , \core_xer_out$next , \core_core_xer_in$next , \core_core_spr1_ok$next , \core_core_spr1$next , \core_spro_ok$next , \core_core_spro$next , \core_core_reg3_ok$next , \core_core_reg3$next , \core_core_reg2_ok$next , \core_core_reg2$next , \core_core_reg1_ok$next , \core_core_reg1$next , \core_ea_ok$next , \core_core_ea$next , \core_rego_ok$next , \core_core_rego$next , \core_asmcode$next } = { dec2_is_32bit, dec2_cr_wr_ok, dec2_cr_wr, dec2_cr_rd_ok, dec2_cr_rd, dec2_trapaddr, dec2_exc_happened, dec2_exc_segment_fault, dec2_exc_rc_error, dec2_exc_perm_error, dec2_exc_badtree, dec2_exc_invalid, dec2_exc_instr_fault, dec2_exc_alignment, dec2_traptype, dec2_input_carry, dec2_oe_ok, dec2_oe, dec2_rc_ok, dec2_rc, dec2_lk, dec2_fn_unit, dec2_insn_type, dec2_insn, dec2_svstate, dec2_cia, dec2_msr, dec2_SV_Ptype, dec2_sv_saturate, dec2_sv_pred_dz, dec2_sv_pred_sz, dec2_cr_out_ok, dec2_cr_out, \dec2_cr_in2_ok$8 , \dec2_cr_in2$7 , dec2_cr_in2_ok, dec2_cr_in2, dec2_cr_in1_ok, dec2_cr_in1, dec2_fasto3_ok, dec2_fasto3, dec2_fasto2_ok, dec2_fasto2, dec2_fasto1_ok, dec2_fasto1, dec2_fast3_ok, dec2_fast3, dec2_fast2_ok, dec2_fast2, dec2_fast1_ok, dec2_fast1, dec2_xer_out, dec2_xer_in, dec2_spr1_ok, dec2_spr1, dec2_spro_ok, dec2_spro, dec2_reg3_ok, dec2_reg3, dec2_reg2_ok, dec2_reg2, dec2_reg1_ok, dec2_reg1, dec2_ea_ok, dec2_ea, dec2_rego_ok, dec2_rego, dec2_asmcode };
+ { \core_core_core_is_32bit$next , \core_core_cr_wr_ok$next , \core_core_core_cr_wr$next , \core_core_core_cr_rd_ok$next , \core_core_core_cr_rd$next , \core_core_core_trapaddr$next , \core_core_core_exc_happened$next , \core_core_core_exc_segment_fault$next , \core_core_core_exc_rc_error$next , \core_core_core_exc_perm_error$next , \core_core_core_exc_badtree$next , \core_core_core_exc_invalid$next , \core_core_core_exc_instr_fault$next , \core_core_core_exc_alignment$next , \core_core_core_traptype$next , \core_core_core_input_carry$next , \core_core_core_oe_ok$next , \core_core_core_oe$next , \core_core_core_rc_ok$next , \core_core_core_rc$next , \core_core_lk$next , \core_core_core_fn_unit$next , \core_core_core_insn_type$next , \core_core_core_insn$next , \core_core_core_svstate$next , \core_core_core_cia$next , \core_core_core_msr$next , \core_core_core__SV_Ptype$next , \core_core_core__sv_ldstmode$next , \core_core_core__sv_saturate$next , \core_core_core__sv_pred_dz$next , \core_core_core__sv_pred_sz$next , \core_cr_out_ok$next , \core_core_cr_out$next , \core_core_cr_in2_ok$2$next , \core_core_cr_in2$1$next , \core_core_cr_in2_ok$next , \core_core_cr_in2$next , \core_core_cr_in1_ok$next , \core_core_cr_in1$next , \core_fasto3_ok$next , \core_core_fasto3$next , \core_fasto2_ok$next , \core_core_fasto2$next , \core_fasto1_ok$next , \core_core_fasto1$next , \core_core_fast3_ok$next , \core_core_fast3$next , \core_core_fast2_ok$next , \core_core_fast2$next , \core_core_fast1_ok$next , \core_core_fast1$next , \core_xer_out$next , \core_core_xer_in$next , \core_core_spr1_ok$next , \core_core_spr1$next , \core_spro_ok$next , \core_core_spro$next , \core_core_reg3_ok$next , \core_core_reg3$next , \core_core_reg2_ok$next , \core_core_reg2$next , \core_core_reg1_ok$next , \core_core_reg1$next , \core_ea_ok$next , \core_core_ea$next , \core_rego_ok$next , \core_core_rego$next , \core_asmcode$next } = { dec2_is_32bit, dec2_cr_wr_ok, dec2_cr_wr, dec2_cr_rd_ok, dec2_cr_rd, dec2_trapaddr, dec2_exc_happened, dec2_exc_segment_fault, dec2_exc_rc_error, dec2_exc_perm_error, dec2_exc_badtree, dec2_exc_invalid, dec2_exc_instr_fault, dec2_exc_alignment, dec2_traptype, dec2_input_carry, dec2_oe_ok, dec2_oe, dec2_rc_ok, dec2_rc, dec2_lk, dec2_fn_unit, dec2_insn_type, dec2_insn, dec2_svstate, dec2_cia, dec2_msr, dec2_SV_Ptype, dec2_sv_ldstmode, dec2_sv_saturate, dec2_sv_pred_dz, dec2_sv_pred_sz, dec2_cr_out_ok, dec2_cr_out, \dec2_cr_in2_ok$8 , \dec2_cr_in2$7 , dec2_cr_in2_ok, dec2_cr_in2, dec2_cr_in1_ok, dec2_cr_in1, dec2_fasto3_ok, dec2_fasto3, dec2_fasto2_ok, dec2_fasto2, dec2_fasto1_ok, dec2_fasto1, dec2_fast3_ok, dec2_fast3, dec2_fast2_ok, dec2_fast2, dec2_fast1_ok, dec2_fast1, dec2_xer_out, dec2_xer_in, dec2_spr1_ok, dec2_spr1, dec2_spro_ok, dec2_spro, dec2_reg3_ok, dec2_reg3, dec2_reg2_ok, dec2_reg2, dec2_reg1_ok, dec2_reg1, dec2_ea_ok, dec2_ea, dec2_rego_ok, dec2_rego, dec2_asmcode };
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
casez (rst)
\core_core_core__sv_pred_sz$next = 1'h0;
\core_core_core__sv_pred_dz$next = 1'h0;
\core_core_core__sv_saturate$next = 2'h0;
+ \core_core_core__sv_ldstmode$next = 2'h0;
\core_core_core__SV_Ptype$next = 2'h0;
\core_core_core_rc_ok$next = 1'h0;
\core_core_core_oe_ok$next = 1'h0;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0" *)
(* generator = "nMigen" *)
-module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_unit, oper_i_alu_trap0__insn, oper_i_alu_trap0__msr, oper_i_alu_trap0__cia, oper_i_alu_trap0__svstate, oper_i_alu_trap0__is_32bit, oper_i_alu_trap0__traptype, oper_i_alu_trap0__trapaddr, oper_i_alu_trap0__ldst_exc, oper_i_alu_trap0__sv_pred_sz, oper_i_alu_trap0__sv_pred_dz, oper_i_alu_trap0__sv_saturate, oper_i_alu_trap0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, src4_i, src5_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, fast1_ok, fast2_ok, fast3_ok, dest2_o, dest3_o, dest4_o, nia_ok, dest5_o, msr_ok, dest6_o, svstate_ok, dest7_o, coresync_clk);
+module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_unit, oper_i_alu_trap0__insn, oper_i_alu_trap0__msr, oper_i_alu_trap0__cia, oper_i_alu_trap0__svstate, oper_i_alu_trap0__is_32bit, oper_i_alu_trap0__traptype, oper_i_alu_trap0__trapaddr, oper_i_alu_trap0__ldst_exc, oper_i_alu_trap0__sv_pred_sz, oper_i_alu_trap0__sv_pred_dz, oper_i_alu_trap0__sv_saturate, oper_i_alu_trap0__sv_ldstmode, oper_i_alu_trap0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, src4_i, src5_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, fast1_ok, fast2_ok, fast3_ok, dest2_o, dest3_o, dest4_o, nia_ok, dest5_o, msr_ok, dest6_o, svstate_ok, dest7_o, coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
wire [4:0] \$100 ;
reg [63:0] alu_trap0_trap_op__msr = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg [63:0] \alu_trap0_trap_op__msr$next ;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] alu_trap0_trap_op__sv_ldstmode = 2'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ reg [1:0] \alu_trap0_trap_op__sv_ldstmode$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg alu_trap0_trap_op__sv_pred_dz = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
output cu_busy_o;
input [7:0] oper_i_alu_trap0__ldst_exc;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input [63:0] oper_i_alu_trap0__msr;
+ (* enum_base_type = "SVP64LDSTmode" *)
+ (* enum_value_00 = "NONE" *)
+ (* enum_value_01 = "INDEXED" *)
+ (* enum_value_10 = "ELSTRIDE" *)
+ (* enum_value_11 = "UNITSTRIDE" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
+ input [1:0] oper_i_alu_trap0__sv_ldstmode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
input oper_i_alu_trap0__sv_pred_dz;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *)
alu_trap0_trap_op__sv_pred_dz <= \alu_trap0_trap_op__sv_pred_dz$next ;
always @(posedge coresync_clk)
alu_trap0_trap_op__sv_saturate <= \alu_trap0_trap_op__sv_saturate$next ;
+ always @(posedge coresync_clk)
+ alu_trap0_trap_op__sv_ldstmode <= \alu_trap0_trap_op__sv_ldstmode$next ;
always @(posedge coresync_clk)
alu_trap0_trap_op__SV_Ptype <= \alu_trap0_trap_op__SV_Ptype$next ;
always @(posedge coresync_clk)
.trap_op__is_32bit(alu_trap0_trap_op__is_32bit),
.trap_op__ldst_exc(alu_trap0_trap_op__ldst_exc),
.trap_op__msr(alu_trap0_trap_op__msr),
+ .trap_op__sv_ldstmode(alu_trap0_trap_op__sv_ldstmode),
.trap_op__sv_pred_dz(alu_trap0_trap_op__sv_pred_dz),
.trap_op__sv_pred_sz(alu_trap0_trap_op__sv_pred_sz),
.trap_op__sv_saturate(alu_trap0_trap_op__sv_saturate),
\alu_trap0_trap_op__sv_pred_sz$next = alu_trap0_trap_op__sv_pred_sz;
\alu_trap0_trap_op__sv_pred_dz$next = alu_trap0_trap_op__sv_pred_dz;
\alu_trap0_trap_op__sv_saturate$next = alu_trap0_trap_op__sv_saturate;
+ \alu_trap0_trap_op__sv_ldstmode$next = alu_trap0_trap_op__sv_ldstmode;
\alu_trap0_trap_op__SV_Ptype$next = alu_trap0_trap_op__SV_Ptype;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *)
casez (cu_issue_i)
/* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */
1'h1:
- { \alu_trap0_trap_op__SV_Ptype$next , \alu_trap0_trap_op__sv_saturate$next , \alu_trap0_trap_op__sv_pred_dz$next , \alu_trap0_trap_op__sv_pred_sz$next , \alu_trap0_trap_op__ldst_exc$next , \alu_trap0_trap_op__trapaddr$next , \alu_trap0_trap_op__traptype$next , \alu_trap0_trap_op__is_32bit$next , \alu_trap0_trap_op__svstate$next , \alu_trap0_trap_op__cia$next , \alu_trap0_trap_op__msr$next , \alu_trap0_trap_op__insn$next , \alu_trap0_trap_op__fn_unit$next , \alu_trap0_trap_op__insn_type$next } = { oper_i_alu_trap0__SV_Ptype, oper_i_alu_trap0__sv_saturate, oper_i_alu_trap0__sv_pred_dz, oper_i_alu_trap0__sv_pred_sz, oper_i_alu_trap0__ldst_exc, oper_i_alu_trap0__trapaddr, oper_i_alu_trap0__traptype, oper_i_alu_trap0__is_32bit, oper_i_alu_trap0__svstate, oper_i_alu_trap0__cia, oper_i_alu_trap0__msr, oper_i_alu_trap0__insn, oper_i_alu_trap0__fn_unit, oper_i_alu_trap0__insn_type };
+ { \alu_trap0_trap_op__SV_Ptype$next , \alu_trap0_trap_op__sv_ldstmode$next , \alu_trap0_trap_op__sv_saturate$next , \alu_trap0_trap_op__sv_pred_dz$next , \alu_trap0_trap_op__sv_pred_sz$next , \alu_trap0_trap_op__ldst_exc$next , \alu_trap0_trap_op__trapaddr$next , \alu_trap0_trap_op__traptype$next , \alu_trap0_trap_op__is_32bit$next , \alu_trap0_trap_op__svstate$next , \alu_trap0_trap_op__cia$next , \alu_trap0_trap_op__msr$next , \alu_trap0_trap_op__insn$next , \alu_trap0_trap_op__fn_unit$next , \alu_trap0_trap_op__insn_type$next } = { oper_i_alu_trap0__SV_Ptype, oper_i_alu_trap0__sv_ldstmode, oper_i_alu_trap0__sv_saturate, oper_i_alu_trap0__sv_pred_dz, oper_i_alu_trap0__sv_pred_sz, oper_i_alu_trap0__ldst_exc, oper_i_alu_trap0__trapaddr, oper_i_alu_trap0__traptype, oper_i_alu_trap0__is_32bit, oper_i_alu_trap0__svstate, oper_i_alu_trap0__cia, oper_i_alu_trap0__msr, oper_i_alu_trap0__insn, oper_i_alu_trap0__fn_unit, oper_i_alu_trap0__insn_type };
endcase
end
always @* begin
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
.a1(\clk_sel_i$2 [1]),
.div_out_test(\pll_test_o$4 ),
.out_v(\clk_pll_o$3 ),
- .\ref (\clk_24_i$1 ),
+ .ref_v(\clk_24_i$1 ),
.vco_test_ana(\pll_vco_o$5 )
);
assign pll_vco_o = \pll_vco_o$5 ;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire [1:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
wire [1:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [1:0] data_i;
(* \nmigen.hierarchy = "test_issuer.ti.xics_icp" *)
(* generator = "nMigen" *)
-module xics_icp(rst, ics_i_src, ics_i_pri, core_irq_o, icp_wb__ack, icp_wb__cyc, icp_wb__dat_r, icp_wb__dat_w, icp_wb__stb, icp_wb__we, icp_wb__adr, icp_wb__sel, clk);
+module xics_icp(ics_i_src, ics_i_pri, core_irq_o, coresync_rst, icp_wb__ack, icp_wb__cyc, icp_wb__dat_r, icp_wb__dat_w, icp_wb__stb, icp_wb__we, icp_wb__adr, icp_wb__sel, coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" *)
wire \$15 ;
wire [31:0] be_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" *)
reg [31:0] be_out;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
- input clk;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" *)
output core_irq_o;
reg core_irq_o = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" *)
reg \core_irq_o$next ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
+ input coresync_clk;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
+ input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" *)
reg [7:0] cppr = 8'h00;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" *)
reg [7:0] min_pri;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" *)
reg [7:0] pending_priority;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
- input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" *)
reg wb_ack = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" *)
assign \$29 = ics_i_pri != (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" *) 8'hff;
assign \$31 = mfrr < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" *) pending_priority;
assign \$7 = wb_ack & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" *) icp_wb__cyc;
- always @(posedge clk)
+ always @(posedge coresync_clk)
core_irq_o <= \core_irq_o$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
xisr <= \xisr$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
cppr <= \cppr$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
mfrr <= \mfrr$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
irq <= \irq$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
wb_rd_data <= \wb_rd_data$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
wb_ack <= \wb_ack$next ;
always @* begin
if (\initial ) begin end
{ \wb_ack$next , \wb_rd_data$next , \irq$next , \mfrr$next , \cppr$next , \xisr$next } = { \wb_ack$6 , \wb_rd_data$5 , \irq$4 , \mfrr$3 , \cppr$2 , \xisr$1 };
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (rst)
+ casez (coresync_rst)
1'h1:
begin
\xisr$next = 24'h000000;
if (\initial ) begin end
\core_irq_o$next = irq;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (rst)
+ casez (coresync_rst)
1'h1:
\core_irq_o$next = 1'h0;
endcase
(* \nmigen.hierarchy = "test_issuer.ti.xics_ics" *)
(* generator = "nMigen" *)
-module xics_ics(rst, icp_o_src, icp_o_pri, ics_wb__adr, int_level_i, ics_wb__cyc, ics_wb__stb, ics_wb__dat_r, ics_wb__ack, ics_wb__dat_w, ics_wb__we, clk);
+module xics_ics(icp_o_src, icp_o_pri, coresync_rst, ics_wb__adr, int_level_i, ics_wb__cyc, ics_wb__stb, ics_wb__dat_r, ics_wb__ack, ics_wb__dat_w, ics_wb__we, coresync_clk);
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" *)
wire \$1 ;
wire [31:0] be_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308" *)
reg [31:0] be_out;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
- input clk;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
+ input coresync_clk;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
+ input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *)
reg [3:0] cur_idx0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *)
wire reg_is_debug;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286" *)
wire reg_is_xive;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
- input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260" *)
wire wb_valid;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
assign \$93 = int_level_l[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$91 ;
assign \$95 = xive2_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri1;
assign \$97 = int_level_l[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$95 ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
icp_o_src <= cur_idx15;
- always @(posedge clk)
+ always @(posedge coresync_clk)
icp_o_pri <= \$203 ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
xive0_pri <= \xive0_pri$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
xive1_pri <= \xive1_pri$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
xive2_pri <= \xive2_pri$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
xive3_pri <= \xive3_pri$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
xive4_pri <= \xive4_pri$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
xive5_pri <= \xive5_pri$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
xive6_pri <= \xive6_pri$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
xive7_pri <= \xive7_pri$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
xive8_pri <= \xive8_pri$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
xive9_pri <= \xive9_pri$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
xive10_pri <= \xive10_pri$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
xive11_pri <= \xive11_pri$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
xive12_pri <= \xive12_pri$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
xive13_pri <= \xive13_pri$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
xive14_pri <= \xive14_pri$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
xive15_pri <= \xive15_pri$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
ics_wb__ack <= \ics_wb__ack$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
ics_wb__dat_r <= \ics_wb__dat_r$next ;
- always @(posedge clk)
+ always @(posedge coresync_clk)
int_level_l <= \int_level_l$next ;
always @* begin
if (\initial ) begin end
endcase
endcase
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (rst)
+ casez (coresync_rst)
1'h1:
begin
\xive0_pri$next = 8'hff;
if (\initial ) begin end
\int_level_l$next = int_level_i;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (rst)
+ casez (coresync_rst)
1'h1:
\int_level_l$next = 16'h0000;
endcase
if (\initial ) begin end
\ics_wb__dat_r$next = { be_out[7:0], be_out[15:8], be_out[23:16], be_out[31:24] };
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (rst)
+ casez (coresync_rst)
1'h1:
\ics_wb__dat_r$next = 32'd0;
endcase
if (\initial ) begin end
\ics_wb__ack$next = wb_valid;
(* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
- casez (rst)
+ casez (coresync_rst)
1'h1:
\ics_wb__ack$next = 1'h0;
endcase
projects / soclayout.git / commitdiff