*/
int r300FlushCmdBufLocked(r300ContextPtr r300, const char *caller)
{
- int ret;
+ int ret = 0;
if (r300->cmdbuf.flushing) {
fprintf(stderr, "Recursive call into r300FlushCmdBufLocked!\n");
exit(-1);
}
r300->cmdbuf.flushing = 1;
- ret = radeon_cs_emit(r300->cmdbuf.cs);
+ if (r300->cmdbuf.cs->cdw) {
+ ret = radeon_cs_emit(r300->cmdbuf.cs);
+ }
radeon_cs_erase(r300->cmdbuf.cs);
r300->cmdbuf.flushing = 0;
return ret;
} else if (!t) {
OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]);
} else {
- OUT_BATCH(t->override_offset);
+ if (t->bo) {
+ OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, 0);
+ } else {
+ OUT_BATCH(t->override_offset);
+ }
}
END_BATCH();
}
0,
};
+static void r300RunPipeline(GLcontext * ctx)
+{
+ _mesa_lock_context_textures(ctx);
+
+ if (ctx->NewState)
+ _mesa_update_state_locked(ctx);
+
+ _tnl_run_pipeline(ctx);
+ _mesa_unlock_context_textures(ctx);
+}
+
/* Create the device specific rendering context.
*/
GLboolean r300CreateContext(const __GLcontextModes * glVisual,
if (!(screen->chip_flags & RADEON_CHIPSET_TCL))
r300InitSwtcl(ctx);
- TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline;
+ TNL_CONTEXT(ctx)->Driver.RunPipeline = r300RunPipeline;
tcl_mode = driQueryOptioni(&r300->radeon.optionCache, "tcl_mode");
if (driQueryOptionb(&r300->radeon.optionCache, "no_rast")) {
/* end hardware registers */
GLuint tile_bits; /* hw texture tile bits used on this texture */
+ struct radeon_bo *bo;
};
static INLINE r300TexObj* r300_tex_obj(struct gl_texture_object *texObj)
#include "r300_mipmap_tree.h"
#include "r300_tex.h"
#include "r300_reg.h"
+#include "radeon_buffer.h"
#define VALID_FORMAT(f) ( ((f) <= MESA_FORMAT_RGBA_DXT5 \
|| ((f) >= MESA_FORMAT_RGBA_FLOAT32 && \
r300_texture_image *baseimage = get_r300_texture_image(texObj->Image[0][texObj->BaseLevel]);
int face, level;
- if (t->validated)
+ if (t->validated || t->image_override)
return GL_TRUE;
if (RADEON_DEBUG & DEBUG_TEXTURE)
if (!offset)
return;
-
+ t->bo = NULL;
t->override_offset = offset;
t->pitch_reg &= (1 << 13) -1;
pitch_val = pitch;
t->pitch_reg |= pitch_val;
}
+
+void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv)
+{
+ struct gl_texture_unit *texUnit;
+ struct gl_texture_object *texObj;
+ struct gl_texture_image *texImage;
+ struct radeon_renderbuffer *rb;
+ radeonContextPtr radeon;
+ r300ContextPtr rmesa;
+ GLframebuffer *fb;
+ r300TexObjPtr t;
+ uint32_t pitch_val;
+
+ target = GL_TEXTURE_RECTANGLE_ARB;
+ radeon = pDRICtx->driverPrivate;
+ rmesa = pDRICtx->driverPrivate;
+ fb = dPriv->driverPrivate;
+ texUnit = &radeon->glCtx->Texture.Unit[radeon->glCtx->Texture.CurrentUnit];
+ texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target);
+ texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0);
+
+ radeon_update_renderbuffers(pDRICtx, dPriv);
+ rb = (void*)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
+ if (rb->bo == NULL) {
+ /* Failed to BO for the buffer */
+ return;
+ }
+
+ _mesa_lock_texture(radeon->glCtx, texObj);
+ _mesa_init_teximage_fields(radeon->glCtx, target, texImage,
+ rb->width, rb->height, rb->cpp, 0, rb->cpp);
+ texImage->TexFormat = &_mesa_texformat_rgba8888_rev;
+
+ t = r300_tex_obj(texObj);
+ if (t == NULL) {
+ return;
+ }
+ t->bo = rb->bo;
+ t->tile_bits = 0;
+ t->image_override = GL_TRUE;
+ t->override_offset = 0;
+ t->pitch_reg &= (1 << 13) -1;
+ pitch_val = rb->pitch;
+ switch (rb->cpp) {
+ case 4:
+ t->format = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8);
+ t->filter |= tx_table[2].filter;
+ pitch_val /= 4;
+ break;
+ case 3:
+ default:
+ t->format = R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8);
+ t->filter |= tx_table[4].filter;
+ pitch_val /= 4;
+ break;
+ case 2:
+ t->format = R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5);
+ t->filter |= tx_table[5].filter;
+ pitch_val /= 2;
+ break;
+ }
+ pitch_val--;
+ t->size = ((rb->width - 1) << R300_TX_WIDTHMASK_SHIFT) |
+ ((rb->height - 1) << R300_TX_HEIGHTMASK_SHIFT);
+ t->size |= R300_TX_SIZE_TXPITCH_EN;
+ t->pitch_reg |= pitch_val;
+ t->validated = GL_TRUE;
+ _mesa_unlock_texture(radeon->glCtx, texObj);
+ return;
+}
rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
rb->cpp = buffers[i].cpp;
rb->pitch = buffers[i].pitch;
+ rb->width = drawable->w;
rb->height = drawable->h;
rb->has_surface = 0;
rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
rb->cpp = buffers[i].cpp;
rb->pitch = buffers[i].pitch;
+ rb->width = drawable->w;
rb->height = drawable->h;
rb->has_surface = 0;
rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer;
rb->cpp = buffers[i].cpp;
rb->pitch = buffers[i].pitch;
+ rb->width = drawable->w;
rb->height = drawable->h;
rb->has_surface = 0;
rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
unsigned int cpp;
/* unsigned int offset; */
unsigned int pitch;
+ unsigned int width;
unsigned int height;
/* boo Xorg 6.8.2 compat */
radeon_cs_write_dword(cs, ull >> 32);
radeon_cs_write_dword(cs, 0);
-
r = cs_process_relocs(cs);
if (r) {
return 0;
return r;
}
cs_set_age(cs);
- for (int i = 0; i < cs->cdw; i++) {
- fprintf(stderr, "pkt[%04d]=0x%08X\n", i, cs->packets[i]);
- }
- exit(0);
return 0;
}
return (cs->relocs_total_size > (7*1024*1024));
}
-struct radeon_cs_funcs radeon_cs_funcs = {
+static struct radeon_cs_funcs radeon_cs_legacy_funcs = {
cs_create,
cs_write_dword,
cs_write_reloc,
if (csm == NULL) {
return NULL;
}
- csm->base.funcs = &radeon_cs_funcs;
+ csm->base.funcs = &radeon_cs_legacy_funcs;
csm->base.fd = ctx->dri.fd;
csm->ctx = ctx;
csm->pending_age = 1;
{ __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
r300SetTexOffset,
};
+
+void r300SetTexBuffer(__DRIcontext *pDRICtx,
+ GLint target,
+ __DRIdrawable *dPriv);
+static const __DRItexBufferExtension r300TexBufferExtension = {
+ { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
+ r300SetTexBuffer,
+};
#endif
/* Create the device specific screen private data struct.
#endif
#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
- //screen->extensions[i++] = &r300texOffsetExtension.base;
+ screen->extensions[i++] = &r300texOffsetExtension.base;
+ screen->extensions[i++] = &r300TexBufferExtension.base;
#endif
screen->extensions[i++] = NULL;
static const
__DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp)
{
- fprintf(stderr, "DRI2 initialization\n");
-
/* Calling driInitExtensions here, with a NULL context pointer,
* does not actually enable the extensions. It just makes sure
* that all the dispatch offsets for all the extensions that
return NULL;
}
- fprintf(stderr, "DRI2 initialized\n");
-
/* for now fill in all modes */
return radeonFillInModes( psp, 24, 24, 8, 1);
}
.CopySubBuffer = r200CopySubBuffer,
};
#endif
+
/* Configuration cache with default values for all contexts */
driOptionCache optionCache;
- const __DRIextension *extensions[8];
+ const __DRIextension *extensions[16];
int num_gb_pipes;
drm_radeon_sarea_t *sarea; /* Private SAREA data */