r300: SetTex extension support
authorJerome Glisse <glisse@freedesktop.org>
Wed, 12 Nov 2008 13:02:57 +0000 (14:02 +0100)
committerJerome Glisse <glisse@freedesktop.org>
Fri, 14 Nov 2008 10:26:17 +0000 (11:26 +0100)
src/mesa/drivers/dri/r300/r300_cmdbuf.c
src/mesa/drivers/dri/r300/r300_context.c
src/mesa/drivers/dri/r300/r300_context.h
src/mesa/drivers/dri/r300/r300_texstate.c
src/mesa/drivers/dri/r300/radeon_context.c
src/mesa/drivers/dri/radeon/radeon_buffer.h
src/mesa/drivers/dri/radeon/radeon_cs_legacy.c
src/mesa/drivers/dri/radeon/radeon_screen.c
src/mesa/drivers/dri/radeon/radeon_screen.h

index dbb7761b3b576c0f92b8914a2c2bcf5fdcc82385..9552778f54101db5335211b44a0f9967f9fc16da 100644 (file)
@@ -74,14 +74,16 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
 int r300FlushCmdBufLocked(r300ContextPtr r300, const char *caller)
 {
-       int ret;
+       int ret = 0;
 
        if (r300->cmdbuf.flushing) {
                fprintf(stderr, "Recursive call into r300FlushCmdBufLocked!\n");
                exit(-1);
        }
        r300->cmdbuf.flushing = 1;
-    ret = radeon_cs_emit(r300->cmdbuf.cs);
+    if (r300->cmdbuf.cs->cdw) {
+        ret = radeon_cs_emit(r300->cmdbuf.cs);
+    }
     radeon_cs_erase(r300->cmdbuf.cs);
        r300->cmdbuf.flushing = 0;
        return ret;
@@ -299,7 +301,11 @@ static void emit_tex_offsets(r300ContextPtr r300, struct r300_state_atom * atom)
                        } else if (!t) {
                                OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]);
                        } else {
-                               OUT_BATCH(t->override_offset);
+                if (t->bo) {
+                    OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, 0);
+                } else {
+                               OUT_BATCH(t->override_offset);
+                }
                        }
             END_BATCH();
                }
index c1e11d5e43bb97841e13c90bb98bf402bdca7c60..5fce8413bbdc829174061262ba05df99974e8f39 100644 (file)
@@ -176,6 +176,17 @@ static const struct tnl_pipeline_stage *r300_pipeline[] = {
        0,
 };
 
+static void r300RunPipeline(GLcontext * ctx)
+{
+    _mesa_lock_context_textures(ctx);
+
+    if (ctx->NewState)
+        _mesa_update_state_locked(ctx);
+    
+    _tnl_run_pipeline(ctx);
+    _mesa_unlock_context_textures(ctx);
+}
+
 /* Create the device specific rendering context.
  */
 GLboolean r300CreateContext(const __GLcontextModes * glVisual,
@@ -348,7 +359,7 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual,
        if (!(screen->chip_flags & RADEON_CHIPSET_TCL))
                r300InitSwtcl(ctx);
 
-       TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline;
+       TNL_CONTEXT(ctx)->Driver.RunPipeline = r300RunPipeline;
 
        tcl_mode = driQueryOptioni(&r300->radeon.optionCache, "tcl_mode");
        if (driQueryOptionb(&r300->radeon.optionCache, "no_rast")) {
index 63bf67e76e8b9db6f942e36653f31d74a21254d7..aec03a81e045ea59ccdb6783f1fafd7e30c394d1 100644 (file)
@@ -176,6 +176,7 @@ struct r300_tex_obj {
        /* end hardware registers */
 
        GLuint tile_bits;       /* hw texture tile bits used on this texture */
+    struct radeon_bo *bo;
 };
 
 static INLINE r300TexObj* r300_tex_obj(struct gl_texture_object *texObj)
index 33673fa0b9c4b62c0437778d412205d51378862a..9153646aa731db6a9078418a26022a43082b8a84 100644 (file)
@@ -51,6 +51,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "r300_mipmap_tree.h"
 #include "r300_tex.h"
 #include "r300_reg.h"
+#include "radeon_buffer.h"
 
 #define VALID_FORMAT(f) ( ((f) <= MESA_FORMAT_RGBA_DXT5                        \
                           || ((f) >= MESA_FORMAT_RGBA_FLOAT32 &&       \
@@ -328,7 +329,7 @@ static GLboolean r300_validate_texture(GLcontext * ctx, struct gl_texture_object
        r300_texture_image *baseimage = get_r300_texture_image(texObj->Image[0][texObj->BaseLevel]);
        int face, level;
 
-       if (t->validated)
+       if (t->validated || t->image_override)
                return GL_TRUE;
 
        if (RADEON_DEBUG & DEBUG_TEXTURE)
@@ -430,7 +431,7 @@ void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
 
        if (!offset)
                return;
-
+    t->bo = NULL;
        t->override_offset = offset;
        t->pitch_reg &= (1 << 13) -1;
        pitch_val = pitch;
@@ -457,3 +458,73 @@ void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
 
        t->pitch_reg |= pitch_val;
 }
+
+void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv)
+{
+    struct gl_texture_unit *texUnit;
+    struct gl_texture_object *texObj;
+    struct gl_texture_image *texImage;
+       struct radeon_renderbuffer *rb;
+       radeonContextPtr radeon;
+       r300ContextPtr rmesa;
+       GLframebuffer *fb;
+       r300TexObjPtr t;
+       uint32_t pitch_val;
+
+    target = GL_TEXTURE_RECTANGLE_ARB;
+       radeon = pDRICtx->driverPrivate;
+       rmesa = pDRICtx->driverPrivate;
+       fb = dPriv->driverPrivate;
+    texUnit = &radeon->glCtx->Texture.Unit[radeon->glCtx->Texture.CurrentUnit];
+    texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target);
+    texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0);
+
+    radeon_update_renderbuffers(pDRICtx, dPriv);
+    rb = (void*)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
+    if (rb->bo == NULL) {
+        /* Failed to BO for the buffer */
+        return;
+    }
+
+    _mesa_lock_texture(radeon->glCtx, texObj);
+    _mesa_init_teximage_fields(radeon->glCtx, target, texImage,
+                               rb->width, rb->height, rb->cpp, 0, rb->cpp);
+       texImage->TexFormat = &_mesa_texformat_rgba8888_rev;
+
+       t = r300_tex_obj(texObj);
+    if (t == NULL) {
+        return;
+    }
+    t->bo = rb->bo;
+    t->tile_bits = 0;
+       t->image_override = GL_TRUE;
+       t->override_offset = 0;
+       t->pitch_reg &= (1 << 13) -1;
+       pitch_val = rb->pitch;
+       switch (rb->cpp) {
+       case 4:
+               t->format = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8);
+               t->filter |= tx_table[2].filter;
+               pitch_val /= 4;
+               break;
+       case 3:
+       default:
+               t->format = R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8);
+               t->filter |= tx_table[4].filter;
+               pitch_val /= 4;
+               break;
+       case 2:
+               t->format = R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5);
+               t->filter |= tx_table[5].filter;
+               pitch_val /= 2;
+               break;
+       }
+       pitch_val--;
+       t->size = ((rb->width - 1) << R300_TX_WIDTHMASK_SHIFT) |
+              ((rb->height - 1) << R300_TX_HEIGHTMASK_SHIFT);
+    t->size |= R300_TX_SIZE_TXPITCH_EN;
+       t->pitch_reg |= pitch_val;
+       t->validated = GL_TRUE;
+    _mesa_unlock_texture(radeon->glCtx, texObj);
+    return;
+}
index e65b8c1cc47cac6159f73e1a399d5bfb4477c7be..9bb95a5a32596c9bc043264fadeab87a75f6b3a7 100644 (file)
@@ -365,6 +365,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
             rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
             rb->cpp = buffers[i].cpp;
             rb->pitch = buffers[i].pitch;
+            rb->width = drawable->w;
             rb->height = drawable->h;
             rb->has_surface = 0;
             rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
@@ -382,6 +383,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
             rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
             rb->cpp = buffers[i].cpp;
             rb->pitch = buffers[i].pitch;
+            rb->width = drawable->w;
             rb->height = drawable->h;
             rb->has_surface = 0;
             rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
@@ -395,6 +397,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
             rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer;
             rb->cpp = buffers[i].cpp;
             rb->pitch = buffers[i].pitch;
+            rb->width = drawable->w;
             rb->height = drawable->h;
             rb->has_surface = 0;
             rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
index d32809ef1a6d1fd88885a2e5698c0d06650c9a17..62cdfad4a0cb10c22a76055d6b542c0cdf9bd765 100644 (file)
@@ -36,6 +36,7 @@ struct radeon_renderbuffer
     unsigned int cpp;
     /* unsigned int offset; */
     unsigned int pitch;
+    unsigned int width;
     unsigned int height;
 
     /* boo Xorg 6.8.2 compat */
index 8de928692a09dd97bdf1e515b985c4e06b77a9b7..ec3919ced69f53e8e5308f15a32b3151b862b42f 100644 (file)
@@ -309,7 +309,6 @@ static int cs_emit(struct radeon_cs *cs)
     radeon_cs_write_dword(cs, ull >> 32);
     radeon_cs_write_dword(cs, 0);
 
-
     r = cs_process_relocs(cs);
     if (r) {
         return 0;
@@ -330,10 +329,6 @@ static int cs_emit(struct radeon_cs *cs)
         return r;
     }
     cs_set_age(cs);
-        for (int i = 0; i < cs->cdw; i++) {
-            fprintf(stderr, "pkt[%04d]=0x%08X\n", i, cs->packets[i]);
-        }
-    exit(0);
     return 0;
 }
 
@@ -362,7 +357,7 @@ static int cs_need_flush(struct radeon_cs *cs)
     return (cs->relocs_total_size > (7*1024*1024));
 }
 
-struct radeon_cs_funcs  radeon_cs_funcs = {
+static struct radeon_cs_funcs  radeon_cs_legacy_funcs = {
     cs_create,
     cs_write_dword,
     cs_write_reloc,
@@ -383,7 +378,7 @@ struct radeon_cs_manager *radeon_cs_manager_legacy(struct radeon_context *ctx)
     if (csm == NULL) {
         return NULL;
     }
-    csm->base.funcs = &radeon_cs_funcs;
+    csm->base.funcs = &radeon_cs_legacy_funcs;
     csm->base.fd = ctx->dri.fd;
     csm->ctx = ctx;
     csm->pending_age = 1;
index 4f76fcf41091824b3080cf6ab50624e3e6af26bf..9cc91ac197f9b306e4fbd199b403c2796a31a151 100644 (file)
@@ -349,6 +349,14 @@ static const __DRItexOffsetExtension r300texOffsetExtension = {
     { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
    r300SetTexOffset,
 };
+
+void r300SetTexBuffer(__DRIcontext *pDRICtx,
+                      GLint target,
+                      __DRIdrawable *dPriv);
+static const __DRItexBufferExtension r300TexBufferExtension = {
+    { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
+   r300SetTexBuffer,
+};
 #endif
 
 /* Create the device specific screen private data struct.
@@ -1024,7 +1032,8 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv)
 #endif
 
 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
-   //screen->extensions[i++] = &r300texOffsetExtension.base;
+   screen->extensions[i++] = &r300texOffsetExtension.base;
+   screen->extensions[i++] = &r300TexBufferExtension.base;
 #endif
 
    screen->extensions[i++] = NULL;
@@ -1455,8 +1464,6 @@ radeonInitScreen(__DRIscreenPrivate *psp)
 static const
 __DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp)
 {
-   fprintf(stderr, "DRI2 initialization\n");
-
    /* Calling driInitExtensions here, with a NULL context pointer,
     * does not actually enable the extensions.  It just makes sure
     * that all the dispatch offsets for all the extensions that
@@ -1480,8 +1487,6 @@ __DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp)
        return NULL;
     }
 
-   fprintf(stderr, "DRI2 initialized\n");
-
    /* for now fill in all modes */
    return radeonFillInModes( psp, 24, 24, 8, 1);
 }
@@ -1555,3 +1560,4 @@ const struct __DriverAPIRec driDriverAPI = {
    .CopySubBuffer   = r200CopySubBuffer,
 };
 #endif
+
index 7b9d036148e51582ce6e2b791621016324961e59..ccddbb8ae02c882822755196b0d05c196f5f1c33 100644 (file)
@@ -104,7 +104,7 @@ typedef struct radeon_screen {
    /* Configuration cache with default values for all contexts */
    driOptionCache optionCache;
 
-   const __DRIextension *extensions[8];
+   const __DRIextension *extensions[16];
 
    int num_gb_pipes;
        drm_radeon_sarea_t *sarea;      /* Private SAREA data */