--- /dev/null
- cxx_namespace = 'ArmISA'
- cxx_class = 'TLB'
+# -*- mode:python -*-
+
+# Copyright (c) 2007-2008 The Florida State University
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Stephen Hines
+
+from m5.SimObject import SimObject
+from m5.params import *
+
+class ArmTLB(SimObject):
+ abstract = True
+ type = 'ArmTLB'
- cxx_namespace = 'ArmISA'
- cxx_class = 'DTB'
++ cxx_class = 'ArmISA::TLB'
+ size = Param.Int("TLB size")
+
+class ArmDTB(ArmTLB):
+ type = 'ArmDTB'
- cxx_namespace = 'ArmISA'
- cxx_class = 'ITB'
++ cxx_class = 'ArmISA::DTB'
+ size = 64
+
+class ArmITB(ArmTLB):
+ type = 'ArmITB'
- cxx_namespace = 'ArmISA'
- cxx_class = 'UTB'
++ cxx_class = 'ArmISA::ITB'
+ size = 64
+
+class ArmUTB(ArmTLB):
+ type = 'ArmUTB'
++ cxx_class = 'ArmISA::UTB'
+ size = 64
+
--- /dev/null
- const int ArgumentReg[] = {0, 1, 2, 3};
- const int NumArgumentRegs = sizeof(ArgumentReg)/ sizeof(const int);
-
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 2007-2008 The Florida State University
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ * Stephen Hines
+ */
+
+#ifndef __ARCH_ARM_ISA_TRAITS_HH__
+#define __ARCH_ARM_ISA_TRAITS_HH__
+
+#include "arch/arm/types.hh"
+#include "sim/host.hh"
+
+namespace LittleEndianGuest {};
+
+#define TARGET_ARM
+
+class StaticInstPtr;
+
+namespace ArmISA
+{
+ using namespace LittleEndianGuest;
+
+ StaticInstPtr decodeInst(ExtMachInst);
+
+ // ARM DOES NOT have a delay slot
+ #define ISA_HAS_DELAY_SLOT 0
+
+ const Addr PageShift = 12;
+ const Addr PageBytes = ULL(1) << PageShift;
+ const Addr Page_Mask = ~(PageBytes - 1);
+ const Addr PageOffset = PageBytes - 1;
+
+
+ ////////////////////////////////////////////////////////////////////////
+ //
+ // Translation stuff
+ //
+
+ const Addr PteShift = 3;
+ const Addr NPtePageShift = PageShift - PteShift;
+ const Addr NPtePage = ULL(1) << NPtePageShift;
+ const Addr PteMask = NPtePage - 1;
+
+ //// All 'Mapped' segments go through the TLB
+ //// All other segments are translated by dropping the MSB, to give
+ //// the corresponding physical address
+ // User Segment - Mapped
+ const Addr USegBase = ULL(0x0);
+ const Addr USegEnd = ULL(0x7FFFFFFF);
+
+ // Kernel Segment 0 - Unmapped
+ const Addr KSeg0End = ULL(0x9FFFFFFF);
+ const Addr KSeg0Base = ULL(0x80000000);
+ const Addr KSeg0Mask = ULL(0x1FFFFFFF);
+
+ // For loading... XXX This maybe could be USegEnd?? --ali
+ const Addr LoadAddrMask = ULL(0xffffffffff);
+
+ const unsigned VABits = 32;
+ const unsigned PABits = 32; // Is this correct?
+ const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
+ const Addr VAddrUnImplMask = ~VAddrImplMask;
+ inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
+ inline Addr VAddrVPN(Addr a) { return a >> ArmISA::PageShift; }
+ inline Addr VAddrOffset(Addr a) { return a & ArmISA::PageOffset; }
+
+ const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
+
+ // return a no-op instruction... used for instruction fetch faults
+ const ExtMachInst NoopMachInst = 0x00000000;
+
+ // Constants Related to the number of registers
+ const int NumIntArchRegs = 16;
+ const int NumIntSpecialRegs = 19;
+ const int NumFloatArchRegs = 16;
+ const int NumFloatSpecialRegs = 5;
+ const int NumControlRegs = 7;
+ const int NumInternalProcRegs = 0;
+
+ const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
+ const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
+ const int NumMiscRegs = NumControlRegs;
+
+ const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
+
+ const int TotalDataRegs = NumIntRegs + NumFloatRegs;
+
+ // Static instruction parameters
+ const int MaxInstSrcRegs = 5;
+ const int MaxInstDestRegs = 3;
+
+ // semantically meaningful register indices
+ const int ReturnValueReg = 0;
+ const int ReturnValueReg1 = 1;
+ const int ReturnValueReg2 = 2;
+ const int ArgumentReg0 = 0;
+ const int ArgumentReg1 = 1;
+ const int ArgumentReg2 = 2;
+ const int ArgumentReg3 = 3;
+ const int FramePointerReg = 11;
+ const int StackPointerReg = 13;
+ const int ReturnAddressReg = 14;
+ const int PCReg = 15;
+
+ const int ZeroReg = NumIntArchRegs;
+ const int AddrReg = ZeroReg + 1; // Used to generate address for uops
+
+ const int SyscallNumReg = ReturnValueReg;
+ const int SyscallPseudoReturnReg = ReturnValueReg;
+ const int SyscallSuccessReg = ReturnValueReg;
+
+ const int LogVMPageSize = 12; // 4K bytes
+ const int VMPageSize = (1 << LogVMPageSize);
+
+ const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
+
+ const int MachineBytes = 4;
+ const int WordBytes = 4;
+ const int HalfwordBytes = 2;
+ const int ByteBytes = 1;
+
+ // These help enumerate all the registers for dependence tracking.
+ const int FP_Base_DepTag = NumIntRegs;
+ const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
+};
+
+using namespace ArmISA;
+
+#endif // __ARCH_ARM_ISA_TRAITS_HH__
--- /dev/null
- TypedBufferArg<Linux::utsname> name(tc->getSyscallArg(0));
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 2007-2008 The Florida State University
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
+ * Stephen Hines
+ */
+
+#include "arch/arm/linux/linux.hh"
+#include "arch/arm/linux/process.hh"
+#include "arch/arm/isa_traits.hh"
+
+#include "base/trace.hh"
+#include "cpu/thread_context.hh"
+#include "kern/linux/linux.hh"
+
+#include "sim/process.hh"
+#include "sim/syscall_emul.hh"
+
+using namespace std;
+using namespace ArmISA;
+
+/// Target uname() handler.
+static SyscallReturn
+unameFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
+ ThreadContext *tc)
+{
- /* 17 */ SyscallDesc("break", obreakFunc), //???
++ TypedBufferArg<Linux::utsname> name(process->getSyscallArg(tc, 0));
+
+ strcpy(name->sysname, "Linux");
+ strcpy(name->nodename, "m5.eecs.umich.edu");
+ strcpy(name->release, "2.4.20");
+ strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
+ strcpy(name->machine, "arm");
+
+ name.copyOut(tc->getMemPort());
+ return 0;
+}
+
+SyscallDesc ArmLinuxProcess::syscallDescs[] = {
+ /* 0 */ SyscallDesc("syscall", unimplementedFunc),
+ /* 1 */ SyscallDesc("exit", exitFunc),
+ /* 2 */ SyscallDesc("fork", unimplementedFunc),
+ /* 3 */ SyscallDesc("read", readFunc),
+ /* 4 */ SyscallDesc("write", writeFunc),
+ /* 5 */ SyscallDesc("open", openFunc<ArmLinux>),
+ /* 6 */ SyscallDesc("close", closeFunc),
+ /* 7 */ SyscallDesc("waitpid", unimplementedFunc), //???
+ /* 8 */ SyscallDesc("creat", unimplementedFunc),
+ /* 9 */ SyscallDesc("link", unimplementedFunc),
+ /* 10 */ SyscallDesc("unlink", unlinkFunc),
+ /* 11 */ SyscallDesc("execve", unimplementedFunc),
+ /* 12 */ SyscallDesc("chdir", unimplementedFunc),
+ /* 13 */ SyscallDesc("time", unimplementedFunc),
+ /* 14 */ SyscallDesc("mknod", unimplementedFunc),
+ /* 15 */ SyscallDesc("chmod", chmodFunc<ArmLinux>),
+ /* 16 */ SyscallDesc("lchown", chownFunc),
- /* 45 */ SyscallDesc("brk", obreakFunc),
++ /* 17 */ SyscallDesc("break", brkFunc), //???
+ /* 18 */ SyscallDesc("unused#18", unimplementedFunc), //???
+ /* 19 */ SyscallDesc("lseek", lseekFunc),
+ /* 20 */ SyscallDesc("getpid", getpidFunc),
+ /* 21 */ SyscallDesc("mount", unimplementedFunc),
+ /* 22 */ SyscallDesc("umount", unimplementedFunc),
+ /* 23 */ SyscallDesc("setuid", setuidFunc),
+ /* 24 */ SyscallDesc("getuid", getuidFunc),
+ /* 25 */ SyscallDesc("stime", unimplementedFunc),
+ /* 26 */ SyscallDesc("ptrace", unimplementedFunc),
+ /* 27 */ SyscallDesc("alarm", unimplementedFunc),
+ /* 28 */ SyscallDesc("unused#28", unimplementedFunc),
+ /* 29 */ SyscallDesc("pause", unimplementedFunc),
+ /* 30 */ SyscallDesc("utime", unimplementedFunc),
+ /* 31 */ SyscallDesc("stty", unimplementedFunc),
+ /* 32 */ SyscallDesc("gtty", unimplementedFunc),
+ /* 33 */ SyscallDesc("access", unimplementedFunc),
+ /* 34 */ SyscallDesc("nice", unimplementedFunc),
+ /* 35 */ SyscallDesc("ftime", unimplementedFunc),
+ /* 36 */ SyscallDesc("sync", unimplementedFunc),
+ /* 37 */ SyscallDesc("kill", ignoreFunc),
+ /* 38 */ SyscallDesc("rename", unimplementedFunc),
+ /* 39 */ SyscallDesc("mkdir", unimplementedFunc),
+ /* 40 */ SyscallDesc("rmdir", unimplementedFunc),
+ /* 41 */ SyscallDesc("dup", unimplementedFunc),
+ /* 42 */ SyscallDesc("pipe", unimplementedFunc),
+ /* 43 */ SyscallDesc("times", unimplementedFunc),
+ /* 44 */ SyscallDesc("prof", unimplementedFunc),
++ /* 45 */ SyscallDesc("brk", brkFunc),
+ /* 46 */ SyscallDesc("setgid", unimplementedFunc),
+ /* 47 */ SyscallDesc("getgid", getgidFunc),
+ /* 48 */ SyscallDesc("signal", ignoreFunc),
+ /* 49 */ SyscallDesc("geteuid", geteuidFunc),
+ /* 50 */ SyscallDesc("getegid", getegidFunc),
+ /* 51 */ SyscallDesc("acct", unimplementedFunc),
+ /* 52 */ SyscallDesc("umount2", unimplementedFunc),
+ /* 53 */ SyscallDesc("lock", unimplementedFunc),
+ /* 54 */ SyscallDesc("ioctl", ioctlFunc<ArmLinux>),
+ /* 55 */ SyscallDesc("fcntl", fcntlFunc),
+ /* 56 */ SyscallDesc("mpx", unimplementedFunc),
+ /* 57 */ SyscallDesc("setpgid", unimplementedFunc),
+ /* 58 */ SyscallDesc("ulimit", unimplementedFunc),
+ /* 59 */ SyscallDesc("unused#59", unimplementedFunc),
+ /* 60 */ SyscallDesc("umask", unimplementedFunc),
+ /* 61 */ SyscallDesc("chroot", unimplementedFunc),
+ /* 62 */ SyscallDesc("ustat", unimplementedFunc),
+ /* 63 */ SyscallDesc("dup2", unimplementedFunc),
+ /* 64 */ SyscallDesc("getppid", getpagesizeFunc),
+ /* 65 */ SyscallDesc("getpgrp", unimplementedFunc),
+ /* 66 */ SyscallDesc("setsid", unimplementedFunc),
+ /* 67 */ SyscallDesc("sigaction",unimplementedFunc),
+ /* 68 */ SyscallDesc("sgetmask", unimplementedFunc),
+ /* 69 */ SyscallDesc("ssetmask", unimplementedFunc),
+ /* 70 */ SyscallDesc("setreuid", unimplementedFunc),
+ /* 71 */ SyscallDesc("setregid", unimplementedFunc),
+ /* 72 */ SyscallDesc("sigsuspend", unimplementedFunc),
+ /* 73 */ SyscallDesc("sigpending", unimplementedFunc),
+ /* 74 */ SyscallDesc("sethostname", ignoreFunc),
+ /* 75 */ SyscallDesc("setrlimit", unimplementedFunc),
+ /* 76 */ SyscallDesc("getrlimit", unimplementedFunc),
+ /* 77 */ SyscallDesc("getrusage", unimplementedFunc),
+ /* 78 */ SyscallDesc("gettimeofday", unimplementedFunc),
+ /* 79 */ SyscallDesc("settimeofday", unimplementedFunc),
+ /* 80 */ SyscallDesc("getgroups", unimplementedFunc),
+ /* 81 */ SyscallDesc("setgroups", unimplementedFunc),
+ /* 82 */ SyscallDesc("reserved#82", unimplementedFunc),
+ /* 83 */ SyscallDesc("symlink", unimplementedFunc),
+ /* 84 */ SyscallDesc("unused#84", unimplementedFunc),
+ /* 85 */ SyscallDesc("readlink", unimplementedFunc),
+ /* 86 */ SyscallDesc("uselib", unimplementedFunc),
+ /* 87 */ SyscallDesc("swapon", gethostnameFunc),
+ /* 88 */ SyscallDesc("reboot", unimplementedFunc),
+ /* 89 */ SyscallDesc("readdir", unimplementedFunc),
+ /* 90 */ SyscallDesc("mmap", mmapFunc<ArmLinux>),
+ /* 91 */ SyscallDesc("munmap",munmapFunc),
+ /* 92 */ SyscallDesc("truncate", truncateFunc),
+ /* 93 */ SyscallDesc("ftruncate", ftruncateFunc),
+ /* 94 */ SyscallDesc("fchmod", unimplementedFunc),
+ /* 95 */ SyscallDesc("fchown", unimplementedFunc),
+ /* 96 */ SyscallDesc("getpriority", unimplementedFunc),
+ /* 97 */ SyscallDesc("setpriority", unimplementedFunc),
+ /* 98 */ SyscallDesc("profil", unimplementedFunc),
+ /* 99 */ SyscallDesc("statfs", unimplementedFunc),
+ /* 100 */ SyscallDesc("fstatfs", unimplementedFunc),
+ /* 101 */ SyscallDesc("ioperm", unimplementedFunc),
+ /* 102 */ SyscallDesc("socketcall", unimplementedFunc),
+ /* 103 */ SyscallDesc("syslog", unimplementedFunc),
+ /* 104 */ SyscallDesc("setitimer", unimplementedFunc),
+ /* 105 */ SyscallDesc("getitimer", unimplementedFunc),
+ /* 106 */ SyscallDesc("stat", statFunc<ArmLinux>),
+ /* 107 */ SyscallDesc("lstat", unimplementedFunc),
+ /* 108 */ SyscallDesc("fstat", fstatFunc<ArmLinux>),
+ /* 109 */ SyscallDesc("unused#109", unimplementedFunc),
+ /* 110 */ SyscallDesc("iopl", unimplementedFunc),
+ /* 111 */ SyscallDesc("vhangup", unimplementedFunc),
+ /* 112 */ SyscallDesc("idle", ignoreFunc),
+ /* 113 */ SyscallDesc("vm86", unimplementedFunc),
+ /* 114 */ SyscallDesc("wait4", unimplementedFunc),
+ /* 115 */ SyscallDesc("swapoff", unimplementedFunc),
+ /* 116 */ SyscallDesc("sysinfo", unimplementedFunc),
+ /* 117 */ SyscallDesc("ipc", unimplementedFunc),
+ /* 118 */ SyscallDesc("fsync", unimplementedFunc),
+ /* 119 */ SyscallDesc("sigreturn", unimplementedFunc),
+ /* 120 */ SyscallDesc("clone", unimplementedFunc),
+ /* 121 */ SyscallDesc("setdomainname", unimplementedFunc),
+ /* 122 */ SyscallDesc("uname", unameFunc),
+ /* 123 */ SyscallDesc("modify_ldt", unimplementedFunc),
+ /* 124 */ SyscallDesc("adjtimex", unimplementedFunc),
+ /* 125 */ SyscallDesc("mprotect", ignoreFunc),
+ /* 126 */ SyscallDesc("sigprocmask", unimplementedFunc),
+ /* 127 */ SyscallDesc("create_module", unimplementedFunc),
+ /* 128 */ SyscallDesc("init_module", unimplementedFunc),
+ /* 129 */ SyscallDesc("delete_module", unimplementedFunc),
+ /* 130 */ SyscallDesc("get_kernel_syms", unimplementedFunc),
+ /* 131 */ SyscallDesc("quotactl", unimplementedFunc),
+ /* 132 */ SyscallDesc("getpgid", unimplementedFunc),
+ /* 133 */ SyscallDesc("fchdir", unimplementedFunc),
+ /* 134 */ SyscallDesc("bdflush", unimplementedFunc),
+ /* 135 */ SyscallDesc("sysfs", unimplementedFunc),
+ /* 136 */ SyscallDesc("personality", unimplementedFunc),
+ /* 137 */ SyscallDesc("afs_syscall", unimplementedFunc),
+ /* 138 */ SyscallDesc("setfsuid", unimplementedFunc),
+ /* 139 */ SyscallDesc("setfsgid", unimplementedFunc),
+ /* 140 */ SyscallDesc("llseek", unimplementedFunc),
+ /* 141 */ SyscallDesc("getdents", unimplementedFunc),
+ /* 142 */ SyscallDesc("newselect", unimplementedFunc),
+ /* 143 */ SyscallDesc("flock", unimplementedFunc),
+ /* 144 */ SyscallDesc("msync", unimplementedFunc),
+ /* 145 */ SyscallDesc("readv", unimplementedFunc),
+ /* 146 */ SyscallDesc("writev", writevFunc<ArmLinux>),
+ /* 147 */ SyscallDesc("getsid", unimplementedFunc),
+ /* 148 */ SyscallDesc("fdatasync", unimplementedFunc),
+ /* 149 */ SyscallDesc("sysctl", unimplementedFunc),
+ /* 150 */ SyscallDesc("mlock", unimplementedFunc),
+ /* 151 */ SyscallDesc("munlock", unimplementedFunc),
+ /* 152 */ SyscallDesc("mlockall", unimplementedFunc),
+ /* 153 */ SyscallDesc("munlockall", unimplementedFunc),
+ /* 154 */ SyscallDesc("sched_setparam", unimplementedFunc),
+ /* 155 */ SyscallDesc("sched_getparam", unimplementedFunc),
+ /* 156 */ SyscallDesc("sched_setscheduler", unimplementedFunc),
+ /* 157 */ SyscallDesc("sched_getscheduler", unimplementedFunc),
+ /* 158 */ SyscallDesc("sched_yield", unimplementedFunc),
+ /* 159 */ SyscallDesc("sched_get_priority_max", unimplementedFunc),
+ /* 160 */ SyscallDesc("sched_get_priority_min", unimplementedFunc),
+ /* 161 */ SyscallDesc("sched_rr_get_interval", unimplementedFunc),
+ /* 162 */ SyscallDesc("nanosleep", unimplementedFunc),
+ /* 163 */ SyscallDesc("mremap", unimplementedFunc), // ARM-specific
+ /* 164 */ SyscallDesc("setresuid", unimplementedFunc),
+ /* 165 */ SyscallDesc("getresuid", unimplementedFunc),
+ /* 166 */ SyscallDesc("vm862", unimplementedFunc),
+ /* 167 */ SyscallDesc("query_module", unimplementedFunc),
+ /* 168 */ SyscallDesc("poll", unimplementedFunc),
+ /* 169 */ SyscallDesc("nfsservctl", unimplementedFunc),
+ /* 170 */ SyscallDesc("setresgid", unimplementedFunc),
+ /* 171 */ SyscallDesc("getresgid", unimplementedFunc),
+ /* 172 */ SyscallDesc("prctl", unimplementedFunc),
+ /* 173 */ SyscallDesc("rt_sigreturn", unimplementedFunc),
+ /* 174 */ SyscallDesc("rt_sigaction", unimplementedFunc),
+ /* 175 */ SyscallDesc("rt_sigprocmask", unimplementedFunc),
+ /* 176 */ SyscallDesc("rt_sigpending", unimplementedFunc),
+ /* 177 */ SyscallDesc("rt_sigtimedwait", unimplementedFunc),
+ /* 178 */ SyscallDesc("rt_sigqueueinfo", ignoreFunc),
+ /* 179 */ SyscallDesc("rt_sigsuspend", unimplementedFunc),
+ /* 180 */ SyscallDesc("pread64", unimplementedFunc),
+ /* 181 */ SyscallDesc("pwrite64", unimplementedFunc),
+ /* 182 */ SyscallDesc("chown", unimplementedFunc),
+ /* 183 */ SyscallDesc("getcwd", unimplementedFunc),
+ /* 184 */ SyscallDesc("capget", unimplementedFunc),
+ /* 185 */ SyscallDesc("capset", unimplementedFunc),
+ /* 186 */ SyscallDesc("sigaltstack", unimplementedFunc),
+ /* 187 */ SyscallDesc("sendfile", unimplementedFunc),
+ /* 188 */ SyscallDesc("getpmsg", unimplementedFunc),
+ /* 189 */ SyscallDesc("putpmsg", unimplementedFunc),
+ /* 190 */ SyscallDesc("vfork", unimplementedFunc),
+ /* 191 */ SyscallDesc("getrlimit", unimplementedFunc),
+ /* 192 */ SyscallDesc("mmap2", unimplementedFunc),
+ /* 193 */ SyscallDesc("truncate64", unimplementedFunc),
+ /* 194 */ SyscallDesc("ftruncate64", unimplementedFunc),
+ /* 195 */ SyscallDesc("stat64", unimplementedFunc),
+ /* 196 */ SyscallDesc("lstat64", lstat64Func<ArmLinux>),
+ /* 197 */ SyscallDesc("fstat64", fstatFunc<ArmLinux>),
+ /* 198 */ SyscallDesc("lchown", unimplementedFunc),
+ /* 199 */ SyscallDesc("getuid", getuidFunc),
+ /* 200 */ SyscallDesc("getgid", getgidFunc),
+ /* 201 */ SyscallDesc("geteuid", geteuidFunc),
+ /* 202 */ SyscallDesc("getegid", getegidFunc),
+ /* 203 */ SyscallDesc("setreuid", unimplementedFunc),
+ /* 204 */ SyscallDesc("setregid", unimplementedFunc),
+ /* 205 */ SyscallDesc("getgroups", unimplementedFunc),
+ /* 206 */ SyscallDesc("setgroups", unimplementedFunc),
+ /* 207 */ SyscallDesc("fchown", unimplementedFunc),
+ /* 208 */ SyscallDesc("setresuid", unimplementedFunc),
+ /* 209 */ SyscallDesc("getresuid", unimplementedFunc),
+ /* 210 */ SyscallDesc("setresgid", unimplementedFunc),
+ /* 211 */ SyscallDesc("getresgid", unimplementedFunc),
+ /* 212 */ SyscallDesc("chown", unimplementedFunc),
+ /* 213 */ SyscallDesc("setuid", unimplementedFunc),
+ /* 214 */ SyscallDesc("setgid", unimplementedFunc),
+ /* 215 */ SyscallDesc("setfsuid", unimplementedFunc),
+ /* 216 */ SyscallDesc("setfsgid", unimplementedFunc),
+ /* 217 */ SyscallDesc("getdents64", unimplementedFunc),
+ /* 218 */ SyscallDesc("pivot_root", unimplementedFunc),
+ /* 219 */ SyscallDesc("mincore", unimplementedFunc),
+ /* 220 */ SyscallDesc("madvise", unimplementedFunc),
+ /* 221 */ SyscallDesc("fcntl64", fcntl64Func),
+ /* 222 */ SyscallDesc("tux", unimplementedFunc),
+ /* 223 */ SyscallDesc("unknown#223", unimplementedFunc),
+ /* 224 */ SyscallDesc("gettid", unimplementedFunc),
+ /* 225 */ SyscallDesc("readahead", unimplementedFunc),
+ /* 226 */ SyscallDesc("setxattr", unimplementedFunc),
+ /* 227 */ SyscallDesc("lsetxattr", unimplementedFunc),
+ /* 228 */ SyscallDesc("fsetxattr", unimplementedFunc),
+ /* 229 */ SyscallDesc("getxattr", unimplementedFunc),
+ /* 230 */ SyscallDesc("lgetxattr", unimplementedFunc),
+ /* 231 */ SyscallDesc("fgetxattr", unimplementedFunc),
+ /* 232 */ SyscallDesc("listxattr", unimplementedFunc),
+ /* 233 */ SyscallDesc("llistxattr", unimplementedFunc),
+ /* 234 */ SyscallDesc("flistxattr", unimplementedFunc),
+ /* 235 */ SyscallDesc("removexattr", unimplementedFunc),
+ /* 236 */ SyscallDesc("lremovexattr", unimplementedFunc),
+ /* 237 */ SyscallDesc("fremovexattr", unimplementedFunc),
+ /* 238 */ SyscallDesc("tkill", unimplementedFunc),
+ /* 239 */ SyscallDesc("sendfile64", unimplementedFunc),
+ /* 240 */ SyscallDesc("futex", unimplementedFunc),
+ /* 241 */ SyscallDesc("sched_setaffinity", unimplementedFunc),
+ /* 242 */ SyscallDesc("sched_getaffinity", unimplementedFunc),
+ /* 243 */ SyscallDesc("io_setup", unimplementedFunc),
+ /* 244 */ SyscallDesc("io_destory", unimplementedFunc),
+ /* 245 */ SyscallDesc("io_getevents", unimplementedFunc),
+ /* 246 */ SyscallDesc("io_submit", unimplementedFunc),
+ /* 247 */ SyscallDesc("io_cancel", unimplementedFunc),
+ /* 248 */ SyscallDesc("exit_group", exitFunc),
+ /* 249 */ SyscallDesc("lookup_dcookie", unimplementedFunc),
+ /* 250 */ SyscallDesc("epoll_create", unimplementedFunc),
+ /* 251 */ SyscallDesc("epoll_ctl", unimplementedFunc),
+ /* 252 */ SyscallDesc("epoll_wait", unimplementedFunc),
+ /* 253 */ SyscallDesc("remap_file_pages", unimplementedFunc),
+ /* 254 */ SyscallDesc("set_thread_area", unimplementedFunc),
+ /* 255 */ SyscallDesc("get_thread_area", unimplementedFunc),
+ /* 256 */ SyscallDesc("set_tid_address", unimplementedFunc),
+ /* 257 */ SyscallDesc("timer_create", unimplementedFunc),
+ /* 258 */ SyscallDesc("timer_settime", unimplementedFunc),
+ /* 259 */ SyscallDesc("timer_gettime", unimplementedFunc),
+ /* 260 */ SyscallDesc("timer_getoverrun", unimplementedFunc),
+ /* 261 */ SyscallDesc("timer_delete", unimplementedFunc),
+ /* 262 */ SyscallDesc("clock_settime", unimplementedFunc),
+ /* 263 */ SyscallDesc("clock_gettime", unimplementedFunc),
+ /* 264 */ SyscallDesc("clock_getres", unimplementedFunc),
+ /* 265 */ SyscallDesc("clock_nanosleep", unimplementedFunc),
+ /* 266 */ SyscallDesc("statfs64", unimplementedFunc),
+ /* 267 */ SyscallDesc("fstatfs64", unimplementedFunc),
+ /* 268 */ SyscallDesc("tgkill", unimplementedFunc),
+ /* 269 */ SyscallDesc("utimes", unimplementedFunc),
+ /* 270 */ SyscallDesc("arm_fadvise64_64", unimplementedFunc),
+ /* 271 */ SyscallDesc("pciconfig_iobase", unimplementedFunc),
+ /* 272 */ SyscallDesc("pciconfig_read", unimplementedFunc),
+ /* 273 */ SyscallDesc("pciconfig_write", unimplementedFunc),
+ /* 274 */ SyscallDesc("mq_open", unimplementedFunc),
+ /* 275 */ SyscallDesc("mq_unlink", unimplementedFunc),
+ /* 276 */ SyscallDesc("mq_timedsend", unimplementedFunc),
+ /* 277 */ SyscallDesc("mq_timedreceive", unimplementedFunc),
+ /* 278 */ SyscallDesc("mq_notify", unimplementedFunc),
+ /* 279 */ SyscallDesc("mq_getsetattr", unimplementedFunc),
+ /* 280 */ SyscallDesc("waitid", unimplementedFunc),
+ /* 281 */ SyscallDesc("socket", unimplementedFunc),
+ /* 282 */ SyscallDesc("bind", unimplementedFunc),
+ /* 283 */ SyscallDesc("connect", unimplementedFunc),
+ /* 284 */ SyscallDesc("listen", unimplementedFunc),
+ /* 285 */ SyscallDesc("accept", unimplementedFunc),
+ /* 286 */ SyscallDesc("getsockname", unimplementedFunc),
+ /* 287 */ SyscallDesc("getpeername", unimplementedFunc),
+ /* 288 */ SyscallDesc("socketpair", unimplementedFunc),
+ /* 289 */ SyscallDesc("send", unimplementedFunc),
+ /* 290 */ SyscallDesc("sendto", unimplementedFunc),
+ /* 291 */ SyscallDesc("recv", unimplementedFunc),
+ /* 292 */ SyscallDesc("recvfrom", unimplementedFunc),
+ /* 293 */ SyscallDesc("shutdown", unimplementedFunc),
+ /* 294 */ SyscallDesc("setsockopt", unimplementedFunc),
+ /* 295 */ SyscallDesc("getsockopt", unimplementedFunc),
+ /* 296 */ SyscallDesc("sendmsg", unimplementedFunc),
+ /* 297 */ SyscallDesc("rcvmsg", unimplementedFunc),
+ /* 298 */ SyscallDesc("semop", unimplementedFunc),
+ /* 299 */ SyscallDesc("semget", unimplementedFunc),
+ /* 300 */ SyscallDesc("semctl", unimplementedFunc),
+ /* 301 */ SyscallDesc("msgsend", unimplementedFunc),
+ /* 302 */ SyscallDesc("msgrcv", unimplementedFunc),
+ /* 303 */ SyscallDesc("msgget", unimplementedFunc),
+ /* 304 */ SyscallDesc("msgctl", unimplementedFunc),
+ /* 305 */ SyscallDesc("shmat", unimplementedFunc),
+ /* 306 */ SyscallDesc("shmdt", unimplementedFunc),
+ /* 307 */ SyscallDesc("shmget", unimplementedFunc),
+ /* 308 */ SyscallDesc("shmctl", unimplementedFunc),
+ /* 309 */ SyscallDesc("add_key", unimplementedFunc),
+ /* 310 */ SyscallDesc("request_key", unimplementedFunc),
+ /* 311 */ SyscallDesc("keyctl", unimplementedFunc),
+ /* 312 */ SyscallDesc("semtimedop", unimplementedFunc),
+ /* 313 */ SyscallDesc("vserver", unimplementedFunc),
+ /* 314 */ SyscallDesc("ioprio_set", unimplementedFunc),
+ /* 315 */ SyscallDesc("ioprio_get", unimplementedFunc),
+ /* 316 */ SyscallDesc("inotify_init", unimplementedFunc),
+ /* 317 */ SyscallDesc("inotify_add_watch", unimplementedFunc),
+ /* 318 */ SyscallDesc("inotify_rm_watch", unimplementedFunc),
+ /* 319 */ SyscallDesc("mbind", unimplementedFunc),
+ /* 320 */ SyscallDesc("get_mempolicy", unimplementedFunc),
+ /* 321 */ SyscallDesc("set_mempolicy", unimplementedFunc),
+ /* 322 */ SyscallDesc("openat", unimplementedFunc),
+ /* 323 */ SyscallDesc("mkdirat", unimplementedFunc),
+ /* 324 */ SyscallDesc("mknodat", unimplementedFunc),
+ /* 325 */ SyscallDesc("fchownat", unimplementedFunc),
+ /* 326 */ SyscallDesc("futimesat", unimplementedFunc),
+ /* 327 */ SyscallDesc("fstatat64", unimplementedFunc),
+ /* 328 */ SyscallDesc("unlinkat", unimplementedFunc),
+ /* 329 */ SyscallDesc("renameat", unimplementedFunc),
+ /* 330 */ SyscallDesc("linkat", unimplementedFunc),
+ /* 331 */ SyscallDesc("symlinkat", unimplementedFunc),
+ /* 332 */ SyscallDesc("readlinkat", unimplementedFunc),
+ /* 333 */ SyscallDesc("fchmodat", unimplementedFunc),
+ /* 334 */ SyscallDesc("faccessat", unimplementedFunc),
+ /* 335 */ SyscallDesc("pselect6", unimplementedFunc),
+ /* 336 */ SyscallDesc("ppoll", unimplementedFunc),
+ /* 337 */ SyscallDesc("unshare", unimplementedFunc),
+ /* 338 */ SyscallDesc("set_robust_list", unimplementedFunc),
+ /* 339 */ SyscallDesc("get_robust_list", unimplementedFunc),
+ /* 340 */ SyscallDesc("splice", unimplementedFunc),
+ /* 341 */ SyscallDesc("arm_sync_file_range", unimplementedFunc),
+ /* 342 */ SyscallDesc("tee", unimplementedFunc),
+ /* 343 */ SyscallDesc("vmsplice", unimplementedFunc),
+ /* 344 */ SyscallDesc("move_pages", unimplementedFunc),
+ /* 345 */ SyscallDesc("getcpu", unimplementedFunc),
+ /* 346 */ SyscallDesc("epoll_pwait", unimplementedFunc),
+};
+
+ArmLinuxProcess::ArmLinuxProcess(LiveProcessParams * params,
+ ObjectFile *objFile)
+ : ArmLiveProcess(params, objFile),
+ Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc))
+{ }
+
+SyscallDesc*
+ArmLinuxProcess::getDesc(int callnum)
+{
+ // Angel SWI syscalls are unsupported in this release
+ if (callnum == 0x123456)
+ panic("Attempt to execute an ANGEL_SWI system call (newlib-related)");
+ else if ((callnum & 0x00f00000) == 0x00900000)
+ callnum &= 0x000fffff;
+ // Linux syscalls have to strip off the 0x00900000
+
+ if (callnum < 0 || callnum > Num_Syscall_Descs)
+ return NULL;
+
+ return &syscallDescs[callnum];
+}
--- /dev/null
- ArmLiveProcess::ArmLiveProcess(LiveProcessParams * params,
- ObjectFile *objFile)
+/*
+ * Copyright (c) 2007-2008 The Florida State University
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Stephen Hines
+ */
+
+#include "arch/arm/isa_traits.hh"
+#include "arch/arm/process.hh"
+#include "arch/arm/types.hh"
+#include "base/loader/elf_object.hh"
+#include "base/loader/object_file.hh"
+#include "base/misc.hh"
+#include "cpu/thread_context.hh"
+#include "mem/page_table.hh"
+#include "mem/translating_port.hh"
+#include "sim/process_impl.hh"
+#include "sim/system.hh"
+
+using namespace std;
+using namespace ArmISA;
+
- threadContexts[0]->setIntReg(ArgumentReg1, argc);
- threadContexts[0]->setIntReg(ArgumentReg2, argv_array_base);
- threadContexts[0]->setIntReg(StackPointerReg, stack_min);
++ArmLiveProcess::ArmLiveProcess(LiveProcessParams *params, ObjectFile *objFile)
+ : LiveProcess(params, objFile)
+{
+ stack_base = 0xc0000000L;
+
+ // Set pointer for next thread stack. Reserve 8M for main stack.
+ next_thread_stack_base = stack_base - (8 * 1024 * 1024);
+
+ // Set up break point (Top of Heap)
+ brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
+ brk_point = roundUp(brk_point, VMPageSize);
+
+ // Set up region for mmaps. For now, start at bottom of kuseg space.
+ mmap_start = mmap_end = 0x70000000L;
+}
+
+void
+ArmLiveProcess::startup()
+{
+ argsInit(MachineBytes, VMPageSize);
+}
+
+void
+ArmLiveProcess::copyStringArray32(std::vector<std::string> &strings,
+ Addr array_ptr, Addr data_ptr,
+ TranslatingPort* memPort)
+{
+ Addr data_ptr_swap;
+ for (int i = 0; i < strings.size(); ++i) {
+ data_ptr_swap = htog(data_ptr);
+ memPort->writeBlob(array_ptr, (uint8_t*)&data_ptr_swap,
+ sizeof(uint32_t));
+ memPort->writeString(data_ptr, strings[i].c_str());
+ array_ptr += sizeof(uint32_t);
+ data_ptr += strings[i].size() + 1;
+ }
+ // add NULL terminator
+ data_ptr = 0;
+
+ memPort->writeBlob(array_ptr, (uint8_t*)&data_ptr, sizeof(uint32_t));
+}
+
+void
+ArmLiveProcess::argsInit(int intSize, int pageSize)
+{
+ // Overloaded argsInit so that we can fine-tune for ARM architecture
+ Process::startup();
+
+ // load object file into target memory
+ objFile->loadSections(initVirtMem);
+
+ // Calculate how much space we need for arg & env arrays.
+ int argv_array_size = intSize * (argv.size() + 1);
+ int envp_array_size = intSize * (envp.size() + 1);
+ int arg_data_size = 0;
+ for (int i = 0; i < argv.size(); ++i) {
+ arg_data_size += argv[i].size() + 1;
+ }
+ int env_data_size = 0;
+ for (int i = 0; i < envp.size(); ++i) {
+ env_data_size += envp[i].size() + 1;
+ }
+
+ int space_needed =
+ argv_array_size + envp_array_size + arg_data_size + env_data_size;
+ if (space_needed < 16*1024)
+ space_needed = 16*1024;
+
+ // set bottom of stack
+ stack_min = stack_base - space_needed;
+ // align it
+ stack_min = roundDown(stack_min, pageSize);
+ stack_size = stack_base - stack_min;
+ // map memory
+ pTable->allocate(stack_min, roundUp(stack_size, pageSize));
+
+ // map out initial stack contents
+ Addr argv_array_base = stack_min + intSize; // room for argc
+ Addr envp_array_base = argv_array_base + argv_array_size;
+ Addr arg_data_base = envp_array_base + envp_array_size;
+ Addr env_data_base = arg_data_base + arg_data_size;
+
+ // write contents to stack
+ uint64_t argc = argv.size();
+ if (intSize == 8)
+ argc = htog((uint64_t)argc);
+ else if (intSize == 4)
+ argc = htog((uint32_t)argc);
+ else
+ panic("Unknown int size");
+
+ initVirtMem->writeBlob(stack_min, (uint8_t*)&argc, intSize);
+
+ copyStringArray32(argv, argv_array_base, arg_data_base, initVirtMem);
+ copyStringArray32(envp, envp_array_base, env_data_base, initVirtMem);
+
+ /*
+ //uint8_t insns[] = {0xe5, 0x9f, 0x00, 0x08, 0xe1, 0xa0, 0xf0, 0x0e};
+ uint8_t insns[] = {0x08, 0x00, 0x9f, 0xe5, 0x0e, 0xf0, 0xa0, 0xe1};
+
+ initVirtMem->writeBlob(0xffff0fe0, insns, 8);
+ */
+
- threadContexts[0]->setPC(prog_entry);
- threadContexts[0]->setNextPC(prog_entry + sizeof(MachInst));
++ ThreadContext *tc = system->getThreadContext(contextIds[0]);
++
++ tc->setIntReg(ArgumentReg1, argc);
++ tc->setIntReg(ArgumentReg2, argv_array_base);
++ tc->setIntReg(StackPointerReg, stack_min);
+
+ Addr prog_entry = objFile->entryPoint();
++ tc->setPC(prog_entry);
++ tc->setNextPC(prog_entry + sizeof(MachInst));
++}
++
++ArmISA::IntReg
++ArmLiveProcess::getSyscallArg(ThreadContext *tc, int i)
++{
++ assert(i < 4);
++ return tc->readIntReg(ArgumentReg0 + i);
+}
+
++void
++ArmLiveProcess::setSyscallArg(ThreadContext *tc,
++ int i, ArmISA::IntReg val)
++{
++ assert(i < 4);
++ tc->setIntReg(ArgumentReg0 + i, val);
++}
++
++void
++ArmLiveProcess::setSyscallReturn(ThreadContext *tc,
++ SyscallReturn return_value)
++{
++ tc->setIntReg(ReturnValueReg, return_value.value());
++}
--- /dev/null
+/*
+ * Copyright (c) 2007-2008 The Florida State University
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Stephen Hines
+ */
+
+#ifndef __ARM_PROCESS_HH__
+#define __ARM_PROCESS_HH__
+
+#include <string>
+#include <vector>
+#include "sim/process.hh"
+
+class LiveProcess;
+class ObjectFile;
+class System;
+
+class ArmLiveProcess : public LiveProcess
+{
+ protected:
+ ArmLiveProcess(LiveProcessParams * params, ObjectFile *objFile);
+
+ void startup();
+
+ void copyStringArray32(std::vector<std::string> &strings,
+ Addr array_ptr, Addr data_ptr,
+ TranslatingPort* memPort);
+
+ public:
+ void argsInit(int intSize, int pageSize);
+
++ ArmISA::IntReg getSyscallArg(ThreadContext *tc, int i);
++ void setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val);
++ void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
+};
+
+#endif // __ARM_PROCESS_HH__
+
--- /dev/null
- RegFile::serialize(std::ostream &os)
+/*
+ * Copyright (c) 2007-2008 The Florida State University
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Stephen Hines
+ */
+
+#include "arch/arm/regfile/regfile.hh"
+#include "sim/serialize.hh"
+
+using namespace std;
+
+namespace ArmISA
+{
+
+void
+copyRegs(ThreadContext *src, ThreadContext *dest)
+{
+ panic("Copy Regs Not Implemented Yet\n");
+}
+
+void
+copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+{
+ panic("Copy Misc. Regs Not Implemented Yet\n");
+}
+
+void
+MiscRegFile::copyMiscRegs(ThreadContext *tc)
+{
+ panic("Copy Misc. Regs Not Implemented Yet\n");
+}
+
+void
- RegFile::unserialize(Checkpoint *cp, const std::string §ion)
++RegFile::serialize(EventManager *em, ostream &os)
+{
+ intRegFile.serialize(os);
+ //SERIALIZE_ARRAY(floatRegFile, NumFloatRegs);
+ //SERIALZE_ARRAY(miscRegFile);
+ //SERIALIZE_SCALAR(miscRegs.fpcr);
+ //SERIALIZE_SCALAR(miscRegs.lock_flag);
+ //SERIALIZE_SCALAR(miscRegs.lock_addr);
+ //SERIALIZE_SCALAR(pc);
+ SERIALIZE_SCALAR(npc);
+ SERIALIZE_SCALAR(nnpc);
+}
+
+void
++RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion)
+{
+ intRegFile.unserialize(cp, section);
+ //UNSERIALIZE_ARRAY(floatRegFile);
+ //UNSERIALZE_ARRAY(miscRegFile);
+ //UNSERIALIZE_SCALAR(miscRegs.fpcr);
+ //UNSERIALIZE_SCALAR(miscRegs.lock_flag);
+ //UNSERIALIZE_SCALAR(miscRegs.lock_addr);
+ //UNSERIALIZE_SCALAR(pc);
+ UNSERIALIZE_SCALAR(npc);
+ UNSERIALIZE_SCALAR(nnpc);
+
+}
+
+} // namespace ArmISA
--- /dev/null
- class RegFile {
+/*
+ * Copyright (c) 2007-2008 The Florida State University
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Stephen Hines
+ */
+
+#ifndef __ARCH_ARM_REGFILE_REGFILE_HH__
+#define __ARCH_ARM_REGFILE_REGFILE_HH__
+
+#include "arch/arm/types.hh"
+#include "arch/arm/regfile/int_regfile.hh"
+#include "arch/arm/regfile/float_regfile.hh"
+#include "arch/arm/regfile/misc_regfile.hh"
+#include "sim/faults.hh"
+
+class Checkpoint;
++class EventManager;
+class ThreadContext;
+
+namespace ArmISA
+{
- void serialize(std::ostream &os);
- void unserialize(Checkpoint *cp, const std::string §ion);
++ class RegFile
++ {
+ protected:
+ IntRegFile intRegFile; // (signed) integer register file
+ FloatRegFile floatRegFile; // floating point register file
+ MiscRegFile miscRegFile; // control register file
+
+ public:
+
+ void clear()
+ {
+ intRegFile.clear();
+ floatRegFile.clear();
+ miscRegFile.clear();
+ }
+
+ MiscReg readMiscRegNoEffect(int miscReg)
+ {
+ return miscRegFile.readRegNoEffect(miscReg);
+ }
+
+ MiscReg readMiscReg(int miscReg, ThreadContext *tc)
+ {
+ return miscRegFile.readReg(miscReg, tc);
+ }
+
+ void setMiscRegNoEffect(int miscReg, const MiscReg &val)
+ {
+ miscRegFile.setRegNoEffect(miscReg, val);
+ }
+
+ void setMiscReg(int miscReg, const MiscReg &val,
+ ThreadContext * tc)
+ {
+ miscRegFile.setReg(miscReg, val, tc);
+ }
+
+ FloatRegVal readFloatReg(int floatReg)
+ {
+ return floatRegFile.readReg(floatReg,SingleWidth);
+ }
+
+ FloatRegVal readFloatReg(int floatReg, int width)
+ {
+ return floatRegFile.readReg(floatReg,width);
+ }
+
+ FloatRegBits readFloatRegBits(int floatReg)
+ {
+ return floatRegFile.readRegBits(floatReg,SingleWidth);
+ }
+
+ FloatRegBits readFloatRegBits(int floatReg, int width)
+ {
+ return floatRegFile.readRegBits(floatReg,width);
+ }
+
+ void setFloatReg(int floatReg, const FloatRegVal &val)
+ {
+ floatRegFile.setReg(floatReg, val, SingleWidth);
+ }
+
+ void setFloatReg(int floatReg, const FloatRegVal &val, int width)
+ {
+ floatRegFile.setReg(floatReg, val, width);
+ }
+
+ void setFloatRegBits(int floatReg, const FloatRegBits &val)
+ {
+ floatRegFile.setRegBits(floatReg, val, SingleWidth);
+ }
+
+ void setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
+ {
+ floatRegFile.setRegBits(floatReg, val, width);
+ }
+
+ IntReg readIntReg(int intReg)
+ {
+ // In the Arm, reading from the PC for a generic instruction yields
+ // the current PC + 8, due to previous pipeline implementations
+ if (intReg == PCReg)
+ return intRegFile.readReg(intReg) + 8;
+ //return pc + 8;
+ else
+ return intRegFile.readReg(intReg);
+ }
+
+ void setIntReg(int intReg, const IntReg &val)
+ {
+ // Have to trap writes to PC so that they update NPC instead
+ if (intReg == PCReg)
+ setNextPC(val);
+ else
+ intRegFile.setReg(intReg, val);
+ }
+ protected:
+
+ Addr pc; // program counter
+ Addr npc; // next-cycle program counter
+ Addr nnpc; // next-next-cycle program counter
+
+ public:
+ Addr readPC()
+ {
+ return intRegFile.readReg(PCReg);
+ //return pc;
+ }
+
+ void setPC(Addr val)
+ {
+ intRegFile.setReg(PCReg, val);
+ //pc = val;
+ }
+
+ Addr readNextPC()
+ {
+ return npc;
+ }
+
+ void setNextPC(Addr val)
+ {
+ npc = val;
+ }
+
+ Addr readNextNPC()
+ {
+ return npc + sizeof(MachInst);
+ }
+
+ void setNextNPC(Addr val)
+ {
+ //nnpc = val;
+ }
+
++ void serialize(EventManager *em, std::ostream &os);
++ void unserialize(EventManager *em, Checkpoint *cp,
++ const std::string §ion);
+
+ void changeContext(RegContextParam param, RegContextVal val)
+ {
+ }
+ };
+
+ static inline int flattenIntIndex(ThreadContext * tc, int reg)
+ {
+ return reg;
+ }
+
+ static inline int flattenFloatIndex(ThreadContext * tc, int reg)
+ {
+ return reg;
+ }
+
+ void copyRegs(ThreadContext *src, ThreadContext *dest);
+
+ void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+
+} // namespace ArmISA
+
+#endif
--- /dev/null
- req->setFlags(req->getFlags() | UNCACHEABLE);
+/*
+ * Copyright (c) 2001-2005 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * Copyright (c) 2007-2008 The Florida State University
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ * Steve Reinhardt
++ * Jaidev Patwardhan
+ * Stephen Hines
+ */
+
+#include <string>
+#include <vector>
+
+#include "arch/arm/pagetable.hh"
+#include "arch/arm/tlb.hh"
+#include "arch/arm/faults.hh"
+#include "arch/arm/utility.hh"
+#include "base/inifile.hh"
+#include "base/str.hh"
+#include "base/trace.hh"
+#include "cpu/thread_context.hh"
+#include "sim/process.hh"
+#include "mem/page_table.hh"
+#include "params/ArmDTB.hh"
+#include "params/ArmITB.hh"
+#include "params/ArmTLB.hh"
+#include "params/ArmUTB.hh"
+
+
+using namespace std;
+using namespace ArmISA;
+
+///////////////////////////////////////////////////////////////////////
+//
+// ARM TLB
+//
+
+#define MODE2MASK(X) (1 << (X))
+
+TLB::TLB(const Params *p)
+ : BaseTLB(p), size(p->size), nlu(0)
+{
+ table = new ArmISA::PTE[size];
+ memset(table, 0, sizeof(ArmISA::PTE[size]));
+ smallPages=0;
+}
+
+TLB::~TLB()
+{
+ if (table)
+ delete [] table;
+}
+
+// look up an entry in the TLB
+ArmISA::PTE *
+TLB::lookup(Addr vpn, uint8_t asn) const
+{
+ // assume not found...
+ ArmISA::PTE *retval = NULL;
+ PageTable::const_iterator i = lookupTable.find(vpn);
+ if (i != lookupTable.end()) {
+ while (i->first == vpn) {
+ int index = i->second;
+ ArmISA::PTE *pte = &table[index];
+
+ /* 1KB TLB Lookup code - from ARM ARM Volume III - Rev. 2.50 */
+ Addr Mask = pte->Mask;
+ Addr InvMask = ~Mask;
+ Addr VPN = pte->VPN;
+ // warn("Valid: %d - %d\n",pte->V0,pte->V1);
+ if(((vpn & InvMask) == (VPN & InvMask)) && (pte->G || (asn == pte->asid)))
+ { // We have a VPN + ASID Match
+ retval = pte;
+ break;
+ }
+ ++i;
+ }
+ }
+
+ DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
+ retval ? "hit" : "miss", retval ? retval->PFN1 : 0);
+ return retval;
+}
+
+ArmISA::PTE* TLB::getEntry(unsigned Index) const
+{
+ // Make sure that Index is valid
+ assert(Index<size);
+ return &table[Index];
+}
+
+int TLB::probeEntry(Addr vpn,uint8_t asn) const
+{
+ // assume not found...
+ ArmISA::PTE *retval = NULL;
+ int Ind=-1;
+ PageTable::const_iterator i = lookupTable.find(vpn);
+ if (i != lookupTable.end()) {
+ while (i->first == vpn) {
+ int index = i->second;
+ ArmISA::PTE *pte = &table[index];
+
+ /* 1KB TLB Lookup code - from ARM ARM Volume III - Rev. 2.50 */
+ Addr Mask = pte->Mask;
+ Addr InvMask = ~Mask;
+ Addr VPN = pte->VPN;
+ if(((vpn & InvMask) == (VPN & InvMask)) && (pte->G || (asn == pte->asid)))
+ { // We have a VPN + ASID Match
+ retval = pte;
+ Ind = index;
+ break;
+ }
+
+ ++i;
+ }
+ }
+ DPRINTF(Arm,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind);
+ return Ind;
+}
+Fault inline
+TLB::checkCacheability(RequestPtr &req)
+{
+ Addr VAddrUncacheable = 0xA0000000;
+ // In ARM, cacheability is controlled by certain bits of the virtual address
+ // or by the TLB entry
+ if((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
+ // mark request as uncacheable
- ITB::translate(RequestPtr &req, ThreadContext *tc)
++ req->setFlags(req->getFlags() | Request::UNCACHEABLE);
+ }
+ return NoFault;
+}
+void TLB::insertAt(ArmISA::PTE &pte, unsigned Index, int _smallPages)
+{
+ smallPages=_smallPages;
+ if(Index > size){
+ warn("Attempted to write at index (%d) beyond TLB size (%d)",Index,size);
+ } else {
+ // Update TLB
+ DPRINTF(TLB,"TLB[%d]: %x %x %x %x\n",Index,pte.Mask<<11,((pte.VPN << 11) | pte.asid),((pte.PFN0 <<6) | (pte.C0 << 3) | (pte.D0 << 2) | (pte.V0 <<1) | pte.G),
+ ((pte.PFN1 <<6) | (pte.C1 << 3) | (pte.D1 << 2) | (pte.V1 <<1) | pte.G));
+ if(table[Index].V0 == true || table[Index].V1 == true){ // Previous entry is valid
+ PageTable::iterator i = lookupTable.find(table[Index].VPN);
+ lookupTable.erase(i);
+ }
+ table[Index]=pte;
+ // Update fast lookup table
+ lookupTable.insert(make_pair(table[Index].VPN, Index));
+ // int TestIndex=probeEntry(pte.VPN,pte.asid);
+ // warn("Inserted at: %d, Found at: %d (%x)\n",Index,TestIndex,pte.Mask);
+ }
+
+}
+
+// insert a new TLB entry
+void
+TLB::insert(Addr addr, ArmISA::PTE &pte)
+{
+ fatal("TLB Insert not yet implemented\n");
+}
+
+void
+TLB::flushAll()
+{
+ DPRINTF(TLB, "flushAll\n");
+ memset(table, 0, sizeof(ArmISA::PTE[size]));
+ lookupTable.clear();
+ nlu = 0;
+}
+
+void
+TLB::serialize(ostream &os)
+{
+ SERIALIZE_SCALAR(size);
+ SERIALIZE_SCALAR(nlu);
+
+ for (int i = 0; i < size; i++) {
+ nameOut(os, csprintf("%s.PTE%d", name(), i));
+ table[i].serialize(os);
+ }
+}
+
+void
+TLB::unserialize(Checkpoint *cp, const string §ion)
+{
+ UNSERIALIZE_SCALAR(size);
+ UNSERIALIZE_SCALAR(nlu);
+
+ for (int i = 0; i < size; i++) {
+ table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
+ if (table[i].V0 || table[i].V1) {
+ lookupTable.insert(make_pair(table[i].VPN, i));
+ }
+ }
+}
+
+void
+TLB::regStats()
+{
+ read_hits
+ .name(name() + ".read_hits")
+ .desc("DTB read hits")
+ ;
+
+ read_misses
+ .name(name() + ".read_misses")
+ .desc("DTB read misses")
+ ;
+
+
+ read_accesses
+ .name(name() + ".read_accesses")
+ .desc("DTB read accesses")
+ ;
+
+ write_hits
+ .name(name() + ".write_hits")
+ .desc("DTB write hits")
+ ;
+
+ write_misses
+ .name(name() + ".write_misses")
+ .desc("DTB write misses")
+ ;
+
+
+ write_accesses
+ .name(name() + ".write_accesses")
+ .desc("DTB write accesses")
+ ;
+
+ hits
+ .name(name() + ".hits")
+ .desc("DTB hits")
+ ;
+
+ misses
+ .name(name() + ".misses")
+ .desc("DTB misses")
+ ;
+
+ invalids
+ .name(name() + ".invalids")
+ .desc("DTB access violations")
+ ;
+
+ accesses
+ .name(name() + ".accesses")
+ .desc("DTB accesses")
+ ;
+
+ hits = read_hits + write_hits;
+ misses = read_misses + write_misses;
+ accesses = read_accesses + write_accesses;
+}
+
+Fault
- DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
++ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
+{
+#if !FULL_SYSTEM
+ Process * p = tc->getProcessPtr();
+
+ Fault fault = p->pTable->translate(req);
+ if(fault != NoFault)
+ return fault;
+
+ return NoFault;
+#else
+ fatal("ITB translate not yet implemented\n");
+#endif
+}
+
++void
++ITB::translateTiming(RequestPtr req, ThreadContext *tc,
++ Translation *translation)
++{
++ assert(translation);
++ translation->finish(translateAtomic(req, tc), req, tc, false);
++}
++
++
+Fault
++DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
+{
+#if !FULL_SYSTEM
+ Process * p = tc->getProcessPtr();
+
+ Fault fault = p->pTable->translate(req);
+ if(fault != NoFault)
+ return fault;
+
+ return NoFault;
+#else
+ fatal("DTB translate not yet implemented\n");
+#endif
+}
+
++void
++DTB::translateTiming(RequestPtr req, ThreadContext *tc,
++ Translation *translation, bool write)
++{
++ assert(translation);
++ translation->finish(translateAtomic(req, tc, write), req, tc, write);
++}
++
+///////////////////////////////////////////////////////////////////////
+//
+// Arm ITB
+//
+ITB::ITB(const Params *p)
+ : TLB(p)
+{}
+
+
+///////////////////////////////////////////////////////////////////////
+//
+// Arm DTB
+//
+DTB::DTB(const Params *p)
+ : TLB(p)
+{}
+
+///////////////////////////////////////////////////////////////////////
+//
+// Arm UTB
+//
+UTB::UTB(const Params *p)
+ : ITB(p), DTB(p)
+{}
+
+ArmISA::PTE &
+TLB::index(bool advance)
+{
+ ArmISA::PTE *pte = &table[nlu];
+
+ if (advance)
+ nextnlu();
+
+ return *pte;
+}
+
+ArmISA::ITB *
+ArmITBParams::create()
+{
+ return new ArmISA::ITB(this);
+}
+
+ArmISA::DTB *
+ArmDTBParams::create()
+{
+ return new ArmISA::DTB(this);
+}
+
+ArmISA::UTB *
+ArmUTBParams::create()
+{
+ return new ArmISA::UTB(this);
+}
--- /dev/null
- mutable Stats::Scalar<> read_hits;
- mutable Stats::Scalar<> read_misses;
- mutable Stats::Scalar<> read_acv;
- mutable Stats::Scalar<> read_accesses;
- mutable Stats::Scalar<> write_hits;
- mutable Stats::Scalar<> write_misses;
- mutable Stats::Scalar<> write_acv;
- mutable Stats::Scalar<> write_accesses;
+/*
+ * Copyright (c) 2001-2005 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * Copyright (c) 2007-2008 The Florida State University
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ * Steve Reinhardt
+ * Stephen Hines
+ */
+
+#ifndef __ARCH_ARM_TLB_HH__
+#define __ARCH_ARM_TLB_HH__
+
+#include <map>
+
+#include "arch/arm/isa_traits.hh"
+#include "arch/arm/utility.hh"
+#include "arch/arm/vtophys.hh"
+#include "arch/arm/pagetable.hh"
+#include "base/statistics.hh"
+#include "mem/request.hh"
+#include "params/ArmDTB.hh"
+#include "params/ArmITB.hh"
+#include "sim/faults.hh"
+#include "sim/tlb.hh"
+
+class ThreadContext;
+
+/* ARM does not distinguish between a DTLB and an ITLB -> unified TLB
+ However, to maintain compatibility with other architectures, we'll
+ simply create an ITLB and DTLB that will point to the real TLB */
+namespace ArmISA {
+
+// WARN: This particular TLB entry is not necessarily conformed to ARM ISA
+struct TlbEntry
+{
+ Addr _pageStart;
+ TlbEntry() {}
+ TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
+
++ void
++ updateVaddr(Addr new_vaddr)
++ {
++ panic("unimplemented");
++ }
++
+ Addr pageStart()
+ {
+ return _pageStart;
+ }
+
+ void serialize(std::ostream &os)
+ {
+ SERIALIZE_SCALAR(_pageStart);
+ }
+
+ void unserialize(Checkpoint *cp, const std::string §ion)
+ {
+ UNSERIALIZE_SCALAR(_pageStart);
+ }
+
+};
+
+class TLB : public BaseTLB
+{
+ protected:
+ typedef std::multimap<Addr, int> PageTable;
+ PageTable lookupTable; // Quick lookup into page table
+
+ ArmISA::PTE *table; // the Page Table
+ int size; // TLB Size
+ int nlu; // not last used entry (for replacement)
+
+ void nextnlu() { if (++nlu >= size) nlu = 0; }
+ ArmISA::PTE *lookup(Addr vpn, uint8_t asn) const;
+
- class ITB : public TLB {
++ mutable Stats::Scalar read_hits;
++ mutable Stats::Scalar read_misses;
++ mutable Stats::Scalar read_acv;
++ mutable Stats::Scalar read_accesses;
++ mutable Stats::Scalar write_hits;
++ mutable Stats::Scalar write_misses;
++ mutable Stats::Scalar write_acv;
++ mutable Stats::Scalar write_accesses;
+ Stats::Formula hits;
+ Stats::Formula misses;
+ Stats::Formula invalids;
+ Stats::Formula accesses;
+
+ public:
+ typedef ArmTLBParams Params;
+ TLB(const Params *p);
+
+ int probeEntry(Addr vpn,uint8_t) const;
+ ArmISA::PTE *getEntry(unsigned) const;
+ virtual ~TLB();
+ int smallPages;
+ int getsize() const { return size; }
+
+ ArmISA::PTE &index(bool advance = true);
+ void insert(Addr vaddr, ArmISA::PTE &pte);
+ void insertAt(ArmISA::PTE &pte, unsigned Index, int _smallPages);
+ void flushAll();
+ void demapPage(Addr vaddr, uint64_t asn)
+ {
+ panic("demapPage unimplemented.\n");
+ }
+
+ // static helper functions... really
+ static bool validVirtualAddress(Addr vaddr);
+
+ static Fault checkCacheability(RequestPtr &req);
+
+ // Checkpointing
+ void serialize(std::ostream &os);
+ void unserialize(Checkpoint *cp, const std::string §ion);
+
+ void regStats();
+};
+
- Fault translate(RequestPtr &req, ThreadContext *tc);
++class ITB : public TLB
++{
+ public:
+ typedef ArmTLBParams Params;
+ ITB(const Params *p);
+
- class DTB : public TLB {
++ Fault translateAtomic(RequestPtr req, ThreadContext *tc);
++ void translateTiming(RequestPtr req, ThreadContext *tc,
++ Translation *translation);
+};
+
- Fault translate(RequestPtr &req, ThreadContext *tc, bool write = false);
++class DTB : public TLB
++{
+ public:
+ typedef ArmTLBParams Params;
+ DTB(const Params *p);
+
- class UTB : public ITB, public DTB {
++ Fault translateAtomic(RequestPtr req, ThreadContext *tc, bool write);
++ void translateTiming(RequestPtr req, ThreadContext *tc,
++ Translation *translation, bool write);
+};
+
++class UTB : public ITB, public DTB
++{
+ public:
+ typedef ArmTLBParams Params;
+ UTB(const Params *p);
+
+};
+
+}
+
+#endif // __ARCH_ARM_TLB_HH__
projects / gem5.git / commitdiff