return mid as part of ports

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 05736f9caa8ae949d01259c71a672516838dcd22..74ce502d65a8fd3209a3ba211a94ab43631a581d 100644 (file)
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -118,7 +118,7 @@ class InputGroup:
         for i in range(self.num_rows):
             inop = self.rs[i]
             res += inop.in_op + [inop.stb]
-        return self.out_op.ports() + res #+ [self.ack + self.stb]
+        return self.out_op.ports() + res + [self.mid]
 
 
 class FPGetOpMod: