getting there with instruction overlapping

diff --git a/src/experiment/compalu.py b/src/experiment/compalu.py
index 3c97c19af99c9938c86a056477492864244ca948..cd781603c243f5f71eaec0ec52cd5aded1842b23 100644 (file)
--- a/src/experiment/compalu.py
+++ b/src/experiment/compalu.py
@@ -53,11 +53,11 @@ class ComputationUnitNoDelay(Elaboratable):
         # outputs
         m.d.comb += self.busy_o.eq(opc_l.q) # busy out
 
-        with m.If(self.go_rd_i):
-            m.d.sync += self.counter.eq(2)
+        with m.If(src_l.q & (self.counter == 0)):
+            m.d.sync += self.counter.eq(3)
         with m.If(self.counter > 0):
             m.d.sync += self.counter.eq(self.counter - 1)
-        with m.If(self.counter == 1):
+        with m.If((self.counter == 1) | (self.counter == 0)):
             m.d.comb += self.req_rel_o.eq(req_l.q & opc_l.q) # req release out
 
         # create a latch/register for src1/src2

diff --git a/src/experiment/cscore.py b/src/experiment/cscore.py
index 32548e25ccb0eb433cedf2763c08fda4a8616f93..4faa049af2c52bdd5dae6fba34223cef9d6ae319 100644 (file)
--- a/src/experiment/cscore.py
+++ b/src/experiment/cscore.py
@@ -183,7 +183,9 @@ class Scoreboard(Elaboratable):
         #---------
         # Connect Register File(s)
         #---------
-        m.d.comb += int_dest.wen.eq(g_int_wr_pend_v.g_pend_o)
+        with m.If(if_l[0].go_wr_i | if_l[1].go_wr_i):
+            m.d.comb += int_dest.wen.eq(g_int_wr_pend_v.g_pend_o)
+        #with m.If(intpick1.go_rd_o):
         m.d.comb += int_src1.ren.eq(g_int_src1_pend_v.g_pend_o)
         m.d.comb += int_src2.ren.eq(g_int_src2_pend_v.g_pend_o)
 
@@ -315,7 +317,7 @@ def scoreboard_sim(dut, alusim):
                 break
         op = randint(0, 1)
         if False:
-            if i == 0:
+            if i % 2 == 0:
                 src1 = 6
                 src2 = 6
                 dest = 1
@@ -329,20 +331,33 @@ def scoreboard_sim(dut, alusim):
 
             op = i
 
+        if True:
+            if i == 0:
+                src1 = 2
+                src2 = 3
+                dest = 3
+            else:
+                src1 = 5
+                src2 = 4
+                dest = 7
+
+            #op = (i+1) % 2
+            op = 0
+
         print ("random %d: %d %d %d %d\n" % (i, op, src1, src2, dest))
         yield from int_instr(dut, alusim, op, src1, src2, dest)
         yield from print_reg(dut, [3,4,5])
-        yield
         while True:
+            yield
             issue_o = yield dut.issue_o
             if issue_o:
+                yield from print_reg(dut, [3,4,5])
+                for i in range(len(dut.int_insn_i)):
+                    yield dut.int_insn_i[i].eq(0)
+                yield
                 break
             print ("busy",)
             yield from print_reg(dut, [3,4,5])
-            yield
-        yield from print_reg(dut, [3,4,5])
-        for i in range(len(dut.int_insn_i)):
-            yield dut.int_insn_i[i].eq(0)
 
 
     yield
@@ -359,7 +374,11 @@ def scoreboard_sim(dut, alusim):
     yield
     yield
     yield
+    yield
+    yield
+    yield
     yield from alusim.check(dut)
+    yield from alusim.dump(dut)
 
 
 def explore_groups(dut):

diff --git a/src/scoreboard/fn_unit.py b/src/scoreboard/fn_unit.py
index a4eff476e387ca764be8fcb623728edfd4a24746..3edabbde16eb2c2dc41eb4b5f9e8a4d508835090 100644 (file)
--- a/src/scoreboard/fn_unit.py
+++ b/src/scoreboard/fn_unit.py
@@ -141,9 +141,9 @@ class FnUnit(Elaboratable):
         src1_r = Signal(max=self.reg_width, reset_less=True)
         src2_r = Signal(max=self.reg_width, reset_less=True)
         # XXX latch based on *issue* rather than !latch (as in book)
-        latchregister(m, self.dest_i, dest_r, wr_l.qn)
-        latchregister(m, self.src1_i, src1_r, wr_l.qn)
-        latchregister(m, self.src2_i, src2_r, wr_l.qn)
+        latchregister(m, self.dest_i, dest_r, self.issue_i) #wr_l.qn)
+        latchregister(m, self.src1_i, src1_r, self.issue_i) #wr_l.qn)
+        latchregister(m, self.src2_i, src2_r, self.issue_i) #wr_l.qn)
 
         # dest decoder (use dest reg as input): write-pending out
         m.d.comb += dest_d.i.eq(dest_r)
@@ -165,7 +165,7 @@ class FnUnit(Elaboratable):
         ro = Signal(reset_less=True)
         m.d.comb += g_rd.eq(self.g_wr_pend_i & self.rd_pend_o)
         m.d.comb += ro.eq(~g_rd.bool())
-        m.d.comb += self.readable_o.eq(ro & wr_l.q)
+        m.d.comb += self.readable_o.eq(ro & rd_l.q)
 
         # writable output signal
         g_wr_v = Signal(self.reg_width, reset_less=True)