Revert "ok ok - for OP_BCREG put CTR in spr2 as well"

This reverts commit 87810631b7ecbd34ad89b2853bbdb763fe003633.

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 61caf55691905c554e0ce549821d2e6debd2ba4f..84d5ed71bda0fa9140e179b429ea75e1fb18d5c1 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -64,6 +64,12 @@ class DecodeA(Elaboratable):
             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
                 comb += self.fast_out.ok.eq(1)
+        with m.Elif(op.internal_op == InternalOp.OP_BCREG):
+            xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
+            xo5 = self.dec.FormXL.XO[5] # 3.0B p38
+            with m.If(xo9 & ~xo5):
+                comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
+                comb += self.fast_out.ok.eq(1)
 
         # MFSPR or MTSPR: move-from / move-to SPRs
         with m.If((op.internal_op == InternalOp.OP_MFSPR) |
@@ -166,9 +172,6 @@ class DecodeB(Elaboratable):
             with m.Elif(xo5):
                 comb += self.fast_out.data.eq(FastRegs.TAR)
                 comb += self.fast_out.ok.eq(1)
-            with m.Else():
-                comb += self.fast_out.data.eq(FastRegs.CTR)
-                comb += self.fast_out.ok.eq(1)
 
         return m