self.comb does not exist, comb is a local temp-var (comb = m.d.comb)

diff --git a/pinmux b/pinmux
index 51b67140fa1160d94824951caa34fa2f8432835b..d96f737c0a53dde983060522816bbef016b449ce 160000 (submodule)
--- a/pinmux
+++ b/pinmux
@@ -1 +1 @@
-Subproject commit 51b67140fa1160d94824951caa34fa2f8432835b
+Subproject commit d96f737c0a53dde983060522816bbef016b449ce

diff --git a/src/soc/bus/tercel.py b/src/soc/bus/tercel.py
index 6380e60569cc4b643a3e95bf8b1c097f04263bd2..870b3dd0695a7277b4f7033900aeab9f46fda81f 100644 (file)
--- a/src/soc/bus/tercel.py
+++ b/src/soc/bus/tercel.py
@@ -95,7 +95,7 @@ class Tercel(Elaboratable):
         # Calculate SPI flash address
         spi_bus_adr = Signal(30)
         # wb address is in words, offset is in bytes
-        self.comb += spi_bus_adr.eq(bus.adr - (adr_offset >> 2))
+        comb += spi_bus_adr.eq(bus.adr - (adr_offset >> 2))
 
         # create definition of external verilog Tercel code here, so that
         # nmigen understands I/O directions (defined by i_ and o_ prefixes)
@@ -153,7 +153,7 @@ class Tercel(Elaboratable):
                     i_USRMCLKTS = 0
                 )
             else:
-                self.comb += pads.clk.eq(self.spi_clk)
+                comb += pads.clk.eq(self.spi_clk)
 
         return m
 

diff --git a/src/soc/litex/florent b/src/soc/litex/florent
index 7d772615665d66a2c281ccbb3fda0e02c169ef12..b55917aafa6bbc9f16e1d97dc095e929c31aa81a 160000 (submodule)
--- a/src/soc/litex/florent
+++ b/src/soc/litex/florent
@@ -1 +1 @@
-Subproject commit 7d772615665d66a2c281ccbb3fda0e02c169ef12
+Subproject commit b55917aafa6bbc9f16e1d97dc095e929c31aa81a