underscore names on submodules possibly interfering with verilator

diff --git a/c4m/nmigen/jtag/tap.py b/c4m/nmigen/jtag/tap.py
index dff63ac989de9f1d5b23419ee6388815af9ebc60..5743363a5b8bc5ba007249f4c764f0742f71c844 100755 (executable)
--- a/c4m/nmigen/jtag/tap.py
+++ b/c4m/nmigen/jtag/tap.py
@@ -355,13 +355,13 @@ class TAP(Elaboratable):
         cmd_preload = 2
         cmd_bypass = 2**ir_width - 1 # All ones
 
-        m.submodules._fsm = fsm = _FSM(bus=self.bus)
+        m.submodules.fsm = fsm = _FSM(bus=self.bus)
         m.domains.posjtag = fsm.posjtag
         m.domains.negjtag = fsm.negjtag
 
         # IR block
         select_ir = fsm.isir
-        m.submodules._irblock = irblock = _IRBlock(
+        m.submodules.irblock = irblock = _IRBlock(
             ir_width=ir_width, cmd_idcode=cmd_idcode, tdi=self.bus.tdi,
             capture=(fsm.isir & fsm.capture),
             shift=(fsm.isir & fsm.shift),
@@ -376,7 +376,7 @@ class TAP(Elaboratable):
         m.d.comb += select_id.eq(fsm.isdr &
                                  ((ir == cmd_idcode) | (ir == cmd_bypass)))
         m.d.comb += id_bypass.eq(ir == cmd_bypass)
-        m.submodules._idblock = idblock = _IDBypassBlock(
+        m.submodules.idblock = idblock = _IDBypassBlock(
             manufacturer_id=self._manufacturer_id,
             part_number=self._part_number,
             version=self._version, tdi=self.bus.tdi,