sort out SPR setting in MMU

diff --git a/src/soc/fu/mmu/test/test_issuer_mmu_rom.py b/src/soc/fu/mmu/test/test_issuer_mmu_rom.py
index 640f8ed8f5f39c9a5a1474701235f7b330b5b0ba..9f5e786df00214652fc7335a975c66741558fab0 100644 (file)
--- a/src/soc/fu/mmu/test/test_issuer_mmu_rom.py
+++ b/src/soc/fu/mmu/test/test_issuer_mmu_rom.py
@@ -48,9 +48,8 @@ class MMUTestCase(TestAccumulatorBase):
         prtbl = 0x1000000
         initial_regs[1] = prtbl
         
-        
-
-        initial_sprs = {}
+        initial_sprs = {'DSISR': 0, 'DAR': 0,
+                         720: 0}
         self.add_case(Program(lst, bigendian),
                       initial_regs, initial_sprs)
 

diff --git a/src/soc/regfile/util.py b/src/soc/regfile/util.py
index 79effa7c251d589d045478a7f6e16ab095fafd21..5ccc4c54c607d1c6cc18f4d0fbd672353d8646d7 100644 (file)
--- a/src/soc/regfile/util.py
+++ b/src/soc/regfile/util.py
@@ -24,7 +24,7 @@ def fast_reg_to_spr(spr_num):
 def spr_to_fast_reg(spr_num):
     if not isinstance(spr_num, str):
         spr_num = spr_dict[spr_num].SPR
-    return sprstr_to_fast[spr_num]
+    return sprstr_to_fast.get(spr_num, None)
 
 
 def slow_reg_to_spr(slow_reg):

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 6f7c8ffdc87e3a983c724a06d4a8026131bda575..0bf1ee42d019ef594df0333e025a2bf7b0371030 100644 (file)
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -100,9 +100,9 @@ def setup_regs(pdecode2, core, test):
             # match behaviour of SPRMap in power_decoder2.py
             for i, x in enumerate(SPR):
                 if sprname == x.name:
-                    yield sregs[i].reg.eq(val)
                     print("setting slow SPR %d (%s) to %x" %
                           (i, sprname, val))
+                    yield sregs.memory._array[i].eq(val)
         else:
             yield fregs.regs[fast].reg.eq(val)
             print("setting fast reg %d (%s) to %x" %