remove MSR and add CIA to MMU Input Record

diff --git a/src/soc/fu/mmu/mmu_input_record.py b/src/soc/fu/mmu/mmu_input_record.py
index 109d2d389327f646404df4dfcaf5ba324b42c466..281e8dd86de04b295d1faf931a77f8bdb97ff482 100644 (file)
--- a/src/soc/fu/mmu/mmu_input_record.py
+++ b/src/soc/fu/mmu/mmu_input_record.py
@@ -13,7 +13,7 @@ class CompMMUOpSubset(CompOpSubsetBase):
         layout = (('insn_type', MicrOp),
                   ('fn_unit', Function),
                   ('insn', 32),
-                  ('msr', 64), # TODO: a lot less bits.  only need PR, DR, SF
+                  ('cia', 64), # for instruction fault (MMU PTE lookup)
                   ('zero_a', 1),
                   )
         super().__init__(layout, name=name)