add external interface definitions

diff --git a/src/bsv/bsv_lib/slow_peripherals_template.bsv b/src/bsv/bsv_lib/slow_peripherals_template.bsv
index 2ea5426fd9e572302d57f98ffde94e9cc6bf175e..57abf4173f574d9228a97bfe2de9f2eaa6b3bcc9 100644 (file)
--- a/src/bsv/bsv_lib/slow_peripherals_template.bsv
+++ b/src/bsv/bsv_lib/slow_peripherals_template.bsv
@@ -56,7 +56,7 @@ package slow_peripherals;
                        method Bit#(`DATA) mtime;
                `endif
                `ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note; `endif
-    interface IOCellSide iocell_side; // mandatory interface
+        interface IOCellSide iocell_side; // mandatory interface
 {1}
        endinterface
        /*================================*/
@@ -183,15 +183,7 @@ package slow_peripherals;
                        method mtip_int=clint.mtip_int;
                        method mtime=clint.mtime;
                `endif
-               `ifdef I2C0
-                       method i2c0_isint=i2c0.isint;
-               `endif
-               `ifdef I2C1
-                       method i2c1_isint=i2c1.isint;
-               `endif
-               `ifdef QSPI0 method     qspi0_isint=qspi0.interrupts[5]; `endif
-               `ifdef QSPI1 method     qspi1_isint=qspi1.interrupts[5]; `endif
-               `ifdef UART0 method uart0_intr=uart0.irq; `endif
+{12}
                interface SP_dedicated_ios slow_ios;
 /* template for dedicated peripherals
                        `ifdef UART0

diff --git a/src/bsv/peripheral_gen.py b/src/bsv/peripheral_gen.py
index 1737ba3662d0d5f0579e8b79f7aad479cb76e0c4..aa09b0bcc4bdc86e6252f1f720861f7855e78902 100644 (file)
--- a/src/bsv/peripheral_gen.py
+++ b/src/bsv/peripheral_gen.py
@@ -21,6 +21,9 @@ class PBase(object):
     def slowifdecl(self):
         return ''
 
+    def get_iname(self, inum):
+        return "{0}{1}".format(self.name, self.mksuffix(self.name, inum))
+
     def axibase(self, name, ifacenum):
         name = name.upper()
         return "%(name)s%(ifacenum)dBase" % locals()
@@ -167,7 +170,7 @@ class PBase(object):
         niq = self.num_irqs()
         if niq == 0:
             return ('', irq_offs)
-        name = "{0}{1}".format(self.name, self.mksuffix(self.name, inum))
+        name = self.get_iname(inum)
         res.append("    // PLIC rules for {0}".format(name))
         for idx in range(niq):
             plic_obj = self.plic_object(name, idx)
@@ -177,6 +180,10 @@ class PBase(object):
             irq_offs += 1 # increment to next irq
         return ('\n'.join(res), irq_offs)
 
+    def mk_ext_ifacedef(self, iname, inum):
+        return ''
+
+
 mkplic_rule = """\
      rule rl_connect_{0}_to_plic_{2};
         if({1} == 1'b1) begin
@@ -265,12 +272,19 @@ class quart(PBase):
         return "{0}_interrupt.read".format(pname)
 
     def mk_plic(self, inum, irq_offs):
-        name = "{0}{1}".format(self.name, self.mksuffix(self.name, inum))
+        name = self.get_iname(inum)
         ret = [uart_plic_template.format(name, irq_offs)]
         (ret2, irq_offs) = PBase.mk_plic(self, inum, irq_offs)
         ret.append(ret2)
         return ('\n'.join(ret), irq_offs)
 
+    def mk_ext_ifacedef(self, iname, inum):
+        name = self.get_iname(inum)
+        return "        method {0}_intr = {0}.irq;".format(name)
+
+    def slowifdeclmux(self):
+        return "        method Bit#(1) {1}{0}_intr;"
+
 uart_plic_template = """\
      // PLIC {0} synchronisation with irq {1}
      SyncBitIfc#(Bit#(1)) {0}_interrupt <-
@@ -354,6 +368,13 @@ class twi(PBase):
                 "{0}.isber()"
                ][idx].format(pname)
 
+    def mk_ext_ifacedef(self, iname, inum):
+        name = self.get_iname(inum)
+        return "        method {0}_isint = {0}.isint;".format(name)
+
+    def slowifdeclmux(self):
+        return "        method Bit#(1) {1}{0}_isint;"
+
 
 class eint(PBase):
 
@@ -421,10 +442,10 @@ class jtag(PBase):
         return ''
 
     def slowifdeclmux(self):
-        return "            method  Action jtag_ms (Bit#(1) in);\n" +  \
-               "            method  Bit#(1) jtag_di;\n" + \
-               "            method  Action jtag_do (Bit#(1) in);\n" + \
-               "            method  Action jtag_ck (Bit#(1) in);"
+        return "        method  Action jtag_ms (Bit#(1) in);\n" +  \
+               "        method  Bit#(1) jtag_di;\n" + \
+               "        method  Action jtag_do (Bit#(1) in);\n" + \
+               "        method  Action jtag_ck (Bit#(1) in);"
 
     def slowifinstance(self):
         return jtag_method_template # bit of a lazy hack this...
@@ -523,6 +544,13 @@ class spi(PBase):
         ret.append("    endrule")
         return '\n'.join(ret)
 
+    def mk_ext_ifacedef(self, iname, inum):
+        name = self.get_iname(inum)
+        return "        method {0}_isint = {0}.interrupts[5];".format(name)
+
+    def slowifdeclmux(self):
+        return "        method Bit#(1) {1}{0}_isint;"
+
 
 class qspi(PBase):
 
@@ -590,6 +618,14 @@ class qspi(PBase):
     def plic_object(self, pname, idx):
         return "{0}.interrupts()[{1}]".format(pname, idx)
 
+    def mk_ext_ifacedef(self, iname, inum):
+        name = self.get_iname(inum)
+        return "        method {0}_isint = {0}.interrupts[5];".format(name)
+
+    def slowifdeclmux(self):
+        return "        method Bit#(1) {1}{0}_isint;"
+
+
 
 class pwm(PBase):
 
@@ -621,7 +657,7 @@ class gpio(PBase):
 
     def slowifdeclmux(self):
         size = len(self.peripheral.pinspecs)
-        return "    interface GPIO_config#(%d) pad_config{0};" % size
+        return "        interface GPIO_config#(%d) pad_config{0};" % size
 
     def num_axi_regs32(self):
         return 2
@@ -739,7 +775,7 @@ class PeripheralIface(object):
             self.slow.peripheral = self
         for fname in ['slowimport', 
                       'slowifinstance', 'slowifdecl', 'slowifdeclmux',
-                      'mkslow_peripheral', 'mk_plic',
+                      'mkslow_peripheral', 'mk_plic', 'mk_ext_ifacedef',
                       'mk_connection', 'mk_cellconn', 'mk_pincon']:
             fn = CallFn(self, fname)
             setattr(self, fname, types.MethodType(fn, self))
@@ -876,6 +912,14 @@ class PeripheralInterfaces(object):
                 ret.append(txt)
         return '\n'.join(list(filter(None, ret)))
 
+    def mk_ext_ifacedef(self):
+        ret = []
+        for (name, count) in self.ifacecount:
+            for i in range(count):
+                txt = self.data[name].mk_ext_ifacedef(name, i)
+                ret.append(txt)
+        return '\n'.join(list(filter(None, ret)))
+
 
     def mk_plic(self):
         ret = []

diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py
index 0e4b1423dc04b7cf6d53ac37a3771c8edc8fe45c..3a9cccb32e68ff85424171ff5414e81bf1a3ce51 100644 (file)
--- a/src/bsv/pinmux_generator.py
+++ b/src/bsv/pinmux_generator.py
@@ -123,11 +123,12 @@ def write_slow(slow, template, p, ifaces, iocells):
     inst = ifaces.slowifinstance()
     mkplic = ifaces.mk_plic()
     numsloirqs = ifaces.mk_sloirqsdef()
+    ifacedef = ifaces.mk_ext_ifacedef()
     with open(slow, "w") as bsv_file:
         bsv_file.write(template.format(imports, ifdecl, regdef, slavedecl,
                                        fnaddrmap, mkslow, mkcon, mkcellcon,
                                        pincon, inst, mkplic,
-                                       numsloirqs))
+                                       numsloirqs, ifacedef))
 
 
 def write_bus(bus, p, ifaces):