+++ /dev/null
-#!/usr/bin/env python
-
-from helpers import l, u, n
-
-
-chip = { 'pads.ioPadGauge' : 'pxlib',
-
- # | Instance | Pad | To Core | From Core | Enable |
- 'pads.instances' :[
- # "a" input.
- [ 'p_a0' , 'a(0)', 'a(0)' ],
- [ 'p_a1' , 'a(1)', 'a(1)' ],
- [ 'p_a2' , 'a(2)', 'a(2)' ],
- [ 'p_a3' , 'a(3)', 'a(3)' ],
- # "b" input.
- [ 'p_b0' , 'b(0)', 'b(0)' ],
- [ 'p_b1' , 'b(1)', 'b(1)' ],
- [ 'p_b2' , 'b(2)', 'b(2)' ],
- [ 'p_b3' , 'b(3)', 'b(3)' ],
- # "f" output.
- [ 'p_f0' , 'f(0)', 'f(0)' ], # , 'f_oe' ],
- [ 'p_f1' , 'f(1)', 'f(1)' ], # , 'f_oe' ],
- [ 'p_f2' , 'f(2)', 'f(2)' ], # , 'f_oe' ],
- [ 'p_f3' , 'f(3)', 'f(3)' ], # , 'f_oe' ],
- ],
- 'pads.south' :
- [ 'p_a1', 'p_vddick_0', 'p_vssick_0' , 'p_a0' ],
- 'pads.east' :
- [ 'p_a2', 'p_a3' , 'p_b3' , 'p_b2' ],
- 'pads.north' :
- [ 'p_b1', 'p_vddeck_0', 'p_b0' , 'p_vsseck_0', 'rst' ],
- 'pads.west' :
- [ 'p_f3', 'p_f2' , 'p_clk_0', 'p_f1' , 'p_f0' ],
- 'core.size' : ( l( 1200), l( 1200) ),
- 'chip.size' : ( l(3200), l(3200) ),
- 'pads.useCoreSize' : True,
- 'chip.clockTree' : True,
- }
-
--- /dev/null
+
+from __future__ import print_function
+import sys
+import traceback
+import collections
+import CRL
+import helpers
+helpers.loadUserSettings()
+from helpers import trace, l, u, n
+from helpers.io import ErrorMessage, WarningMessage
+from helpers.overlay import UpdateSession
+import plugins
+from Hurricane import Breakpoint, DbU, Transformation, Box, Instance
+from plugins.alpha.block.block import Block
+from plugins.alpha.block.configuration import IoPin, GaugeConf
+from plugins.alpha.core2chip.libresocio import CoreToChip
+from plugins.alpha.chip.configuration import ChipConf
+from plugins.alpha.chip.chip import Chip
+
+
+af = CRL.AllianceFramework.get()
+
+
+def isiterable ( pyobj ):
+ if isinstance(pyobj,collections.Iterable): return True
+ return False
+
+
+def doIoPinVector ( ioSpec, bits ):
+ v = []
+ if not isiterable(bits): bits = range(bits)
+ if len(ioSpec) != 5:
+ raise ErrorMessage( 1, [ 'doIoPinVector(): Argument "ioSpec" must have excatly 5 fields ({})'.format(len(ioSpec))
+ , '(ioSpec={})'.format(ioSpec)
+ ] )
+ if not bits:
+ raise ErrorMessage( 1, [ 'doIoPinVector(): Argument "bits" is neither a width nor an iterable.'
+ , '(bits={})'.format(bits)
+ ] )
+ for bit in bits:
+ v.append(( ioSpec[0]
+ , ioSpec[1]
+ , ioSpec[2].format(bit)
+ , ioSpec[3].format(bit)
+ , ioSpec[4].format(bit) ))
+ return v
+
+
+def scriptMain ( **kw ):
+ """The mandatory function to be called by Coriolis CGT/Unicorn."""
+ global af
+ rvalue = True
+ try:
+ #helpers.setTraceLevel( 540 )
+ Breakpoint.setStopLevel( 100 )
+ buildChip = True
+ cell, editor = plugins.kwParseMain( **kw )
+ cell = af.getCell( 'memory', CRL.Catalog.State.Logical )
+ if editor:
+ editor.setCell( cell )
+ editor.setDbuMode( DbU.StringModePhysical )
+
+ ioPadsSpec = []
+ ioPadsSpec += doIoPinVector( (IoPin.WEST , None, 'a_{}', 'a({})', 'a({})'), 8 )
+ ioPadsSpec += doIoPinVector( (IoPin.SOUTH, None, 'b_{}', 'b({})', 'b({})'), 8 )
+ ioPadsSpec += doIoPinVector( (IoPin.EAST , None, 'f_{}', 'f({})', 'f({})'), 8 )
+ ioPadsSpec += doIoPinVector( (IoPin.NORTH, None, 'we_{}', 'we({})', 'we({})'), range(0,4) )
+ ioPadsSpec += [ (IoPin.NORTH, None, 'clk' , 'clk', 'clk' )
+ , (IoPin.NORTH, None, 'power_0' , 'vdd' )
+ , (IoPin.NORTH, None, 'ground_0' , 'vss' )
+ , (IoPin.NORTH, None, 'ioground_0', 'iovss' )
+ , (IoPin.NORTH, None, 'iopower_0' , 'iovdd' )
+ , (IoPin.NORTH, None, 'iopower_1' , 'iovdd' )
+ , (IoPin.NORTH, None, 'rst' , 'rst', 'rst' )
+ ]
+ ioPadsSpec += doIoPinVector( (IoPin.NORTH, None, 'we_{}', 'we({})', 'we({})'), range(4,8) )
+ ioPinsSpec = [ (IoPin.WEST |IoPin.A_BEGIN, 'a({})' , u( 3.3), u( 6.6), 64)
+ , (IoPin.SOUTH|IoPin.A_BEGIN, 'b({})' , u( 3.3), u( 6.6), 64)
+ , (IoPin.EAST |IoPin.A_BEGIN, 'f({})' , u( 3.3), u( 6.6), 64)
+ , (IoPin.NORTH|IoPin.A_BEGIN, 'we({})' , u( 3.3), u( 6.6), 8)
+ , (IoPin.NORTH|IoPin.A_BEGIN, 'rst' , u( 33.0), 0 , 1)
+ , (IoPin.NORTH|IoPin.A_BEGIN, 'clk' , u( 66.0), 0 , 1)
+ ]
+ memoryConf = ChipConf( cell, ioPins=ioPinsSpec, ioPads=ioPadsSpec )
+ memoryConf.cfg.viewer.pixelThreshold = 5
+ memoryConf.cfg.etesian.bloat = 'nsxlib'
+ memoryConf.cfg.etesian.uniformDensity = True
+ memoryConf.cfg.etesian.aspectRatio = 1.0
+ # etesian.spaceMargin is ignored if the coreSize is directly set.
+ memoryConf.cfg.etesian.spaceMargin = 0.20
+ memoryConf.cfg.anabatic.searchHalo = 2
+ memoryConf.cfg.anabatic.globalIterations = 20
+ memoryConf.cfg.anabatic.topRoutingLayer = 'METAL5'
+ memoryConf.cfg.katana.hTracksReservedLocal = 6
+ memoryConf.cfg.katana.vTracksReservedLocal = 3
+ memoryConf.cfg.katana.hTracksReservedMin = 3
+ memoryConf.cfg.katana.vTracksReservedMin = 1
+ memoryConf.cfg.block.spareSide = u(200)
+ #memoryConf.cfg.chip.padCoreSide = 'North'
+ #memoryConf.cfg.chip.use45corners = False
+ memoryConf.cfg.chip.useAbstractPads = True
+ memoryConf.editor = editor
+ memoryConf.useSpares = False
+ memoryConf.useClockTree = False
+ memoryConf.useHFNS = False
+ memoryConf.bColumns = 2
+ memoryConf.bRows = 3
+ memoryConf.chipName = 'chip'
+ memoryConf.chipConf.ioPadGauge = 'LibreSOCIO'
+ memoryConf.coreSize = ( u( 988.0), u( 988.0) )
+ memoryConf.chipSize = ( u(2000.0), u(2000.0) )
+
+ with UpdateSession():
+ sliceHeight = memoryConf.sliceHeight
+ coreAb = Box( 0, 0, u(988.0), u(988.0) )
+ cell.setAbutmentBox( coreAb )
+ sramName = 'subckt_500_SPBlock_512W64B8W'
+ sram = cell.getInstance( sramName )
+ if not sram:
+ print( '[ERROR] SRAM instance "{}" not found.'.format(sramName) )
+ else:
+ sramAb = sram.getMasterCell().getAbutmentBox()
+ sram.setTransformation( Transformation( coreAb.getXMax() - sramAb.getWidth()
+ , u(0.0)
+ , Transformation.Orientation.ID ) )
+ sram.setPlacementStatus( Instance.PlacementStatus.FIXED )
+ sramAb = sram.getAbutmentBox()
+ memoryConf.placeArea = Box( coreAb.getXMin()
+ , coreAb.getYMax() - sliceHeight*10
+ , coreAb.getXMax()
+ , coreAb.getYMax()
+ )
+ Breakpoint.stop( 99, 'After core block placement.' )
+
+ if buildChip:
+ arlet6502ToChip = CoreToChip( memoryConf )
+ arlet6502ToChip.buildChip()
+ chipBuilder = Chip( memoryConf )
+ rvalue = chipBuilder.doPnR()
+ chipBuilder.save()
+ CRL.Gds.save( memoryConf.chip )
+ else:
+ blockBuilder = Block( memoryConf )
+ rvalue = blockBuilder.doPnR()
+ blockBuilder.save()
+ CRL.Gds.save( memoryConf.cell )
+ except Exception, e:
+ helpers.io.catch( e )
+ rvalue = False
+ sys.stdout.flush()
+ sys.stderr.flush()
+ return rvalue
projects / soclayout.git / commitdiff