self.add_case(Program(lst, bigendian),
initial_regs, initial_sprs, initial_msr=msr)
+ def case_4_mfspr_slow(self):
+ lst = ["mfspr 1, 272", # SPRG0
+ "mfspr 4, 273", ] # SPRG1
+ initial_regs = [0] * 32
+ initial_sprs = {'SPRG0_priv': 0x12345678, 'SPRG1_priv': 0x5678,
+ }
+ self.add_case(Program(lst, bigendian),
+ initial_regs, initial_sprs)
+
+ def case_5_mtspr(self):
+ lst = ["mtspr 272, 1", # SPRG0
+ "mtspr 273, 2", # SPRG1
+ ]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x129518230011feed
+ initial_regs[2] = 0x123518230011fee0
+ initial_sprs = {'SPRG0_priv': 0x12345678, 'SPRG1_priv': 0x5678,
+ }
+ self.add_case(Program(lst, bigendian),
+ initial_regs, initial_sprs)
+
def case_ilang(self):
pspec = SPRPipeSpec(id_wid=2)
alu = SPRBasePipe(pspec)
import functools
import types
from soc.decoder.power_enums import XER_bits, CryIn, spr_dict
-from soc.regfile.util import fast_reg_to_spr # HACK!
+from soc.regfile.util import fast_reg_to_spr, slow_reg_to_spr # HACK!
from soc.regfile.regfiles import XERRegs, FastRegs
spr1_en = yield dec2.e.read_spr1.ok
if spr1_en:
spr1_sel = yield dec2.e.read_spr1.data
+ spr1_sel = slow_reg_to_spr(spr1_sel)
spr1_data = sim.spr[spr1_sel].value
res['spr1'] = spr1_data
ok = yield dec2.e.write_spr.ok
if ok:
spr_num = yield dec2.e.write_spr.data
+ spr_num = slow_reg_to_spr(spr_num)
spr_name = spr_dict[spr_num].SPR
res['spr1'] = sim.spr[spr_name].value
if not isinstance(spr_num, str):
spr_num = spr_dict[spr_num].SPR
return sprstr_to_fast[spr_num]
+
+
+def slow_reg_to_spr(slow_reg):
+ for i, x in enumerate(SPR):
+ if slow_reg == i:
+ return x.value
+
+
+def spr_to_slow_reg(spr_num):
+ for i, x in enumerate(SPR):
+ if spr_num == x.value:
+ return i