remove reading port 3 for CR pipeline. RS moved to port 1

diff --git a/src/soc/fu/compunits/test/test_cr_compunit.py b/src/soc/fu/compunits/test/test_cr_compunit.py
index b1b6332d36df21791d062ad57e84694bad9493f0..cf8572e9be6600f58561bc8568e3a1dac89d493b 100644 (file)
--- a/src/soc/fu/compunits/test/test_cr_compunit.py
+++ b/src/soc/fu/compunits/test/test_cr_compunit.py
@@ -43,13 +43,9 @@ class CRTestRunner(TestRunner):
 
         # RA/RC
         reg1_ok = yield dec2.e.read_reg1.ok
-        reg3_ok = yield dec2.e.read_reg3.ok
         if reg1_ok:
             data1 = yield dec2.e.read_reg1.data
             res['a'] = sim.gpr(data1).value
-        if reg3_ok:
-            data1 = yield dec2.e.read_reg3.data
-            res['a'] = sim.gpr(data1).value
 
         # RB (or immediate)
         reg2_ok = yield dec2.e.read_reg2.ok

diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py
index e0d529b23558723005fb0d50e40ca553bae63b01..ffe6bad558040d923985017c136038f48ae0f61b 100644 (file)
--- a/src/soc/fu/cr/test/test_pipe_caller.py
+++ b/src/soc/fu/cr/test/test_pipe_caller.py
@@ -169,12 +169,6 @@ class TestRunner(FHDLTestCase):
                 cr3 = simulator.crl[cr3_sel].get_range().value
                 yield alu.p.data_i.cr_c.eq(cr3)
 
-        reg3_ok = yield dec2.e.read_reg3.ok
-        if reg3_ok:
-            reg3_sel = yield dec2.e.read_reg3.data
-            reg3 = simulator.gpr(reg3_sel).value
-            yield alu.p.data_i.a.eq(reg3)
-
         reg1_ok = yield dec2.e.read_reg1.ok
         if reg1_ok:
             reg1_sel = yield dec2.e.read_reg1.data