must always set ok for writing out data otherwise it never hits regfile

(and causes compunit to fail)

diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index c2e82f4a694c02eaa9fd8991f32aa37cd7aa06e4..0b3b728e5104be0a038782b457ab9336aafbea1b 100644 (file)
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -257,7 +257,7 @@ class FSMMMUStage(ControlBase):
                             comb += o.data.eq(dsisr)
                         with m.Else():
                             comb += o.data.eq(dar)
-                        #FIXME comb += o.ok.eq(1)
+                        comb += o.ok.eq(1)
                         comb += done.eq(1)
                     # pass it over to the MMU instead
                     with m.Else():