link litex ls180soc JTAG pads

diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index 660760e6fde5e803fa96da2678f7d7af622f599c..4f4b3d24a6c7588448b28b4a2e88a468061e945c 100755 (executable)
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -115,7 +115,6 @@ class LibreSoCSim(SoCCore):
         if False: # not self.integrated_main_ram_size:
             self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
 
-
         if cpu == "libresoc":
             # XICS interrupt devices
             icp_addr = self.mem_map['icp']
@@ -192,6 +191,13 @@ class LibreSoCSim(SoCCore):
         # EINTs - very simple, wire up top 3 bits to ls180 "eint" pins
         self.comb += self.cpu.interrupt[12:16].eq(platform.request("eint"))
 
+        # JTAG
+        jtagpads = platform.request("jtag")
+        self.comb += self.cpu.jtag_tck.eq(jtagpads.tck)
+        self.comb += self.cpu.jtag_tms.eq(jtagpads.tms)
+        self.comb += self.cpu.jtag_tdi.eq(jtagpads.tdi)
+        self.comb += jtagpads.tdo.eq(self.cpu.jtag_tdo)
+
         # Debug ---------------------------------------------------------------
         if not debug:
             return