"""
def __init__(self, name,
- name_ = None,
+ name_=None,
idx=None,
ready=True,
enabled=True,
def ifacedef2(self, fmtoutfn, fmtinfn, fmtdecfn):
if self.action:
fmtname = fmtinfn(self.name)
- res = " interface %s = interface Put\n" % self.name_
+ res = " interface %s = interface Put\n" % self.name_
res += ' method '
res += "Action put"
#res += fmtdecfn(self.name)
res += ' endinterface;'
else:
fmtname = fmtoutfn(self.name)
- res = " interface %s = interface Get\n" % self.name_
+ res = " interface %s = interface Get\n" % self.name_
res += ' method ActionValue#'
res += '(%s) get;\n' % self.bitspec
res += " return %s;\n" % (fmtname)
name = 'tget'
return (name, res)
+
class Interface(PeripheralIface):
""" create an interface from a list of pinspecs.
each pinspec is a dictionary, see Pin class arguments
# NOTice - outen key is removed
else:
name = p['name']
- if name.isdigit(): # HACK! deals with EINT case
+ if name.isdigit(): # HACK! deals with EINT case
name = self.pname(name)
_p['name_'] = name
_p['idx'] = idx
decfn = self.ifacefmtdecfn3
outfn = self.ifacefmtoutenfn
return pin.ifacedef2(outfn, self.ifacefmtinfn,
- decfn)
+ decfn)
def ifacedef(self, *args):
res = '\n'.join(map(self.ifacefmtpin, self.pins))
def wirefmt(self, *args):
return generic_io.format(*args)
+
class InterfaceGPIO(Interface):
def ifacepfmt(self, *args):
decfn = self.ifacefmtdecfn3
outfn = self.ifacefmtoutenfn
return pin.ifacedef3(outfn, self.ifacefmtinfn,
- decfn)
+ decfn)
class Interfaces(InterfacesBase, PeripheralInterfaces):
def __init__(self, pth=None):
InterfacesBase.__init__(self, Interface, pth,
- {'gpio': InterfaceGPIO })
+ {'gpio': InterfaceGPIO})
PeripheralInterfaces.__init__(self)
def ifacedef(self, f, *args):
import types
+
class PBase(object):
def __init__(self, name):
self.name = name
ps_ = ps + '_out'
else:
ps_ = ps
- ret.append(" mkConnection({0},\n\t\t\t{1}.{2});" \
- .format(ps_, n_, fname))
+ ret.append(" mkConnection({0},\n\t\t\t{1}.{2});"
+ .format(ps_, n_, fname))
fname = None
if p.get('outen'):
fname = self.pinname_outen(pname)
if isinstance(fname, str):
fname = "{0}.{1}".format(n_, fname)
fname = self.pinname_tweak(pname, 'outen', fname)
- ret.append(" mkConnection({0}_outen,\n\t\t\t{1});"\
- .format(ps, fname))
+ ret.append(" mkConnection({0}_outen,\n\t\t\t{1});"
+ .format(ps, fname))
if typ == 'in' or typ == 'inout':
fname = self.pinname_in(pname)
if fname:
print "plic_obj", name, idx, plic_obj
plic = mkplic_rule.format(name, plic_obj, irq_offs)
res.append(plic)
- irq_offs += 1 # increment to next irq
+ irq_offs += 1 # increment to next irq
return ('\n'.join(res), irq_offs)
def mk_ext_ifacedef(self, iname, inum):
if slow:
self.slow = slow(ifacename)
self.slow.peripheral = self
- for fname in ['slowimport',
+ for fname in ['slowimport',
'slowifinstance', 'slowifdecl', 'slowifdeclmux',
'mkslow_peripheral', 'mk_plic', 'mk_ext_ifacedef',
'mk_connection', 'mk_cellconn', 'mk_pincon']:
ret.append(txt)
return '\n'.join(list(filter(None, ret)))
-
def mk_plic(self):
ret = []
- irq_offs = 8 # XXX: DMA scovers 0-7?
+ irq_offs = 8 # XXX: DMA scovers 0-7?
for (name, count) in self.ifacecount:
for i in range(count):
res = self.data[name].mk_plic(i, irq_offs)
return v
return None
+
slowfactory = PFactory()
if __name__ == '__main__':
from bsv.peripheral_gen.base import PBase
+
class eint(PBase):
def slowimport(self):
from bsv.peripheral_gen.base import PBase
+
class gpio(PBase):
def slowimport(self):
from bsv.peripheral_gen.base import PBase
+
class jtag(PBase):
def axi_slave_name(self, name, ifacenum):
" method Action jtag_ck (Bit#(1) in);"
def slowifinstance(self):
- return jtag_method_template # bit of a lazy hack this...
+ return jtag_method_template # bit of a lazy hack this...
+
jtag_method_template = """\
method Action jtag_ms (Bit#(1) in);
from bsv.peripheral_gen.base import PBase
+
class pwm(PBase):
def slowimport(self):
from bsv.peripheral_gen.base import PBase
+
class qspi(PBase):
def slowimport(self):
from bsv.peripheral_gen.base import PBase
+
class quart(PBase):
def slowimport(self):
return "quart{0}.slave_axi_uart"
def pinname_out(self, pname):
- return {'tx' : 'coe_rs232.stx_out',
+ return {'tx': 'coe_rs232.stx_out',
'rts': 'coe_rs232.rts_out',
- }.get(pname, '')
+ }.get(pname, '')
def pinname_in(self, pname):
- return {'rx': 'coe_rs232.srx_in',
+ return {'rx': 'coe_rs232.srx_in',
'cts': 'coe_rs232.cts_in'
- }.get(pname, '')
+ }.get(pname, '')
def __disabled_mk_pincon(self, name, count):
ret = [PBase.mk_pincon(self, name, count)]
def slowifdeclmux(self):
return " method Bit#(1) {1}{0}_intr;"
+
uart_plic_template = """\
// PLIC {0} synchronisation with irq {1}
SyncBitIfc#(Bit#(1)) {0}_interrupt <-
{0}_interrupt.send({0}.irq);
endrule
"""
-
from bsv.peripheral_gen.base import PBase
+
class rgbttl(PBase):
def slowimport(self):
return 10
def mkslow_peripheral(self):
- sz = len(self.peripheral.pinspecs) - 4 # subtract CK, DE, HS, VS
+ sz = len(self.peripheral.pinspecs) - 4 # subtract CK, DE, HS, VS
return " Ifc_rgbttl_dummy lcd{0} <- mkrgbttl_dummy();"
def _mk_connection(self, name=None, count=0):
from bsv.peripheral_gen.base import PBase
+
class rs232(PBase):
def slowimport(self):
from bsv.peripheral_gen.base import PBase
+
class sdmmc(PBase):
def slowimport(self):
from bsv.peripheral_gen.base import PBase
+
class spi(PBase):
def slowimport(self):
def slowifdeclmux(self):
return " method Bit#(1) {1}{0}_isint;"
-
-
from bsv.peripheral_gen.base import PBase
+
class twi(PBase):
def slowimport(self):
return ["{0}.isint()",
"{0}.timerint()",
"{0}.isber()"
- ][idx].format(pname)
+ ][idx].format(pname)
def mk_ext_ifacedef(self, iname, inum):
name = self.get_iname(inum)
def slowifdeclmux(self):
return " method Bit#(1) {1}{0}_isint;"
-
-
from bsv.peripheral_gen.base import PBase
+
class uart(PBase):
def slowimport(self):
shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
os.path.join(bp, 'Makefile'))
cwd = os.path.join(cwd, 'bsv_lib')
- for fname in [ ]:
+ for fname in []:
shutil.copyfile(os.path.join(cwd, fname),
os.path.join(bl, fname))
ifacedef = ifaces.mk_ext_ifacedef()
with open(slow, "w") as bsv_file:
bsv_file.write(slowt.format(imports, ifdecl, regdef, slavedecl,
- fnaddrmap, mkslow, mkcon, mkcellcon,
- pincon, inst, mkplic,
- numsloirqs, ifacedef))
+ fnaddrmap, mkslow, mkcon, mkcellcon,
+ pincon, inst, mkplic,
+ numsloirqs, ifacedef))
def write_bus(bus, p, ifaces):
projects / pinmux.git / commitdiff