crank A7 FPGA speed down to experiment

diff --git a/src/arty_a7.py b/src/arty_a7.py
index 55ef6ed9bac412705f8f9aadd40dbfe94f4cdd81..4091072599c0deca86aa8e9281b2d6040a1225e1 100644 (file)
--- a/src/arty_a7.py
+++ b/src/arty_a7.py
@@ -9,7 +9,7 @@ from arty_crg import ArtyA7CRG
 class BlinkyClocked(Elaboratable):
     def elaborate(self, platform):
         m = Module()
-        m.submodules.crg = ArtyA7CRG(25e6)
+        m.submodules.crg = ArtyA7CRG(12e6)
         m.submodules.blinky = Blinky()
         return m
 

diff --git a/src/ls2.py b/src/ls2.py
index 5e0997d6eb2cc8fb116751f2cf88c3e1ff9b02b0..855ddd3dd2dfbfe381d2ad3c7ae6e3e4552077b4 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -589,7 +589,7 @@ if __name__ == "__main__":
     if fpga == 'versa_ecp5_85':
         clk_freq = 55e6
     if fpga == 'arty_a7':
-        clk_freq = 25e6
+        clk_freq = 12e6
 
     # select a firmware file
     firmware = None