add extra port for debug read of int regs via DMI

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index 7bcf5c9ca4bf1185bc533cc1ab99b572b6d1c280..4fe98d3a3b14e8519f5e8a70add459ed9fc3a882 100644 (file)
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -42,7 +42,8 @@ class IntRegs(RegFileArray):
                         'o1': self.write_port("dest2")} # for now (LD/ST update)
         self.r_ports = {'ra': self.read_port("src1"),
                         'rb': self.read_port("src2"),
-                        'rc': self.read_port("src3")}
+                        'rc': self.read_port("src3"),
+                        'dmi': self.read_port("dmi")} # needed for Debug (DMI)
 
 
 # Fast SPRs Regfile