corrections to trap main_stage.py OP_RFID according to reading spec

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 325fb373546673df3ec19a15554e775bcc6fe9a9..e5ea4cd23498dd98fa0c82109e990d2a4f89c128 100644 (file)
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -201,9 +201,9 @@ class TrapMainStage(PipeModBase):
                 msr_check_pr(m, msr_o.data)
 
                 # hypervisor stuff
-                comb += msr_o.data[MSR.HV].eq(msr_i[MSR.HV] & srr1_i[MSR.HV])
-                comb += msr_o.data[MSR.ME].eq((msr_i[MSR.HV] & srr1_i[MSR.HV]) |
-                                             (~msr_i[MSR.HV] & srr1_i[MSR.HV]))
+                with m.If(msr_i[MSR.HV]):
+                    comb += msr_o.data[MSR.HV].eq(srr1_i[MSR.HV])
+                    comb += msr_o.data[MSR.ME].eq(srr1_i[MSR.ME])
                 # don't understand but it's in the spec
                 with m.If((msr_i[63-31:63-29] != Const(0b010, 3)) |
                           (srr1_i[63-31:63-29] != Const(0b000, 3))):