j = i + 1 # name numbering to match dest1/2...
name = "dest%d_o" % j
rw = self._get_dstwid(i)
+ #dreg = Data(rw, name=name) XXX ??? output needs to be a Data type?
dreg = Signal(rw, name=name, reset_less=True)
setattr(self, name, dreg)
dst.append(dreg)
from soc.experiment.compalu_multi import go_record, CompUnitRecord
from soc.experiment.l0_cache import PortInterface
from soc.experiment.testmem import TestMemory
+from soc.fu.regspec import RegSpecAPI
from soc.decoder.power_enums import InternalOp, Function
from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
+from soc.decoder.power_decoder2 import Data
class LDSTCompUnitRecord(CompUnitRecord):
self.stwd_mem_o = Signal(reset_less=True) # activate memory STORE
-class LDSTCompUnit(Elaboratable):
+class LDSTCompUnit(RegSpecAPI, Elaboratable):
"""LOAD / STORE Computation Unit
Inputs
def __init__(self, pi=None, rwid=64, awid=48, opsubset=CompLDSTOpSubset,
debugtest=False):
- self.rwid = rwid
+ super().__init__(rwid)
self.awid = awid
self.pi = pi
self.cu = cu = LDSTCompUnitRecord(rwid, opsubset)
# convenience names
self.rd = cu.rd
self.wr = cu.wr
+ self.rdmaskn = cu.rdmaskn
+ self.wrmask = cu.wrmask
self.ad = cu.ad
self.st = cu.st
+ self.dest = cu._dest
+
+ # HACK: get data width from dest[0]. this is used across the board
+ # (it really shouldn't be)
+ self.data_wid = self.dest[0].shape()
self.go_rd_i = self.rd.go # temporary naming
self.go_wr_i = self.wr.go # temporary naming
self.oper_i = cu.oper_i
self.src_i = cu._src_i
- self.dest = cu._dest
- self.data_o = self.dest[0] # Dest1 out: RT
- self.addr_o = self.dest[1] # Address out (LD or ST) - Update => RA
+ self.data_o = Data(self.data_wid, name="o") # Dest1 out: RT
+ self.addr_o = Data(self.data_wid, name="ea") # Addr out: Update => RA
self.addr_exc_o = cu.addr_exc_o
self.done_o = cu.done_o
self.busy_o = cu.busy_o
self.load_mem_o = cu.load_mem_o
self.stwd_mem_o = cu.stwd_mem_o
- # HACK: get data width from dest[0]. this is used across the board
- # (it really shouldn't be)
- self.data_wid = self.dest[0].shape()
-
def elaborate(self, platform):
m = Module()
comb += self.busy_o.eq(opc_l.q) # | self.pi.busy_o) # busy out
# 1st operand read-request only when zero not active
- comb += self.rd.rel[0].eq(src_l.q[0] & busy_o & ~op_is_z)
-
# 2nd operand only needed when immediate is not active
- comb += self.rd.rel[1].eq(src_l.q[1] & busy_o & ~op_is_imm)
+ slg = Cat(op_is_z, op_is_imm)
+ bro = Repl(self.busy_o, self.n_src)
+ comb += self.rd.rel.eq(src_l.q & bro & ~slg & ~self.rdmaskn)
# note when the address-related read "go" signals are active
comb += rda_any.eq(self.rd.go[0] | self.rd.go[1])
# Data/Address outputs
# put the LD-output register directly onto the output bus on a go_write
+ comb += self.data_o.data.eq(self.dest[0])
with m.If(self.wr.go[0]):
- comb += self.data_o.eq(ldd_r)
+ comb += self.dest[0].eq(ldd_r)
# "update" mode, put address out on 2nd go-write
+ comb += self.addr_o.data.eq(self.dest[1])
with m.If(op_is_update & self.wr.go[1]):
- comb += self.addr_o.eq(addr_r)
+ comb += self.dest[1].eq(addr_r)
+
+ # need to look like MultiCompUnit: put wrmask out
+ comb += self.wrmask.eq(self.wr.rel)
###########################
# PortInterface connections
return m
+ def get_out(self, i):
+ """make LDSTCompUnit look like RegSpecALUAPI"""
+ if i == 0:
+ return self.data_o
+ if i == 1:
+ return self.addr_o
+ #return self.dest[i]
+
def __iter__(self):
yield self.rd.go
yield self.go_ad_i
from soc.fu.shift_rot.pipeline import ShiftRotBasePipe
from soc.fu.shift_rot.pipe_data import ShiftRotPipeSpec
+from soc.fu.ldst.pipe_data import LDSTPipeSpec
+from soc.experiment.compldst_multi import LDSTCompUnit # special-case
+
###################################################################
###### FunctionUnitBaseSingle - use to make single-stge pipes #####
import unittest
from soc.decoder.power_decoder import (create_pdecode)
from soc.decoder.power_decoder2 import (PowerDecode2)
+from soc.decoder.power_enums import Function
from soc.decoder.isa.all import ISA
from soc.experiment.compalu_multi import find_ok # hack
pdecode = create_pdecode()
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- m.submodules.cu = cu = self.fukls()
+ if self.funit == Function.LDST:
+ from soc.experiment.l0_cache import TstL0CacheBuffer
+ m.submodules.l0 = l0 = TstL0CacheBuffer(n_units=1, regwid=64)
+ pi = l0.l0.dports[0].pi
+ m.submodules.cu = cu = self.fukls(pi, awid=4)
+ m.d.comb += cu.ad.go.eq(cu.ad.rel) # link addr-go direct to rel
+ else:
+ m.submodules.cu = cu = self.fukls()
comb += pdecode2.dec.raw_opcode_in.eq(instruction)
sim = Simulator(m)
regspec = [('INT', 'ra', '0:63'), # RA
('INT', 'rb', '0:63'), # RB/immediate
('INT', 'rc', '0:63'), # RC
- ('XER', 'xer_so', '32') # XER bit 32: SO
+ # XXX TODO, later ('XER', 'xer_so', '32') # XER bit 32: SO
]
def __init__(self, pspec):
super().__init__(pspec, False)
class LDSTOutputData(IntegerData):
regspec = [('INT', 'o', '0:63'), # RT
('INT', 'o1', '0:63'), # RA (effective address, update mode)
- ('CR', 'cr_a', '0:3'),
- ('XER', 'xer_so', '32')]
+ # TODO, later ('CR', 'cr_a', '0:3'),
+ # TODO, later ('XER', 'xer_so', '32')
+ ]
def __init__(self, pspec):
super().__init__(pspec, True)
# convenience
lst = ["stw 2, 0(1)",
"lwz 3, 0(1)"]
initial_regs = [0] * 32
- initial_regs[1] = 0x0010
- initial_regs[2] = 0x1234
+ initial_regs[1] = 0x0004
+ initial_regs[2] = 0x0008
self.run_tst_program(Program(lst), initial_regs)
def test_ilang(self):
return get_regspec_bitwidth(self._rwid, 0, i)
-class RegSpecALUAPI:
- def __init__(self, rwid, alu):
+class RegSpecAPI:
+ def __init__(self, rwid):
"""RegSpecAPI
* :rwid: regspec
- * :alu: ALU covered by this regspec
"""
self.rwid = rwid
- self.alu = alu # actual ALU - set as a "submodule" of the CU
def get_in_spec(self, i):
return self.rwid[0][i]
def get_out_name(self, i):
return self.get_out_spec(i)[1]
+
+class RegSpecALUAPI(RegSpecAPI):
+ def __init__(self, rwid, alu):
+ """RegSpecAPI
+
+ * :rwid: regspec
+ * :alu: ALU covered by this regspec
+ """
+ super().__init__(rwid)
+ self.alu = alu
+
def get_out(self, i):
if isinstance(self.rwid, int): # old - testing - API (rwid is int)
return self.alu.out[i]
projects / soc.git / commitdiff