Add test for addpcis

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index bcc9a551eaca3ec89e41a76dd14cf2c73d31963e..0e9c113185e53b053b1b6976948b26370e998d1f 100644 (file)
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -79,6 +79,16 @@ class DecoderTestCase(FHDLTestCase):
             print(sim.gpr(1))
             self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64))
 
+    def test_addpcis(self):
+        lst = ["addpcis 1, 0x1",
+               "addpcis 2, 0x1",
+               "addpcis 3, 0x1"]
+        with Program(lst) as program:
+            sim = self.run_test_program(program)
+            self.assertEqual(sim.gpr(1), SelectableInt(0x10004, 64))
+            self.assertEqual(sim.gpr(2), SelectableInt(0x10008, 64))
+            self.assertEqual(sim.gpr(3), SelectableInt(0x1000c, 64))
+
     def run_test_program(self, prog, initial_regs=[0] * 32):
         simulator = self.run_tst(prog, initial_regs)
         simulator.gpr.dump()

diff --git a/src/soc/simulator/program.py b/src/soc/simulator/program.py
index b3c1e87fc2fa2bc62ffa645dbc0710a021160fba..9857f037146ab2ab2d5fe7aec9f81f24c123ddb0 100644 (file)
--- a/src/soc/simulator/program.py
+++ b/src/soc/simulator/program.py
@@ -45,6 +45,7 @@ class Program:
     def _assemble(self):
         with tempfile.NamedTemporaryFile(suffix=".o") as outfile:
             args = ["powerpc64-linux-gnu-as",
+                    '-mpower9',
                     obj_fmt,
                     "-o",
                     outfile.name]