fu/mmu/fsm.py: mfspr!=mtspr

diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index 690a1c041f988255dcb9b99da1041b06617d60ef..5cce2dde63f0f8bd4d424cf8d294d44b4d8e6d89 100644 (file)
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -185,7 +185,7 @@ class FSMMMUStage(ControlBase):
                         # blip the MMU and wait for it to complete
                         comb += valid.eq(1)   # start "pulse"
                         comb += l_in.valid.eq(blip)   # start
-                        comb += l_in.mtspr.eq(1)   # mtspr mode
+                        comb += l_in.mtspr.eq(0)   # mfspr!=mtspr
                         comb += l_in.sprn.eq(spr)  # which SPR
                         comb += l_in.rs.eq(a_i)    # incoming operand (RS)
                         comb += o.data.eq(l_out.sprval) # SPR from MMU