whitespace cleanup

diff --git a/src/soc/fu/cr/main_stage.py b/src/soc/fu/cr/main_stage.py
index 98d10cfab0f7ae3b03254d7fa1eb2da50fc844bb..7240ebe51bb005868564c9fa93a33c1026be42cf 100644 (file)
--- a/src/soc/fu/cr/main_stage.py
+++ b/src/soc/fu/cr/main_stage.py
@@ -86,7 +86,7 @@ class CRMainStage(PipeModBase):
                 ba = Signal(2, reset_less=True)
                 bb = Signal(2, reset_less=True)
 
-                # Stupid bit ordering stuff
+                # Stupid bit ordering stuff.  Because POWER.
                 comb += bt.eq(3-BT[0:2])
                 comb += ba.eq(3-BA[0:2])
                 comb += bb.eq(3-BB[0:2])