Reduce BMC depth on proof_main_stage.py

diff --git a/src/soc/alu/formal/proof_main_stage.py b/src/soc/alu/formal/proof_main_stage.py
index df73815b745f246cdc7ebec0cf4be537580b296c..3ce8f19a27abc3ce182a5e703ee4a09e86b2b4c4 100644 (file)
--- a/src/soc/alu/formal/proof_main_stage.py
+++ b/src/soc/alu/formal/proof_main_stage.py
@@ -100,8 +100,8 @@ class Driver(Elaboratable):
 class ALUTestCase(FHDLTestCase):
     def test_formal(self):
         module = Driver()
-        self.assertFormal(module, mode="bmc", depth=4)
-        self.assertFormal(module, mode="cover", depth=4)
+        self.assertFormal(module, mode="bmc", depth=2)
+        self.assertFormal(module, mode="cover", depth=2)
     def test_ilang(self):
         dut = Driver()
         vl = rtlil.convert(dut, ports=[])