<bitfield name="CLAMP_Y" low="13" high="15" type="sq_tex_clamp"/>"
<bitfield name="CLAMP_Z" low="16" high="18" type="sq_tex_clamp"/>"
<bitfield name="PITCH" low="22" high="30" shr="5" type="uint"/>
- <bitfield name="TILED" pos="1" type="boolean"/>
+ <bitfield name="TILED" pos="31" type="boolean"/>
</reg32>
<reg32 offset="1" name="1">
<bitfield name="FORMAT" low="0" high="5" type="a2xx_sq_surfaceformat"/>
OUT_RING(ring, slice->pitch >> 5); /* RB_COPY_DEST_PITCH */
OUT_RING(ring, /* RB_COPY_DEST_INFO */
A2XX_RB_COPY_DEST_INFO_FORMAT(fd2_pipe2color(psurf->format)) |
- A2XX_RB_COPY_DEST_INFO_LINEAR |
+ COND(!rsc->tile_mode, A2XX_RB_COPY_DEST_INFO_LINEAR) |
A2XX_RB_COPY_DEST_INFO_SWAP(swap) |
A2XX_RB_COPY_DEST_INFO_WRITE_RED |
A2XX_RB_COPY_DEST_INFO_WRITE_GREEN |
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
- OUT_RELOCW(ring, rsc->bo, offset, A2XX_RB_COLOR_INFO_LINEAR |
+ OUT_RELOCW(ring, rsc->bo, offset,
+ COND(!rsc->tile_mode, A2XX_RB_COLOR_INFO_LINEAR) |
A2XX_RB_COLOR_INFO_SWAP(fmt2swap(psurf->format)) |
A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(psurf->format)), 0);
}
return size;
}
+
+unsigned
+fd2_tile_mode(const struct pipe_resource *tmpl)
+{
+ /* disable tiling for cube maps, freedreno uses a 2D array for the staging texture,
+ * (a2xx supports 2D arrays but it is not implemented)
+ */
+ if (tmpl->target == PIPE_TEXTURE_CUBE)
+ return 0;
+ /* we can enable tiling for any resource we can render to */
+ return (tmpl->bind & PIPE_BIND_RENDER_TARGET) ? 1 : 0;
+}
#include "freedreno_resource.h"
uint32_t fd2_setup_slices(struct fd_resource *rsc);
+unsigned fd2_tile_mode(const struct pipe_resource *tmpl);
#endif /* FD2_RESOURCE_H_ */
screen->max_rts = 1;
pscreen->context_create = fd2_context_create;
pscreen->is_format_supported = fd2_screen_is_format_supported;
+
screen->setup_slices = fd2_setup_slices;
+ if (fd_mesa_debug & FD_DBG_TTILE)
+ screen->tile_mode = fd2_tile_mode;
if (fd_mesa_debug & FD_DBG_PERFC) {
screen->perfcntr_groups = a2xx_perfcntr_groups;
so->base.reference.count = 1;
so->base.context = pctx;
- so->tex0 = A2XX_SQ_TEX_0_PITCH(rsc->slices[0].pitch);
+ so->tex0 =
+ A2XX_SQ_TEX_0_PITCH(rsc->slices[0].pitch) |
+ COND(rsc->tile_mode, A2XX_SQ_TEX_0_TILED);
so->tex1 =
A2XX_SQ_TEX_1_FORMAT(fd2_pipe2surface(cso->format)) |
A2XX_SQ_TEX_1_CLAMP_POLICY(SQ_TEX_CLAMP_POLICY_OGL);
{"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
{"noblit", FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"},
{"hiprio", FD_DBG_HIPRIO, "Force high-priority context"},
- {"ttile", FD_DBG_TTILE, "Enable texture tiling (a5xx)"},
+ {"ttile", FD_DBG_TTILE, "Enable texture tiling (a2xx/a5xx)"},
{"perfcntrs", FD_DBG_PERFC, "Expose performance counters"},
{"noubwc", FD_DBG_NOUBWC, "Disable UBWC for all internal buffers"},
DEBUG_NAMED_VALUE_END