add blockram style to regfile Memory

diff --git a/src/soc/regfile/regfile.py b/src/soc/regfile/regfile.py
index e1274b4b1ad970bd3772345b99b3c54aa46a40aa..07cee2dd6773eb0644da0f9b5216d4f0a1dde7f6 100644 (file)
--- a/src/soc/regfile/regfile.py
+++ b/src/soc/regfile/regfile.py
@@ -199,7 +199,8 @@ class RegFileMem(Elaboratable):
         self.fwd_bus_mode = fwd_bus_mode
         self.synced = synced
         self.width, self.depth = width, depth
-        self.memory = Memory(width=width, depth=depth)
+        self.memory = Memory(width=width, depth=depth,
+                             attrs={'syn_ramstyle': "block_ram"})
         self._rdports = {}
         self._wrports = {}