radv: rework how the number of VGPRs is computed

Just a cleanup, it shouldn't change anything.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index ead4e379a8240d8c3999cbdb9576a42bae3fa534..1346299b75237f68e1ff46c524ae876fbe9a07fe 100644 (file)
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -2191,14 +2191,6 @@ handle_vs_input_decl(struct radv_shader_context *ctx,
                                        buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
                                                                     LLVMConstInt(ctx->ac.i32, divisor, 0), "");
                                }
-
-                               if (ctx->options->key.vs.as_ls) {
-                                       ctx->shader_info->vs.vgpr_comp_cnt =
-                                               MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
-                               } else {
-                                       ctx->shader_info->vs.vgpr_comp_cnt =
-                                               MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
-                               }
                        } else {
                                buffer_index = ctx->ac.i32_0;
                        }
@@ -3047,8 +3039,6 @@ handle_vs_outputs_post(struct radv_shader_context *ctx,
                LLVMValueRef values[4];
 
                values[0] = ctx->vs_prim_id;
-               ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
-                                                         ctx->shader_info->vs.vgpr_comp_cnt);
                for (unsigned j = 1; j < 4; j++)
                        values[j] = ctx->ac.f32_0;
 
@@ -3756,15 +3746,6 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
                        ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
                        ctx.tcs_num_patches = ctx.options->key.tes.num_patches;
                } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
-                       if (shader_info->info.vs.needs_instance_id) {
-                               if (ctx.options->key.vs.as_ls) {
-                                       ctx.shader_info->vs.vgpr_comp_cnt =
-                                               MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
-                               } else {
-                                       ctx.shader_info->vs.vgpr_comp_cnt =
-                                               MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
-                               }
-                       }
                        ctx.abi.load_base_vertex = radv_load_base_vertex;
                } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
                        shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
@@ -3999,9 +3980,6 @@ ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_sha
         case MESA_SHADER_VERTEX:
                 shader_info->vs.as_es = options->key.vs.as_es;
                 shader_info->vs.as_ls = options->key.vs.as_ls;
-                /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
-                if (options->key.vs.as_ls)
-                        shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
                 break;
         default:
                 break;

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 5205dc1bfc53b46d6492e286bffa175ddf3f97be..0ec0d67e3b6477ed85c4d845be6dadcdb542962d 100644 (file)
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -507,13 +507,40 @@ radv_fill_shader_variant(struct radv_device *device,
                break;
        case MESA_SHADER_TESS_CTRL:
                if (device->physical_device->rad_info.chip_class >= GFX9) {
-                       vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
+                       /* We need at least 2 components for LS.
+                        * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
+                        * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
+                        */
+                       vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
                } else {
                        variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
                }
                break;
        case MESA_SHADER_VERTEX:
-               vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
+               if (variant->info.vs.as_ls) {
+                       assert(device->physical_device->rad_info.chip_class <= GFX8);
+                       /* We need at least 2 components for LS.
+                        * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
+                        * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
+                        */
+                       vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
+               } else if (variant->info.vs.as_es) {
+                       assert(device->physical_device->rad_info.chip_class <= GFX8);
+                       /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
+                       vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0;
+               } else {
+                       /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
+                        * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
+                        * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
+                        */
+                       if (options->key.vs.export_prim_id) {
+                               vgpr_comp_cnt = 2;
+                       } else if (info->vs.needs_instance_id) {
+                               vgpr_comp_cnt = 1;
+                       } else {
+                               vgpr_comp_cnt = 0;
+                       }
+               }
                break;
        case MESA_SHADER_FRAGMENT:
        case MESA_SHADER_GEOMETRY:
@@ -539,7 +566,8 @@ radv_fill_shader_variant(struct radv_device *device,
                unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
 
                if (es_type == MESA_SHADER_VERTEX) {
-                       es_vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
+                       /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
+                       es_vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0;
                } else if (es_type == MESA_SHADER_TESS_EVAL) {
                        es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
                } else {

diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 17779cd0c4230693d99805425fc9b2868765e1cf..d3d8a2dd37bae46d15443033c32b14e5e4e14696 100644 (file)
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -266,7 +266,6 @@ struct radv_shader_variant_info {
                struct {
                        struct radv_vs_output_info outinfo;
                        struct radv_es_output_info es_info;
-                       unsigned vgpr_comp_cnt;
                        bool as_es;
                        bool as_ls;
                } vs;