whoops context-indentation by mistake (no harm done, just odd)

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 4a98c5faff13d7ef355315153fba09d0a9aa6fb1..d8815c72601ee9c835aa12852c85cbf1fa557145 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -614,8 +614,8 @@ class NonProductionCore(ControlBase):
                         comb += wvaddr_en.eq(write)
                     else:
                         comb += wvaddr_en.eq(1<<write)
-                    wvseten.append(wvaddr_en)
-                    wvsets.append(wvaddr_en)
+                wvseten.append(wvaddr_en)
+                wvsets.append(wvaddr_en)
 
         # here is where we create the Write Broadcast Bus. simple, eh?
         comb += wport.i_data.eq(ortreereduce_sig(wsigs))