add way to capture CR from DMI in litex sim

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index f0852aebc3abbcd502aba4e2194cadaf2c694c6c..994678eea71d27d74a1854f97f7c30349e308674 100644 (file)
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -55,7 +55,7 @@ class LibreSoC(CPU):
         self.periph_buses = [ibus, dbus]
         self.memory_buses = []
 
-        self.dmi_addr = Signal(3)
+        self.dmi_addr = Signal(4)
         self.dmi_din = Signal(64)
         self.dmi_dout = Signal(64)
         self.dmi_wr = Signal(1)

diff --git a/src/soc/litex/florent/microwatt/core.py b/src/soc/litex/florent/microwatt/core.py
index 344c7c6fe4708c9d033a8f38d0cad78e405be786..1dbeb346416e2083db3999d13480ab16b7d2e427 100644 (file)
--- a/src/soc/litex/florent/microwatt/core.py
+++ b/src/soc/litex/florent/microwatt/core.py
@@ -53,7 +53,7 @@ class Microwatt(CPU):
         self.periph_buses = [ibus, dbus]
         self.memory_buses = []
 
-        self.dmi_addr = Signal(3)
+        self.dmi_addr = Signal(4)
         self.dmi_din = Signal(64)
         self.dmi_dout = Signal(64)
         self.dmi_wr = Signal(1)

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index 688fde4b67dfdf1d46eb579ff99eb22b58baf198..3b693fda76cf6d9833103cfd4b27f504a5028f54 100755 (executable)
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -125,20 +125,21 @@ class LibreSoCSim(SoCSDRAM):
             return
 
         # setup running of DMI FSM
-        dmi_addr = Signal(3)
+        dmi_addr = Signal(4)
         dmi_din = Signal(64)
         dmi_dout = Signal(64)
         dmi_wen = Signal(1)
         dmi_req = Signal(1)
 
         # debug log out
-        dbg_addr = Signal(3)
+        dbg_addr = Signal(4)
         dbg_dout = Signal(64)
         dbg_msg = Signal(1)
 
         # capture pc from dmi
         pc = Signal(64)
         active_dbg = Signal()
+        active_dbg_cr = Signal()
 
         # increment counter, Stop after 100000 cycles
         uptime = Signal(64)
@@ -216,6 +217,9 @@ class LibreSoCSim(SoCSDRAM):
              #If(dbg_addr == 0b11, # MSR
              #   Display("    msr: %016x", dbg_dout),
              #),
+             If(dbg_addr == 0b1000, # CR
+                Display("    cr: %016x", dbg_dout),
+             ),
              If(dbg_addr == 0b101, # GPR
                 Display("    gpr: %016x", dbg_dout),
              ),
@@ -275,6 +279,7 @@ class LibreSoCSim(SoCSDRAM):
         #self.comb += active_dbg.eq((0x0 < pc) & (pc < 0x58))
         self.comb += active_dbg.eq(1)
 
+
         # get the MSR
         self.sync += If(active_dbg & (dmicount == 12),
             (dmi_addr.eq(0b11), # MSR
@@ -283,9 +288,21 @@ class LibreSoCSim(SoCSDRAM):
             )
         )
 
+        if cpu == "libresoc":
+            self.comb += active_dbg_cr.eq((0x10300 <= pc) & (pc <= 0x105ec))
+            #self.comb += active_dbg_cr.eq(1)
+
+            # get the CR
+            self.sync += If(active_dbg_cr & (dmicount == 16),
+                (dmi_addr.eq(0b1000), # CR
+                 dmi_req.eq(1),
+                 dmi_wen.eq(0),
+                )
+            )
+
         # read all 32 GPRs
         for i in range(32):
-            self.sync += If(active_dbg & (dmicount == 16+(i*8)),
+            self.sync += If(active_dbg & (dmicount == 20+(i*8)),
                 (dmi_addr.eq(0b100), # GSPR addr
                  dmi_din.eq(i), # r1
                  dmi_req.eq(1),
@@ -293,7 +310,7 @@ class LibreSoCSim(SoCSDRAM):
                 )
             )
 
-            self.sync += If(active_dbg & (dmicount == 20+(i*8)),
+            self.sync += If(active_dbg & (dmicount == 24+(i*8)),
                 (dmi_addr.eq(0b101), # GSPR data
                  dmi_req.eq(1),
                  dmi_wen.eq(0),