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author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Thu, 1 Aug 2019 22:54:52 +0000
(23:54 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Thu, 1 Aug 2019 22:54:52 +0000
(23:54 +0100)
src/nmutil/singlepipe.py
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diff --git
a/src/nmutil/singlepipe.py
b/src/nmutil/singlepipe.py
index 8a5b06dcaa41cb043d175f65beb34716a0f3fbea..76fa06847c9f25a1c344644a101951d290721907 100644
(file)
--- a/
src/nmutil/singlepipe.py
+++ b/
src/nmutil/singlepipe.py
@@
-579,6
+579,7
@@
class UnbufferedPipeline(ControlBase):
return self.m
+
class UnbufferedPipeline2(ControlBase):
""" A simple pipeline stage with single-clock synchronisation
and two-way valid/ready synchronised signalling.