#define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
#define DRM_IOCTL_V3D_SUBMIT_CSD DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd)
+#define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01
+
/**
* struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
* engine.
/* Number of BO handles passed in (size is that times 4). */
__u32 bo_handle_count;
- /* Pad, must be zero-filled. */
- __u32 pad;
+ __u32 flags;
};
/**
DRM_V3D_PARAM_V3D_CORE0_IDENT2,
DRM_V3D_PARAM_SUPPORTS_TFU,
DRM_V3D_PARAM_SUPPORTS_CSD,
+ DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH,
};
struct drm_v3d_get_param {
job->submit.bcl_end = job->bcl.bo->offset + cl_offset(&job->bcl);
job->submit.rcl_end = job->rcl.bo->offset + cl_offset(&job->rcl);
+ job->submit.flags = 0;
+ if (job->tmu_dirty_rcl && screen->has_cache_flush)
+ job->submit.flags |= DRM_V3D_SUBMIT_CL_FLUSH_CACHE;
+
/* On V3D 4.1, the tile alloc/state setup moved to register writes
* instead of binner packets.
*/
return 4;
case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
- return 4;
+ if (screen->has_cache_flush)
+ return 4;
+ else
+ return 0; /* Disables shader storage */
case PIPE_CAP_GLSL_FEATURE_LEVEL:
return 330;
return V3D_MAX_TEXTURE_SAMPLERS;
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
- if (shader == PIPE_SHADER_VERTEX)
- return 0;
+ if (screen->has_cache_flush) {
+ if (shader == PIPE_SHADER_VERTEX)
+ return 0;
- return PIPE_MAX_SHADER_BUFFERS;
+ return PIPE_MAX_SHADER_BUFFERS;
+ } else {
+ return 0;
+ }
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
- if (screen->devinfo.ver < 41)
+ if (screen->has_cache_flush) {
+ if (screen->devinfo.ver < 41)
+ return 0;
+ else
+ return PIPE_MAX_SHADER_IMAGES;
+ } else {
return 0;
- else
- return PIPE_MAX_SHADER_IMAGES;
+ }
case PIPE_SHADER_CAP_PREFERRED_IR:
return PIPE_SHADER_IR_NIR;
slab_create_parent(&screen->transfer_pool, sizeof(struct v3d_transfer), 16);
screen->has_csd = v3d_has_feature(screen, DRM_V3D_PARAM_SUPPORTS_CSD);
+ screen->has_cache_flush =
+ v3d_has_feature(screen, DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH);
v3d_fence_init(screen);
uint32_t bo_count;
bool has_csd;
+ bool has_cache_flush;
bool nonmsaa_texture_size_limit;
struct v3d_simulator_file *sim_file;
}
}
- if (job->tmu_dirty_rcl) {
- cl_emit(&job->rcl, L1_CACHE_FLUSH_CONTROL, flush) {
- flush.tmu_config_cache_clear = 0xf;
- flush.tmu_data_cache_clear = 0xf;
- flush.uniforms_cache_clear = 0xf;
- flush.instruction_cache_clear = 0xf;
- }
-
- cl_emit(&job->rcl, L2T_CACHE_FLUSH_CONTROL, flush) {
- flush.l2t_flush_mode = L2T_FLUSH_MODE_CLEAN;
- flush.l2t_flush_start = cl_address(NULL, 0);
- flush.l2t_flush_end = cl_address(NULL, ~0);
- }
- }
-
cl_emit(&job->rcl, END_OF_RENDERING, end);
}
case DRM_V3D_PARAM_SUPPORTS_CSD:
args->value = V3D_VERSION >= 41;
return 0;
+ case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH:
+ args->value = 1;
+ return 0;
}
if (args->param < ARRAY_SIZE(reg_map) && reg_map[args->param]) {