not perfect but close enough: add read registers RA/S/B/C in parser

diff --git a/libreriscv b/libreriscv
index fbdd3574edccf1fa79b5181470bf7d8d00cea8df..cde4b6519f6f23520899e1c1bba71548746015ec 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit fbdd3574edccf1fa79b5181470bf7d8d00cea8df
+Subproject commit cde4b6519f6f23520899e1c1bba71548746015ec

diff --git a/src/soc/decoder/pseudo/parser.py b/src/soc/decoder/pseudo/parser.py
index 8c6a1f2e1de2ba2150747beab8936f44b90af5ad..9da2f372fbf0981368f5f1b7853827738c996eba 100644 (file)
--- a/src/soc/decoder/pseudo/parser.py
+++ b/src/soc/decoder/pseudo/parser.py
@@ -663,6 +663,11 @@ class PowerParser:
             self.op_fields.add(name)
         if name == 'overflow':
             self.write_regs.add(name)
+        # XXX yuk.  this results in extraneous registers being added.
+        # really should be analysing slice (Assign) and working out if
+        # the variable being sliced is a GPR.
+        if name in ['RA', 'RS', 'RB', 'RC']:
+            self.read_regs.add(name)  # add to list of regs to read
         if self.include_ca_in_write:
             if name in ['CA', 'CA32']:
                 self.write_regs.add(name)