add additional SVP64 RM decode fields

diff --git a/src/soc/sv/svp64.py b/src/soc/sv/svp64.py
index f966533199a15bc511694d421f1b61bc756e3ccf..bbe03a601290d8c7e4f8089962a9424db9b35b61 100644 (file)
--- a/src/soc/sv/svp64.py
+++ b/src/soc/sv/svp64.py
@@ -38,7 +38,7 @@ class SVP64Rec(Record):
 
 """RM Mode
 
-LD/ST:
+LD/ST immed:
 00     str     sz dz   normal mode
 01     inv     CR-bit  Rc=1: ffirst CR sel
 01     inv     els RC1 Rc=0: ffirst z/nonz
@@ -46,6 +46,15 @@ LD/ST:
 11     inv     CR-bit  Rc=1: pred-result CR sel
 11     inv     els RC1 Rc=0: pred-result z/nonz
 
+LD/ST indexed:
+00     0       sz dz   normal mode
+00     rsv     rsvd    reserved
+01     inv     CR-bit  Rc=1: ffirst CR sel
+01     inv     sz RC1  Rc=0: ffirst z/nonz
+10     N       sz dz   sat mode: N=0/1 u/s
+11     inv     CR-bit  Rc=1: pred-result CR sel
+11     inv     sz RC1  Rc=0: pred-result z/nonz
+
 Arithmetic:
 00     0       sz dz   normal mode
 00     1       sz CRM  reduce mode (mapreduce), SUBVL=1
@@ -62,11 +71,24 @@ class SVP64RMMode(Elaboratable):
         self.rm_in = SVP64Rec(name=name)
         self.fn_in = Signal(Function) # LD/ST is different
         self.ptype_in = Signal(SVPtype)
+        self.rc_in = Signal()
+
+        # main mode (normal, reduce, saturate, ffirst, pred-result)
         self.mode = Signal(SVP64RMMode)
+
+        # predication
         self.predmode = Signal(SVP64PredMode)
-        self.srcpred = Signal(3)
-        self.dstpred = Signal(3)
+        self.srcpred = Signal(3) # source predicate
+        self.dstpred = Signal(3) # destination predicate
+        self.pred_sz = Signal(1) # predicate source zeroing
+        self.pred_dz = Signal(1) # predicate dest zeroing
+        
         self.saturate = Signal(SVP64sat)
+        self.RC1 = Signal()
+        self.cr_sel = Signal(2)
+        self.inv = Signal(1)
+        self.map_evm = Signal(1)
+        self.map_crm = Signal(1)
 
     def elaborate(self, platform):
         m = Module()
@@ -108,7 +130,7 @@ class SVP64RMMode(Elaboratable):
             comb += self.srcpred.eq(srcmask)
         comb += self.dstpred.eq(dstmask)
 
-        # TODO: detect zeroing mode, a few more.
+        # TODO: detect zeroing mode, saturation mode, a few more.
 
         return m