ooo far too late at night to be doing this

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index ded7e395c88f7b483407ba2cb3bd9fa200dde1d8..cabb52253a0a92b7f5b6ddb7939d3aa34a37ed3c 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -1744,7 +1744,7 @@ class DCache(Elaboratable):
         # deal with litex not doing wishbone pipeline mode
         # XXX in wrong way.  FIFOs are needed in the SRAM test
         # so that stb/ack match up. same thing done in icache.py
-        comb += self.bus.stall.eq(self.bus.cyc & ~bus.ack)
+        comb += self.bus.stall.eq(self.bus.cyc & ~self.bus.ack)
 
         # Wire up wishbone request latch out of stage 1
         comb += self.bus.we.eq(r1.wb.we)