whoops names of regfiles are lower-case

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index cb212dfa6685905fd57634029c188e134ed74672..f3cfa3d0ad1cd6fc8972888856ce68566926bfe7 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -84,7 +84,7 @@ class NonProductionCore(Elaboratable):
                 (regname, rdflag, read, wid) = byregfiles_rdspec[regfile]
 
                 # "munge" the regfile port index, due to full-port access
-                if regfile in ['XER', 'CR']:
+                if regfile in ['xer', 'cr']:
                     if regname.startswith('full'):
                         rpidx = 0 # by convention, first port
                     else: