replace PartitionedSignal with SimdSignal

diff --git a/pinmux b/pinmux
index 096caad8418250693c93ccf90047750704adcaa7..d96f737c0a53dde983060522816bbef016b449ce 160000 (submodule)
--- a/pinmux
+++ b/pinmux
@@ -1 +1 @@
-Subproject commit 096caad8418250693c93ccf90047750704adcaa7
+Subproject commit d96f737c0a53dde983060522816bbef016b449ce

diff --git a/src/soc/fu/alu/main_stage.py b/src/soc/fu/alu/main_stage.py
index 4d5fe2313bb9184e63fff9b3f81422650d1d9ba4..f4ad49183c1ffbd686644238a676d7dd807c64b6 100644 (file)
--- a/src/soc/fu/alu/main_stage.py
+++ b/src/soc/fu/alu/main_stage.py
@@ -13,7 +13,7 @@ from nmigen import (Module, Signal, Cat, Repl, Mux, Const)
 from nmutil.pipemodbase import PipeModBase
 from nmutil.extend import exts, extz
 from soc.fu.alu.pipe_data import ALUInputData, ALUOutputData
-from ieee754.part.partsig import PartitionedSignal
+from ieee754.part.partsig import SimdSignal
 from openpower.decoder.power_enums import MicrOp
 
 from openpower.decoder.power_fields import DecodeFields

diff --git a/src/soc/fu/alu/output_stage.py b/src/soc/fu/alu/output_stage.py
index 49444e97b1449eeab0e7ea7927aaa51b18c34116..395b268bdc9fe970540bef08d51a78fed57b25ab 100644 (file)
--- a/src/soc/fu/alu/output_stage.py
+++ b/src/soc/fu/alu/output_stage.py
@@ -4,7 +4,7 @@
 from nmigen import (Module, Signal, Cat, Repl)
 from soc.fu.alu.pipe_data import ALUInputData, ALUOutputData
 from soc.fu.common_output_stage import CommonOutputStage
-from ieee754.part.partsig import PartitionedSignal
+from ieee754.part.partsig import SimdSignal
 from openpower.decoder.power_enums import MicrOp
 
 

diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py
index dc17410af790998086d38643518860aab0406cd3..45106984a0e1469a255d5ad5e198974c2d37cc70 100644 (file)
--- a/src/soc/fu/common_output_stage.py
+++ b/src/soc/fu/common_output_stage.py
@@ -2,7 +2,7 @@
 # and updating the condition register
 from nmigen import (Module, Signal, Cat, Const)
 from nmutil.pipemodbase import PipeModBase
-from ieee754.part.partsig import PartitionedSignal
+from ieee754.part.partsig import SimdSignal
 from openpower.decoder.power_enums import MicrOp
 
 

diff --git a/src/soc/fu/div/core_stages.py b/src/soc/fu/div/core_stages.py
index 9f63a63117ac5e0d4a72f4e7d0dc901d721fd504..e271876b26e41b1f74a6bd919dd985691cae00b0 100644 (file)
--- a/src/soc/fu/div/core_stages.py
+++ b/src/soc/fu/div/core_stages.py
@@ -3,7 +3,7 @@
 
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
 from nmutil.pipemodbase import PipeModBase
-from ieee754.part.partsig import PartitionedSignal
+from ieee754.part.partsig import SimdSignal
 from openpower.decoder.power_enums import MicrOp
 
 from openpower.decoder.power_fields import DecodeFields

diff --git a/src/soc/fu/div/output_stage.py b/src/soc/fu/div/output_stage.py
index 903770ddd0b50b0dc23c647654adcab265f6126e..31218c66ef0af904704b7cfbbabd397d76290e33 100644 (file)
--- a/src/soc/fu/div/output_stage.py
+++ b/src/soc/fu/div/output_stage.py
@@ -8,7 +8,7 @@ from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array, signed)
 from nmutil.pipemodbase import PipeModBase
 from soc.fu.logical.pipe_data import LogicalInputData
 from soc.fu.div.pipe_data import DivMulOutputData
-from ieee754.part.partsig import PartitionedSignal
+from ieee754.part.partsig import SimdSignal
 from openpower.decoder.power_enums import MicrOp
 
 from openpower.decoder.power_fields import DecodeFields

diff --git a/src/soc/fu/div/setup_stage.py b/src/soc/fu/div/setup_stage.py
index 937bcbb029a8ce00231522dd17353637b7d36bc0..0625159e123b67658a7e667327835ec637b2a038 100644 (file)
--- a/src/soc/fu/div/setup_stage.py
+++ b/src/soc/fu/div/setup_stage.py
@@ -4,7 +4,7 @@
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
 from nmutil.pipemodbase import PipeModBase
 from soc.fu.div.pipe_data import DivInputData
-from ieee754.part.partsig import PartitionedSignal
+from ieee754.part.partsig import SimdSignal
 from openpower.decoder.power_enums import MicrOp
 
 from openpower.decoder.power_fields import DecodeFields

diff --git a/src/soc/fu/logical/main_stage.py b/src/soc/fu/logical/main_stage.py
index e56f3445f4cd538ede6c72b36995eaf620a5c19e..253664032fc16a1401665416a70e33688c6caa65 100644 (file)
--- a/src/soc/fu/logical/main_stage.py
+++ b/src/soc/fu/logical/main_stage.py
@@ -13,7 +13,7 @@ from soc.fu.logical.pipe_data import LogicalInputData
 from soc.fu.logical.bpermd import Bpermd
 from soc.fu.logical.popcount import Popcount
 from soc.fu.logical.pipe_data import LogicalOutputData
-from ieee754.part.partsig import PartitionedSignal
+from ieee754.part.partsig import SimdSignal
 from openpower.decoder.power_enums import MicrOp
 
 from openpower.decoder.power_fields import DecodeFields

diff --git a/src/soc/fu/logical/output_stage.py b/src/soc/fu/logical/output_stage.py
index 73b48d1eecdd33a58245c5fba91685b53c07e52c..81a1c5247de848509bea6b2e577ea78401225e60 100644 (file)
--- a/src/soc/fu/logical/output_stage.py
+++ b/src/soc/fu/logical/output_stage.py
@@ -6,7 +6,7 @@ from nmutil.pipemodbase import PipeModBase
 from soc.fu.common_output_stage import CommonOutputStage
 from soc.fu.logical.pipe_data import (LogicalInputData, LogicalOutputData,
                                       LogicalOutputDataFinal)
-from ieee754.part.partsig import PartitionedSignal
+from ieee754.part.partsig import SimdSignal
 from openpower.decoder.power_enums import MicrOp
 
 

diff --git a/src/soc/fu/mul/main_stage.py b/src/soc/fu/mul/main_stage.py
index 68bcf47d5df861ec71708dac7b3b26121a3e4dc4..e2a2727f2c1de56cbdbfa9c72e7dc320166f12cb 100644 (file)
--- a/src/soc/fu/mul/main_stage.py
+++ b/src/soc/fu/mul/main_stage.py
@@ -3,7 +3,7 @@
 from nmigen import Module
 from nmutil.pipemodbase import PipeModBase
 from soc.fu.mul.pipe_data import MulIntermediateData, MulOutputData
-from ieee754.part.partsig import PartitionedSignal
+from ieee754.part.partsig import SimdSignal
 
 
 class MulMainStage2(PipeModBase):

diff --git a/src/soc/fu/mul/post_stage.py b/src/soc/fu/mul/post_stage.py
index 0b45c791ade830433a5cde5ce2638d2eb7e07d6e..d7e8df417a4a699861b59ff86705a11b11281dc4 100644 (file)
--- a/src/soc/fu/mul/post_stage.py
+++ b/src/soc/fu/mul/post_stage.py
@@ -10,7 +10,7 @@ from nmigen import (Module, Signal, Cat, Repl, Mux, signed)
 from nmutil.pipemodbase import PipeModBase
 from soc.fu.div.pipe_data import DivMulOutputData
 from soc.fu.mul.pipe_data import MulOutputData
-from ieee754.part.partsig import PartitionedSignal
+from ieee754.part.partsig import SimdSignal
 from openpower.decoder.power_enums import MicrOp
 
 

diff --git a/src/soc/fu/mul/pre_stage.py b/src/soc/fu/mul/pre_stage.py
index f22964dd5b50be0930fe6fa77c1841486b1363e1..c5e696ae415afbe03e294c4f386c22316c34c7d0 100644 (file)
--- a/src/soc/fu/mul/pre_stage.py
+++ b/src/soc/fu/mul/pre_stage.py
@@ -4,7 +4,7 @@ from nmigen import (Module, Signal, Mux)
 from nmutil.pipemodbase import PipeModBase
 from soc.fu.div.pipe_data import DivInputData
 from soc.fu.mul.pipe_data import MulIntermediateData
-from ieee754.part.partsig import PartitionedSignal
+from ieee754.part.partsig import SimdSignal
 from nmutil.util import eq32
 
 class MulMainStage1(PipeModBase):

diff --git a/src/soc/fu/shift_rot/main_stage.py b/src/soc/fu/shift_rot/main_stage.py
index 0be12d1b2fd08a9a90456fd81eac606c4f0117bc..76550854096324fbae365ff5d263e529474a5977 100644 (file)
--- a/src/soc/fu/shift_rot/main_stage.py
+++ b/src/soc/fu/shift_rot/main_stage.py
@@ -10,7 +10,7 @@ from nmigen import (Module, Signal, Cat, Repl, Mux, Const)
 from nmutil.pipemodbase import PipeModBase
 from soc.fu.shift_rot.pipe_data import (ShiftRotOutputData,
                                        ShiftRotInputData)
-from ieee754.part.partsig import PartitionedSignal
+from ieee754.part.partsig import SimdSignal
 from openpower.decoder.power_enums import MicrOp
 from soc.fu.shift_rot.rotator import Rotator
 

diff --git a/src/soc/litex/florent b/src/soc/litex/florent
index b55917aafa6bbc9f16e1d97dc095e929c31aa81a..42f7357660b245c4491297d24eebc28b4ac2c21f 160000 (submodule)
--- a/src/soc/litex/florent
+++ b/src/soc/litex/florent
@@ -1 +1 @@
-Subproject commit b55917aafa6bbc9f16e1d97dc095e929c31aa81a
+Subproject commit 42f7357660b245c4491297d24eebc28b4ac2c21f