+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
-atags_addr=134217728
-boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
-early_kernel_symbols=false
-enable_context_switch_stats_dump=false
-eventq_index=0
-exit_on_work_items=false
-flags_addr=469827632
-gic_cpu_addr=738205696
-have_large_asid_64=false
-have_lpae=true
-have_security=false
-have_virtualization=false
-highest_el_is_64=false
-init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
-kernel_addr_check=true
-load_addr_mask=268435455
-load_offset=2147483648
-machine_type=VExpress_EMM
-mem_mode=atomic
-mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.nvmem system.realview.vram
-mmap_using_noreserve=false
-multi_proc=true
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-panic_on_oops=true
-panic_on_panic=true
-phys_addr_range_64=40
-power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
-reset_addr_64=0
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img
-read_only=true
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=AtomicSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu0.dstage2_mmu
-dtb=system.cpu0.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-istage2_mmu=system.cpu0.istage2_mmu
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu0.tracer
-width=1
-workload=
-dcache_port=system.cpu0.dcache.cpu_side
-icache_port=system.cpu0.icache.cpu_side
-
-[system.cpu0.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=6
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.dcache.tags
-tgts_per_mshr=8
-write_buffers=16
-writeback_clean=true
-cpu_side=system.cpu0.dcache_port
-mem_side=system.cpu0.toL2Bus.slave[1]
-
-[system.cpu0.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu0.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.dtb
-
-[system.cpu0.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu0.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu0.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.dtb.walker
-
-[system.cpu0.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu0.toL2Bus.slave[3]
-
-[system.cpu0.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=1
-is_read_only=true
-max_miss_count=0
-mshrs=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=1
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.icache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu0.icache_port
-mem_side=system.cpu0.toL2Bus.slave[0]
-
-[system.cpu0.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu0.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu0.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu0.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.itb
-
-[system.cpu0.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.istage2_mmu.stage2_tlb.walker
-
-[system.cpu0.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu0.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.itb.walker
-
-[system.cpu0.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu0.toL2Bus.slave[2]
-
-[system.cpu0.l2cache]
-type=Cache
-children=prefetcher tags
-addr_ranges=0:18446744073709551615
-assoc=16
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_excl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=12
-is_read_only=false
-max_miss_count=0
-mshrs=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=true
-prefetcher=system.cpu0.l2cache.prefetcher
-response_latency=12
-sequential_access=false
-size=1048576
-system=system
-tags=system.cpu0.l2cache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu0.toL2Bus.master[0]
-mem_side=system.toL2Bus.slave[0]
-
-[system.cpu0.l2cache.prefetcher]
-type=StridePrefetcher
-cache_snoop=false
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-degree=8
-eventq_index=0
-latency=1
-max_conf=7
-min_conf=0
-on_data=true
-on_inst=true
-on_miss=false
-on_read=true
-on_write=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-queue_filter=true
-queue_size=32
-queue_squash=true
-start_conf=4
-sys=system
-table_assoc=4
-table_sets=16
-tag_prefetch=true
-thresh_conf=4
-use_master_id=true
-
-[system.cpu0.l2cache.tags]
-type=RandomRepl
-assoc=16
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=12
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1048576
-
-[system.cpu0.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu0.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu0.l2cache.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
-
-[system.cpu0.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu0.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu1]
-type=AtomicSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu1.dstage2_mmu
-dtb=system.cpu1.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu1.interrupts
-isa=system.cpu1.isa
-istage2_mmu=system.cpu1.istage2_mmu
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu1.tracer
-width=1
-workload=
-dcache_port=system.cpu1.dcache.cpu_side
-icache_port=system.cpu1.icache.cpu_side
-
-[system.cpu1.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=6
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu1.dcache.tags
-tgts_per_mshr=8
-write_buffers=16
-writeback_clean=true
-cpu_side=system.cpu1.dcache_port
-mem_side=system.cpu1.toL2Bus.slave[1]
-
-[system.cpu1.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu1.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.dtb
-
-[system.cpu1.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu1.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.dtb.walker
-
-[system.cpu1.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu1.toL2Bus.slave[3]
-
-[system.cpu1.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=1
-is_read_only=true
-max_miss_count=0
-mshrs=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=1
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu1.icache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu1.icache_port
-mem_side=system.cpu1.toL2Bus.slave[0]
-
-[system.cpu1.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu1.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu1.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu1.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.itb
-
-[system.cpu1.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.istage2_mmu.stage2_tlb.walker
-
-[system.cpu1.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.itb.walker
-
-[system.cpu1.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu1.toL2Bus.slave[2]
-
-[system.cpu1.l2cache]
-type=Cache
-children=prefetcher tags
-addr_ranges=0:18446744073709551615
-assoc=16
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_excl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=12
-is_read_only=false
-max_miss_count=0
-mshrs=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=true
-prefetcher=system.cpu1.l2cache.prefetcher
-response_latency=12
-sequential_access=false
-size=1048576
-system=system
-tags=system.cpu1.l2cache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu1.toL2Bus.master[0]
-mem_side=system.toL2Bus.slave[1]
-
-[system.cpu1.l2cache.prefetcher]
-type=StridePrefetcher
-cache_snoop=false
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-degree=8
-eventq_index=0
-latency=1
-max_conf=7
-min_conf=0
-on_data=true
-on_inst=true
-on_miss=false
-on_read=true
-on_write=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-queue_filter=true
-queue_size=32
-queue_squash=true
-start_conf=4
-sys=system
-table_assoc=4
-table_sets=16
-tag_prefetch=true
-thresh_conf=4
-use_master_id=true
-
-[system.cpu1.l2cache.tags]
-type=RandomRepl
-assoc=16
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=12
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1048576
-
-[system.cpu1.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu1.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu1.l2cache.cpu_side
-slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
-
-[system.cpu1.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu1.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=2147483648:2415919103
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[3]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=50
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-
-[system.l2c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.l2c.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.l2c.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=2147483648:2415919103
-port=system.membus.master[5]
-
-[system.realview]
-type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470024192
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[18]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=471465984
-BAR0LegacyIO=true
-BAR0Size=256
-BAR1=471466240
-BAR1LegacyIO=true
-BAR1Size=4096
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=2
-default_p_state=UNDEFINED
-disks=
-eventq_index=0
-host=system.realview.pci_host
-io_shift=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=2
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[2]
-pio=system.iobus.master[9]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=46
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471793664
-pio_latency=10000
-pixel_clock=41667
-power_model=Null
-system=system
-vnc=system.vncserver
-dma=system.iobus.slave[1]
-pio=system.iobus.master[5]
-
-[system.realview.dcc]
-type=SubSystem
-children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.dcc.osc_cpu]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_ddr]
-type=RealViewOsc
-dcc=0
-device=8
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_hsbm]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_pxl]
-type=RealViewOsc
-dcc=0
-device=5
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_smb]
-type=RealViewOsc
-dcc=0
-device=6
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_sys]
-type=RealViewOsc
-dcc=0
-device=7
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.energy_ctrl]
-type=EnergyCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dvfs_handler=system.dvfs_handler
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470286336
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[22]
-
-[system.realview.ethernet]
-type=IGbE
-BAR0=0
-BAR0LegacyIO=false
-BAR0Size=131072
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=0
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=4213
-ExpansionROM=0
-HeaderType=0
-InterruptLine=1
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=255
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=0
-SubClassCode=0
-SubsystemID=4104
-SubsystemVendorID=32902
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-eventq_index=0
-fetch_comp_delay=10000
-fetch_delay=10000
-hardware_address=00:90:00:00:00:01
-host=system.realview.pci_host
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-phy_epid=896
-phy_pid=680
-pio_latency=30000
-power_model=Null
-rx_desc_cache_size=64
-rx_fifo_size=393216
-rx_write_delay=0
-system=system
-tx_desc_cache_size=64
-tx_fifo_size=393216
-tx_read_delay=0
-wb_comp_delay=10000
-wb_delay=10000
-dma=system.iobus.slave[4]
-pio=system.iobus.master[24]
-
-[system.realview.generic_timer]
-type=GenericTimer
-eventq_index=0
-gic=system.realview.gic
-int_phys=29
-int_virt=27
-system=system
-
-[system.realview.gic]
-type=Pl390
-clk_domain=system.clk_domain
-cpu_addr=738205696
-cpu_pio_delay=10000
-default_p_state=UNDEFINED
-dist_addr=738201600
-dist_pio_delay=10000
-eventq_index=0
-gem5_extensions=true
-int_latency=10000
-it_lines=128
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-platform=system.realview
-power_model=Null
-system=system
-pio=system.membus.master[2]
-
-[system.realview.hdlcd]
-type=HDLcd
-amba_id=1314816
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=117
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=721420288
-pio_latency=10000
-pixel_buffer_size=2048
-pixel_chunk=32
-power_model=Null
-pxl_clk=system.realview.dcc.osc_pxl
-system=system
-vnc=system.vncserver
-workaround_dma_line_count=true
-workaround_swap_rb=true
-dma=system.membus.slave[0]
-pio=system.iobus.master[6]
-
-[system.realview.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=2
-InterruptPin=2
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.cf0
-eventq_index=0
-host=system.realview.pci_host
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[3]
-pio=system.iobus.master[23]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=44
-is_mouse=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470155264
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[7]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=45
-is_mouse=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470220800
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[8]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=739246080
-pio_latency=100000
-pio_size=4095
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.realview.lan_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=436207616
-pio_latency=100000
-pio_size=65535
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=738721792
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.membus.master[4]
-
-[system.realview.mcc]
-type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.mcc.osc_clcd]
-type=RealViewOsc
-dcc=0
-device=1
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_mcc]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_peripheral]
-type=RealViewOsc
-dcc=0
-device=2
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_system_bus]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.temp_crtl]
-type=RealViewTemperatureSensor
-dcc=0
-device=0
-eventq_index=0
-parent=system.realview.realview_io
-position=0
-site=0
-system=system
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470089728
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.realview.nvmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:67108863
-port=system.membus.master[1]
-
-[system.realview.pci_host]
-type=GenericPciHost
-clk_domain=system.clk_domain
-conf_base=805306368
-conf_device_bits=16
-conf_size=268435456
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=0
-pci_pio_base=0
-platform=system.realview
-power_model=Null
-system=system
-pio=system.iobus.master[2]
-
-[system.realview.realview_io]
-type=RealViewCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-idreg=35979264
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469827584
-pio_latency=100000
-power_model=Null
-proc_id0=335544320
-proc_id1=335544320
-system=system
-pio=system.iobus.master[1]
-
-[system.realview.rtc]
-type=PL031
-amba_id=3412017
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=36
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471269376
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[10]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469893120
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=34
-int_num1=34
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470876160
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[3]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=35
-int_num1=35
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470941696
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[4]
-
-[system.realview.uart]
-type=Pl011
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-end_on_eot=false
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=37
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470351872
-pio_latency=100000
-platform=system.realview
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[0]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470417408
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470482944
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470548480
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[15]
-
-[system.realview.usb_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=452984832
-pio_latency=100000
-pio_size=131071
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.realview.vgic]
-type=VGic
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-hv_addr=738213888
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_delay=10000
-platform=system.realview
-power_model=Null
-ppint=25
-system=system
-vcpu_addr=738222080
-pio=system.membus.master[3]
-
-[system.realview.vram]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=402653184:436207615
-port=system.iobus.master[11]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470745088
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[17]
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2c.cpu_side
-slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
-
-[system.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.vncserver]
-type=VncServer
-eventq_index=0
-frame_capture=false
-number=0
-port=5900
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
-warn: Not doing anything for miscreg ACTLR
-warn: Not doing anything for write of miscreg ACTLR
-warn: The clidr register always reports 0 caches.
-warn: clidr LoUIS field of 0b001 to match current ARM implementations.
-warn: The csselr register isn't implemented.
-warn: instruction 'mcr dccmvau' unimplemented
-warn: instruction 'mcr icimvau' unimplemented
-warn: instruction 'mcr bpiallis' unimplemented
-warn: instruction 'mcr icialluis' unimplemented
-warn: instruction 'mcr dccimvac' unimplemented
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Not doing anything for miscreg ACTLR
-warn: Not doing anything for write of miscreg ACTLR
-warn: instruction 'mcr bpiall' unimplemented
-warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
-warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
-warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
-warn: Returning zero for read from miscreg pmcr
-warn: Ignoring write to miscreg pmcntenclr
-warn: Ignoring write to miscreg pmintenclr
-warn: Ignoring write to miscreg pmovsr
-warn: Ignoring write to miscreg pmcr
-warn: Ignoring write to miscreg pmcntenclr
-warn: Ignoring write to miscreg pmintenclr
-warn: Ignoring write to miscreg pmovsr
-warn: Ignoring write to miscreg pmcr
+++ /dev/null
-Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual/simout
-Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Aug 1 2016 17:10:05
-gem5 started Aug 1 2016 17:37:31
-gem5 executing on e108600-lin, pid 13229
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
-
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
-info: Using bootloader at address 0x10
-info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
-info: Entering event queue @ 0. Starting simulation...
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2802883274000 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 2.802884 # Number of seconds simulated
-sim_ticks 2802884446000 # Number of ticks simulated
-final_tick 2802884446000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1499640 # Simulator instruction rate (inst/s)
-host_op_rate 1827287 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 28629719673 # Simulator tick rate (ticks/s)
-host_mem_usage 593616 # Number of bytes of host memory used
-host_seconds 97.90 # Real time elapsed on the host
-sim_insts 146816546 # Number of instructions simulated
-sim_ops 178893643 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 1163556 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 9541156 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 165076 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 1111568 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11983020 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 1163556 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 165076 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1328632 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8871872 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8889436 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 26634 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 149600 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 2734 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 17388 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 196382 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 138623 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 143014 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 415128 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 3404049 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 58895 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 396580 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4275246 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 415128 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 58895 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 474023 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3165265 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3171531 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3165265 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 415128 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3410301 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 58895 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 396594 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7446777 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks 7964 # Table walker walks requested
-system.cpu0.dtb.walker.walksShort 7964 # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples 7964 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 7964 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 7964 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 5079 77.31% 77.31% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M 1491 22.69% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 6570 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7964 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7964 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6570 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6570 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 14534 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.inst_hits 0 # ITB inst hits
-system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 20338335 # DTB read hits
-system.cpu0.dtb.read_misses 6871 # DTB read misses
-system.cpu0.dtb.write_hits 16389802 # DTB write hits
-system.cpu0.dtb.write_misses 1093 # DTB write misses
-system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 3435 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch
-system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 20345206 # DTB read accesses
-system.cpu0.dtb.write_accesses 16390895 # DTB write accesses
-system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 36728137 # DTB hits
-system.cpu0.dtb.misses 7964 # DTB misses
-system.cpu0.dtb.accesses 36736101 # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks 3358 # Table walker walks requested
-system.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 2040 87.11% 87.11% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M 302 12.89% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 2342 # Table walker page sizes translated
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3358 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 97433825 # ITB inst hits
-system.cpu0.itb.inst_misses 3358 # ITB inst misses
-system.cpu0.itb.read_hits 0 # DTB read hits
-system.cpu0.itb.read_misses 0 # DTB read misses
-system.cpu0.itb.write_hits 0 # DTB write hits
-system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2096 # Number of entries that have been flushed from TLB
-system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.itb.read_accesses 0 # DTB read accesses
-system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 97437183 # ITB inst accesses
-system.cpu0.itb.hits 97433825 # DTB hits
-system.cpu0.itb.misses 3358 # DTB misses
-system.cpu0.itb.accesses 97437183 # DTB accesses
-system.cpu0.numPwrStateTransitions 3948 # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples 1974 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean 1390119373.406788 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev 23077022550.794018 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows 1158 58.66% 58.66% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10 810 41.03% 99.70% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.75% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.80% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.20% 100.00% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 499983361388 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total 1974 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON 58788802895 # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 2744095643105 # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles 5605770867 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 1974 # number of quiesce instructions executed
-system.cpu0.committedInsts 95421368 # Number of instructions committed
-system.cpu0.committedOps 115553536 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 100756492 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses
-system.cpu0.num_func_calls 8000109 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 13203633 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 100756492 # number of integer instructions
-system.cpu0.num_fp_insts 9755 # number of float instructions
-system.cpu0.num_int_register_reads 182435981 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 69130832 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 349950831 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 44904973 # number of times the CC registers were written
-system.cpu0.num_mem_refs 37870982 # number of memory refs
-system.cpu0.num_load_insts 20595866 # Number of load instructions
-system.cpu0.num_store_insts 17275116 # Number of store instructions
-system.cpu0.num_idle_cycles 5488193219.783614 # Number of idle cycles
-system.cpu0.num_busy_cycles 117577647.216386 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.020974 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.979026 # Percentage of idle cycles
-system.cpu0.Branches 21940830 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 78883265 67.49% 67.50% # Class of executed instruction
-system.cpu0.op_class::IntMult 110622 0.09% 67.59% # Class of executed instruction
-system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction
-system.cpu0.op_class::FloatMultAcc 0 0.00% 67.59% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction
-system.cpu0.op_class::FloatMisc 0 0.00% 67.59% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 67.59% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 67.59% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 67.59% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 67.59% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 67.59% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 67.59% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 67.59% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.59% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 67.59% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.59% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction
-system.cpu0.op_class::MemRead 20593610 17.62% 85.22% # Class of executed instruction
-system.cpu0.op_class::MemWrite 17267621 14.77% 99.99% # Class of executed instruction
-system.cpu0.op_class::FloatMemRead 2256 0.00% 99.99% # Class of executed instruction
-system.cpu0.op_class::FloatMemWrite 7495 0.01% 100.00% # Class of executed instruction
-system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 116875229 # Class of executed instruction
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements 693487 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 494.728118 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 35929711 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 693999 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 51.771992 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.728118 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966266 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.966266 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 74108594 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 74108594 # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data 19107187 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 19107187 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 15689146 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 15689146 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346045 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 346045 # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379608 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 379608 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363041 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 363041 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 34796333 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 34796333 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 35142378 # number of overall hits
-system.cpu0.dcache.overall_hits::total 35142378 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 373137 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 373137 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 295785 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 295785 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100323 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 100323 # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6741 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 6741 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18422 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 18422 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 668922 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 668922 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 769245 # number of overall misses
-system.cpu0.dcache.overall_misses::total 769245 # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 19480324 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 19480324 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 15984931 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 15984931 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446368 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 446368 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386349 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 386349 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381463 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 381463 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 35465255 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 35465255 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 35911623 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 35911623 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019155 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.019155 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018504 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.018504 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224754 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224754 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017448 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017448 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048293 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048293 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018861 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.018861 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021421 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.021421 # miss rate for overall accesses
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks 693487 # number of writebacks
-system.cpu0.dcache.writebacks::total 693487 # number of writebacks
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements 1109393 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 96326253 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 1109905 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 86.787836 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 6345718500 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 195982248 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 195982248 # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst 96326253 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 96326253 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 96326253 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 96326253 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 96326253 # number of overall hits
-system.cpu0.icache.overall_hits::total 96326253 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 1109914 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 1109914 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 1109914 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 1109914 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 1109914 # number of overall misses
-system.cpu0.icache.overall_misses::total 1109914 # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 97436167 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 97436167 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 97436167 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 97436167 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 97436167 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 97436167 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011391 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011391 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.011391 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011391 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.011391 # miss rate for overall accesses
-system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks 1109393 # number of writebacks
-system.cpu0.icache.writebacks::total 1109393 # number of writebacks
-system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
-system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
-system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.tags.replacements 245116 # number of replacements
-system.cpu0.l2cache.tags.tagsinuse 15690.277500 # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs 1517282 # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs 260748 # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs 5.818959 # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 15688.004723 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.222065 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.050711 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks 0.957520 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000136 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000003 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total 0.957659 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023 3 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15629 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 528 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 881 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7801 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5151 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1268 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000183 # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.953918 # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses 60866660 # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses 60866660 # Number of data accesses
-system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10118 # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4491 # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total 14609 # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks 509920 # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total 509920 # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks 1265098 # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total 1265098 # number of WritebackClean hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94164 # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total 94164 # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1049983 # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total 1049983 # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 344453 # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total 344453 # number of ReadSharedReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10118 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4491 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst 1049983 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data 438617 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total 1503209 # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10118 # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4491 # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst 1049983 # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data 438617 # number of overall hits
-system.cpu0.l2cache.overall_hits::total 1503209 # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 266 # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 132 # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total 398 # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26262 # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total 26262 # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18422 # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total 18422 # number of SCUpgradeReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175359 # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total 175359 # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 59931 # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total 59931 # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 135748 # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total 135748 # number of ReadSharedReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 266 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker 132 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst 59931 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data 311107 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total 371436 # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 266 # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker 132 # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst 59931 # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data 311107 # number of overall misses
-system.cpu0.l2cache.overall_misses::total 371436 # number of overall misses
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10384 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4623 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total 15007 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::writebacks 509920 # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::total 509920 # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::writebacks 1265098 # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::total 1265098 # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26262 # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total 26262 # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18422 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total 18422 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269523 # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total 269523 # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1109914 # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total 1109914 # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480201 # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total 480201 # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10384 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4623 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst 1109914 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data 749724 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total 1874645 # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10384 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4623 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst 1109914 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data 749724 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total 1874645 # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.025616 # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.028553 # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total 0.026521 # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650627 # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650627 # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.053996 # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.053996 # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.282690 # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.282690 # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.025616 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.028553 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.053996 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.414962 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total 0.198137 # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.025616 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.028553 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.053996 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.414962 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total 0.198137 # miss rate for overall accesses
-system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.l2cache.writebacks::writebacks 192903 # number of writebacks
-system.cpu0.l2cache.writebacks::total 192903 # number of writebacks
-system.cpu0.toL2Bus.snoop_filter.tot_requests 3719568 # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1859945 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27875 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops 111615 # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 109909 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1706 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.cpu0.toL2Bus.trans_dist::ReadReq 61410 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 1651525 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 28340 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 28340 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty 509920 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean 1292960 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 26262 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18422 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 44684 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 269523 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 269523 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1109914 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480201 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3347265 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402135 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 5791024 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 142071736 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92556032 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 234711016 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 530821 # Total snoops (count)
-system.cpu0.toL2Bus.snoopTraffic 12390272 # Total snoop traffic (bytes)
-system.cpu0.toL2Bus.snoop_fanout::samples 4225152 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 0.042946 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.204717 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 4045406 95.75% 95.75% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 178040 4.21% 99.96% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 1706 0.04% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 4225152 # Request fanout histogram
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks 3359 # Table walker walks requested
-system.cpu1.dtb.walker.walksShort 3359 # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walkWaitTime::samples 3359 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 3359 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 3359 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walksPending::samples -1804201736 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 -1804201736 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total -1804201736 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 1919 74.12% 74.12% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M 670 25.88% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 2589 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3359 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3359 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2589 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2589 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 5948 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.inst_hits 0 # ITB inst hits
-system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 12172433 # DTB read hits
-system.cpu1.dtb.read_misses 2853 # DTB read misses
-system.cpu1.dtb.write_hits 7586113 # DTB write hits
-system.cpu1.dtb.write_misses 506 # DTB write misses
-system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1949 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch
-system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 12175286 # DTB read accesses
-system.cpu1.dtb.write_accesses 7586619 # DTB write accesses
-system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 19758546 # DTB hits
-system.cpu1.dtb.misses 3359 # DTB misses
-system.cpu1.dtb.accesses 19761905 # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks 1734 # Table walker walks requested
-system.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walksPending::samples -1804204236 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 -1804204236 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total -1804204236 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1734 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1734 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 53665397 # ITB inst hits
-system.cpu1.itb.inst_misses 1734 # ITB inst misses
-system.cpu1.itb.read_hits 0 # DTB read hits
-system.cpu1.itb.read_misses 0 # DTB read misses
-system.cpu1.itb.write_hits 0 # DTB write hits
-system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1072 # Number of entries that have been flushed from TLB
-system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.itb.read_accesses 0 # DTB read accesses
-system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 53667131 # ITB inst accesses
-system.cpu1.itb.hits 53665397 # DTB hits
-system.cpu1.itb.misses 1734 # DTB misses
-system.cpu1.itb.accesses 53667131 # DTB accesses
-system.cpu1.numPwrStateTransitions 5467 # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples 2734 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean 1013196310.731163 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev 25944771747.523987 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows 1955 71.51% 71.51% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10 774 28.31% 99.82% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.89% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 979984970108 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total 2734 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON 32805732461 # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 2770078713539 # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles 5605299760 # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2734 # number of quiesce instructions executed
-system.cpu1.committedInsts 51395178 # Number of instructions committed
-system.cpu1.committedOps 63340107 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 56977448 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses
-system.cpu1.num_func_calls 9170327 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 5966466 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 56977448 # number of integer instructions
-system.cpu1.num_fp_insts 1792 # number of float instructions
-system.cpu1.num_int_register_reads 110657896 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 41293618 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 196245989 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 18891972 # number of times the CC registers were written
-system.cpu1.num_mem_refs 20023642 # number of memory refs
-system.cpu1.num_load_insts 12288014 # Number of load instructions
-system.cpu1.num_store_insts 7735628 # Number of store instructions
-system.cpu1.num_idle_cycles 5539693785.928316 # Number of idle cycles
-system.cpu1.num_busy_cycles 65605974.071684 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.011704 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.988296 # Percentage of idle cycles
-system.cpu1.Branches 15216333 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 45396557 69.36% 69.36% # Class of executed instruction
-system.cpu1.op_class::IntMult 28337 0.04% 69.40% # Class of executed instruction
-system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction
-system.cpu1.op_class::FloatMultAcc 0 0.00% 69.40% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction
-system.cpu1.op_class::FloatMisc 0 0.00% 69.40% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 3315 0.01% 69.41% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction
-system.cpu1.op_class::MemRead 12287498 18.77% 88.18% # Class of executed instruction
-system.cpu1.op_class::MemWrite 7734352 11.82% 100.00% # Class of executed instruction
-system.cpu1.op_class::FloatMemRead 516 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::FloatMemWrite 1276 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 65451917 # Class of executed instruction
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements 191899 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 472.757768 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 19500995 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 192253 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 101.434022 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 105851556000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.757768 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923355 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.923355 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 39746768 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 39746768 # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data 11857290 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 11857290 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 7396404 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 7396404 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50103 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 50103 # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91426 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 91426 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72438 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 72438 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 19253694 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 19253694 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 19303797 # number of overall hits
-system.cpu1.dcache.overall_hits::total 19303797 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 136572 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 136572 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 92482 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 92482 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30717 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 30717 # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22523 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 22523 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 229054 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 229054 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 259771 # number of overall misses
-system.cpu1.dcache.overall_misses::total 259771 # number of overall misses
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 11993862 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 11993862 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 7488886 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 7488886 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80820 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total 80820 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96744 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 96744 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94961 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 94961 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 19482748 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 19482748 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 19563568 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 19563568 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011387 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.011387 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012349 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.012349 # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380067 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380067 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054970 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054970 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237182 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237182 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013278 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.013278 # miss rate for overall accesses
-system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks 191899 # number of writebacks
-system.cpu1.dcache.writebacks::total 191899 # number of writebacks
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.cpu1.icache.tags.replacements 523278 # number of replacements
-system.cpu1.icache.tags.tagsinuse 499.709352 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 53142697 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 523790 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 101.458021 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 76931398500 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.709352 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975995 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.975995 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 107856764 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 107856764 # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst 53142697 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 53142697 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 53142697 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 53142697 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 53142697 # number of overall hits
-system.cpu1.icache.overall_hits::total 53142697 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 523790 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 523790 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 523790 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 523790 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 523790 # number of overall misses
-system.cpu1.icache.overall_misses::total 523790 # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 53666487 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 53666487 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 53666487 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 53666487 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 53666487 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 53666487 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009760 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.009760 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009760 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.009760 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009760 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.009760 # miss rate for overall accesses
-system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks 523278 # number of writebacks
-system.cpu1.icache.writebacks::total 523278 # number of writebacks
-system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
-system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
-system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.tags.replacements 45622 # number of replacements
-system.cpu1.l2cache.tags.tagsinuse 14812.583642 # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs 612745 # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs 60182 # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs 10.181533 # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 14808.341040 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.229622 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.012979 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks 0.903829 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000136 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total 0.904088 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14538 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1592 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8923 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4023 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001343 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.887329 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses 25046700 # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses 25046700 # Number of data accesses
-system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3523 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1897 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total 5420 # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks 120664 # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total 120664 # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks 583352 # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total 583352 # number of WritebackClean hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19842 # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total 19842 # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 502374 # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total 502374 # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 97505 # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total 97505 # number of ReadSharedReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3523 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1897 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst 502374 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data 117347 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total 625141 # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3523 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1897 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst 502374 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data 117347 # number of overall hits
-system.cpu1.l2cache.overall_hits::total 625141 # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 442 # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 294 # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total 736 # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28867 # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total 28867 # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22523 # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total 22523 # number of SCUpgradeReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43773 # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total 43773 # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21416 # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total 21416 # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 75102 # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total 75102 # number of ReadSharedReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 442 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker 294 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst 21416 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data 118875 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total 141027 # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 442 # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker 294 # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst 21416 # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data 118875 # number of overall misses
-system.cpu1.l2cache.overall_misses::total 141027 # number of overall misses
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3965 # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2191 # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total 6156 # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::writebacks 120664 # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::total 120664 # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::writebacks 583352 # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::total 583352 # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28867 # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total 28867 # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22523 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total 22523 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523790 # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total 523790 # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172607 # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total 172607 # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3965 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2191 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst 523790 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data 236222 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total 766168 # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3965 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2191 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst 523790 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data 236222 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total 766168 # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.111475 # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.134185 # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total 0.119558 # miss rate for ReadReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688092 # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688092 # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.040887 # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.040887 # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.435104 # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.435104 # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.111475 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.134185 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.040887 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.503234 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total 0.184068 # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.111475 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.134185 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.040887 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.503234 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total 0.184068 # miss rate for overall accesses
-system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.l2cache.writebacks::writebacks 32251 # number of writebacks
-system.cpu1.l2cache.writebacks::total 32251 # number of writebacks
-system.cpu1.toL2Bus.snoop_filter.tot_requests 1533131 # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773122 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11161 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops 97486 # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 90800 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 6686 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.cpu1.toL2Bus.trans_dist::ReadReq 12749 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 709146 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 2504 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 2504 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty 120664 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean 594513 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 28867 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22523 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 51390 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523790 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172607 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571212 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778579 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 2368487 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 67013060 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27418918 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 94469370 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 297967 # Total snoops (count)
-system.cpu1.toL2Bus.snoopTraffic 2396032 # Total snoop traffic (bytes)
-system.cpu1.toL2Bus.snoop_fanout::samples 1770091 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 0.075165 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.277614 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 1643728 92.86% 92.86% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 119677 6.76% 99.62% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 6686 0.38% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 1770091 # Request fanout histogram
-system.iobus.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq 30995 # Transaction distribution
-system.iobus.trans_dist::ReadResp 30995 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59419 # Transaction distribution
-system.iobus.trans_dist::WriteResp 59419 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 107876 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 180828 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71526 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements 36442 # number of replacements
-system.iocache.tags.tagsinuse 14.586087 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 246641129509 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide 14.586087 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 328284 # Number of tag accesses
-system.iocache.tags.data_accesses 328284 # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
-system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses
-system.iocache.demand_misses::total 36476 # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide 36476 # number of overall misses
-system.iocache.overall_misses::total 36476 # number of overall misses
-system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks 36190 # number of writebacks
-system.iocache.writebacks::total 36190 # number of writebacks
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements 135222 # number of replacements
-system.l2c.tags.tagsinuse 65177.722092 # Cycle average of tags in use
-system.l2c.tags.total_refs 431767 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 200667 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 2.151659 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 86559025000 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 6644.063591 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.937413 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 0.032742 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 7087.775672 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 43017.281235 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001947 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 1645.603615 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 6779.025879 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.101380 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.108151 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.656392 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.025110 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.103440 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.994533 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024 65438 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 446 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 15850 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 49136 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024 0.998505 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 5329877 # Number of tag accesses
-system.l2c.tags.data_accesses 5329877 # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks 225154 # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total 225154 # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0.data 10176 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 3291 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 13467 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 773 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 1151 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 1924 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 13542 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 2929 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 16471 # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 96 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker 62 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst 42312 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data 82718 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 38 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker 19 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst 18847 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data 12996 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total 157088 # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 96 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 62 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 42312 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 96260 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 38 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 19 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 18847 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 15925 # number of demand (read+write) hits
-system.l2c.demand_hits::total 173559 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 96 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 62 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 42312 # number of overall hits
-system.l2c.overall_hits::cpu0.data 96260 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 38 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 19 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 18847 # number of overall hits
-system.l2c.overall_hits::cpu1.data 15925 # number of overall hits
-system.l2c.overall_hits::total 173559 # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data 280 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 93 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 373 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data 35 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data 37 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 72 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 137052 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 15935 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 152987 # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 8 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst 17619 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data 12284 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst 2569 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data 1434 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total 33917 # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 17619 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 149336 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 2569 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 17369 # number of demand (read+write) misses
-system.l2c.demand_misses::total 186904 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
-system.l2c.overall_misses::cpu0.inst 17619 # number of overall misses
-system.l2c.overall_misses::cpu0.data 149336 # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 2569 # number of overall misses
-system.l2c.overall_misses::cpu1.data 17369 # number of overall misses
-system.l2c.overall_misses::total 186904 # number of overall misses
-system.l2c.WritebackDirty_accesses::writebacks 225154 # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total 225154 # number of WritebackDirty accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 10456 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 3384 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 13840 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data 808 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data 1188 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 1996 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 150594 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 18864 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 169458 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 104 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 64 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst 59931 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data 95002 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 38 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 20 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst 21416 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data 14430 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total 191005 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker 104 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker 64 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 59931 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 245596 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker 38 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker 20 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 21416 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 33294 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 360463 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker 104 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker 64 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 59931 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 245596 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker 38 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker 20 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 21416 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 33294 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 360463 # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.026779 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.027482 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.026951 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.043317 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.031145 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total 0.036072 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.910076 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.844731 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.902802 # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.076923 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.031250 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.293988 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.129303 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.050000 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.119957 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.099376 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total 0.177571 # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker 0.076923 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker 0.031250 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.293988 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.608056 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker 0.050000 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.119957 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.521686 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.518511 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker 0.076923 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.031250 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.293988 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.608056 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker 0.050000 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.119957 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.521686 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.518511 # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks 102433 # number of writebacks
-system.l2c.writebacks::total 102433 # number of writebacks
-system.membus.snoop_filter.tot_requests 459623 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 242074 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 539 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 43995 # Transaction distribution
-system.membus.trans_dist::ReadResp 78164 # Transaction distribution
-system.membus.trans_dist::WriteReq 30844 # Transaction distribution
-system.membus.trans_dist::WriteResp 30844 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 138623 # Transaction distribution
-system.membus.trans_dist::CleanEvict 11066 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 47127 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 39021 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 464 # Transaction distribution
-system.membus.trans_dist::ReadExReq 153374 # Transaction distribution
-system.membus.trans_dist::ReadExResp 152968 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 34169 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
-system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13468 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 602335 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 723713 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 833107 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26936 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18573064 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 18762834 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 21095122 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 534443 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.010413 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.101510 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 528878 98.96% 98.96% # Request fanout histogram
-system.membus.snoop_fanout::1 5565 1.04% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 534443 # Request fanout histogram
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
-system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
-system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
-system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
-system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
-system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
-system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests 899310 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 443343 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 166356 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 30515 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 29463 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 1052 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq 43999 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 337330 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 30844 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 30844 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 225154 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 65596 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 60575 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 40945 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 101520 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 213686 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 213686 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 293331 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1215242 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 442268 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 1657510 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36117688 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10987754 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 47105442 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 144217 # Total snoops (count)
-system.toL2Bus.snoopTraffic 6573440 # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples 1114653 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.328092 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.471525 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 749996 67.29% 67.29% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 363605 32.62% 99.91% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 1052 0.09% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 1114653 # Request fanout histogram
-
----------- End Simulation Statistics ----------
+++ /dev/null
-Booting Linux on physical CPU 0x0\r
-\rInitializing cgroup subsys cpuset\r
-\rLinux version 3.13.0-rc2 (tony@vamp) (gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4) ) #1 SMP PREEMPT Mon Oct 13 15:09:23 EDT 2014\r
-\rKernel was built at commit id ''\r
-\rCPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d\r
-\rCPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache\r
-\rMachine model: V2P-CA15\r
-\rbootconsole [earlycon0] enabled\r
-\rMemory policy: Data cache writealloc\r
-\rkdebugv2m: Following are test values to confirm proper working\r
-\rkdebugv2m: Ranges 42000000 0 \r
-\rkdebugv2m: Regs 30000000 1000000 \r
-\rkdebugv2m: Virtual-Reg f0000000 \r
-\rkdebugv2m: pci node addr_cells 3 \r
-\rkdebugv2m: pci node size_cells 2 \r
-\rkdebugv2m: motherboard addr_cells 2 \r
-\rOn node 0 totalpages: 65536\r
-\rfree_area_init_node: node 0, pgdat 8072dcc0, node_mem_map 8078f000\r
-\r Normal zone: 512 pages used for memmap\r
-\r Normal zone: 0 pages reserved\r
-\r Normal zone: 65536 pages, LIFO batch:15\r
-\rsched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns\r
-\rPERCPU: Embedded 8 pages/cpu @80996000 s11648 r8192 d12928 u32768\r
-\rpcpu-alloc: s11648 r8192 d12928 u32768 alloc=8*4096\r
-\rpcpu-alloc: [0] 0 [0] 1 \r
-\rBuilt 1 zonelists in Zone order, mobility grouping on. Total pages: 65024\r
-\rKernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
-\rPID hash table entries: 1024 (order: 0, 4096 bytes)\r
-\rDentry cache hash table entries: 32768 (order: 5, 131072 bytes)\r
-\rInode-cache hash table entries: 16384 (order: 4, 65536 bytes)\r
-\rMemory: 235656K/262144K available (5248K kernel code, 249K rwdata, 1540K rodata, 295K init, 368K bss, 26488K reserved, 0K highmem)\r
-\rVirtual kernel memory layout:\r
-\r vector : 0xffff0000 - 0xffff1000 ( 4 kB)\r
-\r fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)\r
-\r vmalloc : 0x90800000 - 0xff000000 (1768 MB)\r
-\r lowmem : 0x80000000 - 0x90000000 ( 256 MB)\r
-\r pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)\r
-\r modules : 0x7f000000 - 0x7fe00000 ( 14 MB)\r
-\r .text : 0x80008000 - 0x806a942c (6790 kB)\r
-\r .init : 0x806aa000 - 0x806f3d80 ( 296 kB)\r
-\r .data : 0x806f4000 - 0x80732754 ( 250 kB)\r
-\r .bss : 0x80732754 - 0x8078e9d8 ( 369 kB)\r
-\rSLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1\r
-\rPreemptible hierarchical RCU implementation.\r
-\r RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=2.\r
-\rNR_IRQS:16 nr_irqs:16 16\r
-\rArchitected cp15 timer(s) running at 25.16MHz (phys).\r
-\rsched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 2730666655744ns\r
-\rSwitching to timer-based delay loop\r
-\rConsole: colour dummy device 80x30\r
-\rCalibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-\rpid_max: default: 32768 minimum: 301\r
-\rMount-cache hash table entries: 512\r
-\rCPU: Testing write buffer coherency: ok\r
-\r/cpus/cpu@1 missing clock-frequency property\r
-\rCPU0: update cpu_power 1024\r
-\rCPU0: thread -1, cpu 0, socket 0, mpidr 80000000\r
-\rSetting up static identity map for 0x804fee68 - 0x804fee9c\r
-\rCPU1: Booted secondary processor\r
-\rCPU1: thread -1, cpu 1, socket 0, mpidr 80000001\r
-\rBrought up 2 CPUs\r
-\rSMP: Total of 2 processors activated.\r
-\rCPU: All CPU(s) started in SVC mode.\r
-\rVFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0\r
-\rNET: Registered protocol family 16\r
-\rDMA: preallocated 256 KiB pool for atomic coherent allocations\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/aaci@040000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/mmci@050000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-\rhw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 1\r
-\rhw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 1\r
-\rhw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 1\r
-\rhw-breakpoint: CPU 1 failed to disable vector catch\r
-\rhw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 0\r
-\rhw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 0\r
-\rhw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0\r
-\rSerial: AMBA PL011 UART driver\r
-\r1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-\rconsole [ttyAMA0] enabled\r
-console [ttyAMA0] enabled\r
-\rbootconsole [earlycon0] disabled\r
-bootconsole [earlycon0] disabled\r
-\rPCI host bridge to bus 0000:00\r
-pci_bus 0000:00: root bus resource [io 0x0000-0xffffffff]\r
-pci_bus 0000:00: root bus resource [mem 0x00000000-0xffffffff]\r
-pci_bus 0000:00: root bus resource [bus 00-ff]\r
-pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-PCI: bus0: Fast back to back transfers disabled\r
-pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-pci 0000:00:01.0: BAR 4: assigned [io 0x2f000000-0x2f00000f]\r
-pci 0000:00:01.0: BAR 0: assigned [io 0x2f000010-0x2f000017]\r
-pci 0000:00:01.0: BAR 2: assigned [io 0x2f000018-0x2f00001f]\r
-pci 0000:00:01.0: BAR 1: assigned [io 0x2f000020-0x2f000023]\r
-pci 0000:00:01.0: BAR 3: assigned [io 0x2f000024-0x2f000027]\r
-pci_bus 0000:00: resource 4 [io 0x0000-0xffffffff]\r
-pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff]\r
-PCI map irq: slot 0, pin 1, devslot 0, irq: 68\r
-PCI map irq: slot 1, pin 2, devslot 1, irq: 69\r
-bio: create slab <bio-0> at 0\r
-vgaarb: loaded\r
-SCSI subsystem initialized\r
-libata version 3.00 loaded.\r
-usbcore: registered new interface driver usbfs\r
-usbcore: registered new interface driver hub\r
-usbcore: registered new device driver usb\r
-pps_core: LinuxPPS API ver. 1 registered\r
-pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-PTP clock support registered\r
-Advanced Linux Sound Architecture Driver Initialized.\r
-Switched to clocksource arch_sys_counter\r
-NET: Registered protocol family 2\r
-TCP established hash table entries: 2048 (order: 1, 8192 bytes)\r
-TCP bind hash table entries: 2048 (order: 2, 16384 bytes)\r
-TCP: Hash tables configured (established 2048 bind 2048)\r
-TCP: reno registered\r
-UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-NET: Registered protocol family 1\r
-RPC: Registered named UNIX socket transport module.\r
-RPC: Registered udp transport module.\r
-RPC: Registered tcp transport module.\r
-RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-PCI: CLS 64 bytes, default 64\r
-hw perfevents: enabled with ARMv7_Cortex_A15 PMU driver, 1 counters available\r
-jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.\r
-msgmni has been set to 460\r
-io scheduler noop registered (default)\r
-brd: module loaded\r
-loop: module loaded\r
-ata_piix 0000:00:01.0: version 2.13\r
-PCI: enabling device 0000:00:01.0 (0040 -> 0041)\r
-scsi0 : ata_piix\r
-scsi1 : ata_piix\r
-ata1: PATA max UDMA/33 cmd 0x2f000010 ctl 0x2f000020 bmdma 0x2f000000 irq 69\r
-ata2: PATA max UDMA/33 cmd 0x2f000018 ctl 0x2f000024 bmdma 0x2f000008 irq 69\r
-e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI\r
-e100: Copyright(c) 1999-2006 Intel Corporation\r
-e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-PCI: enabling device 0000:00:00.0 (0040 -> 0042)\r
-ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-ata1.00: 1048320 sectors, multi 0: LBA \r
-ata1.00: configured for UDMA/33\r
-scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)\r
-sd 0:0:0:0: [sda] Write Protect is off\r
-sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-sd 0:0:0:0: Attached scsi generic sg0 type 0\r
- sda: sda1\r
-sd 0:0:0:0: [sda] Attached SCSI disk\r
-e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-e1000e: Copyright(c) 1999 - 2013 Intel Corporation.\r
-igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-igb: Copyright (c) 2007-2013 Intel Corporation.\r
-igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.0.2-k\r
-igbvf: Copyright (c) 2009 - 2012 Intel Corporation.\r
-ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver - version 3.15.1-k\r
-ixgbe: Copyright (c) 1999-2013 Intel Corporation.\r
-ixgbevf: Intel(R) 10 Gigabit PCI Express Virtual Function Network Driver - version 2.11.3-k\r
-ixgbevf: Copyright (c) 2009 - 2012 Intel Corporation.\r
-ixgb: Intel(R) PRO/10GbE Network Driver - version 1.0.135-k2-NAPI\r
-ixgb: Copyright (c) 1999-2008 Intel Corporation.\r
-smsc911x: Driver version 2008-10-21\r
-smsc911x 1a000000.ethernet (unregistered net_device): couldn't get clock -2\r
-nxp-isp1760 1b000000.usb: NXP ISP1760 USB Host Controller\r
-nxp-isp1760 1b000000.usb: new USB bus registered, assigned bus number 1\r
-nxp-isp1760 1b000000.usb: Scratch test failed.\r
-nxp-isp1760 1b000000.usb: can't setup: -19\r
-nxp-isp1760 1b000000.usb: USB bus 1 deregistered\r
-usbcore: registered new interface driver usb-storage\r
-mousedev: PS/2 mouse device common for all mice\r
-rtc-pl031 1c170000.rtc: rtc core: registered pl031 as rtc0\r
-usbcore: registered new interface driver usbhid\r
-usbhid: USB HID core driver\r
-ashmem: initialized\r
-logger: created 256K log 'log_main'\r
-logger: created 256K log 'log_events'\r
-logger: created 256K log 'log_radio'\r
-logger: created 256K log 'log_system'\r
-oprofile: using timer interrupt.\r
-TCP: cubic registered\r
-NET: Registered protocol family 10\r
-NET: Registered protocol family 17\r
-rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 00:00:00 UTC (1230768000)\r
-ALSA device list:\r
- No soundcards found.\r
-\0input: AT Raw Set 2 keyboard as /devices/smb.14/motherboard.15/iofpga.17/1c060000.kmi/serio0/input/input0\r
-input: touchkitPS/2 eGalax Touchscreen as /devices/smb.14/motherboard.15/iofpga.17/1c070000.kmi/serio1/input/input2\r
-VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-Freeing unused kernel memory: 292K (806aa000 - 806f3000)\r
-\rinit started: BusyBox v1.15.3 (2010-05-07 01:27:07 BST)\r
-\rstarting pid 680, tty '': '/etc/rc.d/rc.local'\r
-warning: can't open /etc/mtab: No such file or directory\r
-Thu Jan 1 00:00:02 UTC 2009\r
-S: devpts\r
-Thu Jan 1 00:00:02 UTC 2009\r
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
-atags_addr=134217728
-boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
-early_kernel_symbols=false
-enable_context_switch_stats_dump=false
-eventq_index=0
-exit_on_work_items=false
-flags_addr=469827632
-gic_cpu_addr=738205696
-have_large_asid_64=false
-have_lpae=true
-have_security=false
-have_virtualization=false
-highest_el_is_64=false
-init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
-kernel_addr_check=true
-load_addr_mask=268435455
-load_offset=2147483648
-machine_type=VExpress_EMM
-mem_mode=atomic
-mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.nvmem system.realview.vram
-mmap_using_noreserve=false
-multi_proc=true
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-panic_on_oops=true
-panic_on_panic=true
-phys_addr_range_64=40
-power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
-reset_addr_64=0
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img
-read_only=true
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=2147483648:2415919103
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[3]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=50
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=Null
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=2147483648:2415919103
-port=system.membus.master[5]
-
-[system.realview]
-type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470024192
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[18]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=471465984
-BAR0LegacyIO=true
-BAR0Size=256
-BAR1=471466240
-BAR1LegacyIO=true
-BAR1Size=4096
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=2
-default_p_state=UNDEFINED
-disks=
-eventq_index=0
-host=system.realview.pci_host
-io_shift=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=2
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[2]
-pio=system.iobus.master[9]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=46
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471793664
-pio_latency=10000
-pixel_clock=41667
-power_model=Null
-system=system
-vnc=system.vncserver
-dma=system.iobus.slave[1]
-pio=system.iobus.master[5]
-
-[system.realview.dcc]
-type=SubSystem
-children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.dcc.osc_cpu]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_ddr]
-type=RealViewOsc
-dcc=0
-device=8
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_hsbm]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_pxl]
-type=RealViewOsc
-dcc=0
-device=5
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_smb]
-type=RealViewOsc
-dcc=0
-device=6
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_sys]
-type=RealViewOsc
-dcc=0
-device=7
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.energy_ctrl]
-type=EnergyCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dvfs_handler=system.dvfs_handler
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470286336
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[22]
-
-[system.realview.ethernet]
-type=IGbE
-BAR0=0
-BAR0LegacyIO=false
-BAR0Size=131072
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=0
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=4213
-ExpansionROM=0
-HeaderType=0
-InterruptLine=1
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=255
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=0
-SubClassCode=0
-SubsystemID=4104
-SubsystemVendorID=32902
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-eventq_index=0
-fetch_comp_delay=10000
-fetch_delay=10000
-hardware_address=00:90:00:00:00:01
-host=system.realview.pci_host
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-phy_epid=896
-phy_pid=680
-pio_latency=30000
-power_model=Null
-rx_desc_cache_size=64
-rx_fifo_size=393216
-rx_write_delay=0
-system=system
-tx_desc_cache_size=64
-tx_fifo_size=393216
-tx_read_delay=0
-wb_comp_delay=10000
-wb_delay=10000
-dma=system.iobus.slave[4]
-pio=system.iobus.master[24]
-
-[system.realview.generic_timer]
-type=GenericTimer
-eventq_index=0
-gic=system.realview.gic
-int_phys=29
-int_virt=27
-system=system
-
-[system.realview.gic]
-type=Pl390
-clk_domain=system.clk_domain
-cpu_addr=738205696
-cpu_pio_delay=10000
-default_p_state=UNDEFINED
-dist_addr=738201600
-dist_pio_delay=10000
-eventq_index=0
-gem5_extensions=true
-int_latency=10000
-it_lines=128
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-platform=system.realview
-power_model=Null
-system=system
-pio=system.membus.master[2]
-
-[system.realview.hdlcd]
-type=HDLcd
-amba_id=1314816
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=117
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=721420288
-pio_latency=10000
-pixel_buffer_size=2048
-pixel_chunk=32
-power_model=Null
-pxl_clk=system.realview.dcc.osc_pxl
-system=system
-vnc=system.vncserver
-workaround_dma_line_count=true
-workaround_swap_rb=true
-dma=system.membus.slave[0]
-pio=system.iobus.master[6]
-
-[system.realview.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=2
-InterruptPin=2
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.cf0
-eventq_index=0
-host=system.realview.pci_host
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[3]
-pio=system.iobus.master[23]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=44
-is_mouse=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470155264
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[7]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=45
-is_mouse=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470220800
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[8]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=739246080
-pio_latency=100000
-pio_size=4095
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.realview.lan_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=436207616
-pio_latency=100000
-pio_size=65535
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=738721792
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.membus.master[4]
-
-[system.realview.mcc]
-type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.mcc.osc_clcd]
-type=RealViewOsc
-dcc=0
-device=1
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_mcc]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_peripheral]
-type=RealViewOsc
-dcc=0
-device=2
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_system_bus]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.temp_crtl]
-type=RealViewTemperatureSensor
-dcc=0
-device=0
-eventq_index=0
-parent=system.realview.realview_io
-position=0
-site=0
-system=system
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470089728
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.realview.nvmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:67108863
-port=system.membus.master[1]
-
-[system.realview.pci_host]
-type=GenericPciHost
-clk_domain=system.clk_domain
-conf_base=805306368
-conf_device_bits=16
-conf_size=268435456
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=0
-pci_pio_base=0
-platform=system.realview
-power_model=Null
-system=system
-pio=system.iobus.master[2]
-
-[system.realview.realview_io]
-type=RealViewCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-idreg=35979264
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469827584
-pio_latency=100000
-power_model=Null
-proc_id0=335544320
-proc_id1=335544320
-system=system
-pio=system.iobus.master[1]
-
-[system.realview.rtc]
-type=PL031
-amba_id=3412017
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=36
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471269376
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[10]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469893120
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=34
-int_num1=34
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470876160
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[3]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=35
-int_num1=35
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470941696
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[4]
-
-[system.realview.uart]
-type=Pl011
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-end_on_eot=false
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=37
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470351872
-pio_latency=100000
-platform=system.realview
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[0]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470417408
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470482944
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470548480
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[15]
-
-[system.realview.usb_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=452984832
-pio_latency=100000
-pio_size=131071
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.realview.vgic]
-type=VGic
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-hv_addr=738213888
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_delay=10000
-platform=system.realview
-power_model=Null
-ppint=25
-system=system
-vcpu_addr=738222080
-pio=system.membus.master[3]
-
-[system.realview.vram]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=402653184:436207615
-port=system.iobus.master[11]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470745088
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[17]
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.vncserver]
-type=VncServer
-eventq_index=0
-frame_capture=false
-number=0
-port=5900
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
-warn: Not doing anything for miscreg ACTLR
-warn: Not doing anything for write of miscreg ACTLR
-warn: The clidr register always reports 0 caches.
-warn: clidr LoUIS field of 0b001 to match current ARM implementations.
-warn: The csselr register isn't implemented.
-warn: instruction 'mcr dccmvau' unimplemented
-warn: instruction 'mcr icimvau' unimplemented
-warn: instruction 'mcr bpiallis' unimplemented
-warn: instruction 'mcr icialluis' unimplemented
-warn: instruction 'mcr dccimvac' unimplemented
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
-warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
-warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
-warn: Returning zero for read from miscreg pmcr
-warn: Ignoring write to miscreg pmcntenclr
-warn: Ignoring write to miscreg pmintenclr
-warn: Ignoring write to miscreg pmovsr
-warn: Ignoring write to miscreg pmcr
+++ /dev/null
-Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Aug 1 2016 17:10:05
-gem5 started Aug 1 2016 17:10:34
-gem5 executing on e108600-lin, pid 12206
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
-
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
-info: Using bootloader at address 0x10
-info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
-info: Entering event queue @ 0. Starting simulation...
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2783855034000 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 2.783856 # Number of seconds simulated
-sim_ticks 2783855588000 # Number of ticks simulated
-final_tick 2783855588000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1539062 # Simulator instruction rate (inst/s)
-host_op_rate 1873561 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 30009675812 # Simulator tick rate (ticks/s)
-host_mem_usage 581968 # Number of bytes of host memory used
-host_seconds 92.77 # Real time elapsed on the host
-sim_insts 142771499 # Number of instructions simulated
-sim_ops 173801409 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10324900 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11533448 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8840896 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8858420 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 161846 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 189183 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 138139 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 142520 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 433576 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3708849 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4142976 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 433576 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3175774 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3182069 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3175774 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 433576 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3715144 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7325045 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 10028 # Table walker walks requested
-system.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0 10028 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 10028 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 6353 80.79% 80.79% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 7864 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10028 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10028 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7864 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 31525952 # DTB read hits
-system.cpu.dtb.read_misses 8580 # DTB read misses
-system.cpu.dtb.write_hits 23124113 # DTB write hits
-system.cpu.dtb.write_misses 1448 # DTB write misses
-system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 4285 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 31534532 # DTB read accesses
-system.cpu.dtb.write_accesses 23125561 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 54650065 # DTB hits
-system.cpu.dtb.misses 10028 # DTB misses
-system.cpu.dtb.accesses 54660093 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 4762 # Table walker walks requested
-system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 147038008 # ITB inst hits
-system.cpu.itb.inst_misses 4762 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 147042770 # ITB inst accesses
-system.cpu.itb.hits 147038008 # DTB hits
-system.cpu.itb.misses 4762 # DTB misses
-system.cpu.itb.accesses 147042770 # DTB accesses
-system.cpu.numPwrStateTransitions 6160 # Number of power state transitions
-system.cpu.pwrStateClkGateDist::samples 3080 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean 874939855.098377 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev 17329944394.226795 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::underflows 3002 97.47% 97.47% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10 72 2.34% 99.81% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::max_value 499984036900 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::total 3080 # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON 89040834297 # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 2694814753703 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 5567714257 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed
-system.cpu.committedInsts 142771499 # Number of instructions committed
-system.cpu.committedOps 173801409 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 153161120 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses
-system.cpu.num_func_calls 16873932 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 18730256 # number of instructions that are conditional controls
-system.cpu.num_int_insts 153161120 # number of integer instructions
-system.cpu.num_fp_insts 11484 # number of float instructions
-system.cpu.num_int_register_reads 285043874 # number of times the integer registers were read
-system.cpu.num_int_register_writes 107178310 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 530848973 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 62363815 # number of times the CC registers were written
-system.cpu.num_mem_refs 55938612 # number of memory refs
-system.cpu.num_load_insts 31855576 # Number of load instructions
-system.cpu.num_store_insts 24083036 # Number of store instructions
-system.cpu.num_idle_cycles 5389632489.859149 # Number of idle cycles
-system.cpu.num_busy_cycles 178081767.140850 # Number of busy cycles
-system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.968015 # Percentage of idle cycles
-system.cpu.Branches 36396926 # Number of branches fetched
-system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 121151851 68.36% 68.36% # Class of executed instruction
-system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 68.43% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 68.43% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 68.43% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 68.43% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 68.43% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 68.43% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 68.43% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 68.43% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 68.43% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 68.43% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 68.43% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 68.43% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 68.43% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 68.43% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 68.43% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 68.43% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 68.43% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 68.43% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 68.43% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 68.43% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 68.43% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 68.43% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction
-system.cpu.op_class::MemRead 31852868 17.97% 86.41% # Class of executed instruction
-system.cpu.op_class::MemWrite 24074264 13.58% 99.99% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 2708 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 8772 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 177218242 # Class of executed instruction
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-system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 53783890 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 819896 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 65.598430 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
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-system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
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-system.cpu.dcache.tags.data_accesses 219235120 # Number of data accesses
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-system.cpu.dcache.ReadReq_hits::total 30128814 # number of ReadReq hits
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-system.cpu.dcache.WriteReq_hits::total 22339797 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 395067 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 395067 # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 457333 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 457333 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 52468611 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 52468611 # number of demand (read+write) hits
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-system.cpu.dcache.overall_hits::total 52863678 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 396270 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 396270 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 301666 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 301666 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 116119 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 116119 # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses
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-system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
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-system.cpu.dcache.demand_misses::total 697936 # number of demand (read+write) misses
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-system.cpu.dcache.overall_misses::total 814055 # number of overall misses
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-system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses)
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-system.cpu.dcache.demand_accesses::total 53166547 # number of demand (read+write) accesses
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-system.cpu.dcache.overall_accesses::total 53677733 # number of overall (read+write) accesses
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-system.cpu.dcache.SoftPFReq_miss_rate::total 0.227156 # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018483 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018483 # miss rate for LoadLockedReq accesses
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-system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
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-system.cpu.dcache.demand_miss_rate::total 0.013127 # miss rate for demand accesses
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-system.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses
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-system.cpu.dcache.writebacks::total 682141 # number of writebacks
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-system.cpu.icache.tags.replacements 1698986 # number of replacements
-system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use
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-system.cpu.icache.tags.avg_refs 85.520319 # Average number of references to valid blocks.
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-system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id
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-system.cpu.icache.demand_hits::total 145341611 # number of demand (read+write) hits
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-system.cpu.icache.overall_hits::total 145341611 # number of overall hits
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-system.cpu.icache.ReadReq_misses::total 1699504 # number of ReadReq misses
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-system.cpu.icache.demand_misses::total 1699504 # number of demand (read+write) misses
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-system.cpu.icache.overall_misses::total 1699504 # number of overall misses
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-system.cpu.icache.writebacks::total 1698986 # number of writebacks
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-system.cpu.l2cache.tags.replacements 109914 # number of replacements
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-system.cpu.l2cache.tags.sampled_refs 175340 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 27.533233 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 71491095000 # Cycle when the warmup percentage was hit.
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-system.cpu.l2cache.tags.occ_blocks::cpu.inst 9170.133245 # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.occ_task_id_blocks::1024 65421 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9745 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55480 # Occupied blocks per task id
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-system.cpu.l2cache.ReadReq_hits::total 8385 # number of ReadReq hits
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-system.cpu.l2cache.WritebackDirty_hits::total 682141 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks 1666986 # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total 1666986 # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 2746 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 2746 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 152792 # number of ReadExReq hits
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-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681189 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total 1681189 # number of ReadCleanReq hits
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-system.cpu.l2cache.demand_hits::cpu.inst 1681189 # number of demand (read+write) hits
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-system.cpu.l2cache.overall_hits::cpu.inst 1681189 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 658225 # number of overall hits
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-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 18298 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses
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-system.cpu.l2cache.WritebackClean_accesses::total 1666986 # number of WritebackClean accesses(hits+misses)
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-system.cpu.l2cache.overall_accesses::cpu.inst 1699487 # number of overall (read+write) accesses
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-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010767 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029881 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029881 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001233 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000736 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010767 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.197200 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.071206 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001233 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000736 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010767 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.197200 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.071206 # miss rate for overall accesses
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks
-system.cpu.l2cache.writebacks::total 101949 # number of writebacks
-system.cpu.toL2Bus.snoop_filter.tot_requests 5059862 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540459 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39267 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 427 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 427 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq 67800 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2288305 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 682141 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 1698986 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 137243 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2757 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 298911 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 298911 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699504 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 521001 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116038 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581944 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 7753408 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217539448 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96314145 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 313964445 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 115353 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 6542464 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 5251071 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.018719 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.135530 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 5152778 98.13% 98.13% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 98293 1.87% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 5251071 # Request fanout histogram
-system.iobus.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
-system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
-system.iobus.trans_dist::WriteResp 59002 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements 36430 # number of replacements
-system.iocache.tags.tagsinuse 0.909895 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 227410176509 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide 0.909895 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 328176 # Number of tag accesses
-system.iocache.tags.data_accesses 328176 # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 240 # number of ReadReq misses
-system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide 36464 # number of demand (read+write) misses
-system.iocache.demand_misses::total 36464 # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide 36464 # number of overall misses
-system.iocache.overall_misses::total 36464 # number of overall misses
-system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide 36464 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 36464 # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide 36464 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 36464 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks 36190 # number of writebacks
-system.iocache.writebacks::total 36190 # number of writebacks
-system.membus.snoop_filter.tot_requests 362813 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 151005 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 526 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 40087 # Transaction distribution
-system.membus.trans_dist::ReadResp 74202 # Transaction distribution
-system.membus.trans_dist::WriteReq 27546 # Transaction distribution
-system.membus.trans_dist::WriteResp 27546 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution
-system.membus.trans_dist::CleanEvict 8205 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 130 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
-system.membus.trans_dist::ReadExReq 145998 # Transaction distribution
-system.membus.trans_dist::ReadExResp 145998 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 34115 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
-system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 497830 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 605190 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 714548 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092476 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255449 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 20586969 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 430446 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.012887 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.112786 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 424899 98.71% 98.71% # Request fanout histogram
-system.membus.snoop_fanout::1 5547 1.29% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 430446 # Request fanout histogram
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
-system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
-system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
-system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
-system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
-system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
-system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
-system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
-
----------- End Simulation Statistics ----------
+++ /dev/null
-Booting Linux on physical CPU 0x0\r
-\rInitializing cgroup subsys cpuset\r
-\rLinux version 3.13.0-rc2 (tony@vamp) (gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4) ) #1 SMP PREEMPT Mon Oct 13 15:09:23 EDT 2014\r
-\rKernel was built at commit id ''\r
-\rCPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d\r
-\rCPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache\r
-\rMachine model: V2P-CA15\r
-\rbootconsole [earlycon0] enabled\r
-\rMemory policy: Data cache writealloc\r
-\rkdebugv2m: Following are test values to confirm proper working\r
-\rkdebugv2m: Ranges 42000000 0 \r
-\rkdebugv2m: Regs 30000000 1000000 \r
-\rkdebugv2m: Virtual-Reg f0000000 \r
-\rkdebugv2m: pci node addr_cells 3 \r
-\rkdebugv2m: pci node size_cells 2 \r
-\rkdebugv2m: motherboard addr_cells 2 \r
-\rOn node 0 totalpages: 65536\r
-\rfree_area_init_node: node 0, pgdat 8072dcc0, node_mem_map 8078f000\r
-\r Normal zone: 512 pages used for memmap\r
-\r Normal zone: 0 pages reserved\r
-\r Normal zone: 65536 pages, LIFO batch:15\r
-\rsched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns\r
-\rPERCPU: Embedded 8 pages/cpu @80996000 s11648 r8192 d12928 u32768\r
-\rpcpu-alloc: s11648 r8192 d12928 u32768 alloc=8*4096\r
-\rpcpu-alloc: [0] 0 \r
-\rBuilt 1 zonelists in Zone order, mobility grouping on. Total pages: 65024\r
-\rKernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
-\rPID hash table entries: 1024 (order: 0, 4096 bytes)\r
-\rDentry cache hash table entries: 32768 (order: 5, 131072 bytes)\r
-\rInode-cache hash table entries: 16384 (order: 4, 65536 bytes)\r
-\rMemory: 235688K/262144K available (5248K kernel code, 249K rwdata, 1540K rodata, 295K init, 368K bss, 26456K reserved, 0K highmem)\r
-\rVirtual kernel memory layout:\r
-\r vector : 0xffff0000 - 0xffff1000 ( 4 kB)\r
-\r fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)\r
-\r vmalloc : 0x90800000 - 0xff000000 (1768 MB)\r
-\r lowmem : 0x80000000 - 0x90000000 ( 256 MB)\r
-\r pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)\r
-\r modules : 0x7f000000 - 0x7fe00000 ( 14 MB)\r
-\r .text : 0x80008000 - 0x806a942c (6790 kB)\r
-\r .init : 0x806aa000 - 0x806f3d80 ( 296 kB)\r
-\r .data : 0x806f4000 - 0x80732754 ( 250 kB)\r
-\r .bss : 0x80732754 - 0x8078e9d8 ( 369 kB)\r
-\rSLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1\r
-\rPreemptible hierarchical RCU implementation.\r
-\r RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1.\r
-\rNR_IRQS:16 nr_irqs:16 16\r
-\rArchitected cp15 timer(s) running at 25.16MHz (phys).\r
-\rsched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 2730666655744ns\r
-\rSwitching to timer-based delay loop\r
-\rConsole: colour dummy device 80x30\r
-\rCalibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-\rpid_max: default: 32768 minimum: 301\r
-\rMount-cache hash table entries: 512\r
-\rCPU: Testing write buffer coherency: ok\r
-\rCPU0: update cpu_power 1024\r
-\rCPU0: thread -1, cpu 0, socket 0, mpidr 80000000\r
-\rSetting up static identity map for 0x804fee68 - 0x804fee9c\r
-\rBrought up 1 CPUs\r
-\rSMP: Total of 1 processors activated.\r
-\rCPU: All CPU(s) started in SVC mode.\r
-\rVFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0\r
-\rNET: Registered protocol family 16\r
-\rDMA: preallocated 256 KiB pool for atomic coherent allocations\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/aaci@040000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/mmci@050000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-\rhw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 0\r
-\rhw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 0\r
-\rhw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0\r
-\rhw-breakpoint: CPU 0 failed to disable vector catch\r
-\rSerial: AMBA PL011 UART driver\r
-\r1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-\rconsole [ttyAMA0] enabled\r
-console [ttyAMA0] enabled\r
-\rbootconsole [earlycon0] disabled\r
-bootconsole [earlycon0] disabled\r
-\rPCI host bridge to bus 0000:00\r
-pci_bus 0000:00: root bus resource [io 0x0000-0xffffffff]\r
-pci_bus 0000:00: root bus resource [mem 0x00000000-0xffffffff]\r
-pci_bus 0000:00: root bus resource [bus 00-ff]\r
-pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-PCI: bus0: Fast back to back transfers disabled\r
-pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-pci 0000:00:01.0: BAR 4: assigned [io 0x2f000000-0x2f00000f]\r
-pci 0000:00:01.0: BAR 0: assigned [io 0x2f000010-0x2f000017]\r
-pci 0000:00:01.0: BAR 2: assigned [io 0x2f000018-0x2f00001f]\r
-pci 0000:00:01.0: BAR 1: assigned [io 0x2f000020-0x2f000023]\r
-pci 0000:00:01.0: BAR 3: assigned [io 0x2f000024-0x2f000027]\r
-pci_bus 0000:00: resource 4 [io 0x0000-0xffffffff]\r
-pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff]\r
-PCI map irq: slot 0, pin 1, devslot 0, irq: 68\r
-PCI map irq: slot 1, pin 2, devslot 1, irq: 69\r
-bio: create slab <bio-0> at 0\r
-vgaarb: loaded\r
-SCSI subsystem initialized\r
-libata version 3.00 loaded.\r
-usbcore: registered new interface driver usbfs\r
-usbcore: registered new interface driver hub\r
-usbcore: registered new device driver usb\r
-pps_core: LinuxPPS API ver. 1 registered\r
-pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-PTP clock support registered\r
-Advanced Linux Sound Architecture Driver Initialized.\r
-Switched to clocksource arch_sys_counter\r
-NET: Registered protocol family 2\r
-TCP established hash table entries: 2048 (order: 1, 8192 bytes)\r
-TCP bind hash table entries: 2048 (order: 2, 16384 bytes)\r
-TCP: Hash tables configured (established 2048 bind 2048)\r
-TCP: reno registered\r
-UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-NET: Registered protocol family 1\r
-RPC: Registered named UNIX socket transport module.\r
-RPC: Registered udp transport module.\r
-RPC: Registered tcp transport module.\r
-RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-PCI: CLS 64 bytes, default 64\r
-hw perfevents: enabled with ARMv7_Cortex_A15 PMU driver, 1 counters available\r
-jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.\r
-msgmni has been set to 460\r
-io scheduler noop registered (default)\r
-brd: module loaded\r
-loop: module loaded\r
-ata_piix 0000:00:01.0: version 2.13\r
-PCI: enabling device 0000:00:01.0 (0040 -> 0041)\r
-scsi0 : ata_piix\r
-scsi1 : ata_piix\r
-ata1: PATA max UDMA/33 cmd 0x2f000010 ctl 0x2f000020 bmdma 0x2f000000 irq 69\r
-ata2: PATA max UDMA/33 cmd 0x2f000018 ctl 0x2f000024 bmdma 0x2f000008 irq 69\r
-e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI\r
-e100: Copyright(c) 1999-2006 Intel Corporation\r
-e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-PCI: enabling device 0000:00:00.0 (0040 -> 0042)\r
-ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-ata1.00: 1048320 sectors, multi 0: LBA \r
-ata1.00: configured for UDMA/33\r
-scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)\r
-sd 0:0:0:0: [sda] Write Protect is off\r
-sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
- sda: sda1\r
-sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-sd 0:0:0:0: [sda] Attached SCSI disk\r
-e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-e1000e: Copyright(c) 1999 - 2013 Intel Corporation.\r
-igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-igb: Copyright (c) 2007-2013 Intel Corporation.\r
-igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.0.2-k\r
-igbvf: Copyright (c) 2009 - 2012 Intel Corporation.\r
-ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver - version 3.15.1-k\r
-ixgbe: Copyright (c) 1999-2013 Intel Corporation.\r
-ixgbevf: Intel(R) 10 Gigabit PCI Express Virtual Function Network Driver - version 2.11.3-k\r
-ixgbevf: Copyright (c) 2009 - 2012 Intel Corporation.\r
-ixgb: Intel(R) PRO/10GbE Network Driver - version 1.0.135-k2-NAPI\r
-ixgb: Copyright (c) 1999-2008 Intel Corporation.\r
-smsc911x: Driver version 2008-10-21\r
-smsc911x 1a000000.ethernet (unregistered net_device): couldn't get clock -2\r
-nxp-isp1760 1b000000.usb: NXP ISP1760 USB Host Controller\r
-nxp-isp1760 1b000000.usb: new USB bus registered, assigned bus number 1\r
-nxp-isp1760 1b000000.usb: Scratch test failed.\r
-nxp-isp1760 1b000000.usb: can't setup: -19\r
-nxp-isp1760 1b000000.usb: USB bus 1 deregistered\r
-usbcore: registered new interface driver usb-storage\r
-mousedev: PS/2 mouse device common for all mice\r
-rtc-pl031 1c170000.rtc: rtc core: registered pl031 as rtc0\r
-usbcore: registered new interface driver usbhid\r
-usbhid: USB HID core driver\r
-ashmem: initialized\r
-logger: created 256K log 'log_main'\r
-logger: created 256K log 'log_events'\r
-logger: created 256K log 'log_radio'\r
-logger: created 256K log 'log_system'\r
-oprofile: using timer interrupt.\r
-TCP: cubic registered\r
-NET: Registered protocol family 10\r
-NET: Registered protocol family 17\r
-rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 00:00:00 UTC (1230768000)\r
-ALSA device list:\r
- No soundcards found.\r
-\0input: AT Raw Set 2 keyboard as /devices/smb.14/motherboard.15/iofpga.17/1c060000.kmi/serio0/input/input0\r
-input: touchkitPS/2 eGalax Touchscreen as /devices/smb.14/motherboard.15/iofpga.17/1c070000.kmi/serio1/input/input2\r
-VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-Freeing unused kernel memory: 292K (806aa000 - 806f3000)\r
-\rinit started: BusyBox v1.15.3 (2010-05-07 01:27:07 BST)\r
-\rstarting pid 673, tty '': '/etc/rc.d/rc.local'\r
-warning: can't open /etc/mtab: No such file or directory\r
-Thu Jan 1 00:00:02 UTC 2009\r
-S: devpts\r
-Thu Jan 1 00:00:02 UTC 2009\r
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
-atags_addr=134217728
-boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
-early_kernel_symbols=false
-enable_context_switch_stats_dump=false
-eventq_index=0
-exit_on_work_items=false
-flags_addr=469827632
-gic_cpu_addr=738205696
-have_large_asid_64=false
-have_lpae=true
-have_security=false
-have_virtualization=false
-highest_el_is_64=false
-init_param=0
-kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
-kernel_addr_check=true
-load_addr_mask=268435455
-load_offset=2147483648
-machine_type=VExpress_EMM
-mem_mode=timing
-mem_ranges=2147483648:2415919103:0:0:0:0
-memories=system.physmem system.realview.nvmem system.realview.vram
-mmap_using_noreserve=false
-multi_proc=true
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-panic_on_oops=true
-panic_on_panic=true
-phys_addr_range_64=40
-power_model=Null
-readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
-reset_addr_64=0
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img
-read_only=true
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=TimingSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu0.dstage2_mmu
-dtb=system.cpu0.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-istage2_mmu=system.cpu0.istage2_mmu
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu0.tracer
-workload=
-dcache_port=system.cpu0.dcache.cpu_side
-icache_port=system.cpu0.icache.cpu_side
-
-[system.cpu0.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=6
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tag_latency=2
-tags=system.cpu0.dcache.tags
-tgts_per_mshr=8
-write_buffers=16
-writeback_clean=true
-cpu_side=system.cpu0.dcache_port
-mem_side=system.cpu0.toL2Bus.slave[1]
-
-[system.cpu0.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-tag_latency=2
-
-[system.cpu0.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.dtb
-
-[system.cpu0.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu0.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu0.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.dtb.walker
-
-[system.cpu0.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu0.toL2Bus.slave[3]
-
-[system.cpu0.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=1
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=true
-max_miss_count=0
-mshrs=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=1
-sequential_access=false
-size=32768
-system=system
-tag_latency=1
-tags=system.cpu0.icache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu0.icache_port
-mem_side=system.cpu0.toL2Bus.slave[0]
-
-[system.cpu0.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=1
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-tag_latency=1
-
-[system.cpu0.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu0.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu0.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.itb
-
-[system.cpu0.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.istage2_mmu.stage2_tlb.walker
-
-[system.cpu0.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu0.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.itb.walker
-
-[system.cpu0.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu0.toL2Bus.slave[2]
-
-[system.cpu0.l2cache]
-type=Cache
-children=prefetcher tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=16
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_excl
-data_latency=12
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=true
-prefetcher=system.cpu0.l2cache.prefetcher
-response_latency=12
-sequential_access=false
-size=1048576
-system=system
-tag_latency=12
-tags=system.cpu0.l2cache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu0.toL2Bus.master[0]
-mem_side=system.toL2Bus.slave[0]
-
-[system.cpu0.l2cache.prefetcher]
-type=StridePrefetcher
-cache_snoop=false
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-degree=8
-eventq_index=0
-latency=1
-max_conf=7
-min_conf=0
-on_data=true
-on_inst=true
-on_miss=false
-on_read=true
-on_write=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-queue_filter=true
-queue_size=32
-queue_squash=true
-start_conf=4
-sys=system
-table_assoc=4
-table_sets=16
-tag_prefetch=true
-thresh_conf=4
-use_master_id=true
-
-[system.cpu0.l2cache.tags]
-type=RandomRepl
-assoc=16
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=12
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1048576
-tag_latency=12
-
-[system.cpu0.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu0.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu0.l2cache.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
-
-[system.cpu0.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu0.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu1]
-type=TimingSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu1.dstage2_mmu
-dtb=system.cpu1.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu1.interrupts
-isa=system.cpu1.isa
-istage2_mmu=system.cpu1.istage2_mmu
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu1.tracer
-workload=
-dcache_port=system.cpu1.dcache.cpu_side
-icache_port=system.cpu1.icache.cpu_side
-
-[system.cpu1.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=6
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tag_latency=2
-tags=system.cpu1.dcache.tags
-tgts_per_mshr=8
-write_buffers=16
-writeback_clean=true
-cpu_side=system.cpu1.dcache_port
-mem_side=system.cpu1.toL2Bus.slave[1]
-
-[system.cpu1.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-tag_latency=2
-
-[system.cpu1.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.dtb
-
-[system.cpu1.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu1.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.dtb.walker
-
-[system.cpu1.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu1.toL2Bus.slave[3]
-
-[system.cpu1.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=1
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=true
-max_miss_count=0
-mshrs=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=1
-sequential_access=false
-size=32768
-system=system
-tag_latency=1
-tags=system.cpu1.icache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu1.icache_port
-mem_side=system.cpu1.toL2Bus.slave[0]
-
-[system.cpu1.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=1
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-tag_latency=1
-
-[system.cpu1.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu1.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu1.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.itb
-
-[system.cpu1.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.istage2_mmu.stage2_tlb.walker
-
-[system.cpu1.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.itb.walker
-
-[system.cpu1.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu1.toL2Bus.slave[2]
-
-[system.cpu1.l2cache]
-type=Cache
-children=prefetcher tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=16
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_excl
-data_latency=12
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=true
-prefetcher=system.cpu1.l2cache.prefetcher
-response_latency=12
-sequential_access=false
-size=1048576
-system=system
-tag_latency=12
-tags=system.cpu1.l2cache.tags
-tgts_per_mshr=8
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu1.toL2Bus.master[0]
-mem_side=system.toL2Bus.slave[1]
-
-[system.cpu1.l2cache.prefetcher]
-type=StridePrefetcher
-cache_snoop=false
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-degree=8
-eventq_index=0
-latency=1
-max_conf=7
-min_conf=0
-on_data=true
-on_inst=true
-on_miss=false
-on_read=true
-on_write=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-queue_filter=true
-queue_size=32
-queue_squash=true
-start_conf=4
-sys=system
-table_assoc=4
-table_sets=16
-tag_prefetch=true
-thresh_conf=4
-use_master_id=true
-
-[system.cpu1.l2cache.tags]
-type=RandomRepl
-assoc=16
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=12
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1048576
-tag_latency=12
-
-[system.cpu1.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu1.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu1.l2cache.cpu_side
-slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
-
-[system.cpu1.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu1.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=2147483648:2415919103:0:0:0:0
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-data_latency=50
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tag_latency=50
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[3]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-data_latency=50
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-tag_latency=50
-
-[system.l2c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=20
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tag_latency=20
-tags=system.l2c.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.l2c.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=20
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-tag_latency=20
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=2147483648:2415919103:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[5]
-
-[system.realview]
-type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470024192
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[18]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=471465984
-BAR0LegacyIO=true
-BAR0Size=256
-BAR1=471466240
-BAR1LegacyIO=true
-BAR1Size=4096
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=2
-default_p_state=UNDEFINED
-disks=
-eventq_index=0
-host=system.realview.pci_host
-io_shift=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=2
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[2]
-pio=system.iobus.master[9]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=46
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471793664
-pio_latency=10000
-pixel_clock=41667
-power_model=Null
-system=system
-vnc=system.vncserver
-dma=system.iobus.slave[1]
-pio=system.iobus.master[5]
-
-[system.realview.dcc]
-type=SubSystem
-children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.dcc.osc_cpu]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_ddr]
-type=RealViewOsc
-dcc=0
-device=8
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_hsbm]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_pxl]
-type=RealViewOsc
-dcc=0
-device=5
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_smb]
-type=RealViewOsc
-dcc=0
-device=6
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_sys]
-type=RealViewOsc
-dcc=0
-device=7
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.energy_ctrl]
-type=EnergyCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dvfs_handler=system.dvfs_handler
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470286336
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[22]
-
-[system.realview.ethernet]
-type=IGbE
-BAR0=0
-BAR0LegacyIO=false
-BAR0Size=131072
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=0
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=4213
-ExpansionROM=0
-HeaderType=0
-InterruptLine=1
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=255
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=0
-SubClassCode=0
-SubsystemID=4104
-SubsystemVendorID=32902
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-eventq_index=0
-fetch_comp_delay=10000
-fetch_delay=10000
-hardware_address=00:90:00:00:00:01
-host=system.realview.pci_host
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-phy_epid=896
-phy_pid=680
-pio_latency=30000
-power_model=Null
-rx_desc_cache_size=64
-rx_fifo_size=393216
-rx_write_delay=0
-system=system
-tx_desc_cache_size=64
-tx_fifo_size=393216
-tx_read_delay=0
-wb_comp_delay=10000
-wb_delay=10000
-dma=system.iobus.slave[4]
-pio=system.iobus.master[24]
-
-[system.realview.generic_timer]
-type=GenericTimer
-eventq_index=0
-gic=system.realview.gic
-int_phys=29
-int_virt=27
-system=system
-
-[system.realview.gic]
-type=Pl390
-clk_domain=system.clk_domain
-cpu_addr=738205696
-cpu_pio_delay=10000
-default_p_state=UNDEFINED
-dist_addr=738201600
-dist_pio_delay=10000
-eventq_index=0
-gem5_extensions=false
-int_latency=10000
-it_lines=128
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-platform=system.realview
-power_model=Null
-system=system
-pio=system.membus.master[2]
-
-[system.realview.hdlcd]
-type=HDLcd
-amba_id=1314816
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=117
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=721420288
-pio_latency=10000
-pixel_buffer_size=2048
-pixel_chunk=32
-power_model=Null
-pxl_clk=system.realview.dcc.osc_pxl
-system=system
-vnc=system.vncserver
-workaround_dma_line_count=true
-workaround_swap_rb=true
-dma=system.membus.slave[0]
-pio=system.iobus.master[6]
-
-[system.realview.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=2
-InterruptPin=2
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.cf0
-eventq_index=0
-host=system.realview.pci_host
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[3]
-pio=system.iobus.master[23]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=44
-is_mouse=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470155264
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[7]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=45
-is_mouse=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470220800
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[8]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=739246080
-pio_latency=100000
-pio_size=4095
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.realview.lan_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=436207616
-pio_latency=100000
-pio_size=65535
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=738721792
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.membus.master[4]
-
-[system.realview.mcc]
-type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.mcc.osc_clcd]
-type=RealViewOsc
-dcc=0
-device=1
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_mcc]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_peripheral]
-type=RealViewOsc
-dcc=0
-device=2
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_system_bus]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.temp_crtl]
-type=RealViewTemperatureSensor
-dcc=0
-device=0
-eventq_index=0
-parent=system.realview.realview_io
-position=0
-site=0
-system=system
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470089728
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.realview.nvmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:67108863:0:0:0:0
-port=system.membus.master[1]
-
-[system.realview.pci_host]
-type=GenericPciHost
-clk_domain=system.clk_domain
-conf_base=805306368
-conf_device_bits=16
-conf_size=268435456
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=0
-pci_pio_base=0
-platform=system.realview
-power_model=Null
-system=system
-pio=system.iobus.master[2]
-
-[system.realview.realview_io]
-type=RealViewCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-idreg=35979264
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469827584
-pio_latency=100000
-power_model=Null
-proc_id0=335544320
-proc_id1=335544320
-system=system
-pio=system.iobus.master[1]
-
-[system.realview.rtc]
-type=PL031
-amba_id=3412017
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=36
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471269376
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[10]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469893120
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=34
-int_num1=34
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470876160
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[3]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=35
-int_num1=35
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470941696
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[4]
-
-[system.realview.uart]
-type=Pl011
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-end_on_eot=false
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=37
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470351872
-pio_latency=100000
-platform=system.realview
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[0]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470417408
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470482944
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470548480
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[15]
-
-[system.realview.usb_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=452984832
-pio_latency=100000
-pio_size=131071
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.realview.vgic]
-type=VGic
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-hv_addr=738213888
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_delay=10000
-platform=system.realview
-power_model=Null
-ppint=25
-system=system
-vcpu_addr=738222080
-pio=system.membus.master[3]
-
-[system.realview.vram]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=402653184:436207615:0:0:0:0
-port=system.iobus.master[11]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470745088
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[17]
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2c.cpu_side
-slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
-
-[system.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.vncserver]
-type=VncServer
-eventq_index=0
-frame_capture=false
-number=0
-port=5900
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Using bootloader at address 0x10
-info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
-warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
-info: Entering event queue @ 0. Starting simulation...
-warn: Not doing anything for miscreg ACTLR
-warn: Not doing anything for write of miscreg ACTLR
-warn: The clidr register always reports 0 caches.
-warn: clidr LoUIS field of 0b001 to match current ARM implementations.
-warn: The csselr register isn't implemented.
-warn: instruction 'mcr dccmvau' unimplemented
-warn: instruction 'mcr icimvau' unimplemented
-warn: instruction 'mcr bpiallis' unimplemented
-warn: instruction 'mcr icialluis' unimplemented
-warn: instruction 'mcr dccimvac' unimplemented
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-warn: Not doing anything for miscreg ACTLR
-warn: Not doing anything for write of miscreg ACTLR
-warn: instruction 'mcr bpiall' unimplemented
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
-warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
-warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
-warn: Returning zero for read from miscreg pmcr
-warn: Ignoring write to miscreg pmcntenclr
-warn: Ignoring write to miscreg pmintenclr
-warn: Ignoring write to miscreg pmovsr
-warn: Ignoring write to miscreg pmcr
-warn: Ignoring write to miscreg pmcntenclr
-warn: Ignoring write to miscreg pmintenclr
-warn: Ignoring write to miscreg pmovsr
-warn: Ignoring write to miscreg pmcr
+++ /dev/null
-Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual/simout
-Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Mar 29 2017 18:44:23
-gem5 started Mar 29 2017 18:44:38
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 53279
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
-
-Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 2871012355500 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 2.871012
-sim_ticks 2871012355500
-final_tick 2871012355500
-sim_freq 1000000000000
-host_inst_rate 1070603
-host_op_rate 1294963
-host_tick_rate 23409963735
-host_mem_usage 628644
-host_seconds 122.64
-sim_insts 131299345
-sim_ops 158815094
-system.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2871012355500
-system.physmem.bytes_read::cpu0.dtb.walker 448
-system.physmem.bytes_read::cpu0.itb.walker 128
-system.physmem.bytes_read::cpu0.inst 1181348
-system.physmem.bytes_read::cpu0.data 1294820
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 8551616
-system.physmem.bytes_read::cpu1.dtb.walker 64
-system.physmem.bytes_read::cpu1.inst 152660
-system.physmem.bytes_read::cpu1.data 573908
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 413696
-system.physmem.bytes_read::realview.ide 960
-system.physmem.bytes_read::total 12169648
-system.physmem.bytes_inst_read::cpu0.inst 1181348
-system.physmem.bytes_inst_read::cpu1.inst 152660
-system.physmem.bytes_inst_read::total 1334008
-system.physmem.bytes_written::writebacks 8749184
-system.physmem.bytes_written::cpu0.data 17524
-system.physmem.bytes_written::cpu1.data 40
-system.physmem.bytes_written::total 8766748
-system.physmem.num_reads::cpu0.dtb.walker 7
-system.physmem.num_reads::cpu0.itb.walker 2
-system.physmem.num_reads::cpu0.inst 26912
-system.physmem.num_reads::cpu0.data 20751
-system.physmem.num_reads::cpu0.l2cache.prefetcher 133619
-system.physmem.num_reads::cpu1.dtb.walker 1
-system.physmem.num_reads::cpu1.inst 2540
-system.physmem.num_reads::cpu1.data 8988
-system.physmem.num_reads::cpu1.l2cache.prefetcher 6464
-system.physmem.num_reads::realview.ide 15
-system.physmem.num_reads::total 199299
-system.physmem.num_writes::writebacks 136706
-system.physmem.num_writes::cpu0.data 4381
-system.physmem.num_writes::cpu1.data 10
-system.physmem.num_writes::total 141097
-system.physmem.bw_read::cpu0.dtb.walker 156
-system.physmem.bw_read::cpu0.itb.walker 45
-system.physmem.bw_read::cpu0.inst 411474
-system.physmem.bw_read::cpu0.data 450998
-system.physmem.bw_read::cpu0.l2cache.prefetcher 2978606
-system.physmem.bw_read::cpu1.dtb.walker 22
-system.physmem.bw_read::cpu1.inst 53173
-system.physmem.bw_read::cpu1.data 199897
-system.physmem.bw_read::cpu1.l2cache.prefetcher 144094
-system.physmem.bw_read::realview.ide 334
-system.physmem.bw_read::total 4238800
-system.physmem.bw_inst_read::cpu0.inst 411474
-system.physmem.bw_inst_read::cpu1.inst 53173
-system.physmem.bw_inst_read::total 464647
-system.physmem.bw_write::writebacks 3047421
-system.physmem.bw_write::cpu0.data 6104
-system.physmem.bw_write::cpu1.data 14
-system.physmem.bw_write::total 3053539
-system.physmem.bw_total::writebacks 3047421
-system.physmem.bw_total::cpu0.dtb.walker 156
-system.physmem.bw_total::cpu0.itb.walker 45
-system.physmem.bw_total::cpu0.inst 411474
-system.physmem.bw_total::cpu0.data 457101
-system.physmem.bw_total::cpu0.l2cache.prefetcher 2978606
-system.physmem.bw_total::cpu1.dtb.walker 22
-system.physmem.bw_total::cpu1.inst 53173
-system.physmem.bw_total::cpu1.data 199911
-system.physmem.bw_total::cpu1.l2cache.prefetcher 144094
-system.physmem.bw_total::realview.ide 334
-system.physmem.bw_total::total 7292339
-system.physmem.readReqs 199299
-system.physmem.writeReqs 141097
-system.physmem.readBursts 199299
-system.physmem.writeBursts 141097
-system.physmem.bytesReadDRAM 12744832
-system.physmem.bytesReadWrQ 10304
-system.physmem.bytesWritten 8779712
-system.physmem.bytesReadSys 12169648
-system.physmem.bytesWrittenSys 8766748
-system.physmem.servicedByWrQ 161
-system.physmem.mergedWrBursts 3897
-system.physmem.neitherReadNorWriteReqs 0
-system.physmem.perBankRdBursts::0 11941
-system.physmem.perBankRdBursts::1 11941
-system.physmem.perBankRdBursts::2 12061
-system.physmem.perBankRdBursts::3 12014
-system.physmem.perBankRdBursts::4 20277
-system.physmem.perBankRdBursts::5 11993
-system.physmem.perBankRdBursts::6 12082
-system.physmem.perBankRdBursts::7 12163
-system.physmem.perBankRdBursts::8 12412
-system.physmem.perBankRdBursts::9 12768
-system.physmem.perBankRdBursts::10 11659
-system.physmem.perBankRdBursts::11 11203
-system.physmem.perBankRdBursts::12 11765
-system.physmem.perBankRdBursts::13 11689
-system.physmem.perBankRdBursts::14 11759
-system.physmem.perBankRdBursts::15 11411
-system.physmem.perBankWrBursts::0 8593
-system.physmem.perBankWrBursts::1 8809
-system.physmem.perBankWrBursts::2 8990
-system.physmem.perBankWrBursts::3 8736
-system.physmem.perBankWrBursts::4 8204
-system.physmem.perBankWrBursts::5 8547
-system.physmem.perBankWrBursts::6 8879
-system.physmem.perBankWrBursts::7 8644
-system.physmem.perBankWrBursts::8 8884
-system.physmem.perBankWrBursts::9 9196
-system.physmem.perBankWrBursts::10 8452
-system.physmem.perBankWrBursts::11 8329
-system.physmem.perBankWrBursts::12 8624
-system.physmem.perBankWrBursts::13 8076
-system.physmem.perBankWrBursts::14 8386
-system.physmem.perBankWrBursts::15 7834
-system.physmem.numRdRetry 0
-system.physmem.numWrRetry 79
-system.physmem.totGap 2871011323500
-system.physmem.readPktSize::0 0
-system.physmem.readPktSize::1 0
-system.physmem.readPktSize::2 9732
-system.physmem.readPktSize::3 28
-system.physmem.readPktSize::4 0
-system.physmem.readPktSize::5 0
-system.physmem.readPktSize::6 189539
-system.physmem.writePktSize::0 0
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-system.physmem.wrPerTurnAround::56-59 1 0.01% 96.46%
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-system.physmem.wrPerTurnAround::64-67 152 2.24% 98.86%
-system.physmem.wrPerTurnAround::68-71 7 0.10% 98.97%
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-system.realview.ethernet.descDmaWriteBytes 0
-system.realview.ethernet.postedSwi 0
-system.realview.ethernet.coalescedSwi nan
-system.realview.ethernet.totalSwi 0
-system.realview.ethernet.postedRxIdle 0
-system.realview.ethernet.coalescedRxIdle nan
-system.realview.ethernet.totalRxIdle 0
-system.realview.ethernet.postedRxOk 0
-system.realview.ethernet.coalescedRxOk nan
-system.realview.ethernet.totalRxOk 0
-system.realview.ethernet.postedRxDesc 0
-system.realview.ethernet.coalescedRxDesc nan
-system.realview.ethernet.totalRxDesc 0
-system.realview.ethernet.postedTxOk 0
-system.realview.ethernet.coalescedTxOk nan
-system.realview.ethernet.totalTxOk 0
-system.realview.ethernet.postedTxIdle 0
-system.realview.ethernet.coalescedTxIdle nan
-system.realview.ethernet.totalTxIdle 0
-system.realview.ethernet.postedTxDesc 0
-system.realview.ethernet.coalescedTxDesc nan
-system.realview.ethernet.totalTxDesc 0
-system.realview.ethernet.postedRxOrn 0
-system.realview.ethernet.coalescedRxOrn nan
-system.realview.ethernet.totalRxOrn 0
-system.realview.ethernet.coalescedTotal nan
-system.realview.ethernet.postedInterrupts 0
-system.realview.ethernet.droppedPackets 0
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2871012355500
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2871012355500
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2871012355500
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2871012355500
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2871012355500
-system.realview.mcc.osc_clcd.clock 42105
-system.realview.mcc.osc_mcc.clock 20000
-system.realview.mcc.osc_peripheral.clock 41667
-system.realview.mcc.osc_system_bus.clock 41667
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2871012355500
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2871012355500
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2871012355500
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2871012355500
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2871012355500
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500
-system.toL2Bus.snoop_filter.tot_requests 1013756
-system.toL2Bus.snoop_filter.hit_single_requests 527510
-system.toL2Bus.snoop_filter.hit_multi_requests 187290
-system.toL2Bus.snoop_filter.tot_snoops 29674
-system.toL2Bus.snoop_filter.hit_single_snoops 28443
-system.toL2Bus.snoop_filter.hit_multi_snoops 1231
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2871012355500
-system.toL2Bus.trans_dist::ReadReq 44026
-system.toL2Bus.trans_dist::ReadResp 511611
-system.toL2Bus.trans_dist::WriteReq 30870
-system.toL2Bus.trans_dist::WriteResp 30870
-system.toL2Bus.trans_dist::WritebackDirty 361082
-system.toL2Bus.trans_dist::CleanEvict 119910
-system.toL2Bus.trans_dist::UpgradeReq 109230
-system.toL2Bus.trans_dist::SCUpgradeReq 42710
-system.toL2Bus.trans_dist::UpgradeResp 151940
-system.toL2Bus.trans_dist::SCUpgradeFailReq 77
-system.toL2Bus.trans_dist::UpgradeFailResp 77
-system.toL2Bus.trans_dist::ReadExReq 50740
-system.toL2Bus.trans_dist::ReadExResp 50740
-system.toL2Bus.trans_dist::ReadSharedReq 467589
-system.toL2Bus.trans_dist::InvalidateReq 4574
-system.toL2Bus.trans_dist::InvalidateResp 3436
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1274602
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 317408
-system.toL2Bus.pkt_count::total 1592010
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35235610
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5660730
-system.toL2Bus.pkt_size::total 40896340
-system.toL2Bus.snoops 391148
-system.toL2Bus.snoopTraffic 15652684
-system.toL2Bus.snoop_fanout::samples 887182
-system.toL2Bus.snoop_fanout::mean 0.397329
-system.toL2Bus.snoop_fanout::stdev 0.492173
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
-system.toL2Bus.snoop_fanout::0 535910 60.41% 60.41%
-system.toL2Bus.snoop_fanout::1 350041 39.46% 99.86%
-system.toL2Bus.snoop_fanout::2 1231 0.14% 100.00%
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
-system.toL2Bus.snoop_fanout::min_value 0
-system.toL2Bus.snoop_fanout::max_value 2
-system.toL2Bus.snoop_fanout::total 887182
-system.toL2Bus.reqLayer0.occupancy 894578674
-system.toL2Bus.reqLayer0.utilization 0.0
-system.toL2Bus.snoopLayer0.occupancy 2158873
-system.toL2Bus.snoopLayer0.utilization 0.0
-system.toL2Bus.respLayer0.occupancy 676162622
-system.toL2Bus.respLayer0.utilization 0.0
-system.toL2Bus.respLayer1.occupancy 239095357
-system.toL2Bus.respLayer1.utilization 0.0
-
----------- End Simulation Statistics ----------
+++ /dev/null
-Booting Linux on physical CPU 0x0\r
-\rInitializing cgroup subsys cpuset\r
-\rLinux version 3.13.0-rc2 (tony@vamp) (gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4) ) #1 SMP PREEMPT Mon Oct 13 15:09:23 EDT 2014\r
-\rKernel was built at commit id ''\r
-\rCPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d\r
-\rCPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache\r
-\rMachine model: V2P-CA15\r
-\rbootconsole [earlycon0] enabled\r
-\rMemory policy: Data cache writealloc\r
-\rkdebugv2m: Following are test values to confirm proper working\r
-\rkdebugv2m: Ranges 42000000 0 \r
-\rkdebugv2m: Regs 30000000 1000000 \r
-\rkdebugv2m: Virtual-Reg f0000000 \r
-\rkdebugv2m: pci node addr_cells 3 \r
-\rkdebugv2m: pci node size_cells 2 \r
-\rkdebugv2m: motherboard addr_cells 2 \r
-\rOn node 0 totalpages: 65536\r
-\rfree_area_init_node: node 0, pgdat 8072dcc0, node_mem_map 8078f000\r
-\r Normal zone: 512 pages used for memmap\r
-\r Normal zone: 0 pages reserved\r
-\r Normal zone: 65536 pages, LIFO batch:15\r
-\rsched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns\r
-\rPERCPU: Embedded 8 pages/cpu @80996000 s11648 r8192 d12928 u32768\r
-\rpcpu-alloc: s11648 r8192 d12928 u32768 alloc=8*4096\r
-\rpcpu-alloc: [0] 0 [0] 1 \r
-\rBuilt 1 zonelists in Zone order, mobility grouping on. Total pages: 65024\r
-\rKernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
-\rPID hash table entries: 1024 (order: 0, 4096 bytes)\r
-\rDentry cache hash table entries: 32768 (order: 5, 131072 bytes)\r
-\rInode-cache hash table entries: 16384 (order: 4, 65536 bytes)\r
-\rMemory: 235656K/262144K available (5248K kernel code, 249K rwdata, 1540K rodata, 295K init, 368K bss, 26488K reserved, 0K highmem)\r
-\rVirtual kernel memory layout:\r
-\r vector : 0xffff0000 - 0xffff1000 ( 4 kB)\r
-\r fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)\r
-\r vmalloc : 0x90800000 - 0xff000000 (1768 MB)\r
-\r lowmem : 0x80000000 - 0x90000000 ( 256 MB)\r
-\r pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)\r
-\r modules : 0x7f000000 - 0x7fe00000 ( 14 MB)\r
-\r .text : 0x80008000 - 0x806a942c (6790 kB)\r
-\r .init : 0x806aa000 - 0x806f3d80 ( 296 kB)\r
-\r .data : 0x806f4000 - 0x80732754 ( 250 kB)\r
-\r .bss : 0x80732754 - 0x8078e9d8 ( 369 kB)\r
-\rSLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1\r
-\rPreemptible hierarchical RCU implementation.\r
-\r RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=2.\r
-\rNR_IRQS:16 nr_irqs:16 16\r
-\rArchitected cp15 timer(s) running at 25.16MHz (phys).\r
-\rsched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 2730666655744ns\r
-\rSwitching to timer-based delay loop\r
-\rConsole: colour dummy device 80x30\r
-\rCalibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-\rpid_max: default: 32768 minimum: 301\r
-\rMount-cache hash table entries: 512\r
-\rCPU: Testing write buffer coherency: ok\r
-\r/cpus/cpu@1 missing clock-frequency property\r
-\rCPU0: update cpu_power 1024\r
-\rCPU0: thread -1, cpu 0, socket 0, mpidr 80000000\r
-\rSetting up static identity map for 0x804fee68 - 0x804fee9c\r
-\rCPU1: Booted secondary processor\r
-\rCPU1: thread -1, cpu 1, socket 0, mpidr 80000001\r
-\rBrought up 2 CPUs\r
-\rSMP: Total of 2 processors activated.\r
-\rCPU: All CPU(s) started in SVC mode.\r
-\rVFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0\r
-\rNET: Registered protocol family 16\r
-\rDMA: preallocated 256 KiB pool for atomic coherent allocations\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/aaci@040000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/mmci@050000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-\rhw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 1\r
-\rhw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 1\r
-\rhw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 1\r
-\rhw-breakpoint: CPU 1 failed to disable vector catch\r
-\rhw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 0\r
-\rhw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 0\r
-\rhw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0\r
-\rSerial: AMBA PL011 UART driver\r
-\r1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-\rconsole [ttyAMA0] enabled\r
-console [ttyAMA0] enabled\r
-\rbootconsole [earlycon0] disabled\r
-bootconsole [earlycon0] disabled\r
-\rPCI host bridge to bus 0000:00\r
-pci_bus 0000:00: root bus resource [io 0x0000-0xffffffff]\r
-pci_bus 0000:00: root bus resource [mem 0x00000000-0xffffffff]\r
-pci_bus 0000:00: root bus resource [bus 00-ff]\r
-pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-PCI: bus0: Fast back to back transfers disabled\r
-pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-pci 0000:00:01.0: BAR 4: assigned [io 0x2f000000-0x2f00000f]\r
-pci 0000:00:01.0: BAR 0: assigned [io 0x2f000010-0x2f000017]\r
-pci 0000:00:01.0: BAR 2: assigned [io 0x2f000018-0x2f00001f]\r
-pci 0000:00:01.0: BAR 1: assigned [io 0x2f000020-0x2f000023]\r
-pci 0000:00:01.0: BAR 3: assigned [io 0x2f000024-0x2f000027]\r
-pci_bus 0000:00: resource 4 [io 0x0000-0xffffffff]\r
-pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff]\r
-PCI map irq: slot 0, pin 1, devslot 0, irq: 68\r
-PCI map irq: slot 1, pin 2, devslot 1, irq: 69\r
-bio: create slab <bio-0> at 0\r
-vgaarb: loaded\r
-SCSI subsystem initialized\r
-libata version 3.00 loaded.\r
-usbcore: registered new interface driver usbfs\r
-usbcore: registered new interface driver hub\r
-usbcore: registered new device driver usb\r
-pps_core: LinuxPPS API ver. 1 registered\r
-pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-PTP clock support registered\r
-Advanced Linux Sound Architecture Driver Initialized.\r
-Switched to clocksource arch_sys_counter\r
-NET: Registered protocol family 2\r
-TCP established hash table entries: 2048 (order: 1, 8192 bytes)\r
-TCP bind hash table entries: 2048 (order: 2, 16384 bytes)\r
-TCP: Hash tables configured (established 2048 bind 2048)\r
-TCP: reno registered\r
-UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-NET: Registered protocol family 1\r
-RPC: Registered named UNIX socket transport module.\r
-RPC: Registered udp transport module.\r
-RPC: Registered tcp transport module.\r
-RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-PCI: CLS 64 bytes, default 64\r
-hw perfevents: enabled with ARMv7_Cortex_A15 PMU driver, 1 counters available\r
-jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.\r
-msgmni has been set to 460\r
-io scheduler noop registered (default)\r
-brd: module loaded\r
-loop: module loaded\r
-ata_piix 0000:00:01.0: version 2.13\r
-PCI: enabling device 0000:00:01.0 (0040 -> 0041)\r
-scsi0 : ata_piix\r
-scsi1 : ata_piix\r
-ata1: PATA max UDMA/33 cmd 0x2f000010 ctl 0x2f000020 bmdma 0x2f000000 irq 69\r
-ata2: PATA max UDMA/33 cmd 0x2f000018 ctl 0x2f000024 bmdma 0x2f000008 irq 69\r
-e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI\r
-e100: Copyright(c) 1999-2006 Intel Corporation\r
-e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-PCI: enabling device 0000:00:00.0 (0040 -> 0042)\r
-ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-ata1.00: 1048320 sectors, multi 0: LBA \r
-ata1.00: configured for UDMA/33\r
-scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)\r
-sd 0:0:0:0: [sda] Write Protect is off\r
-sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-sd 0:0:0:0: Attached scsi generic sg0 type 0\r
- sda: sda1\r
-sd 0:0:0:0: [sda] Attached SCSI disk\r
-e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-e1000e: Copyright(c) 1999 - 2013 Intel Corporation.\r
-igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-igb: Copyright (c) 2007-2013 Intel Corporation.\r
-igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.0.2-k\r
-igbvf: Copyright (c) 2009 - 2012 Intel Corporation.\r
-ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver - version 3.15.1-k\r
-ixgbe: Copyright (c) 1999-2013 Intel Corporation.\r
-ixgbevf: Intel(R) 10 Gigabit PCI Express Virtual Function Network Driver - version 2.11.3-k\r
-ixgbevf: Copyright (c) 2009 - 2012 Intel Corporation.\r
-ixgb: Intel(R) PRO/10GbE Network Driver - version 1.0.135-k2-NAPI\r
-ixgb: Copyright (c) 1999-2008 Intel Corporation.\r
-smsc911x: Driver version 2008-10-21\r
-smsc911x 1a000000.ethernet (unregistered net_device): couldn't get clock -2\r
-nxp-isp1760 1b000000.usb: NXP ISP1760 USB Host Controller\r
-nxp-isp1760 1b000000.usb: new USB bus registered, assigned bus number 1\r
-nxp-isp1760 1b000000.usb: Scratch test failed.\r
-nxp-isp1760 1b000000.usb: can't setup: -19\r
-nxp-isp1760 1b000000.usb: USB bus 1 deregistered\r
-usbcore: registered new interface driver usb-storage\r
-mousedev: PS/2 mouse device common for all mice\r
-rtc-pl031 1c170000.rtc: rtc core: registered pl031 as rtc0\r
-usbcore: registered new interface driver usbhid\r
-usbhid: USB HID core driver\r
-ashmem: initialized\r
-logger: created 256K log 'log_main'\r
-logger: created 256K log 'log_events'\r
-logger: created 256K log 'log_radio'\r
-logger: created 256K log 'log_system'\r
-oprofile: using timer interrupt.\r
-TCP: cubic registered\r
-NET: Registered protocol family 10\r
-NET: Registered protocol family 17\r
-rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 00:00:00 UTC (1230768000)\r
-ALSA device list:\r
- No soundcards found.\r
-\0input: AT Raw Set 2 keyboard as /devices/smb.14/motherboard.15/iofpga.17/1c060000.kmi/serio0/input/input0\r
-input: touchkitPS/2 eGalax Touchscreen as /devices/smb.14/motherboard.15/iofpga.17/1c070000.kmi/serio1/input/input2\r
-VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-Freeing unused kernel memory: 292K (806aa000 - 806f3000)\r
-\rinit started: BusyBox v1.15.3 (2010-05-07 01:27:07 BST)\r
-\rstarting pid 680, tty '': '/etc/rc.d/rc.local'\r
-warning: can't open /etc/mtab: No such file or directory\r
-Thu Jan 1 00:00:02 UTC 2009\r
-S: devpts\r
-Thu Jan 1 00:00:02 UTC 2009\r
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
-atags_addr=134217728
-boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
-early_kernel_symbols=false
-enable_context_switch_stats_dump=false
-eventq_index=0
-exit_on_work_items=false
-flags_addr=469827632
-gic_cpu_addr=738205696
-have_large_asid_64=false
-have_lpae=true
-have_security=false
-have_virtualization=false
-highest_el_is_64=false
-init_param=0
-kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
-kernel_addr_check=true
-load_addr_mask=268435455
-load_offset=2147483648
-machine_type=VExpress_EMM
-mem_mode=timing
-mem_ranges=2147483648:2415919103:0:0:0:0
-memories=system.physmem system.realview.nvmem system.realview.vram
-mmap_using_noreserve=false
-multi_proc=true
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-panic_on_oops=true
-panic_on_panic=true
-phys_addr_range_64=40
-power_model=Null
-readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
-reset_addr_64=0
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img
-read_only=true
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-workload=
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tag_latency=2
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-tag_latency=2
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tag_latency=2
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-tag_latency=2
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=20
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tag_latency=20
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=20
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-tag_latency=20
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=2147483648:2415919103:0:0:0:0
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-data_latency=50
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tag_latency=50
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[3]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-data_latency=50
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-tag_latency=50
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=2147483648:2415919103:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[5]
-
-[system.realview]
-type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470024192
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[18]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=471465984
-BAR0LegacyIO=true
-BAR0Size=256
-BAR1=471466240
-BAR1LegacyIO=true
-BAR1Size=4096
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=2
-default_p_state=UNDEFINED
-disks=
-eventq_index=0
-host=system.realview.pci_host
-io_shift=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=2
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[2]
-pio=system.iobus.master[9]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=46
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471793664
-pio_latency=10000
-pixel_clock=41667
-power_model=Null
-system=system
-vnc=system.vncserver
-dma=system.iobus.slave[1]
-pio=system.iobus.master[5]
-
-[system.realview.dcc]
-type=SubSystem
-children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.dcc.osc_cpu]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_ddr]
-type=RealViewOsc
-dcc=0
-device=8
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_hsbm]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_pxl]
-type=RealViewOsc
-dcc=0
-device=5
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_smb]
-type=RealViewOsc
-dcc=0
-device=6
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_sys]
-type=RealViewOsc
-dcc=0
-device=7
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.energy_ctrl]
-type=EnergyCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dvfs_handler=system.dvfs_handler
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470286336
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[22]
-
-[system.realview.ethernet]
-type=IGbE
-BAR0=0
-BAR0LegacyIO=false
-BAR0Size=131072
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=0
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=4213
-ExpansionROM=0
-HeaderType=0
-InterruptLine=1
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=255
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=0
-SubClassCode=0
-SubsystemID=4104
-SubsystemVendorID=32902
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-eventq_index=0
-fetch_comp_delay=10000
-fetch_delay=10000
-hardware_address=00:90:00:00:00:01
-host=system.realview.pci_host
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-phy_epid=896
-phy_pid=680
-pio_latency=30000
-power_model=Null
-rx_desc_cache_size=64
-rx_fifo_size=393216
-rx_write_delay=0
-system=system
-tx_desc_cache_size=64
-tx_fifo_size=393216
-tx_read_delay=0
-wb_comp_delay=10000
-wb_delay=10000
-dma=system.iobus.slave[4]
-pio=system.iobus.master[24]
-
-[system.realview.generic_timer]
-type=GenericTimer
-eventq_index=0
-gic=system.realview.gic
-int_phys=29
-int_virt=27
-system=system
-
-[system.realview.gic]
-type=Pl390
-clk_domain=system.clk_domain
-cpu_addr=738205696
-cpu_pio_delay=10000
-default_p_state=UNDEFINED
-dist_addr=738201600
-dist_pio_delay=10000
-eventq_index=0
-gem5_extensions=false
-int_latency=10000
-it_lines=128
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-platform=system.realview
-power_model=Null
-system=system
-pio=system.membus.master[2]
-
-[system.realview.hdlcd]
-type=HDLcd
-amba_id=1314816
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=117
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=721420288
-pio_latency=10000
-pixel_buffer_size=2048
-pixel_chunk=32
-power_model=Null
-pxl_clk=system.realview.dcc.osc_pxl
-system=system
-vnc=system.vncserver
-workaround_dma_line_count=true
-workaround_swap_rb=true
-dma=system.membus.slave[0]
-pio=system.iobus.master[6]
-
-[system.realview.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=2
-InterruptPin=2
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.cf0
-eventq_index=0
-host=system.realview.pci_host
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[3]
-pio=system.iobus.master[23]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=44
-is_mouse=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470155264
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[7]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=45
-is_mouse=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470220800
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[8]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=739246080
-pio_latency=100000
-pio_size=4095
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.realview.lan_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=436207616
-pio_latency=100000
-pio_size=65535
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=738721792
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.membus.master[4]
-
-[system.realview.mcc]
-type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.mcc.osc_clcd]
-type=RealViewOsc
-dcc=0
-device=1
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_mcc]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_peripheral]
-type=RealViewOsc
-dcc=0
-device=2
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_system_bus]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.temp_crtl]
-type=RealViewTemperatureSensor
-dcc=0
-device=0
-eventq_index=0
-parent=system.realview.realview_io
-position=0
-site=0
-system=system
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470089728
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.realview.nvmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:67108863:0:0:0:0
-port=system.membus.master[1]
-
-[system.realview.pci_host]
-type=GenericPciHost
-clk_domain=system.clk_domain
-conf_base=805306368
-conf_device_bits=16
-conf_size=268435456
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=0
-pci_pio_base=0
-platform=system.realview
-power_model=Null
-system=system
-pio=system.iobus.master[2]
-
-[system.realview.realview_io]
-type=RealViewCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-idreg=35979264
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469827584
-pio_latency=100000
-power_model=Null
-proc_id0=335544320
-proc_id1=335544320
-system=system
-pio=system.iobus.master[1]
-
-[system.realview.rtc]
-type=PL031
-amba_id=3412017
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=36
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471269376
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[10]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469893120
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=34
-int_num1=34
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470876160
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[3]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=35
-int_num1=35
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470941696
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[4]
-
-[system.realview.uart]
-type=Pl011
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-end_on_eot=false
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=37
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470351872
-pio_latency=100000
-platform=system.realview
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[0]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470417408
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470482944
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470548480
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[15]
-
-[system.realview.usb_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=452984832
-pio_latency=100000
-pio_size=131071
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.realview.vgic]
-type=VGic
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-hv_addr=738213888
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_delay=10000
-platform=system.realview
-power_model=Null
-ppint=25
-system=system
-vcpu_addr=738222080
-pio=system.membus.master[3]
-
-[system.realview.vram]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=402653184:436207615:0:0:0:0
-port=system.iobus.master[11]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470745088
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[17]
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.vncserver]
-type=VncServer
-eventq_index=0
-frame_capture=false
-number=0
-port=5900
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Using bootloader at address 0x10
-info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
-warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
-info: Entering event queue @ 0. Starting simulation...
-warn: Not doing anything for miscreg ACTLR
-warn: Not doing anything for write of miscreg ACTLR
-warn: The clidr register always reports 0 caches.
-warn: clidr LoUIS field of 0b001 to match current ARM implementations.
-warn: The csselr register isn't implemented.
-warn: instruction 'mcr dccmvau' unimplemented
-warn: instruction 'mcr icimvau' unimplemented
-warn: instruction 'mcr bpiallis' unimplemented
-warn: instruction 'mcr icialluis' unimplemented
-warn: instruction 'mcr dccimvac' unimplemented
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
-warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
-warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
-warn: Returning zero for read from miscreg pmcr
-warn: Ignoring write to miscreg pmcntenclr
-warn: Ignoring write to miscreg pmintenclr
-warn: Ignoring write to miscreg pmovsr
-warn: Ignoring write to miscreg pmcr
+++ /dev/null
-Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Mar 29 2017 18:44:23
-gem5 started Mar 29 2017 18:44:38
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 53278
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing
-
-Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 2905305537500 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 2.905306
-sim_ticks 2905305537500
-final_tick 2905305537500
-sim_freq 1000000000000
-host_inst_rate 1111245
-host_op_rate 1339819
-host_tick_rate 28710628480
-host_mem_usage 591900
-host_seconds 101.19
-sim_insts 112449853
-sim_ops 135579871
-system.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.physmem.bytes_read::cpu.dtb.walker 448
-system.physmem.bytes_read::cpu.itb.walker 128
-system.physmem.bytes_read::cpu.inst 1186468
-system.physmem.bytes_read::cpu.data 8969572
-system.physmem.bytes_read::realview.ide 960
-system.physmem.bytes_read::total 10157576
-system.physmem.bytes_inst_read::cpu.inst 1186468
-system.physmem.bytes_inst_read::total 1186468
-system.physmem.bytes_written::writebacks 7562240
-system.physmem.bytes_written::cpu.data 17524
-system.physmem.bytes_written::total 7579764
-system.physmem.num_reads::cpu.dtb.walker 7
-system.physmem.num_reads::cpu.itb.walker 2
-system.physmem.num_reads::cpu.inst 26992
-system.physmem.num_reads::cpu.data 140669
-system.physmem.num_reads::realview.ide 15
-system.physmem.num_reads::total 167685
-system.physmem.num_writes::writebacks 118160
-system.physmem.num_writes::cpu.data 4381
-system.physmem.num_writes::total 122541
-system.physmem.bw_read::cpu.dtb.walker 154
-system.physmem.bw_read::cpu.itb.walker 44
-system.physmem.bw_read::cpu.inst 408380
-system.physmem.bw_read::cpu.data 3087308
-system.physmem.bw_read::realview.ide 330
-system.physmem.bw_read::total 3496216
-system.physmem.bw_inst_read::cpu.inst 408380
-system.physmem.bw_inst_read::total 408380
-system.physmem.bw_write::writebacks 2602907
-system.physmem.bw_write::cpu.data 6032
-system.physmem.bw_write::total 2608939
-system.physmem.bw_total::writebacks 2602907
-system.physmem.bw_total::cpu.dtb.walker 154
-system.physmem.bw_total::cpu.itb.walker 44
-system.physmem.bw_total::cpu.inst 408380
-system.physmem.bw_total::cpu.data 3093339
-system.physmem.bw_total::realview.ide 330
-system.physmem.bw_total::total 6105155
-system.physmem.readReqs 167685
-system.physmem.writeReqs 122541
-system.physmem.readBursts 167685
-system.physmem.writeBursts 122541
-system.physmem.bytesReadDRAM 10724672
-system.physmem.bytesReadWrQ 7168
-system.physmem.bytesWritten 7592640
-system.physmem.bytesReadSys 10157576
-system.physmem.bytesWrittenSys 7579764
-system.physmem.servicedByWrQ 112
-system.physmem.mergedWrBursts 3887
-system.physmem.neitherReadNorWriteReqs 0
-system.physmem.perBankRdBursts::0 9873
-system.physmem.perBankRdBursts::1 9614
-system.physmem.perBankRdBursts::2 9963
-system.physmem.perBankRdBursts::3 9595
-system.physmem.perBankRdBursts::4 18744
-system.physmem.perBankRdBursts::5 9936
-system.physmem.perBankRdBursts::6 10635
-system.physmem.perBankRdBursts::7 11205
-system.physmem.perBankRdBursts::8 9589
-system.physmem.perBankRdBursts::9 10032
-system.physmem.perBankRdBursts::10 9283
-system.physmem.perBankRdBursts::11 8863
-system.physmem.perBankRdBursts::12 10211
-system.physmem.perBankRdBursts::13 10190
-system.physmem.perBankRdBursts::14 10325
-system.physmem.perBankRdBursts::15 9515
-system.physmem.perBankWrBursts::0 7137
-system.physmem.perBankWrBursts::1 7022
-system.physmem.perBankWrBursts::2 7742
-system.physmem.perBankWrBursts::3 7365
-system.physmem.perBankWrBursts::4 7465
-system.physmem.perBankWrBursts::5 7289
-system.physmem.perBankWrBursts::6 7716
-system.physmem.perBankWrBursts::7 8300
-system.physmem.perBankWrBursts::8 7184
-system.physmem.perBankWrBursts::9 7439
-system.physmem.perBankWrBursts::10 6836
-system.physmem.perBankWrBursts::11 6804
-system.physmem.perBankWrBursts::12 7947
-system.physmem.perBankWrBursts::13 7681
-system.physmem.perBankWrBursts::14 7752
-system.physmem.perBankWrBursts::15 6956
-system.physmem.numRdRetry 0
-system.physmem.numWrRetry 63
-system.physmem.totGap 2905305175500
-system.physmem.readPktSize::0 0
-system.physmem.readPktSize::1 0
-system.physmem.readPktSize::2 9558
-system.physmem.readPktSize::3 14
-system.physmem.readPktSize::4 0
-system.physmem.readPktSize::5 0
-system.physmem.readPktSize::6 158113
-system.physmem.writePktSize::0 0
-system.physmem.writePktSize::1 0
-system.physmem.writePktSize::2 4381
-system.physmem.writePktSize::3 0
-system.physmem.writePktSize::4 0
-system.physmem.writePktSize::5 0
-system.physmem.writePktSize::6 118160
-system.physmem.rdQLenPdf::0 166739
-system.physmem.rdQLenPdf::1 559
-system.physmem.rdQLenPdf::2 263
-system.physmem.rdQLenPdf::3 1
-system.physmem.rdQLenPdf::4 1
-system.physmem.rdQLenPdf::5 1
-system.physmem.rdQLenPdf::6 1
-system.physmem.rdQLenPdf::7 1
-system.physmem.rdQLenPdf::8 1
-system.physmem.rdQLenPdf::9 1
-system.physmem.rdQLenPdf::10 1
-system.physmem.rdQLenPdf::11 1
-system.physmem.rdQLenPdf::12 1
-system.physmem.rdQLenPdf::13 1
-system.physmem.rdQLenPdf::14 1
-system.physmem.rdQLenPdf::15 0
-system.physmem.rdQLenPdf::16 0
-system.physmem.rdQLenPdf::17 0
-system.physmem.rdQLenPdf::18 0
-system.physmem.rdQLenPdf::19 0
-system.physmem.rdQLenPdf::20 0
-system.physmem.rdQLenPdf::21 0
-system.physmem.rdQLenPdf::22 0
-system.physmem.rdQLenPdf::23 0
-system.physmem.rdQLenPdf::24 0
-system.physmem.rdQLenPdf::25 0
-system.physmem.rdQLenPdf::26 0
-system.physmem.rdQLenPdf::27 0
-system.physmem.rdQLenPdf::28 0
-system.physmem.rdQLenPdf::29 0
-system.physmem.rdQLenPdf::30 0
-system.physmem.rdQLenPdf::31 0
-system.physmem.wrQLenPdf::0 1
-system.physmem.wrQLenPdf::1 1
-system.physmem.wrQLenPdf::2 1
-system.physmem.wrQLenPdf::3 1
-system.physmem.wrQLenPdf::4 1
-system.physmem.wrQLenPdf::5 1
-system.physmem.wrQLenPdf::6 1
-system.physmem.wrQLenPdf::7 1
-system.physmem.wrQLenPdf::8 1
-system.physmem.wrQLenPdf::9 1
-system.physmem.wrQLenPdf::10 1
-system.physmem.wrQLenPdf::11 1
-system.physmem.wrQLenPdf::12 1
-system.physmem.wrQLenPdf::13 1
-system.physmem.wrQLenPdf::14 1
-system.physmem.wrQLenPdf::15 1874
-system.physmem.wrQLenPdf::16 2840
-system.physmem.wrQLenPdf::17 5990
-system.physmem.wrQLenPdf::18 5890
-system.physmem.wrQLenPdf::19 6230
-system.physmem.wrQLenPdf::20 5856
-system.physmem.wrQLenPdf::21 6225
-system.physmem.wrQLenPdf::22 6586
-system.physmem.wrQLenPdf::23 7530
-system.physmem.wrQLenPdf::24 7116
-system.physmem.wrQLenPdf::25 8216
-system.physmem.wrQLenPdf::26 8865
-system.physmem.wrQLenPdf::27 7091
-system.physmem.wrQLenPdf::28 6561
-system.physmem.wrQLenPdf::29 6513
-system.physmem.wrQLenPdf::30 6308
-system.physmem.wrQLenPdf::31 6117
-system.physmem.wrQLenPdf::32 6210
-system.physmem.wrQLenPdf::33 449
-system.physmem.wrQLenPdf::34 397
-system.physmem.wrQLenPdf::35 386
-system.physmem.wrQLenPdf::36 303
-system.physmem.wrQLenPdf::37 299
-system.physmem.wrQLenPdf::38 283
-system.physmem.wrQLenPdf::39 257
-system.physmem.wrQLenPdf::40 228
-system.physmem.wrQLenPdf::41 270
-system.physmem.wrQLenPdf::42 247
-system.physmem.wrQLenPdf::43 240
-system.physmem.wrQLenPdf::44 228
-system.physmem.wrQLenPdf::45 174
-system.physmem.wrQLenPdf::46 175
-system.physmem.wrQLenPdf::47 154
-system.physmem.wrQLenPdf::48 169
-system.physmem.wrQLenPdf::49 180
-system.physmem.wrQLenPdf::50 174
-system.physmem.wrQLenPdf::51 137
-system.physmem.wrQLenPdf::52 121
-system.physmem.wrQLenPdf::53 122
-system.physmem.wrQLenPdf::54 117
-system.physmem.wrQLenPdf::55 150
-system.physmem.wrQLenPdf::56 246
-system.physmem.wrQLenPdf::57 214
-system.physmem.wrQLenPdf::58 117
-system.physmem.wrQLenPdf::59 199
-system.physmem.wrQLenPdf::60 201
-system.physmem.wrQLenPdf::61 189
-system.physmem.wrQLenPdf::62 68
-system.physmem.wrQLenPdf::63 127
-system.physmem.bytesPerActivate::samples 57696
-system.physmem.bytesPerActivate::mean 317.478647
-system.physmem.bytesPerActivate::gmean 186.529934
-system.physmem.bytesPerActivate::stdev 335.962495
-system.physmem.bytesPerActivate::0-127 20572 35.66% 35.66%
-system.physmem.bytesPerActivate::128-255 14702 25.48% 61.14%
-system.physmem.bytesPerActivate::256-383 5653 9.80% 70.94%
-system.physmem.bytesPerActivate::384-511 3146 5.45% 76.39%
-system.physmem.bytesPerActivate::512-639 2423 4.20% 80.59%
-system.physmem.bytesPerActivate::640-767 1393 2.41% 83.00%
-system.physmem.bytesPerActivate::768-895 1271 2.20% 85.21%
-system.physmem.bytesPerActivate::896-1023 917 1.59% 86.79%
-system.physmem.bytesPerActivate::1024-1151 7619 13.21% 100.00%
-system.physmem.bytesPerActivate::total 57696
-system.physmem.rdPerTurnAround::samples 5793
-system.physmem.rdPerTurnAround::mean 28.926463
-system.physmem.rdPerTurnAround::stdev 588.910199
-system.physmem.rdPerTurnAround::0-2047 5792 99.98% 99.98%
-system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00%
-system.physmem.rdPerTurnAround::total 5793
-system.physmem.wrPerTurnAround::samples 5793
-system.physmem.wrPerTurnAround::mean 20.479026
-system.physmem.wrPerTurnAround::gmean 18.531275
-system.physmem.wrPerTurnAround::stdev 14.943169
-system.physmem.wrPerTurnAround::16-19 5068 87.48% 87.48%
-system.physmem.wrPerTurnAround::20-23 43 0.74% 88.23%
-system.physmem.wrPerTurnAround::24-27 40 0.69% 88.92%
-system.physmem.wrPerTurnAround::28-31 53 0.91% 89.83%
-system.physmem.wrPerTurnAround::32-35 289 4.99% 94.82%
-system.physmem.wrPerTurnAround::36-39 23 0.40% 95.22%
-system.physmem.wrPerTurnAround::40-43 16 0.28% 95.49%
-system.physmem.wrPerTurnAround::44-47 6 0.10% 95.60%
-system.physmem.wrPerTurnAround::48-51 5 0.09% 95.68%
-system.physmem.wrPerTurnAround::52-55 2 0.03% 95.72%
-system.physmem.wrPerTurnAround::56-59 1 0.02% 95.74%
-system.physmem.wrPerTurnAround::60-63 5 0.09% 95.82%
-system.physmem.wrPerTurnAround::64-67 158 2.73% 98.55%
-system.physmem.wrPerTurnAround::68-71 7 0.12% 98.67%
-system.physmem.wrPerTurnAround::72-75 5 0.09% 98.76%
-system.physmem.wrPerTurnAround::76-79 5 0.09% 98.84%
-system.physmem.wrPerTurnAround::80-83 8 0.14% 98.98%
-system.physmem.wrPerTurnAround::84-87 5 0.09% 99.07%
-system.physmem.wrPerTurnAround::96-99 2 0.03% 99.10%
-system.physmem.wrPerTurnAround::104-107 2 0.03% 99.14%
-system.physmem.wrPerTurnAround::108-111 9 0.16% 99.29%
-system.physmem.wrPerTurnAround::116-119 2 0.03% 99.33%
-system.physmem.wrPerTurnAround::120-123 1 0.02% 99.34%
-system.physmem.wrPerTurnAround::124-127 2 0.03% 99.38%
-system.physmem.wrPerTurnAround::128-131 8 0.14% 99.52%
-system.physmem.wrPerTurnAround::132-135 5 0.09% 99.60%
-system.physmem.wrPerTurnAround::136-139 5 0.09% 99.69%
-system.physmem.wrPerTurnAround::140-143 6 0.10% 99.79%
-system.physmem.wrPerTurnAround::144-147 1 0.02% 99.81%
-system.physmem.wrPerTurnAround::156-159 1 0.02% 99.83%
-system.physmem.wrPerTurnAround::160-163 4 0.07% 99.90%
-system.physmem.wrPerTurnAround::172-175 2 0.03% 99.93%
-system.physmem.wrPerTurnAround::180-183 2 0.03% 99.97%
-system.physmem.wrPerTurnAround::184-187 1 0.02% 99.98%
-system.physmem.wrPerTurnAround::188-191 1 0.02% 100.00%
-system.physmem.wrPerTurnAround::total 5793
-system.physmem.totQLat 4571022000
-system.physmem.totMemAccLat 7713015750
-system.physmem.totBusLat 837865000
-system.physmem.avgQLat 27277.80
-system.physmem.avgBusLat 5000.00
-system.physmem.avgMemAccLat 46027.80
-system.physmem.avgRdBW 3.69
-system.physmem.avgWrBW 2.61
-system.physmem.avgRdBWSys 3.50
-system.physmem.avgWrBWSys 2.61
-system.physmem.peakBW 12800.00
-system.physmem.busUtil 0.05
-system.physmem.busUtilRead 0.03
-system.physmem.busUtilWrite 0.02
-system.physmem.avgRdQLen 1.00
-system.physmem.avgWrQLen 24.59
-system.physmem.readRowHits 138588
-system.physmem.writeRowHits 89923
-system.physmem.readRowHitRate 82.70
-system.physmem.writeRowHitRate 75.79
-system.physmem.avgGap 10010492.43
-system.physmem.pageHitRate 79.84
-system.physmem_0.actEnergy 209923140
-system.physmem_0.preEnergy 111576795
-system.physmem_0.readEnergy 639494100
-system.physmem_0.writeEnergy 313387920
-system.physmem_0.refreshEnergy 6670687920.000002
-system.physmem_0.actBackEnergy 4809422880
-system.physmem_0.preBackEnergy 413752800
-system.physmem_0.actPowerDownEnergy 13946789640
-system.physmem_0.prePowerDownEnergy 9398763360
-system.physmem_0.selfRefreshEnergy 682626603840
-system.physmem_0.totalEnergy 719142677895
-system.physmem_0.averagePower 247.527383
-system.physmem_0.totalIdleTime 2893152718000
-system.physmem_0.memoryStateTime::IDLE 777067000
-system.physmem_0.memoryStateTime::REF 2836732000
-system.physmem_0.memoryStateTime::SREF 2838614964500
-system.physmem_0.memoryStateTime::PRE_PDN 24475941750
-system.physmem_0.memoryStateTime::ACT 8015385500
-system.physmem_0.memoryStateTime::ACT_PDN 30585446750
-system.physmem_1.actEnergy 202033440
-system.physmem_1.preEnergy 107379525
-system.physmem_1.readEnergy 556977120
-system.physmem_1.writeEnergy 305886780
-system.physmem_1.refreshEnergy 6674990400.000002
-system.physmem_1.actBackEnergy 4528240170
-system.physmem_1.preBackEnergy 413409600
-system.physmem_1.actPowerDownEnergy 13646578620
-system.physmem_1.prePowerDownEnergy 9540468000
-system.physmem_1.selfRefreshEnergy 682917113460
-system.physmem_1.totalEnergy 718894076985
-system.physmem_1.averagePower 247.441816
-system.physmem_1.totalIdleTime 2894296337500
-system.physmem_1.memoryStateTime::IDLE 785533000
-system.physmem_1.memoryStateTime::REF 2839260000
-system.physmem_1.memoryStateTime::SREF 2839524651500
-system.physmem_1.memoryStateTime::PRE_PDN 24844849250
-system.physmem_1.memoryStateTime::ACT 7384341000
-system.physmem_1.memoryStateTime::ACT_PDN 29926902750
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.nvmem.bytes_read::cpu.inst 20
-system.realview.nvmem.bytes_read::total 20
-system.realview.nvmem.bytes_inst_read::cpu.inst 20
-system.realview.nvmem.bytes_inst_read::total 20
-system.realview.nvmem.num_reads::cpu.inst 5
-system.realview.nvmem.num_reads::total 5
-system.realview.nvmem.bw_read::cpu.inst 7
-system.realview.nvmem.bw_read::total 7
-system.realview.nvmem.bw_inst_read::cpu.inst 7
-system.realview.nvmem.bw_inst_read::total 7
-system.realview.nvmem.bw_total::cpu.inst 7
-system.realview.nvmem.bw_total::total 7
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.bridge.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.cf0.dma_read_full_pages 0
-system.cf0.dma_read_bytes 1024
-system.cf0.dma_read_txs 1
-system.cf0.dma_write_full_pages 540
-system.cf0.dma_write_bytes 2318336
-system.cf0.dma_write_txs 631
-system.cpu_clk_domain.clock 500
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
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-system.iocache.demand_accesses::total 36434
-system.iocache.overall_accesses::realview.ide 36434
-system.iocache.overall_accesses::total 36434
-system.iocache.ReadReq_miss_rate::realview.ide 1
-system.iocache.ReadReq_miss_rate::total 1
-system.iocache.WriteLineReq_miss_rate::realview.ide 1
-system.iocache.WriteLineReq_miss_rate::total 1
-system.iocache.demand_miss_rate::realview.ide 1
-system.iocache.demand_miss_rate::total 1
-system.iocache.overall_miss_rate::realview.ide 1
-system.iocache.overall_miss_rate::total 1
-system.iocache.ReadReq_avg_miss_latency::realview.ide 162220.838095
-system.iocache.ReadReq_avg_miss_latency::total 162220.838095
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120806.834198
-system.iocache.WriteLineReq_avg_miss_latency::total 120806.834198
-system.iocache.demand_avg_miss_latency::realview.ide 121045.538179
-system.iocache.demand_avg_miss_latency::total 121045.538179
-system.iocache.overall_avg_miss_latency::realview.ide 121045.538179
-system.iocache.overall_avg_miss_latency::total 121045.538179
-system.iocache.blocked_cycles::no_mshrs 208
-system.iocache.blocked_cycles::no_targets 0
-system.iocache.blocked::no_mshrs 4
-system.iocache.blocked::no_targets 0
-system.iocache.avg_blocked_cycles::no_mshrs 52
-system.iocache.avg_blocked_cycles::no_targets nan
-system.iocache.writebacks::writebacks 36190
-system.iocache.writebacks::total 36190
-system.iocache.ReadReq_mshr_misses::realview.ide 210
-system.iocache.ReadReq_mshr_misses::total 210
-system.iocache.WriteLineReq_mshr_misses::realview.ide 36224
-system.iocache.WriteLineReq_mshr_misses::total 36224
-system.iocache.demand_mshr_misses::realview.ide 36434
-system.iocache.demand_mshr_misses::total 36434
-system.iocache.overall_mshr_misses::realview.ide 36434
-system.iocache.overall_mshr_misses::total 36434
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 23566376
-system.iocache.ReadReq_mshr_miss_latency::total 23566376
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2563140504
-system.iocache.WriteLineReq_mshr_miss_latency::total 2563140504
-system.iocache.demand_mshr_miss_latency::realview.ide 2586706880
-system.iocache.demand_mshr_miss_latency::total 2586706880
-system.iocache.overall_mshr_miss_latency::realview.ide 2586706880
-system.iocache.overall_mshr_miss_latency::total 2586706880
-system.iocache.ReadReq_mshr_miss_rate::realview.ide 1
-system.iocache.ReadReq_mshr_miss_rate::total 1
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1
-system.iocache.WriteLineReq_mshr_miss_rate::total 1
-system.iocache.demand_mshr_miss_rate::realview.ide 1
-system.iocache.demand_mshr_miss_rate::total 1
-system.iocache.overall_mshr_miss_rate::realview.ide 1
-system.iocache.overall_mshr_miss_rate::total 1
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112220.838095
-system.iocache.ReadReq_avg_mshr_miss_latency::total 112220.838095
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70758.074867
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70758.074867
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 70997.059889
-system.iocache.demand_avg_mshr_miss_latency::total 70997.059889
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 70997.059889
-system.iocache.overall_avg_mshr_miss_latency::total 70997.059889
-system.membus.snoop_filter.tot_requests 319999
-system.membus.snoop_filter.hit_single_requests 129537
-system.membus.snoop_filter.hit_multi_requests 496
-system.membus.snoop_filter.tot_snoops 0
-system.membus.snoop_filter.hit_single_snoops 0
-system.membus.snoop_filter.hit_multi_snoops 0
-system.membus.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.membus.trans_dist::ReadReq 40140
-system.membus.trans_dist::ReadResp 70408
-system.membus.trans_dist::WriteReq 27579
-system.membus.trans_dist::WriteResp 27579
-system.membus.trans_dist::WritebackDirty 118160
-system.membus.trans_dist::CleanEvict 6837
-system.membus.trans_dist::UpgradeReq 128
-system.membus.trans_dist::SCUpgradeReq 2
-system.membus.trans_dist::UpgradeResp 2
-system.membus.trans_dist::ReadExReq 128317
-system.membus.trans_dist::ReadExResp 128317
-system.membus.trans_dist::ReadSharedReq 30268
-system.membus.trans_dist::InvalidateReq 36224
-system.membus.trans_dist::InvalidateResp 4315
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105458
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2064
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 433106
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 540638
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72849
-system.membus.pkt_count_system.iocache.mem_side::total 72849
-system.membus.pkt_count::total 613487
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159115
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4128
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15420220
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15583483
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120
-system.membus.pkt_size_system.iocache.mem_side::total 2317120
-system.membus.pkt_size::total 17900603
-system.membus.snoops 4789
-system.membus.snoopTraffic 30208
-system.membus.snoop_fanout::samples 262658
-system.membus.snoop_fanout::mean 0.018385
-system.membus.snoop_fanout::stdev 0.134340
-system.membus.snoop_fanout::underflows 0 0.00% 0.00%
-system.membus.snoop_fanout::0 257829 98.16% 98.16%
-system.membus.snoop_fanout::1 4829 1.84% 100.00%
-system.membus.snoop_fanout::2 0 0.00% 100.00%
-system.membus.snoop_fanout::overflows 0 0.00% 100.00%
-system.membus.snoop_fanout::min_value 0
-system.membus.snoop_fanout::max_value 1
-system.membus.snoop_fanout::total 262658
-system.membus.reqLayer0.occupancy 90452000
-system.membus.reqLayer0.utilization 0.0
-system.membus.reqLayer1.occupancy 7500
-system.membus.reqLayer1.utilization 0.0
-system.membus.reqLayer2.occupancy 1690500
-system.membus.reqLayer2.utilization 0.0
-system.membus.reqLayer5.occupancy 822823297
-system.membus.reqLayer5.utilization 0.0
-system.membus.respLayer2.occupancy 948595750
-system.membus.respLayer2.utilization 0.0
-system.membus.respLayer3.occupancy 5614930
-system.membus.respLayer3.utilization 0.0
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.dcc.osc_cpu.clock 16667
-system.realview.dcc.osc_ddr.clock 25000
-system.realview.dcc.osc_hsbm.clock 25000
-system.realview.dcc.osc_pxl.clock 42105
-system.realview.dcc.osc_smb.clock 20000
-system.realview.dcc.osc_sys.clock 16667
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.ethernet.descDMAReads 0
-system.realview.ethernet.descDMAWrites 0
-system.realview.ethernet.descDmaReadBytes 0
-system.realview.ethernet.descDmaWriteBytes 0
-system.realview.ethernet.postedSwi 0
-system.realview.ethernet.coalescedSwi nan
-system.realview.ethernet.totalSwi 0
-system.realview.ethernet.postedRxIdle 0
-system.realview.ethernet.coalescedRxIdle nan
-system.realview.ethernet.totalRxIdle 0
-system.realview.ethernet.postedRxOk 0
-system.realview.ethernet.coalescedRxOk nan
-system.realview.ethernet.totalRxOk 0
-system.realview.ethernet.postedRxDesc 0
-system.realview.ethernet.coalescedRxDesc nan
-system.realview.ethernet.totalRxDesc 0
-system.realview.ethernet.postedTxOk 0
-system.realview.ethernet.coalescedTxOk nan
-system.realview.ethernet.totalTxOk 0
-system.realview.ethernet.postedTxIdle 0
-system.realview.ethernet.coalescedTxIdle nan
-system.realview.ethernet.totalTxIdle 0
-system.realview.ethernet.postedTxDesc 0
-system.realview.ethernet.coalescedTxDesc nan
-system.realview.ethernet.totalTxDesc 0
-system.realview.ethernet.postedRxOrn 0
-system.realview.ethernet.coalescedRxOrn nan
-system.realview.ethernet.totalRxOrn 0
-system.realview.ethernet.coalescedTotal nan
-system.realview.ethernet.postedInterrupts 0
-system.realview.ethernet.droppedPackets 0
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.mcc.osc_clcd.clock 42105
-system.realview.mcc.osc_mcc.clock 20000
-system.realview.mcc.osc_peripheral.clock 41667
-system.realview.mcc.osc_system_bus.clock 41667
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2905305537500
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500
-
----------- End Simulation Statistics ----------
+++ /dev/null
-Booting Linux on physical CPU 0x0\r
-\rInitializing cgroup subsys cpuset\r
-\rLinux version 3.13.0-rc2 (tony@vamp) (gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4) ) #1 SMP PREEMPT Mon Oct 13 15:09:23 EDT 2014\r
-\rKernel was built at commit id ''\r
-\rCPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d\r
-\rCPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache\r
-\rMachine model: V2P-CA15\r
-\rbootconsole [earlycon0] enabled\r
-\rMemory policy: Data cache writealloc\r
-\rkdebugv2m: Following are test values to confirm proper working\r
-\rkdebugv2m: Ranges 42000000 0 \r
-\rkdebugv2m: Regs 30000000 1000000 \r
-\rkdebugv2m: Virtual-Reg f0000000 \r
-\rkdebugv2m: pci node addr_cells 3 \r
-\rkdebugv2m: pci node size_cells 2 \r
-\rkdebugv2m: motherboard addr_cells 2 \r
-\rOn node 0 totalpages: 65536\r
-\rfree_area_init_node: node 0, pgdat 8072dcc0, node_mem_map 8078f000\r
-\r Normal zone: 512 pages used for memmap\r
-\r Normal zone: 0 pages reserved\r
-\r Normal zone: 65536 pages, LIFO batch:15\r
-\rsched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns\r
-\rPERCPU: Embedded 8 pages/cpu @80996000 s11648 r8192 d12928 u32768\r
-\rpcpu-alloc: s11648 r8192 d12928 u32768 alloc=8*4096\r
-\rpcpu-alloc: [0] 0 \r
-\rBuilt 1 zonelists in Zone order, mobility grouping on. Total pages: 65024\r
-\rKernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
-\rPID hash table entries: 1024 (order: 0, 4096 bytes)\r
-\rDentry cache hash table entries: 32768 (order: 5, 131072 bytes)\r
-\rInode-cache hash table entries: 16384 (order: 4, 65536 bytes)\r
-\rMemory: 235688K/262144K available (5248K kernel code, 249K rwdata, 1540K rodata, 295K init, 368K bss, 26456K reserved, 0K highmem)\r
-\rVirtual kernel memory layout:\r
-\r vector : 0xffff0000 - 0xffff1000 ( 4 kB)\r
-\r fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)\r
-\r vmalloc : 0x90800000 - 0xff000000 (1768 MB)\r
-\r lowmem : 0x80000000 - 0x90000000 ( 256 MB)\r
-\r pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)\r
-\r modules : 0x7f000000 - 0x7fe00000 ( 14 MB)\r
-\r .text : 0x80008000 - 0x806a942c (6790 kB)\r
-\r .init : 0x806aa000 - 0x806f3d80 ( 296 kB)\r
-\r .data : 0x806f4000 - 0x80732754 ( 250 kB)\r
-\r .bss : 0x80732754 - 0x8078e9d8 ( 369 kB)\r
-\rSLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1\r
-\rPreemptible hierarchical RCU implementation.\r
-\r RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1.\r
-\rNR_IRQS:16 nr_irqs:16 16\r
-\rArchitected cp15 timer(s) running at 25.16MHz (phys).\r
-\rsched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 2730666655744ns\r
-\rSwitching to timer-based delay loop\r
-\rConsole: colour dummy device 80x30\r
-\rCalibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-\rpid_max: default: 32768 minimum: 301\r
-\rMount-cache hash table entries: 512\r
-\rCPU: Testing write buffer coherency: ok\r
-\rCPU0: update cpu_power 1024\r
-\rCPU0: thread -1, cpu 0, socket 0, mpidr 80000000\r
-\rSetting up static identity map for 0x804fee68 - 0x804fee9c\r
-\rBrought up 1 CPUs\r
-\rSMP: Total of 1 processors activated.\r
-\rCPU: All CPU(s) started in SVC mode.\r
-\rVFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0\r
-\rNET: Registered protocol family 16\r
-\rDMA: preallocated 256 KiB pool for atomic coherent allocations\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/aaci@040000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/mmci@050000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-\rof_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-\rhw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 0\r
-\rhw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 0\r
-\rhw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0\r
-\rhw-breakpoint: CPU 0 failed to disable vector catch\r
-\rSerial: AMBA PL011 UART driver\r
-\r1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-\rconsole [ttyAMA0] enabled\r
-console [ttyAMA0] enabled\r
-\rbootconsole [earlycon0] disabled\r
-bootconsole [earlycon0] disabled\r
-\rPCI host bridge to bus 0000:00\r
-pci_bus 0000:00: root bus resource [io 0x0000-0xffffffff]\r
-pci_bus 0000:00: root bus resource [mem 0x00000000-0xffffffff]\r
-pci_bus 0000:00: root bus resource [bus 00-ff]\r
-pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-PCI: bus0: Fast back to back transfers disabled\r
-pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-pci 0000:00:01.0: BAR 4: assigned [io 0x2f000000-0x2f00000f]\r
-pci 0000:00:01.0: BAR 0: assigned [io 0x2f000010-0x2f000017]\r
-pci 0000:00:01.0: BAR 2: assigned [io 0x2f000018-0x2f00001f]\r
-pci 0000:00:01.0: BAR 1: assigned [io 0x2f000020-0x2f000023]\r
-pci 0000:00:01.0: BAR 3: assigned [io 0x2f000024-0x2f000027]\r
-pci_bus 0000:00: resource 4 [io 0x0000-0xffffffff]\r
-pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff]\r
-PCI map irq: slot 0, pin 1, devslot 0, irq: 68\r
-PCI map irq: slot 1, pin 2, devslot 1, irq: 69\r
-bio: create slab <bio-0> at 0\r
-vgaarb: loaded\r
-SCSI subsystem initialized\r
-libata version 3.00 loaded.\r
-usbcore: registered new interface driver usbfs\r
-usbcore: registered new interface driver hub\r
-usbcore: registered new device driver usb\r
-pps_core: LinuxPPS API ver. 1 registered\r
-pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-PTP clock support registered\r
-Advanced Linux Sound Architecture Driver Initialized.\r
-Switched to clocksource arch_sys_counter\r
-NET: Registered protocol family 2\r
-TCP established hash table entries: 2048 (order: 1, 8192 bytes)\r
-TCP bind hash table entries: 2048 (order: 2, 16384 bytes)\r
-TCP: Hash tables configured (established 2048 bind 2048)\r
-TCP: reno registered\r
-UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-NET: Registered protocol family 1\r
-RPC: Registered named UNIX socket transport module.\r
-RPC: Registered udp transport module.\r
-RPC: Registered tcp transport module.\r
-RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-PCI: CLS 64 bytes, default 64\r
-hw perfevents: enabled with ARMv7_Cortex_A15 PMU driver, 1 counters available\r
-jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.\r
-msgmni has been set to 460\r
-io scheduler noop registered (default)\r
-brd: module loaded\r
-loop: module loaded\r
-ata_piix 0000:00:01.0: version 2.13\r
-PCI: enabling device 0000:00:01.0 (0040 -> 0041)\r
-scsi0 : ata_piix\r
-scsi1 : ata_piix\r
-ata1: PATA max UDMA/33 cmd 0x2f000010 ctl 0x2f000020 bmdma 0x2f000000 irq 69\r
-ata2: PATA max UDMA/33 cmd 0x2f000018 ctl 0x2f000024 bmdma 0x2f000008 irq 69\r
-e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI\r
-e100: Copyright(c) 1999-2006 Intel Corporation\r
-e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-PCI: enabling device 0000:00:00.0 (0040 -> 0042)\r
-ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-ata1.00: 1048320 sectors, multi 0: LBA \r
-ata1.00: configured for UDMA/33\r
-scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)\r
-sd 0:0:0:0: [sda] Write Protect is off\r
-sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
- sda: sda1\r
-sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-sd 0:0:0:0: [sda] Attached SCSI disk\r
-e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-e1000e: Copyright(c) 1999 - 2013 Intel Corporation.\r
-igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-igb: Copyright (c) 2007-2013 Intel Corporation.\r
-igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.0.2-k\r
-igbvf: Copyright (c) 2009 - 2012 Intel Corporation.\r
-ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver - version 3.15.1-k\r
-ixgbe: Copyright (c) 1999-2013 Intel Corporation.\r
-ixgbevf: Intel(R) 10 Gigabit PCI Express Virtual Function Network Driver - version 2.11.3-k\r
-ixgbevf: Copyright (c) 2009 - 2012 Intel Corporation.\r
-ixgb: Intel(R) PRO/10GbE Network Driver - version 1.0.135-k2-NAPI\r
-ixgb: Copyright (c) 1999-2008 Intel Corporation.\r
-smsc911x: Driver version 2008-10-21\r
-smsc911x 1a000000.ethernet (unregistered net_device): couldn't get clock -2\r
-nxp-isp1760 1b000000.usb: NXP ISP1760 USB Host Controller\r
-nxp-isp1760 1b000000.usb: new USB bus registered, assigned bus number 1\r
-nxp-isp1760 1b000000.usb: Scratch test failed.\r
-nxp-isp1760 1b000000.usb: can't setup: -19\r
-nxp-isp1760 1b000000.usb: USB bus 1 deregistered\r
-usbcore: registered new interface driver usb-storage\r
-mousedev: PS/2 mouse device common for all mice\r
-rtc-pl031 1c170000.rtc: rtc core: registered pl031 as rtc0\r
-usbcore: registered new interface driver usbhid\r
-usbhid: USB HID core driver\r
-ashmem: initialized\r
-logger: created 256K log 'log_main'\r
-logger: created 256K log 'log_events'\r
-logger: created 256K log 'log_radio'\r
-logger: created 256K log 'log_system'\r
-oprofile: using timer interrupt.\r
-TCP: cubic registered\r
-NET: Registered protocol family 10\r
-NET: Registered protocol family 17\r
-rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 00:00:00 UTC (1230768000)\r
-ALSA device list:\r
- No soundcards found.\r
-\0input: AT Raw Set 2 keyboard as /devices/smb.14/motherboard.15/iofpga.17/1c060000.kmi/serio0/input/input0\r
-input: touchkitPS/2 eGalax Touchscreen as /devices/smb.14/motherboard.15/iofpga.17/1c070000.kmi/serio1/input/input2\r
-VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-Freeing unused kernel memory: 292K (806aa000 - 806f3000)\r
-\rinit started: BusyBox v1.15.3 (2010-05-07 01:27:07 BST)\r
-\rstarting pid 673, tty '': '/etc/rc.d/rc.local'\r
-warning: can't open /etc/mtab: No such file or directory\r
-Thu Jan 1 00:00:02 UTC 2009\r
-S: devpts\r
-Thu Jan 1 00:00:02 UTC 2009\r
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxX86System
-children=acpi_description_table_pointer apicbridge bridge clk_domain cpu cpu_clk_domain dvfs_handler e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache membus pc physmem smbios_table voltage_domain
-acpi_description_table_pointer=system.acpi_description_table_pointer
-boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
-cache_line_size=64
-clk_domain=system.clk_domain
-e820_table=system.e820_table
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-intel_mp_pointer=system.intel_mp_pointer
-intel_mp_table=system.intel_mp_table
-kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
-kernel_addr_check=true
-load_addr_mask=18446744073709551615
-load_offset=0
-mem_mode=atomic
-mem_ranges=0:134217727
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
-smbios_table=system.smbios_table
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.acpi_description_table_pointer]
-type=X86ACPIRSDP
-children=xsdt
-eventq_index=0
-oem_id=
-revision=2
-rsdt=Null
-xsdt=system.acpi_description_table_pointer.xsdt
-
-[system.acpi_description_table_pointer.xsdt]
-type=X86ACPIXSDT
-creator_id=
-creator_revision=0
-entries=
-eventq_index=0
-oem_id=
-oem_revision=0
-oem_table_id=
-
-[system.apicbridge]
-type=Bridge
-clk_domain=system.clk_domain
-delay=50000
-eventq_index=0
-ranges=11529215046068469760:11529215046068473855
-req_size=16
-resp_size=16
-master=system.membus.slave[0]
-slave=system.iobus.master[0]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-delay=50000
-eventq_index=0
-ranges=3221225472:4294901760 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=apic_clk_domain dcache dtb dtb_walker_cache icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.apic_clk_domain]
-type=DerivedClockDomain
-clk_divider=16
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=32768
-
-[system.cpu.dtb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-port=system.cpu.dtb_walker_cache.cpu_side
-
-[system.cpu.dtb_walker_cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=10
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=1024
-system=system
-tags=system.cpu.dtb_walker_cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dtb.walker.port
-mem_side=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.dtb_walker_cache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=1024
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=32768
-
-[system.cpu.interrupts]
-type=X86LocalApic
-clk_domain=system.cpu.apic_clk_domain
-eventq_index=0
-int_latency=1000
-pio_addr=2305843009213693952
-pio_latency=100000
-system=system
-int_master=system.membus.slave[3]
-int_slave=system.membus.master[2]
-pio=system.membus.master[1]
-
-[system.cpu.isa]
-type=X86ISA
-eventq_index=0
-
-[system.cpu.itb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-port=system.cpu.itb_walker_cache.cpu_side
-
-[system.cpu.itb_walker_cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=10
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=1024
-system=system
-tags=system.cpu.itb_walker_cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.itb.walker.port
-mem_side=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.itb_walker_cache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=1024
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=20
-sequential_access=false
-size=4194304
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-point_of_coherency=false
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.e820_table]
-type=X86E820Table
-children=entries0 entries1 entries2 entries3 entries4
-entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 system.e820_table.entries4
-eventq_index=0
-
-[system.e820_table.entries0]
-type=X86E820Entry
-addr=0
-eventq_index=0
-range_type=1
-size=654336
-
-[system.e820_table.entries1]
-type=X86E820Entry
-addr=654336
-eventq_index=0
-range_type=2
-size=394240
-
-[system.e820_table.entries2]
-type=X86E820Entry
-addr=1048576
-eventq_index=0
-range_type=1
-size=133169152
-
-[system.e820_table.entries3]
-type=X86E820Entry
-addr=134217728
-eventq_index=0
-range_type=2
-size=3087007744
-
-[system.e820_table.entries4]
-type=X86E820Entry
-addr=4294901760
-eventq_index=0
-range_type=2
-size=65536
-
-[system.intel_mp_pointer]
-type=X86IntelMPFloatingPointer
-default_config=0
-eventq_index=0
-imcr_present=true
-spec_rev=4
-
-[system.intel_mp_table]
-type=X86IntelMPConfigTable
-children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries
-base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32
-eventq_index=0
-ext_entries=system.intel_mp_table.ext_entries
-local_apic=4276092928
-oem_id=
-oem_table_addr=0
-oem_table_size=0
-product_id=
-spec_rev=4
-
-[system.intel_mp_table.base_entries00]
-type=X86IntelMPProcessor
-bootstrap=true
-enable=true
-eventq_index=0
-family=0
-feature_flags=0
-local_apic_id=0
-local_apic_version=20
-model=0
-stepping=0
-
-[system.intel_mp_table.base_entries01]
-type=X86IntelMPIOAPIC
-address=4273995776
-enable=true
-eventq_index=0
-id=1
-version=17
-
-[system.intel_mp_table.base_entries02]
-type=X86IntelMPBus
-bus_id=0
-bus_type=PCI
-eventq_index=0
-
-[system.intel_mp_table.base_entries03]
-type=X86IntelMPBus
-bus_id=1
-bus_type=ISA
-eventq_index=0
-
-[system.intel_mp_table.base_entries04]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=16
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=16
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries05]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries06]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=2
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries07]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries08]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=1
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries09]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries10]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=3
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries11]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries12]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=4
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries13]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries14]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=5
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries15]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries16]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=6
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries17]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries18]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=7
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries19]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries20]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=8
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries21]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries22]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=9
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries23]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries24]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=10
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries25]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries26]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=11
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries27]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries28]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=12
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries29]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries30]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=13
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries31]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries32]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=14
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.ext_entries]
-type=X86IntelMPBusHierarchy
-bus_id=1
-eventq_index=0
-parent_bus=0
-subtractive_decode=true
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-response_latency=2
-use_default_range=false
-width=16
-default=system.pc.pci_host.pio
-master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
-slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=0:134217727
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[18]
-mem_side=system.membus.slave[4]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-hit_latency=50
-sequential_access=false
-size=1024
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder
-clk_domain=system.clk_domain
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-point_of_coherency=true
-response_latency=2
-snoop_filter=Null
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.physmem.port
-slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=0
-pio_latency=100000
-pio_size=8
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.default
-
-[system.pc]
-type=Pc
-children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pci_host south_bridge
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.pc.behind_pci]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854779128
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.pc.com_1]
-type=Uart8250
-children=terminal
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=9223372036854776824
-pio_latency=100000
-platform=system.pc
-system=system
-terminal=system.pc.com_1.terminal
-pio=system.iobus.master[13]
-
-[system.pc.com_1.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.pc.fake_com_2]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776568
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[14]
-
-[system.pc.fake_com_3]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776808
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[15]
-
-[system.pc.fake_com_4]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776552
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[16]
-
-[system.pc.fake_floppy]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776818
-pio_latency=100000
-pio_size=2
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[17]
-
-[system.pc.i_dont_exist1]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854775936
-pio_latency=100000
-pio_size=1
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[10]
-
-[system.pc.i_dont_exist2]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776045
-pio_latency=100000
-pio_size=1
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[11]
-
-[system.pc.pci_host]
-type=GenericPciHost
-clk_domain=system.clk_domain
-conf_base=13835058055282163712
-conf_device_bits=8
-conf_size=16777216
-eventq_index=0
-pci_dma_base=0
-pci_mem_base=0
-pci_pio_base=9223372036854775808
-platform=system.pc
-system=system
-pio=system.iobus.default
-
-[system.pc.south_bridge]
-type=SouthBridge
-children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
-cmos=system.pc.south_bridge.cmos
-dma1=system.pc.south_bridge.dma1
-eventq_index=0
-io_apic=system.pc.south_bridge.io_apic
-keyboard=system.pc.south_bridge.keyboard
-pic1=system.pc.south_bridge.pic1
-pic2=system.pc.south_bridge.pic2
-pit=system.pc.south_bridge.pit
-platform=system.pc
-speaker=system.pc.south_bridge.speaker
-
-[system.pc.south_bridge.cmos]
-type=Cmos
-children=int_pin
-clk_domain=system.clk_domain
-eventq_index=0
-int_pin=system.pc.south_bridge.cmos.int_pin
-pio_addr=9223372036854775920
-pio_latency=100000
-system=system
-time=Sun Jan 1 00:00:00 2012
-pio=system.iobus.master[1]
-
-[system.pc.south_bridge.cmos.int_pin]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.dma1]
-type=I8237
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=9223372036854775808
-pio_latency=100000
-system=system
-pio=system.iobus.master[2]
-
-[system.pc.south_bridge.ide]
-type=IdeController
-children=disks0 disks1
-BAR0=496
-BAR0LegacyIO=true
-BAR0Size=8
-BAR1=1012
-BAR1LegacyIO=true
-BAR1Size=3
-BAR2=368
-BAR2LegacyIO=true
-BAR2Size=8
-BAR3=884
-BAR3LegacyIO=true
-BAR3Size=3
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=14
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=9223372036854775808
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=128
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
-eventq_index=0
-host=system.pc.pci_host
-io_shift=0
-pci_bus=0
-pci_dev=4
-pci_func=0
-pio_latency=30000
-system=system
-dma=system.iobus.slave[1]
-pio=system.iobus.master[3]
-
-[system.pc.south_bridge.ide.disks0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.pc.south_bridge.ide.disks0.image
-
-[system.pc.south_bridge.ide.disks0.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/dist/m5/system/disks/linux-x86.img
-read_only=true
-
-[system.pc.south_bridge.ide.disks1]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.pc.south_bridge.ide.disks1.image
-
-[system.pc.south_bridge.ide.disks1.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks1.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks1.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/dist/m5/system/disks/linux-bigswap2.img
-read_only=true
-
-[system.pc.south_bridge.int_lines0]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines0.sink
-source=system.pc.south_bridge.pic1.output
-
-[system.pc.south_bridge.int_lines0.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-eventq_index=0
-number=0
-
-[system.pc.south_bridge.int_lines1]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines1.sink
-source=system.pc.south_bridge.pic2.output
-
-[system.pc.south_bridge.int_lines1.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-eventq_index=0
-number=2
-
-[system.pc.south_bridge.int_lines2]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines2.sink
-source=system.pc.south_bridge.cmos.int_pin
-
-[system.pc.south_bridge.int_lines2.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic2
-eventq_index=0
-number=0
-
-[system.pc.south_bridge.int_lines3]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines3.sink
-source=system.pc.south_bridge.pit.int_pin
-
-[system.pc.south_bridge.int_lines3.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-eventq_index=0
-number=0
-
-[system.pc.south_bridge.int_lines4]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines4.sink
-source=system.pc.south_bridge.pit.int_pin
-
-[system.pc.south_bridge.int_lines4.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-eventq_index=0
-number=2
-
-[system.pc.south_bridge.int_lines5]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines5.sink
-source=system.pc.south_bridge.keyboard.keyboard_int_pin
-
-[system.pc.south_bridge.int_lines5.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-eventq_index=0
-number=1
-
-[system.pc.south_bridge.int_lines6]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines6.sink
-source=system.pc.south_bridge.keyboard.mouse_int_pin
-
-[system.pc.south_bridge.int_lines6.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-eventq_index=0
-number=12
-
-[system.pc.south_bridge.io_apic]
-type=I82094AA
-apic_id=1
-clk_domain=system.clk_domain
-eventq_index=0
-external_int_pic=system.pc.south_bridge.pic1
-int_latency=1000
-pio_addr=4273995776
-pio_latency=100000
-system=system
-int_master=system.iobus.slave[2]
-pio=system.iobus.master[9]
-
-[system.pc.south_bridge.keyboard]
-type=I8042
-children=keyboard_int_pin mouse_int_pin
-clk_domain=system.clk_domain
-command_port=9223372036854775908
-data_port=9223372036854775904
-eventq_index=0
-keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
-mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
-pio_addr=0
-pio_latency=100000
-system=system
-pio=system.iobus.master[4]
-
-[system.pc.south_bridge.keyboard.keyboard_int_pin]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.keyboard.mouse_int_pin]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.pic1]
-type=I8259
-children=output
-clk_domain=system.clk_domain
-eventq_index=0
-mode=I8259Master
-output=system.pc.south_bridge.pic1.output
-pio_addr=9223372036854775840
-pio_latency=100000
-slave=system.pc.south_bridge.pic2
-system=system
-pio=system.iobus.master[5]
-
-[system.pc.south_bridge.pic1.output]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.pic2]
-type=I8259
-children=output
-clk_domain=system.clk_domain
-eventq_index=0
-mode=I8259Slave
-output=system.pc.south_bridge.pic2.output
-pio_addr=9223372036854775968
-pio_latency=100000
-slave=Null
-system=system
-pio=system.iobus.master[6]
-
-[system.pc.south_bridge.pic2.output]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.pit]
-type=I8254
-children=int_pin
-clk_domain=system.clk_domain
-eventq_index=0
-int_pin=system.pc.south_bridge.pit.int_pin
-pio_addr=9223372036854775872
-pio_latency=100000
-system=system
-pio=system.iobus.master[7]
-
-[system.pc.south_bridge.pit.int_pin]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.speaker]
-type=PcSpeaker
-clk_domain=system.clk_domain
-eventq_index=0
-i8254=system.pc.south_bridge.pit
-pio_addr=9223372036854775905
-pio_latency=100000
-system=system
-pio=system.iobus.master[8]
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-port=system.membus.master[3]
-
-[system.smbios_table]
-type=X86SMBiosSMBiosTable
-children=structures
-eventq_index=0
-major_version=2
-minor_version=5
-structures=system.smbios_table.structures
-
-[system.smbios_table.structures]
-type=X86SMBiosBiosInformation
-characteristic_ext_bytes=
-characteristics=
-emb_cont_firmware_major=0
-emb_cont_firmware_minor=0
-eventq_index=0
-major=0
-minor=0
-release_date=06/08/2008
-rom_size=0
-starting_addr_segment=0
-vendor=
-version=
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: Reading current count from inactive timer.
-warn: Don't know what interrupt to clear for console.
-warn: x86 cpuid: unknown family 0x8086
-warn: Tried to clear PCI interrupt 14
-warn: Unknown mouse command 0xe1.
-warn: instruction 'wbinvd' unimplemented
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 21 2016 14:41:03
-gem5 started Jan 21 2016 14:41:54
-gem5 executing on zizzer, pid 17910
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic
-
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
- 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5112152301500 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 5.112152 # Number of seconds simulated
-sim_ticks 5112151729000 # Number of ticks simulated
-final_tick 5112151729000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1314225 # Simulator instruction rate (inst/s)
-host_op_rate 2690507 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 33581335470 # Simulator tick rate (ticks/s)
-host_mem_usage 609616 # Number of bytes of host memory used
-host_seconds 152.23 # Real time elapsed on the host
-sim_insts 200067055 # Number of instructions simulated
-sim_ops 409581065 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 846912 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10615104 # Number of bytes read from this memory
-system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11490752 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 846912 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 846912 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9269888 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9269888 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 13233 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 165861 # Number of read requests responded to by this memory
-system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 179543 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 144842 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 144842 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 165666 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2076445 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2247733 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 165666 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 165666 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1813305 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1813305 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1813305 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 165666 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2076445 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 5546 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4061038 # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.numCycles 10224307424 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu.committedInsts 200067055 # Number of instructions committed
-system.cpu.committedOps 409581065 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 374584177 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
-system.cpu.num_func_calls 2308905 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 40001120 # number of instructions that are conditional controls
-system.cpu.num_int_insts 374584177 # number of integer instructions
-system.cpu.num_fp_insts 48 # number of float instructions
-system.cpu.num_int_register_reads 682690924 # number of times the integer registers were read
-system.cpu.num_int_register_writes 323558192 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 48 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 233837631 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 157316591 # number of times the CC registers were written
-system.cpu.num_mem_refs 35667176 # number of memory refs
-system.cpu.num_load_insts 27243343 # Number of load instructions
-system.cpu.num_store_insts 8423833 # Number of store instructions
-system.cpu.num_idle_cycles 9770322790.617842 # Number of idle cycles
-system.cpu.num_busy_cycles 453984633.382158 # Number of busy cycles
-system.cpu.not_idle_fraction 0.044402 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.955598 # Percentage of idle cycles
-system.cpu.Branches 43152262 # Number of branches fetched
-system.cpu.op_class::No_OpClass 172765 0.04% 0.04% # Class of executed instruction
-system.cpu.op_class::IntAlu 373477070 91.18% 91.23% # Class of executed instruction
-system.cpu.op_class::IntMult 144574 0.04% 91.26% # Class of executed instruction
-system.cpu.op_class::IntDiv 123086 0.03% 91.29% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::FloatCvt 16 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction
-system.cpu.op_class::MemRead 27240752 6.65% 97.94% # Class of executed instruction
-system.cpu.op_class::MemWrite 8423833 2.06% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 409582096 # Class of executed instruction
-system.cpu.dcache.tags.replacements 1621909 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.999425 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 20181333 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 1622421 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 12.439024 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.999425 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 282 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 88837527 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 88837527 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 12023410 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 12023410 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 8096819 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 8096819 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 58904 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 58904 # number of SoftPFReq hits
-system.cpu.dcache.demand_hits::cpu.data 20120229 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 20120229 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 20179133 # number of overall hits
-system.cpu.dcache.overall_hits::total 20179133 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 905268 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 905268 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 316618 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 316618 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 402753 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 402753 # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data 1221886 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1221886 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1624639 # number of overall misses
-system.cpu.dcache.overall_misses::total 1624639 # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data 12928678 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 12928678 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 8413437 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 8413437 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 461657 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 461657 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 21342115 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 21342115 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 21803772 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 21803772 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070020 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.070020 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037632 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.037632 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872407 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.872407 # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.057252 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.057252 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.074512 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.074512 # miss rate for overall accesses
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 1535790 # number of writebacks
-system.cpu.dcache.writebacks::total 1535790 # number of writebacks
-system.cpu.dtb_walker_cache.tags.replacements 7749 # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse 5.014001 # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs 12936 # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs 7763 # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs 1.666366 # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 5100450626500 # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014001 # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313375 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313375 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses 52745 # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses 52745 # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12937 # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total 12937 # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12937 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total 12937 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12937 # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total 12937 # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8957 # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total 8957 # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8957 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total 8957 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8957 # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total 8957 # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21894 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total 21894 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21894 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total 21894 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21894 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total 21894 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409108 # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.409108 # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409108 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total 0.409108 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409108 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total 0.409108 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dtb_walker_cache.writebacks::writebacks 2897 # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total 2897 # number of writebacks
-system.cpu.icache.tags.replacements 792340 # number of replacements
-system.cpu.icache.tags.tagsinuse 510.662956 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 243675443 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 792852 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 307.340390 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 148913118500 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 510.662956 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.997389 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.997389 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 245261161 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 245261161 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 243675443 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 243675443 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 243675443 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 243675443 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 243675443 # number of overall hits
-system.cpu.icache.overall_hits::total 243675443 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 792859 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 792859 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 792859 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 792859 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 792859 # number of overall misses
-system.cpu.icache.overall_misses::total 792859 # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst 244468302 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 244468302 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 244468302 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 244468302 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 244468302 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 244468302 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003243 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.003243 # miss rate for ReadReq accesses
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-system.cpu.icache.demand_miss_rate::total 0.003243 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.003243 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.003243 # miss rate for overall accesses
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks 792340 # number of writebacks
-system.cpu.icache.writebacks::total 792340 # number of writebacks
-system.cpu.itb_walker_cache.tags.replacements 3586 # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse 3.026555 # Cycle average of tags in use
-system.cpu.itb_walker_cache.tags.total_refs 7763 # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.sampled_refs 3597 # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.tags.avg_refs 2.158187 # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5102137159500 # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026555 # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189160 # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total 0.189160 # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id
-system.cpu.itb_walker_cache.tags.tag_accesses 28899 # Number of tag accesses
-system.cpu.itb_walker_cache.tags.data_accesses 28899 # Number of data accesses
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7765 # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total 7765 # number of ReadReq hits
-system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
-system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7767 # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total 7767 # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7767 # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total 7767 # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4455 # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total 4455 # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4455 # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total 4455 # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4455 # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total 4455 # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12220 # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total 12220 # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12222 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total 12222 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12222 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total 12222 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.364566 # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.364566 # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.364507 # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total 0.364507 # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.364507 # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total 0.364507 # miss rate for overall accesses
-system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.itb_walker_cache.writebacks::writebacks 700 # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total 700 # number of writebacks
-system.cpu.l2cache.tags.replacements 106202 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 64823.935074 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 4340729 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 170162 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 25.509391 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 51928.967732 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002478 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.135114 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 2458.317021 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 10436.512729 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.792373 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.037511 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.159249 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.989135 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 63960 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3348 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20880 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39442 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975952 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 39254568 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 39254568 # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks 1539387 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total 1539387 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks 792329 # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total 792329 # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 312 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 312 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 179766 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 179766 # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 779612 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total 779612 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6533 # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 2871 # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1275070 # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total 1284474 # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker 6533 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker 2871 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst 779612 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 1454836 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2243852 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker 6533 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker 2871 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 779612 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 1454836 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2243852 # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 1349 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 1349 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 134647 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 134647 # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13234 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total 13234 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 1 # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data 32164 # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total 32170 # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst 13234 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 166811 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 180051 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst 13234 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 166811 # number of overall misses
-system.cpu.l2cache.overall_misses::total 180051 # number of overall misses
-system.cpu.l2cache.WritebackDirty_accesses::writebacks 1539387 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total 1539387 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks 792329 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total 792329 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1661 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 1661 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 314413 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 314413 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 792846 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total 792846 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 6534 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 2876 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1307234 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total 1316644 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6534 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker 2876 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst 792846 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1621647 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 2423903 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6534 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker 2876 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 792846 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1621647 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2423903 # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.812161 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.812161 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428249 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.428249 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016692 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016692 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000153 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.001739 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024605 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024433 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000153 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001739 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016692 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.102865 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.074281 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000153 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001739 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016692 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.102865 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.074281 # miss rate for overall accesses
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks 98175 # number of writebacks
-system.cpu.l2cache.writebacks::total 98175 # number of writebacks
-system.cpu.toL2Bus.snoop_filter.tot_requests 4856494 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425336 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11672 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 1230 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1230 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq 13857337 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 15971629 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 13943 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 13943 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 1539387 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 792340 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 93857 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2200 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2200 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 314418 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 314418 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 792859 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 1321433 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2378058 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32613747 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 12496 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 25663 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 35029964 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 101452736 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227551417 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 329920 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 758656 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 330092729 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 203468 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 18930863 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.001304 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.042949 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 18911304 99.90% 99.90% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 14428 0.08% 99.97% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 5131 0.03% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 18930863 # Request fanout histogram
-system.iobus.trans_dist::ReadReq 10012057 # Transaction distribution
-system.iobus.trans_dist::ReadResp 10012057 # Transaction distribution
-system.iobus.trans_dist::WriteReq 57724 # Transaction distribution
-system.iobus.trans_dist::WriteResp 57724 # Transaction distribution
-system.iobus.trans_dist::MessageReq 1696 # Transaction distribution
-system.iobus.trans_dist::MessageResp 1696 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 19999988 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1098 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27940 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 20044316 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95246 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95246 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3392 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3392 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 20142954 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 9999994 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2196 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13970 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 10028276 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027768 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027768 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6784 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6784 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 13062828 # Cumulative packet size per connected master and slave (bytes)
-system.iocache.tags.replacements 47568 # number of replacements
-system.iocache.tags.tagsinuse 0.042439 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 47584 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 4994875253009 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042439 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002652 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.002652 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 428607 # Number of tag accesses
-system.iocache.tags.data_accesses 428607 # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 903 # number of ReadReq misses
-system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 47623 # number of demand (read+write) misses
-system.iocache.demand_misses::total 47623 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 47623 # number of overall misses
-system.iocache.overall_misses::total 47623 # number of overall misses
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 47623 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 47623 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 47623 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 47623 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks 46667 # number of writebacks
-system.iocache.writebacks::total 46667 # number of writebacks
-system.membus.trans_dist::ReadReq 13857337 # Transaction distribution
-system.membus.trans_dist::ReadResp 13903644 # Transaction distribution
-system.membus.trans_dist::WriteReq 13943 # Transaction distribution
-system.membus.trans_dist::WriteResp 13943 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 144842 # Transaction distribution
-system.membus.trans_dist::CleanEvict 8802 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 2189 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 1650 # Transaction distribution
-system.membus.trans_dist::ReadExReq 134346 # Transaction distribution
-system.membus.trans_dist::ReadExResp 134346 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 46307 # Transaction distribution
-system.membus.trans_dist::MessageReq 1696 # Transaction distribution
-system.membus.trans_dist::MessageResp 1696 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution
-system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3392 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044316 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 469415 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28211975 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142814 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 142814 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 28358181 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028276 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17787200 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43211961 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3044480 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 3044480 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 46263225 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 14256182 # Request fanout histogram
-system.membus.snoop_fanout::mean 1.000119 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.010907 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 14254486 99.99% 99.99% # Request fanout histogram
-system.membus.snoop_fanout::2 1696 0.01% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 2 # Request fanout histogram
-system.membus.snoop_fanout::total 14256182 # Request fanout histogram
-system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
-system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxX86System
-children=acpi_description_table_pointer apicbridge bridge clk_domain cpu cpu_clk_domain dvfs_handler e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache membus pc physmem smbios_table voltage_domain
-acpi_description_table_pointer=system.acpi_description_table_pointer
-boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
-cache_line_size=64
-clk_domain=system.clk_domain
-e820_table=system.e820_table
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-intel_mp_pointer=system.intel_mp_pointer
-intel_mp_table=system.intel_mp_table
-kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
-kernel_addr_check=true
-load_addr_mask=18446744073709551615
-load_offset=0
-mem_mode=timing
-mem_ranges=0:134217727
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
-smbios_table=system.smbios_table
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.acpi_description_table_pointer]
-type=X86ACPIRSDP
-children=xsdt
-eventq_index=0
-oem_id=
-revision=2
-rsdt=Null
-xsdt=system.acpi_description_table_pointer.xsdt
-
-[system.acpi_description_table_pointer.xsdt]
-type=X86ACPIXSDT
-creator_id=
-creator_revision=0
-entries=
-eventq_index=0
-oem_id=
-oem_revision=0
-oem_table_id=
-
-[system.apicbridge]
-type=Bridge
-clk_domain=system.clk_domain
-delay=50000
-eventq_index=0
-ranges=11529215046068469760:11529215046068473855
-req_size=16
-resp_size=16
-master=system.membus.slave[0]
-slave=system.iobus.master[0]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-delay=50000
-eventq_index=0
-ranges=3221225472:4294901760 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=TimingSimpleCPU
-children=apic_clk_domain dcache dtb dtb_walker_cache icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-workload=
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.apic_clk_domain]
-type=DerivedClockDomain
-clk_divider=16
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=32768
-
-[system.cpu.dtb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-port=system.cpu.dtb_walker_cache.cpu_side
-
-[system.cpu.dtb_walker_cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=10
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=1024
-system=system
-tags=system.cpu.dtb_walker_cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dtb.walker.port
-mem_side=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.dtb_walker_cache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=1024
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=32768
-
-[system.cpu.interrupts]
-type=X86LocalApic
-clk_domain=system.cpu.apic_clk_domain
-eventq_index=0
-int_latency=1000
-pio_addr=2305843009213693952
-pio_latency=100000
-system=system
-int_master=system.membus.slave[3]
-int_slave=system.membus.master[2]
-pio=system.membus.master[1]
-
-[system.cpu.isa]
-type=X86ISA
-eventq_index=0
-
-[system.cpu.itb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-port=system.cpu.itb_walker_cache.cpu_side
-
-[system.cpu.itb_walker_cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=10
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=1024
-system=system
-tags=system.cpu.itb_walker_cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.itb.walker.port
-mem_side=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.itb_walker_cache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=1024
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=20
-sequential_access=false
-size=4194304
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-point_of_coherency=false
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.e820_table]
-type=X86E820Table
-children=entries0 entries1 entries2 entries3 entries4
-entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 system.e820_table.entries4
-eventq_index=0
-
-[system.e820_table.entries0]
-type=X86E820Entry
-addr=0
-eventq_index=0
-range_type=1
-size=654336
-
-[system.e820_table.entries1]
-type=X86E820Entry
-addr=654336
-eventq_index=0
-range_type=2
-size=394240
-
-[system.e820_table.entries2]
-type=X86E820Entry
-addr=1048576
-eventq_index=0
-range_type=1
-size=133169152
-
-[system.e820_table.entries3]
-type=X86E820Entry
-addr=134217728
-eventq_index=0
-range_type=2
-size=3087007744
-
-[system.e820_table.entries4]
-type=X86E820Entry
-addr=4294901760
-eventq_index=0
-range_type=2
-size=65536
-
-[system.intel_mp_pointer]
-type=X86IntelMPFloatingPointer
-default_config=0
-eventq_index=0
-imcr_present=true
-spec_rev=4
-
-[system.intel_mp_table]
-type=X86IntelMPConfigTable
-children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries
-base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32
-eventq_index=0
-ext_entries=system.intel_mp_table.ext_entries
-local_apic=4276092928
-oem_id=
-oem_table_addr=0
-oem_table_size=0
-product_id=
-spec_rev=4
-
-[system.intel_mp_table.base_entries00]
-type=X86IntelMPProcessor
-bootstrap=true
-enable=true
-eventq_index=0
-family=0
-feature_flags=0
-local_apic_id=0
-local_apic_version=20
-model=0
-stepping=0
-
-[system.intel_mp_table.base_entries01]
-type=X86IntelMPIOAPIC
-address=4273995776
-enable=true
-eventq_index=0
-id=1
-version=17
-
-[system.intel_mp_table.base_entries02]
-type=X86IntelMPBus
-bus_id=0
-bus_type=PCI
-eventq_index=0
-
-[system.intel_mp_table.base_entries03]
-type=X86IntelMPBus
-bus_id=1
-bus_type=ISA
-eventq_index=0
-
-[system.intel_mp_table.base_entries04]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=16
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=16
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries05]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries06]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=2
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries07]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries08]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=1
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries09]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries10]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=3
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries11]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries12]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=4
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries13]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries14]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=5
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries15]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries16]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=6
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries17]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries18]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=7
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries19]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries20]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=8
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries21]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries22]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=9
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries23]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries24]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=10
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries25]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries26]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=11
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries27]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries28]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=12
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries29]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries30]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=13
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries31]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries32]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=14
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.ext_entries]
-type=X86IntelMPBusHierarchy
-bus_id=1
-eventq_index=0
-parent_bus=0
-subtractive_decode=true
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-response_latency=2
-use_default_range=false
-width=16
-default=system.pc.pci_host.pio
-master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
-slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=0:134217727
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[18]
-mem_side=system.membus.slave[4]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-hit_latency=50
-sequential_access=false
-size=1024
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder
-clk_domain=system.clk_domain
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-point_of_coherency=true
-response_latency=2
-snoop_filter=Null
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.physmem.port
-slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=0
-pio_latency=100000
-pio_size=8
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.default
-
-[system.pc]
-type=Pc
-children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pci_host south_bridge
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.pc.behind_pci]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854779128
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.pc.com_1]
-type=Uart8250
-children=terminal
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=9223372036854776824
-pio_latency=100000
-platform=system.pc
-system=system
-terminal=system.pc.com_1.terminal
-pio=system.iobus.master[13]
-
-[system.pc.com_1.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.pc.fake_com_2]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776568
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[14]
-
-[system.pc.fake_com_3]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776808
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[15]
-
-[system.pc.fake_com_4]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776552
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[16]
-
-[system.pc.fake_floppy]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776818
-pio_latency=100000
-pio_size=2
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[17]
-
-[system.pc.i_dont_exist1]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854775936
-pio_latency=100000
-pio_size=1
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[10]
-
-[system.pc.i_dont_exist2]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776045
-pio_latency=100000
-pio_size=1
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[11]
-
-[system.pc.pci_host]
-type=GenericPciHost
-clk_domain=system.clk_domain
-conf_base=13835058055282163712
-conf_device_bits=8
-conf_size=16777216
-eventq_index=0
-pci_dma_base=0
-pci_mem_base=0
-pci_pio_base=9223372036854775808
-platform=system.pc
-system=system
-pio=system.iobus.default
-
-[system.pc.south_bridge]
-type=SouthBridge
-children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
-cmos=system.pc.south_bridge.cmos
-dma1=system.pc.south_bridge.dma1
-eventq_index=0
-io_apic=system.pc.south_bridge.io_apic
-keyboard=system.pc.south_bridge.keyboard
-pic1=system.pc.south_bridge.pic1
-pic2=system.pc.south_bridge.pic2
-pit=system.pc.south_bridge.pit
-platform=system.pc
-speaker=system.pc.south_bridge.speaker
-
-[system.pc.south_bridge.cmos]
-type=Cmos
-children=int_pin
-clk_domain=system.clk_domain
-eventq_index=0
-int_pin=system.pc.south_bridge.cmos.int_pin
-pio_addr=9223372036854775920
-pio_latency=100000
-system=system
-time=Sun Jan 1 00:00:00 2012
-pio=system.iobus.master[1]
-
-[system.pc.south_bridge.cmos.int_pin]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.dma1]
-type=I8237
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=9223372036854775808
-pio_latency=100000
-system=system
-pio=system.iobus.master[2]
-
-[system.pc.south_bridge.ide]
-type=IdeController
-children=disks0 disks1
-BAR0=496
-BAR0LegacyIO=true
-BAR0Size=8
-BAR1=1012
-BAR1LegacyIO=true
-BAR1Size=3
-BAR2=368
-BAR2LegacyIO=true
-BAR2Size=8
-BAR3=884
-BAR3LegacyIO=true
-BAR3Size=3
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=14
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=9223372036854775808
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=128
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
-eventq_index=0
-host=system.pc.pci_host
-io_shift=0
-pci_bus=0
-pci_dev=4
-pci_func=0
-pio_latency=30000
-system=system
-dma=system.iobus.slave[1]
-pio=system.iobus.master[3]
-
-[system.pc.south_bridge.ide.disks0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.pc.south_bridge.ide.disks0.image
-
-[system.pc.south_bridge.ide.disks0.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/dist/m5/system/disks/linux-x86.img
-read_only=true
-
-[system.pc.south_bridge.ide.disks1]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.pc.south_bridge.ide.disks1.image
-
-[system.pc.south_bridge.ide.disks1.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks1.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks1.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/dist/m5/system/disks/linux-bigswap2.img
-read_only=true
-
-[system.pc.south_bridge.int_lines0]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines0.sink
-source=system.pc.south_bridge.pic1.output
-
-[system.pc.south_bridge.int_lines0.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-eventq_index=0
-number=0
-
-[system.pc.south_bridge.int_lines1]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines1.sink
-source=system.pc.south_bridge.pic2.output
-
-[system.pc.south_bridge.int_lines1.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-eventq_index=0
-number=2
-
-[system.pc.south_bridge.int_lines2]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines2.sink
-source=system.pc.south_bridge.cmos.int_pin
-
-[system.pc.south_bridge.int_lines2.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic2
-eventq_index=0
-number=0
-
-[system.pc.south_bridge.int_lines3]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines3.sink
-source=system.pc.south_bridge.pit.int_pin
-
-[system.pc.south_bridge.int_lines3.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-eventq_index=0
-number=0
-
-[system.pc.south_bridge.int_lines4]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines4.sink
-source=system.pc.south_bridge.pit.int_pin
-
-[system.pc.south_bridge.int_lines4.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-eventq_index=0
-number=2
-
-[system.pc.south_bridge.int_lines5]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines5.sink
-source=system.pc.south_bridge.keyboard.keyboard_int_pin
-
-[system.pc.south_bridge.int_lines5.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-eventq_index=0
-number=1
-
-[system.pc.south_bridge.int_lines6]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines6.sink
-source=system.pc.south_bridge.keyboard.mouse_int_pin
-
-[system.pc.south_bridge.int_lines6.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-eventq_index=0
-number=12
-
-[system.pc.south_bridge.io_apic]
-type=I82094AA
-apic_id=1
-clk_domain=system.clk_domain
-eventq_index=0
-external_int_pic=system.pc.south_bridge.pic1
-int_latency=1000
-pio_addr=4273995776
-pio_latency=100000
-system=system
-int_master=system.iobus.slave[2]
-pio=system.iobus.master[9]
-
-[system.pc.south_bridge.keyboard]
-type=I8042
-children=keyboard_int_pin mouse_int_pin
-clk_domain=system.clk_domain
-command_port=9223372036854775908
-data_port=9223372036854775904
-eventq_index=0
-keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
-mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
-pio_addr=0
-pio_latency=100000
-system=system
-pio=system.iobus.master[4]
-
-[system.pc.south_bridge.keyboard.keyboard_int_pin]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.keyboard.mouse_int_pin]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.pic1]
-type=I8259
-children=output
-clk_domain=system.clk_domain
-eventq_index=0
-mode=I8259Master
-output=system.pc.south_bridge.pic1.output
-pio_addr=9223372036854775840
-pio_latency=100000
-slave=system.pc.south_bridge.pic2
-system=system
-pio=system.iobus.master[5]
-
-[system.pc.south_bridge.pic1.output]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.pic2]
-type=I8259
-children=output
-clk_domain=system.clk_domain
-eventq_index=0
-mode=I8259Slave
-output=system.pc.south_bridge.pic2.output
-pio_addr=9223372036854775968
-pio_latency=100000
-slave=Null
-system=system
-pio=system.iobus.master[6]
-
-[system.pc.south_bridge.pic2.output]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.pit]
-type=I8254
-children=int_pin
-clk_domain=system.clk_domain
-eventq_index=0
-int_pin=system.pc.south_bridge.pit.int_pin
-pio_addr=9223372036854775872
-pio_latency=100000
-system=system
-pio=system.iobus.master[7]
-
-[system.pc.south_bridge.pit.int_pin]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.speaker]
-type=PcSpeaker
-clk_domain=system.clk_domain
-eventq_index=0
-i8254=system.pc.south_bridge.pit
-pio_addr=9223372036854775905
-pio_latency=100000
-system=system
-pio=system.iobus.master[8]
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.075000
-IDD02=0.000000
-IDD2N=0.050000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.000000
-IDD2P12=0.000000
-IDD3N=0.057000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.000000
-IDD3P12=0.000000
-IDD4R=0.187000
-IDD4R2=0.000000
-IDD4W=0.165000
-IDD4W2=0.000000
-IDD5=0.220000
-IDD52=0.000000
-IDD6=0.000000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-page_policy=open_adaptive
-range=0:134217727
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=0
-tXPDLL=0
-tXS=0
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[3]
-
-[system.smbios_table]
-type=X86SMBiosSMBiosTable
-children=structures
-eventq_index=0
-major_version=2
-minor_version=5
-structures=system.smbios_table.structures
-
-[system.smbios_table.structures]
-type=X86SMBiosBiosInformation
-characteristic_ext_bytes=
-characteristics=
-emb_cont_firmware_major=0
-emb_cont_firmware_minor=0
-eventq_index=0
-major=0
-minor=0
-release_date=06/08/2008
-rom_size=0
-starting_addr_segment=0
-vendor=
-version=
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: Reading current count from inactive timer.
-warn: Don't know what interrupt to clear for console.
-warn: x86 cpuid: unknown family 0x8086
-warn: Tried to clear PCI interrupt 14
-warn: Unknown mouse command 0xe1.
-warn: instruction 'wbinvd' unimplemented
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 21 2016 14:41:03
-gem5 started Jan 21 2016 14:41:53
-gem5 executing on zizzer, pid 17907
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
-
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
- 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5194947216500 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 5.194946 # Number of seconds simulated
-sim_ticks 5194946000500 # Number of ticks simulated
-final_tick 5194946000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 930999 # Simulator instruction rate (inst/s)
-host_op_rate 1794485 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 37656529565 # Simulator tick rate (ticks/s)
-host_mem_usage 609616 # Number of bytes of host memory used
-host_seconds 137.96 # Real time elapsed on the host
-sim_insts 128436892 # Number of instructions simulated
-sim_ops 247560077 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 821248 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9031168 # Number of bytes read from this memory
-system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
-system.physmem.bytes_read::total 9881152 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 821248 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 821248 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8151616 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8151616 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12832 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 141112 # Number of read requests responded to by this memory
-system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 154393 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 127369 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 127369 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 158086 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1738453 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::pc.south_bridge.ide 5458 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1902070 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 158086 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 158086 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1569144 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1569144 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1569144 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 158086 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1738453 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 5458 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3471214 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 154393 # Number of read requests accepted
-system.physmem.writeReqs 127369 # Number of write requests accepted
-system.physmem.readBursts 154393 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 127369 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 9872000 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 9152 # Total number of bytes read from write queue
-system.physmem.bytesWritten 8149824 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 9881152 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 8151616 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 143 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 10087 # Per bank write bursts
-system.physmem.perBankRdBursts::1 9534 # Per bank write bursts
-system.physmem.perBankRdBursts::2 9814 # Per bank write bursts
-system.physmem.perBankRdBursts::3 9653 # Per bank write bursts
-system.physmem.perBankRdBursts::4 10130 # Per bank write bursts
-system.physmem.perBankRdBursts::5 9948 # Per bank write bursts
-system.physmem.perBankRdBursts::6 9317 # Per bank write bursts
-system.physmem.perBankRdBursts::7 9200 # Per bank write bursts
-system.physmem.perBankRdBursts::8 8918 # Per bank write bursts
-system.physmem.perBankRdBursts::9 9357 # Per bank write bursts
-system.physmem.perBankRdBursts::10 9071 # Per bank write bursts
-system.physmem.perBankRdBursts::11 9331 # Per bank write bursts
-system.physmem.perBankRdBursts::12 9713 # Per bank write bursts
-system.physmem.perBankRdBursts::13 9915 # Per bank write bursts
-system.physmem.perBankRdBursts::14 10131 # Per bank write bursts
-system.physmem.perBankRdBursts::15 10131 # Per bank write bursts
-system.physmem.perBankWrBursts::0 8252 # Per bank write bursts
-system.physmem.perBankWrBursts::1 7742 # Per bank write bursts
-system.physmem.perBankWrBursts::2 7578 # Per bank write bursts
-system.physmem.perBankWrBursts::3 7567 # Per bank write bursts
-system.physmem.perBankWrBursts::4 7987 # Per bank write bursts
-system.physmem.perBankWrBursts::5 8326 # Per bank write bursts
-system.physmem.perBankWrBursts::6 7984 # Per bank write bursts
-system.physmem.perBankWrBursts::7 7858 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7447 # Per bank write bursts
-system.physmem.perBankWrBursts::9 8118 # Per bank write bursts
-system.physmem.perBankWrBursts::10 7706 # Per bank write bursts
-system.physmem.perBankWrBursts::11 7949 # Per bank write bursts
-system.physmem.perBankWrBursts::12 8417 # Per bank write bursts
-system.physmem.perBankWrBursts::13 8510 # Per bank write bursts
-system.physmem.perBankWrBursts::14 8023 # Per bank write bursts
-system.physmem.perBankWrBursts::15 7877 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 15 # Number of times write queue was full causing retry
-system.physmem.totGap 5194945939500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 154393 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 127369 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 151022 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 2785 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 67 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 59 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 39 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 36 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 27 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 2198 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 3757 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 7707 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 6176 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 7371 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 6314 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 6198 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 6474 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 7322 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 6886 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 7581 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 8523 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 7183 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 7744 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 9513 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 7269 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 6984 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 7148 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 1628 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 270 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 182 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 153 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 139 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 129 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 107 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 95 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 143 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 84 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 79 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 117 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 141 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 126 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 123 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 90 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 117 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 146 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 98 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 147 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 76 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 84 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 71 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 119 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 133 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 57 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 62 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 116 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 105 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 29 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 40 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 56869 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 316.898416 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 189.066814 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 329.232113 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 20064 35.28% 35.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 13820 24.30% 59.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6395 11.25% 70.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3441 6.05% 76.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2422 4.26% 81.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1595 2.80% 83.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1163 2.05% 85.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 983 1.73% 87.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 6986 12.28% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 56869 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5701 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 27.056657 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 634.190971 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 5700 99.98% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5701 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 5700 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 22.339649 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 19.500075 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 17.394307 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 4849 85.07% 85.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 101 1.77% 86.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 44 0.77% 87.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 52 0.91% 88.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 17 0.30% 88.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 15 0.26% 89.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 60 1.05% 90.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 6 0.11% 90.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 207 3.63% 93.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 10 0.18% 94.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 6 0.11% 94.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 16 0.28% 94.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 91 1.60% 96.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 6 0.11% 96.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 3 0.05% 96.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 36 0.63% 96.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 144 2.53% 99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 1 0.02% 99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 1 0.02% 99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 11 0.19% 99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 1 0.02% 99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 3 0.05% 99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 9 0.16% 99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155 1 0.02% 99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 1 0.02% 99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 4 0.07% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 3 0.05% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211 2 0.04% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5700 # Writes before turning the bus around for reads
-system.physmem.totQLat 1573374325 # Total ticks spent queuing
-system.physmem.totMemAccLat 4465561825 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 771250000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 10200.16 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 28950.16 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.03 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.80 # Average write queue length when enqueuing
-system.physmem.readRowHits 125550 # Number of row buffer hits during reads
-system.physmem.writeRowHits 99170 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.39 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 77.86 # Row buffer hit rate for writes
-system.physmem.avgGap 18437354.72 # Average gap between requests
-system.physmem.pageHitRate 79.80 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 210916440 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 115083375 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 605927400 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 410119200 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 339308180640 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 137084456790 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 2996714193750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 3474448877595 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.814114 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 4985194974722 # Time in different power states
-system.physmem_0.memoryStateTime::REF 173470440000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 36280536278 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 218998080 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 119493000 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 597214800 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 415018080 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 339308180640 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 137426526900 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 2996414132250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 3474499563750 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.823871 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 4984690777488 # Time in different power states
-system.physmem_1.memoryStateTime::REF 173470440000 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 36784611512 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.numCycles 10389892001 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu.committedInsts 128436892 # Number of instructions committed
-system.cpu.committedOps 247560077 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 232158810 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
-system.cpu.num_func_calls 2315811 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 23152999 # number of instructions that are conditional controls
-system.cpu.num_int_insts 232158810 # number of integer instructions
-system.cpu.num_fp_insts 48 # number of float instructions
-system.cpu.num_int_register_reads 434959716 # number of times the integer registers were read
-system.cpu.num_int_register_writes 197963277 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 48 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 132873102 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 95461248 # number of times the CC registers were written
-system.cpu.num_mem_refs 22321002 # number of memory refs
-system.cpu.num_load_insts 13911426 # Number of load instructions
-system.cpu.num_store_insts 8409576 # Number of store instructions
-system.cpu.num_idle_cycles 9774021635.086119 # Number of idle cycles
-system.cpu.num_busy_cycles 615870365.913881 # Number of busy cycles
-system.cpu.not_idle_fraction 0.059276 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.940724 # Percentage of idle cycles
-system.cpu.Branches 26327440 # Number of branches fetched
-system.cpu.op_class::No_OpClass 172203 0.07% 0.07% # Class of executed instruction
-system.cpu.op_class::IntAlu 224810530 90.81% 90.88% # Class of executed instruction
-system.cpu.op_class::IntMult 140088 0.06% 90.94% # Class of executed instruction
-system.cpu.op_class::IntDiv 122745 0.05% 90.99% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::FloatCvt 16 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::MemRead 13906455 5.62% 96.60% # Class of executed instruction
-system.cpu.op_class::MemWrite 8409576 3.40% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 247561613 # Class of executed instruction
-system.cpu.dcache.tags.replacements 1623668 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.995482 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 20139358 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 1624180 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 12.399708 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 81561500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.995482 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999991 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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-system.cpu.dcache.ReadReq_hits::total 12002599 # number of ReadReq hits
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-system.cpu.dcache.WriteReq_hits::total 8075450 # number of WriteReq hits
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-system.cpu.dcache.overall_hits::total 20137141 # number of overall hits
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-system.cpu.dcache.SoftPFReq_misses::total 402796 # number of SoftPFReq misses
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-system.cpu.dcache.demand_misses::total 1233420 # number of demand (read+write) misses
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-system.cpu.dcache.overall_misses::total 1636216 # number of overall misses
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-system.cpu.dcache.ReadReq_miss_latency::total 13559380500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 18441171467 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 18441171467 # number of WriteReq miss cycles
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-system.cpu.dcache.demand_miss_latency::total 32000551967 # number of demand (read+write) miss cycles
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-system.cpu.dcache.ReadReq_accesses::cpu.data 12909889 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 12909889 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 8401580 # number of WriteReq accesses(hits+misses)
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-system.cpu.dcache.SoftPFReq_accesses::cpu.data 461888 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 461888 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 21311469 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 21311469 # number of demand (read+write) accesses
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-system.cpu.dcache.overall_accesses::total 21773357 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070279 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.070279 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038818 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.038818 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872064 # miss rate for SoftPFReq accesses
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-system.cpu.dcache.demand_miss_rate::total 0.057876 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.075148 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.075148 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14944.924445 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14944.924445 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56545.461831 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 56545.461831 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 25944.570355 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 25944.570355 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 19557.657404 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 19557.657404 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 19286 # number of cycles access was blocked
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-system.cpu.dcache.blocked::no_mshrs 514 # number of cycles access was blocked
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-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 1540773 # number of writebacks
-system.cpu.dcache.writebacks::total 1540773 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 285 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 285 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9475 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 9475 # number of WriteReq MSHR hits
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-system.cpu.dcache.demand_mshr_hits::total 9760 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 9760 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 9760 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 907005 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 907005 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316655 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 316655 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402762 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 402762 # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1223660 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1223660 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1626422 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1626422 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 546346 # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total 546346 # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13920 # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total 13920 # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 560266 # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total 560266 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12650383500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 12650383500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17142668967 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 17142668967 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6518448000 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6518448000 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29793052467 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 29793052467 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36311500467 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 36311500467 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 95132085000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 95132085000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 95132085000 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 95132085000 # number of overall MSHR uncacheable cycles
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-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070257 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037690 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037690 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871991 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871991 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057418 # mshr miss rate for demand accesses
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-system.cpu.dcache.overall_mshr_miss_rate::total 0.074698 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13947.424215 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13947.424215 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54136.738618 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54136.738618 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16184.366946 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16184.366946 # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24347.492332 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 24347.492332 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22326.001780 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22326.001780 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 174124.245442 # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174124.245442 # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 169798.069131 # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 169798.069131 # average overall mshr uncacheable latency
-system.cpu.dtb_walker_cache.tags.replacements 7581 # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse 5.052199 # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs 13343 # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs 7597 # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs 1.756351 # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 5163352546000 # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.052199 # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315762 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315762 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses 53059 # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses 53059 # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13343 # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total 13343 # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13343 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total 13343 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13343 # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total 13343 # number of overall hits
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-system.cpu.dtb_walker_cache.ReadReq_misses::total 8791 # number of ReadReq misses
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-system.cpu.dtb_walker_cache.overall_miss_latency::total 96450500 # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22134 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total 22134 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22134 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total 22134 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22134 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total 22134 # number of overall (read+write) accesses
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-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.397172 # miss rate for ReadReq accesses
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-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.397172 # miss rate for overall accesses
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-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10971.504948 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10971.504948 # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10971.504948 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10971.504948 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10971.504948 # average overall miss latency
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-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8791 # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total 8791 # number of overall MSHR misses
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-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 87659500 # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 87659500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 87659500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 87659500 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 87659500 # number of overall MSHR miss cycles
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-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.397172 # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 9971.504948 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9971.504948 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9971.504948 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9971.504948 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9971.504948 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9971.504948 # average overall mshr miss latency
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-system.cpu.icache.tags.sampled_refs 791001 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 182.851771 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 164551519500 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 510.213579 # Average occupied blocks per requestor
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-system.cpu.icache.tags.occ_percent::total 0.996511 # Average percentage of cache occupancy
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-system.cpu.icache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 292 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 146217950 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 146217950 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 144635934 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 144635934 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 144635934 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 144635934 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 144635934 # number of overall hits
-system.cpu.icache.overall_hits::total 144635934 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 791008 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 791008 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 791008 # number of demand (read+write) misses
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-system.cpu.l2cache.ReadExReq_accesses::total 314432 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 790995 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total 790995 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 6472 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 2858 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1309018 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total 1318348 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6472 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker 2858 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst 790995 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1623450 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 2423775 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6472 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker 2858 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 790995 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1623450 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2423775 # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.814600 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.814600 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.361003 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.361003 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016224 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016224 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000155 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.001749 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.021769 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.021619 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000155 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001749 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016224 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.087472 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.063886 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000155 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001749 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016224 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.087472 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.063886 # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 37114.153627 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 37114.153627 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127215.115716 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127215.115716 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131541.104964 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131541.104964 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 119000 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 127500 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 131537.531583 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 131536.383412 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 119000 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 127500 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131541.104964 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128082.478329 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 128369.037624 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 119000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 127500 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131541.104964 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128082.478329 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 128369.037624 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks 80702 # number of writebacks
-system.cpu.l2cache.writebacks::total 80702 # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1406 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 1406 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113511 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 113511 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 12833 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 12833 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker 1 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 5 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 28496 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 28502 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses
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-system.cpu.l2cache.demand_mshr_misses::cpu.inst 12833 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 142007 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 154846 # number of demand (read+write) MSHR misses
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-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 12833 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 142007 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 154846 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 546346 # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total 546346 # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13920 # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13920 # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 560266 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total 560266 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 96565500 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 96565500 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13305205000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13305205000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1559737000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1559737000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 109000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 587500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3463333500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3464030000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 109000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 587500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1559737000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16768538500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 18328972000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 109000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 587500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1559737000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16768538500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 18328972000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88302755000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88302755000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88302755000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88302755000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.814600 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.814600 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361003 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361003 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016224 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016224 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000155 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.001749 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.021769 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.021619 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000155 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001749 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016224 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087472 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.063886 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000155 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001749 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016224 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087472 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.063886 # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68681.009957 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68681.009957 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117215.115716 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117215.115716 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121541.104964 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121541.104964 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 109000 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 117500 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 121537.531583 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 121536.383412 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 109000 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 117500 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121541.104964 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118082.478329 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118369.037624 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 109000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 117500 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121541.104964 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118082.478329 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118369.037624 # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161624.236290 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161624.236290 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 157608.626974 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157608.626974 # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 4855602 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425060 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11070 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 1020 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1020 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq 546346 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2660470 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 13920 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 13920 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 1671913 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 790489 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 97528 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2230 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2230 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 314438 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 314438 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 791008 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 1323647 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::MessageReq 1654 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2372492 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5996122 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 10488 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 22844 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 8401946 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 101214976 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204098920 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 232384 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 605120 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 306151400 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 189316 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 3174772 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.004492 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.077876 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 3163038 99.63% 99.63% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 9206 0.29% 99.92% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 2528 0.08% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 3174772 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 5049912000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 571290 # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1186512000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 2990732492 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 6370500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 13186500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 216035 # Transaction distribution
-system.iobus.trans_dist::ReadResp 216035 # Transaction distribution
-system.iobus.trans_dist::WriteReq 57726 # Transaction distribution
-system.iobus.trans_dist::WriteResp 57726 # Transaction distribution
-system.iobus.trans_dist::MessageReq 1654 # Transaction distribution
-system.iobus.trans_dist::MessageResp 1654 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 408166 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 452398 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 550830 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 204083 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 232479 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027280 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027280 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 3266375 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 4014316 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 10060500 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 1094500 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer5.occupancy 79000 # Layer occupancy (ticks)
-system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 50500 # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 26000 # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer8.occupancy 306124500 # Layer occupancy (ticks)
-system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer9.occupancy 1113000 # Layer occupancy (ticks)
-system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 177500 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
-system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 24285000 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 241923874 # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 1216500 # Layer occupancy (ticks)
-system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 441392000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 50036000 # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks)
-system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 47507 # number of replacements
-system.iocache.tags.tagsinuse 0.108260 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 47523 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 5048330957000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108260 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006766 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.006766 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 428058 # Number of tag accesses
-system.iocache.tags.data_accesses 428058 # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide 842 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 842 # number of ReadReq misses
-system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 47562 # number of demand (read+write) misses
-system.iocache.demand_misses::total 47562 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 47562 # number of overall misses
-system.iocache.overall_misses::total 47562 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 138525690 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 138525690 # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5867864184 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 5867864184 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 6006389874 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 6006389874 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 6006389874 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 6006389874 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 842 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 842 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 47562 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 47562 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 47562 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 47562 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 164519.821853 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 164519.821853 # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125596.408048 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125596.408048 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 126285.477356 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 126285.477356 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 126285.477356 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 126285.477356 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 428 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 33 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 12.969697 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks 46667 # number of writebacks
-system.iocache.writebacks::total 46667 # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 842 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 842 # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 47562 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 47562 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 47562 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 47562 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96425690 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 96425690 # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3530059456 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 3530059456 # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3626485146 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 3626485146 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3626485146 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 3626485146 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114519.821853 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 114519.821853 # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75557.779452 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75557.779452 # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 76247.532610 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 76247.532610 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 76247.532610 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 76247.532610 # average overall mshr miss latency
-system.membus.trans_dist::ReadReq 546346 # Transaction distribution
-system.membus.trans_dist::ReadResp 588523 # Transaction distribution
-system.membus.trans_dist::WriteReq 13920 # Transaction distribution
-system.membus.trans_dist::WriteResp 13920 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 127369 # Transaction distribution
-system.membus.trans_dist::CleanEvict 7403 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 2156 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 18 # Transaction distribution
-system.membus.trans_dist::ReadExReq 113265 # Transaction distribution
-system.membus.trans_dist::ReadExResp 113265 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 42177 # Transaction distribution
-system.membus.trans_dist::MessageReq 1654 # Transaction distribution
-system.membus.trans_dist::MessageResp 1654 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 452398 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 668134 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397971 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1518503 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95512 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 95512 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1617323 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 232479 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1336265 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15017728 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16586472 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 19608128 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 1571 # Total snoops (count)
-system.membus.snoop_fanout::samples 901025 # Request fanout histogram
-system.membus.snoop_fanout::mean 1.001836 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.042806 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 899371 99.82% 99.82% # Request fanout histogram
-system.membus.snoop_fanout::2 1654 0.18% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 2 # Request fanout histogram
-system.membus.snoop_fanout::total 901025 # Request fanout histogram
-system.membus.reqLayer0.occupancy 344310500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 503566000 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 4013684 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 852733442 # Layer occupancy (ticks)
-system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer0.occupancy 2359684 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1924956500 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer4.occupancy 4280140 # Layer occupancy (ticks)
-system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
-system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-
----------- End Simulation Statistics ----------
+++ /dev/null
-# Copyright (c) 2006 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-root.system.readfile = os.path.join(tests_root, 'halt.sh')
+++ /dev/null
-# Copyright (c) 2006 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+++ /dev/null
-# Copyright (c) 2006 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-# workload
-benchmarks = [
- "tests/test-progs/hello/bin/alpha/linux/hello", "'hello'",
- "tests/test-progs/hello/bin/alpha/linux/hello", "'hello'",
- "tests/test-progs/hello/bin/alpha/linux/hello", "'hello'",
- "tests/test-progs/hello/bin/alpha/linux/hello", "'hello'",
- ]
-
-for i, cpu in zip(range(len(cpus)), root.system.cpu):
- p = Process()
- p.executable = benchmarks[i*2]
- p.cmd = benchmarks[(i*2)+1]
- root.system.cpu[i].workload = p
- root.system.cpu[i].max_insts_all_threads = 10000000
-#root.system.cpu.workload = Process(cmd = 'hello',
- # executable = binpath('hello'))
+++ /dev/null
-# Copyright (c) 2006 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-process1 = Process(cmd = 'hello', executable = binpath('hello'), pid = 100)
-process2 = Process(cmd = 'hello', executable = binpath('hello'),
- pid = 101, ppid = 100)
-
-root.system.cpu[0].workload = [process1, process2]
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu dvfs_handler mem_ctrl membus
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:536870911:0:0:0:0
-memories=system.mem_ctrl
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[2]
-
-[system.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.clk_domain.voltage_domain
-
-[system.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.clk_domain
-cpu_id=-1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.membus.slave[1]
-icache_port=system.membus.slave[0]
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=Process
-cmd=tests/test-progs/hello/bin/arm/linux/hello
-cwd=
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=
-gid=100
-input=cin
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.mem_ctrl]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:536870911:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.mem_ctrl.port
-slave=system.cpu.icache_port system.cpu.dcache_port system.system_port
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Entering event queue @ 0. Starting simulation...
+++ /dev/null
-Redirecting stdout to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Apr 3 2017 17:55:48
-gem5 started Apr 3 2017 18:05:51
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 55329
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple
-
-Global frequency set at 1000000000000 ticks per second
-Beginning simulation!
-Hello world!
-Exiting @ tick 372284000 because exiting with last active thread context
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000372
-sim_ticks 372284000
-final_tick 372284000
-sim_freq 1000000000000
-host_inst_rate 111411
-host_op_rate 128815
-host_tick_rate 8307715104
-host_mem_usage 662496
-host_seconds 0.05
-sim_insts 4988
-sim_ops 5770
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 372284000
-system.mem_ctrl.bytes_read::cpu.inst 20108
-system.mem_ctrl.bytes_read::cpu.data 4672
-system.mem_ctrl.bytes_read::total 24780
-system.mem_ctrl.bytes_inst_read::cpu.inst 20108
-system.mem_ctrl.bytes_inst_read::total 20108
-system.mem_ctrl.bytes_written::cpu.data 3696
-system.mem_ctrl.bytes_written::total 3696
-system.mem_ctrl.num_reads::cpu.inst 5027
-system.mem_ctrl.num_reads::cpu.data 1061
-system.mem_ctrl.num_reads::total 6088
-system.mem_ctrl.num_writes::cpu.data 936
-system.mem_ctrl.num_writes::total 936
-system.mem_ctrl.bw_read::cpu.inst 54012528
-system.mem_ctrl.bw_read::cpu.data 12549559
-system.mem_ctrl.bw_read::total 66562087
-system.mem_ctrl.bw_inst_read::cpu.inst 54012528
-system.mem_ctrl.bw_inst_read::total 54012528
-system.mem_ctrl.bw_write::cpu.data 9927905
-system.mem_ctrl.bw_write::total 9927905
-system.mem_ctrl.bw_total::cpu.inst 54012528
-system.mem_ctrl.bw_total::cpu.data 22477463
-system.mem_ctrl.bw_total::total 76489992
-system.mem_ctrl.readReqs 6089
-system.mem_ctrl.writeReqs 936
-system.mem_ctrl.readBursts 6089
-system.mem_ctrl.writeBursts 936
-system.mem_ctrl.bytesReadDRAM 383296
-system.mem_ctrl.bytesReadWrQ 6400
-system.mem_ctrl.bytesWritten 4096
-system.mem_ctrl.bytesReadSys 24784
-system.mem_ctrl.bytesWrittenSys 3696
-system.mem_ctrl.servicedByWrQ 100
-system.mem_ctrl.mergedWrBursts 855
-system.mem_ctrl.neitherReadNorWriteReqs 0
-system.mem_ctrl.perBankRdBursts::0 911
-system.mem_ctrl.perBankRdBursts::1 1454
-system.mem_ctrl.perBankRdBursts::2 724
-system.mem_ctrl.perBankRdBursts::3 364
-system.mem_ctrl.perBankRdBursts::4 505
-system.mem_ctrl.perBankRdBursts::5 303
-system.mem_ctrl.perBankRdBursts::6 487
-system.mem_ctrl.perBankRdBursts::7 206
-system.mem_ctrl.perBankRdBursts::8 42
-system.mem_ctrl.perBankRdBursts::9 155
-system.mem_ctrl.perBankRdBursts::10 192
-system.mem_ctrl.perBankRdBursts::11 422
-system.mem_ctrl.perBankRdBursts::12 108
-system.mem_ctrl.perBankRdBursts::13 36
-system.mem_ctrl.perBankRdBursts::14 0
-system.mem_ctrl.perBankRdBursts::15 80
-system.mem_ctrl.perBankWrBursts::0 0
-system.mem_ctrl.perBankWrBursts::1 0
-system.mem_ctrl.perBankWrBursts::2 0
-system.mem_ctrl.perBankWrBursts::3 0
-system.mem_ctrl.perBankWrBursts::4 0
-system.mem_ctrl.perBankWrBursts::5 0
-system.mem_ctrl.perBankWrBursts::6 0
-system.mem_ctrl.perBankWrBursts::7 0
-system.mem_ctrl.perBankWrBursts::8 0
-system.mem_ctrl.perBankWrBursts::9 0
-system.mem_ctrl.perBankWrBursts::10 13
-system.mem_ctrl.perBankWrBursts::11 46
-system.mem_ctrl.perBankWrBursts::12 5
-system.mem_ctrl.perBankWrBursts::13 0
-system.mem_ctrl.perBankWrBursts::14 0
-system.mem_ctrl.perBankWrBursts::15 0
-system.mem_ctrl.numRdRetry 0
-system.mem_ctrl.numWrRetry 0
-system.mem_ctrl.totGap 372207000
-system.mem_ctrl.readPktSize::0 70
-system.mem_ctrl.readPktSize::1 1
-system.mem_ctrl.readPktSize::2 5858
-system.mem_ctrl.readPktSize::3 160
-system.mem_ctrl.readPktSize::4 0
-system.mem_ctrl.readPktSize::5 0
-system.mem_ctrl.readPktSize::6 0
-system.mem_ctrl.writePktSize::0 16
-system.mem_ctrl.writePktSize::1 0
-system.mem_ctrl.writePktSize::2 920
-system.mem_ctrl.writePktSize::3 0
-system.mem_ctrl.writePktSize::4 0
-system.mem_ctrl.writePktSize::5 0
-system.mem_ctrl.writePktSize::6 0
-system.mem_ctrl.rdQLenPdf::0 5980
-system.mem_ctrl.rdQLenPdf::1 9
-system.mem_ctrl.rdQLenPdf::2 0
-system.mem_ctrl.rdQLenPdf::3 0
-system.mem_ctrl.rdQLenPdf::4 0
-system.mem_ctrl.rdQLenPdf::5 0
-system.mem_ctrl.rdQLenPdf::6 0
-system.mem_ctrl.rdQLenPdf::7 0
-system.mem_ctrl.rdQLenPdf::8 0
-system.mem_ctrl.rdQLenPdf::9 0
-system.mem_ctrl.rdQLenPdf::10 0
-system.mem_ctrl.rdQLenPdf::11 0
-system.mem_ctrl.rdQLenPdf::12 0
-system.mem_ctrl.rdQLenPdf::13 0
-system.mem_ctrl.rdQLenPdf::14 0
-system.mem_ctrl.rdQLenPdf::15 0
-system.mem_ctrl.rdQLenPdf::16 0
-system.mem_ctrl.rdQLenPdf::17 0
-system.mem_ctrl.rdQLenPdf::18 0
-system.mem_ctrl.rdQLenPdf::19 0
-system.mem_ctrl.rdQLenPdf::20 0
-system.mem_ctrl.rdQLenPdf::21 0
-system.mem_ctrl.rdQLenPdf::22 0
-system.mem_ctrl.rdQLenPdf::23 0
-system.mem_ctrl.rdQLenPdf::24 0
-system.mem_ctrl.rdQLenPdf::25 0
-system.mem_ctrl.rdQLenPdf::26 0
-system.mem_ctrl.rdQLenPdf::27 0
-system.mem_ctrl.rdQLenPdf::28 0
-system.mem_ctrl.rdQLenPdf::29 0
-system.mem_ctrl.rdQLenPdf::30 0
-system.mem_ctrl.rdQLenPdf::31 0
-system.mem_ctrl.wrQLenPdf::0 1
-system.mem_ctrl.wrQLenPdf::1 1
-system.mem_ctrl.wrQLenPdf::2 1
-system.mem_ctrl.wrQLenPdf::3 1
-system.mem_ctrl.wrQLenPdf::4 1
-system.mem_ctrl.wrQLenPdf::5 1
-system.mem_ctrl.wrQLenPdf::6 1
-system.mem_ctrl.wrQLenPdf::7 1
-system.mem_ctrl.wrQLenPdf::8 1
-system.mem_ctrl.wrQLenPdf::9 1
-system.mem_ctrl.wrQLenPdf::10 1
-system.mem_ctrl.wrQLenPdf::11 1
-system.mem_ctrl.wrQLenPdf::12 1
-system.mem_ctrl.wrQLenPdf::13 1
-system.mem_ctrl.wrQLenPdf::14 1
-system.mem_ctrl.wrQLenPdf::15 1
-system.mem_ctrl.wrQLenPdf::16 1
-system.mem_ctrl.wrQLenPdf::17 4
-system.mem_ctrl.wrQLenPdf::18 4
-system.mem_ctrl.wrQLenPdf::19 4
-system.mem_ctrl.wrQLenPdf::20 4
-system.mem_ctrl.wrQLenPdf::21 4
-system.mem_ctrl.wrQLenPdf::22 4
-system.mem_ctrl.wrQLenPdf::23 4
-system.mem_ctrl.wrQLenPdf::24 4
-system.mem_ctrl.wrQLenPdf::25 4
-system.mem_ctrl.wrQLenPdf::26 4
-system.mem_ctrl.wrQLenPdf::27 4
-system.mem_ctrl.wrQLenPdf::28 4
-system.mem_ctrl.wrQLenPdf::29 4
-system.mem_ctrl.wrQLenPdf::30 4
-system.mem_ctrl.wrQLenPdf::31 4
-system.mem_ctrl.wrQLenPdf::32 4
-system.mem_ctrl.wrQLenPdf::33 0
-system.mem_ctrl.wrQLenPdf::34 0
-system.mem_ctrl.wrQLenPdf::35 0
-system.mem_ctrl.wrQLenPdf::36 0
-system.mem_ctrl.wrQLenPdf::37 0
-system.mem_ctrl.wrQLenPdf::38 0
-system.mem_ctrl.wrQLenPdf::39 0
-system.mem_ctrl.wrQLenPdf::40 0
-system.mem_ctrl.wrQLenPdf::41 0
-system.mem_ctrl.wrQLenPdf::42 0
-system.mem_ctrl.wrQLenPdf::43 0
-system.mem_ctrl.wrQLenPdf::44 0
-system.mem_ctrl.wrQLenPdf::45 0
-system.mem_ctrl.wrQLenPdf::46 0
-system.mem_ctrl.wrQLenPdf::47 0
-system.mem_ctrl.wrQLenPdf::48 0
-system.mem_ctrl.wrQLenPdf::49 0
-system.mem_ctrl.wrQLenPdf::50 0
-system.mem_ctrl.wrQLenPdf::51 0
-system.mem_ctrl.wrQLenPdf::52 0
-system.mem_ctrl.wrQLenPdf::53 0
-system.mem_ctrl.wrQLenPdf::54 0
-system.mem_ctrl.wrQLenPdf::55 0
-system.mem_ctrl.wrQLenPdf::56 0
-system.mem_ctrl.wrQLenPdf::57 0
-system.mem_ctrl.wrQLenPdf::58 0
-system.mem_ctrl.wrQLenPdf::59 0
-system.mem_ctrl.wrQLenPdf::60 0
-system.mem_ctrl.wrQLenPdf::61 0
-system.mem_ctrl.wrQLenPdf::62 0
-system.mem_ctrl.wrQLenPdf::63 0
-system.mem_ctrl.bytesPerActivate::samples 514
-system.mem_ctrl.bytesPerActivate::mean 749.322957
-system.mem_ctrl.bytesPerActivate::gmean 608.037375
-system.mem_ctrl.bytesPerActivate::stdev 344.826867
-system.mem_ctrl.bytesPerActivate::0-127 25 4.86% 4.86%
-system.mem_ctrl.bytesPerActivate::128-255 42 8.17% 13.04%
-system.mem_ctrl.bytesPerActivate::256-383 44 8.56% 21.60%
-system.mem_ctrl.bytesPerActivate::384-511 26 5.06% 26.65%
-system.mem_ctrl.bytesPerActivate::512-639 25 4.86% 31.52%
-system.mem_ctrl.bytesPerActivate::640-767 34 6.61% 38.13%
-system.mem_ctrl.bytesPerActivate::768-895 27 5.25% 43.39%
-system.mem_ctrl.bytesPerActivate::896-1023 27 5.25% 48.64%
-system.mem_ctrl.bytesPerActivate::1024-1151 264 51.36% 100.00%
-system.mem_ctrl.bytesPerActivate::total 514
-system.mem_ctrl.rdPerTurnAround::samples 4
-system.mem_ctrl.rdPerTurnAround::mean 1490.500000
-system.mem_ctrl.rdPerTurnAround::gmean 1373.591360
-system.mem_ctrl.rdPerTurnAround::stdev 606.712727
-system.mem_ctrl.rdPerTurnAround::640-767 1 25.00% 25.00%
-system.mem_ctrl.rdPerTurnAround::1408-1535 1 25.00% 50.00%
-system.mem_ctrl.rdPerTurnAround::1792-1919 1 25.00% 75.00%
-system.mem_ctrl.rdPerTurnAround::2048-2175 1 25.00% 100.00%
-system.mem_ctrl.rdPerTurnAround::total 4
-system.mem_ctrl.wrPerTurnAround::samples 4
-system.mem_ctrl.wrPerTurnAround::mean 16
-system.mem_ctrl.wrPerTurnAround::gmean 16.000000
-system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00%
-system.mem_ctrl.wrPerTurnAround::total 4
-system.mem_ctrl.totQLat 57609500
-system.mem_ctrl.totMemAccLat 169903250
-system.mem_ctrl.totBusLat 29945000
-system.mem_ctrl.avgQLat 9619.22
-system.mem_ctrl.avgBusLat 5000.00
-system.mem_ctrl.avgMemAccLat 28369.22
-system.mem_ctrl.avgRdBW 1029.58
-system.mem_ctrl.avgWrBW 11.00
-system.mem_ctrl.avgRdBWSys 66.57
-system.mem_ctrl.avgWrBWSys 9.93
-system.mem_ctrl.peakBW 12800.00
-system.mem_ctrl.busUtil 8.13
-system.mem_ctrl.busUtilRead 8.04
-system.mem_ctrl.busUtilWrite 0.09
-system.mem_ctrl.avgRdQLen 1.00
-system.mem_ctrl.avgWrQLen 24.94
-system.mem_ctrl.readRowHits 5473
-system.mem_ctrl.writeRowHits 62
-system.mem_ctrl.readRowHitRate 91.38
-system.mem_ctrl.writeRowHitRate 76.54
-system.mem_ctrl.avgGap 52983.20
-system.mem_ctrl.pageHitRate 91.19
-system.mem_ctrl_0.actEnergy 2727480
-system.mem_ctrl_0.preEnergy 1438305
-system.mem_ctrl_0.readEnergy 35364420
-system.mem_ctrl_0.writeEnergy 0
-system.mem_ctrl_0.refreshEnergy 28888080.000000
-system.mem_ctrl_0.actBackEnergy 64999380
-system.mem_ctrl_0.preBackEnergy 1619520
-system.mem_ctrl_0.actPowerDownEnergy 98643060
-system.mem_ctrl_0.prePowerDownEnergy 3533760
-system.mem_ctrl_0.selfRefreshEnergy 0
-system.mem_ctrl_0.totalEnergy 237214005
-system.mem_ctrl_0.averagePower 637.183891
-system.mem_ctrl_0.totalIdleTime 225396250
-system.mem_ctrl_0.memoryStateTime::IDLE 954000
-system.mem_ctrl_0.memoryStateTime::REF 12220000
-system.mem_ctrl_0.memoryStateTime::SREF 0
-system.mem_ctrl_0.memoryStateTime::PRE_PDN 9196500
-system.mem_ctrl_0.memoryStateTime::ACT 133713750
-system.mem_ctrl_0.memoryStateTime::ACT_PDN 216199750
-system.mem_ctrl_1.actEnergy 971040
-system.mem_ctrl_1.preEnergy 512325
-system.mem_ctrl_1.readEnergy 7389900
-system.mem_ctrl_1.writeEnergy 334080
-system.mem_ctrl_1.refreshEnergy 27658800.000000
-system.mem_ctrl_1.actBackEnergy 18607080
-system.mem_ctrl_1.preBackEnergy 791520
-system.mem_ctrl_1.actPowerDownEnergy 128152530
-system.mem_ctrl_1.prePowerDownEnergy 7837920
-system.mem_ctrl_1.selfRefreshEnergy 7265340
-system.mem_ctrl_1.totalEnergy 199520535
-system.mem_ctrl_1.averagePower 535.934929
-system.mem_ctrl_1.totalIdleTime 328663750
-system.mem_ctrl_1.memoryStateTime::IDLE 770000
-system.mem_ctrl_1.memoryStateTime::REF 11706000
-system.mem_ctrl_1.memoryStateTime::SREF 27971000
-system.mem_ctrl_1.memoryStateTime::PRE_PDN 20415250
-system.mem_ctrl_1.memoryStateTime::ACT 30385000
-system.mem_ctrl_1.memoryStateTime::ACT_PDN 281036750
-system.pwrStateResidencyTicks::UNDEFINED 372284000
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 372284000
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
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-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
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-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0
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-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
-system.cpu.dstage2_mmu.stage2_tlb.hits 0
-system.cpu.dstage2_mmu.stage2_tlb.misses 0
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 372284000
-system.cpu.dtb.walker.walks 0
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0
-system.cpu.dtb.walker.walkRequestOrigin::total 0
-system.cpu.dtb.inst_hits 0
-system.cpu.dtb.inst_misses 0
-system.cpu.dtb.read_hits 0
-system.cpu.dtb.read_misses 0
-system.cpu.dtb.write_hits 0
-system.cpu.dtb.write_misses 0
-system.cpu.dtb.flush_tlb 0
-system.cpu.dtb.flush_tlb_mva 0
-system.cpu.dtb.flush_tlb_mva_asid 0
-system.cpu.dtb.flush_tlb_asid 0
-system.cpu.dtb.flush_entries 0
-system.cpu.dtb.align_faults 0
-system.cpu.dtb.prefetch_faults 0
-system.cpu.dtb.domain_faults 0
-system.cpu.dtb.perms_faults 0
-system.cpu.dtb.read_accesses 0
-system.cpu.dtb.write_accesses 0
-system.cpu.dtb.inst_accesses 0
-system.cpu.dtb.hits 0
-system.cpu.dtb.misses 0
-system.cpu.dtb.accesses 0
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 372284000
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
-system.cpu.istage2_mmu.stage2_tlb.hits 0
-system.cpu.istage2_mmu.stage2_tlb.misses 0
-system.cpu.istage2_mmu.stage2_tlb.accesses 0
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 372284000
-system.cpu.itb.walker.walks 0
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0
-system.cpu.itb.walker.walkRequestOrigin::total 0
-system.cpu.itb.inst_hits 0
-system.cpu.itb.inst_misses 0
-system.cpu.itb.read_hits 0
-system.cpu.itb.read_misses 0
-system.cpu.itb.write_hits 0
-system.cpu.itb.write_misses 0
-system.cpu.itb.flush_tlb 0
-system.cpu.itb.flush_tlb_mva 0
-system.cpu.itb.flush_tlb_mva_asid 0
-system.cpu.itb.flush_tlb_asid 0
-system.cpu.itb.flush_entries 0
-system.cpu.itb.align_faults 0
-system.cpu.itb.prefetch_faults 0
-system.cpu.itb.domain_faults 0
-system.cpu.itb.perms_faults 0
-system.cpu.itb.read_accesses 0
-system.cpu.itb.write_accesses 0
-system.cpu.itb.inst_accesses 0
-system.cpu.itb.hits 0
-system.cpu.itb.misses 0
-system.cpu.itb.accesses 0
-system.cpu.workload.numSyscalls 13
-system.cpu.pwrStateResidencyTicks::ON 372284000
-system.cpu.numCycles 372284
-system.cpu.numWorkItemsStarted 0
-system.cpu.numWorkItemsCompleted 0
-system.cpu.committedInsts 4988
-system.cpu.committedOps 5770
-system.cpu.num_int_alu_accesses 4977
-system.cpu.num_fp_alu_accesses 16
-system.cpu.num_func_calls 215
-system.cpu.num_conditional_control_insts 800
-system.cpu.num_int_insts 4977
-system.cpu.num_fp_insts 16
-system.cpu.num_int_register_reads 8049
-system.cpu.num_int_register_writes 2992
-system.cpu.num_fp_register_reads 16
-system.cpu.num_fp_register_writes 0
-system.cpu.num_cc_register_reads 20681
-system.cpu.num_cc_register_writes 2647
-system.cpu.num_mem_refs 2035
-system.cpu.num_load_insts 1085
-system.cpu.num_store_insts 950
-system.cpu.num_idle_cycles 0
-system.cpu.num_busy_cycles 372284
-system.cpu.not_idle_fraction 1
-system.cpu.idle_fraction 0
-system.cpu.Branches 1107
-system.cpu.op_class::No_OpClass 0 0.00% 0.00%
-system.cpu.op_class::IntAlu 3789 64.98% 64.98%
-system.cpu.op_class::IntMult 4 0.07% 65.05%
-system.cpu.op_class::IntDiv 0 0.00% 65.05%
-system.cpu.op_class::FloatAdd 0 0.00% 65.05%
-system.cpu.op_class::FloatCmp 0 0.00% 65.05%
-system.cpu.op_class::FloatCvt 0 0.00% 65.05%
-system.cpu.op_class::FloatMult 0 0.00% 65.05%
-system.cpu.op_class::FloatMultAcc 0 0.00% 65.05%
-system.cpu.op_class::FloatDiv 0 0.00% 65.05%
-system.cpu.op_class::FloatMisc 0 0.00% 65.05%
-system.cpu.op_class::FloatSqrt 0 0.00% 65.05%
-system.cpu.op_class::SimdAdd 0 0.00% 65.05%
-system.cpu.op_class::SimdAddAcc 0 0.00% 65.05%
-system.cpu.op_class::SimdAlu 0 0.00% 65.05%
-system.cpu.op_class::SimdCmp 0 0.00% 65.05%
-system.cpu.op_class::SimdCvt 0 0.00% 65.05%
-system.cpu.op_class::SimdMisc 0 0.00% 65.05%
-system.cpu.op_class::SimdMult 0 0.00% 65.05%
-system.cpu.op_class::SimdMultAcc 0 0.00% 65.05%
-system.cpu.op_class::SimdShift 0 0.00% 65.05%
-system.cpu.op_class::SimdShiftAcc 0 0.00% 65.05%
-system.cpu.op_class::SimdSqrt 0 0.00% 65.05%
-system.cpu.op_class::SimdFloatAdd 0 0.00% 65.05%
-system.cpu.op_class::SimdFloatAlu 0 0.00% 65.05%
-system.cpu.op_class::SimdFloatCmp 0 0.00% 65.05%
-system.cpu.op_class::SimdFloatCvt 0 0.00% 65.05%
-system.cpu.op_class::SimdFloatDiv 0 0.00% 65.05%
-system.cpu.op_class::SimdFloatMisc 3 0.05% 65.10%
-system.cpu.op_class::SimdFloatMult 0 0.00% 65.10%
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10%
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10%
-system.cpu.op_class::MemRead 1085 18.61% 83.71%
-system.cpu.op_class::MemWrite 934 16.02% 99.73%
-system.cpu.op_class::FloatMemRead 0 0.00% 99.73%
-system.cpu.op_class::FloatMemWrite 16 0.27% 100.00%
-system.cpu.op_class::IprAccess 0 0.00% 100.00%
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
-system.cpu.op_class::total 5831
-system.membus.snoop_filter.tot_requests 0
-system.membus.snoop_filter.hit_single_requests 0
-system.membus.snoop_filter.hit_multi_requests 0
-system.membus.snoop_filter.tot_snoops 0
-system.membus.snoop_filter.hit_single_snoops 0
-system.membus.snoop_filter.hit_multi_snoops 0
-system.membus.pwrStateResidencyTicks::UNDEFINED 372284000
-system.membus.trans_dist::ReadReq 6078
-system.membus.trans_dist::ReadResp 6088
-system.membus.trans_dist::WriteReq 925
-system.membus.trans_dist::WriteResp 925
-system.membus.trans_dist::LoadLockedReq 11
-system.membus.trans_dist::StoreCondReq 11
-system.membus.trans_dist::StoreCondResp 11
-system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 10055
-system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 3994
-system.membus.pkt_count::total 14049
-system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 20108
-system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 8368
-system.membus.pkt_size::total 28476
-system.membus.snoops 0
-system.membus.snoopTraffic 0
-system.membus.snoop_fanout::samples 7025
-system.membus.snoop_fanout::mean 0
-system.membus.snoop_fanout::stdev 0
-system.membus.snoop_fanout::underflows 0 0.00% 0.00%
-system.membus.snoop_fanout::0 7025 100.00% 100.00%
-system.membus.snoop_fanout::1 0 0.00% 100.00%
-system.membus.snoop_fanout::overflows 0 0.00% 100.00%
-system.membus.snoop_fanout::min_value 0
-system.membus.snoop_fanout::max_value 0
-system.membus.snoop_fanout::total 7025
-system.membus.reqLayer0.occupancy 7961000
-system.membus.reqLayer0.utilization 2.1
-system.membus.respLayer0.occupancy 11413250
-system.membus.respLayer0.utilization 3.1
-system.membus.respLayer1.occupancy 3327250
-system.membus.respLayer1.utilization 0.9
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:536870911:0:0:0:0
-memories=system.mem_ctrl
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.clk_domain.voltage_domain
-
-[system.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.clk_domain
-cpu_id=-1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=65536
-system=system
-tag_latency=2
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.l2bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=65536
-tag_latency=2
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=16384
-system=system
-tag_latency=2
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.icache_port
-mem_side=system.l2bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=16384
-tag_latency=2
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=Process
-cmd=tests/test-progs/hello/bin/arm/linux/hello
-cwd=
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=
-gid=100
-input=cin
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.l2bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.l2bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.l2bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-data_latency=20
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=262144
-system=system
-tag_latency=20
-tags=system.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.l2bus.master[0]
-mem_side=system.membus.slave[0]
-
-[system.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-data_latency=20
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-tag_latency=20
-
-[system.mem_ctrl]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:536870911:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.mem_ctrl.port
-slave=system.l2cache.mem_side system.system_port
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Entering event queue @ 0. Starting simulation...
+++ /dev/null
-Redirecting stdout to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Apr 3 2017 17:55:48
-gem5 started Apr 3 2017 18:08:19
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 55755
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level
-
-Global frequency set at 1000000000000 ticks per second
-Beginning simulation!
-Hello world!
-Exiting @ tick 52453000 because exiting with last active thread context
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000052
-sim_ticks 52453000
-final_tick 52453000
-sim_freq 1000000000000
-host_inst_rate 255460
-host_op_rate 295178
-host_tick_rate 2680706051
-host_mem_usage 666596
-host_seconds 0.02
-sim_insts 4988
-sim_ops 5770
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 52453000
-system.mem_ctrl.bytes_read::cpu.inst 14400
-system.mem_ctrl.bytes_read::cpu.data 8064
-system.mem_ctrl.bytes_read::total 22464
-system.mem_ctrl.bytes_inst_read::cpu.inst 14400
-system.mem_ctrl.bytes_inst_read::total 14400
-system.mem_ctrl.num_reads::cpu.inst 225
-system.mem_ctrl.num_reads::cpu.data 126
-system.mem_ctrl.num_reads::total 351
-system.mem_ctrl.bw_read::cpu.inst 274531485
-system.mem_ctrl.bw_read::cpu.data 153737632
-system.mem_ctrl.bw_read::total 428269117
-system.mem_ctrl.bw_inst_read::cpu.inst 274531485
-system.mem_ctrl.bw_inst_read::total 274531485
-system.mem_ctrl.bw_total::cpu.inst 274531485
-system.mem_ctrl.bw_total::cpu.data 153737632
-system.mem_ctrl.bw_total::total 428269117
-system.mem_ctrl.readReqs 351
-system.mem_ctrl.writeReqs 0
-system.mem_ctrl.readBursts 351
-system.mem_ctrl.writeBursts 0
-system.mem_ctrl.bytesReadDRAM 22464
-system.mem_ctrl.bytesReadWrQ 0
-system.mem_ctrl.bytesWritten 0
-system.mem_ctrl.bytesReadSys 22464
-system.mem_ctrl.bytesWrittenSys 0
-system.mem_ctrl.servicedByWrQ 0
-system.mem_ctrl.mergedWrBursts 0
-system.mem_ctrl.neitherReadNorWriteReqs 0
-system.mem_ctrl.perBankRdBursts::0 78
-system.mem_ctrl.perBankRdBursts::1 42
-system.mem_ctrl.perBankRdBursts::2 13
-system.mem_ctrl.perBankRdBursts::3 33
-system.mem_ctrl.perBankRdBursts::4 14
-system.mem_ctrl.perBankRdBursts::5 31
-system.mem_ctrl.perBankRdBursts::6 34
-system.mem_ctrl.perBankRdBursts::7 9
-system.mem_ctrl.perBankRdBursts::8 4
-system.mem_ctrl.perBankRdBursts::9 6
-system.mem_ctrl.perBankRdBursts::10 25
-system.mem_ctrl.perBankRdBursts::11 43
-system.mem_ctrl.perBankRdBursts::12 8
-system.mem_ctrl.perBankRdBursts::13 5
-system.mem_ctrl.perBankRdBursts::14 0
-system.mem_ctrl.perBankRdBursts::15 6
-system.mem_ctrl.perBankWrBursts::0 0
-system.mem_ctrl.perBankWrBursts::1 0
-system.mem_ctrl.perBankWrBursts::2 0
-system.mem_ctrl.perBankWrBursts::3 0
-system.mem_ctrl.perBankWrBursts::4 0
-system.mem_ctrl.perBankWrBursts::5 0
-system.mem_ctrl.perBankWrBursts::6 0
-system.mem_ctrl.perBankWrBursts::7 0
-system.mem_ctrl.perBankWrBursts::8 0
-system.mem_ctrl.perBankWrBursts::9 0
-system.mem_ctrl.perBankWrBursts::10 0
-system.mem_ctrl.perBankWrBursts::11 0
-system.mem_ctrl.perBankWrBursts::12 0
-system.mem_ctrl.perBankWrBursts::13 0
-system.mem_ctrl.perBankWrBursts::14 0
-system.mem_ctrl.perBankWrBursts::15 0
-system.mem_ctrl.numRdRetry 0
-system.mem_ctrl.numWrRetry 0
-system.mem_ctrl.totGap 52348000
-system.mem_ctrl.readPktSize::0 0
-system.mem_ctrl.readPktSize::1 0
-system.mem_ctrl.readPktSize::2 0
-system.mem_ctrl.readPktSize::3 0
-system.mem_ctrl.readPktSize::4 0
-system.mem_ctrl.readPktSize::5 0
-system.mem_ctrl.readPktSize::6 351
-system.mem_ctrl.writePktSize::0 0
-system.mem_ctrl.writePktSize::1 0
-system.mem_ctrl.writePktSize::2 0
-system.mem_ctrl.writePktSize::3 0
-system.mem_ctrl.writePktSize::4 0
-system.mem_ctrl.writePktSize::5 0
-system.mem_ctrl.writePktSize::6 0
-system.mem_ctrl.rdQLenPdf::0 351
-system.mem_ctrl.rdQLenPdf::1 0
-system.mem_ctrl.rdQLenPdf::2 0
-system.mem_ctrl.rdQLenPdf::3 0
-system.mem_ctrl.rdQLenPdf::4 0
-system.mem_ctrl.rdQLenPdf::5 0
-system.mem_ctrl.rdQLenPdf::6 0
-system.mem_ctrl.rdQLenPdf::7 0
-system.mem_ctrl.rdQLenPdf::8 0
-system.mem_ctrl.rdQLenPdf::9 0
-system.mem_ctrl.rdQLenPdf::10 0
-system.mem_ctrl.rdQLenPdf::11 0
-system.mem_ctrl.rdQLenPdf::12 0
-system.mem_ctrl.rdQLenPdf::13 0
-system.mem_ctrl.rdQLenPdf::14 0
-system.mem_ctrl.rdQLenPdf::15 0
-system.mem_ctrl.rdQLenPdf::16 0
-system.mem_ctrl.rdQLenPdf::17 0
-system.mem_ctrl.rdQLenPdf::18 0
-system.mem_ctrl.rdQLenPdf::19 0
-system.mem_ctrl.rdQLenPdf::20 0
-system.mem_ctrl.rdQLenPdf::21 0
-system.mem_ctrl.rdQLenPdf::22 0
-system.mem_ctrl.rdQLenPdf::23 0
-system.mem_ctrl.rdQLenPdf::24 0
-system.mem_ctrl.rdQLenPdf::25 0
-system.mem_ctrl.rdQLenPdf::26 0
-system.mem_ctrl.rdQLenPdf::27 0
-system.mem_ctrl.rdQLenPdf::28 0
-system.mem_ctrl.rdQLenPdf::29 0
-system.mem_ctrl.rdQLenPdf::30 0
-system.mem_ctrl.rdQLenPdf::31 0
-system.mem_ctrl.wrQLenPdf::0 0
-system.mem_ctrl.wrQLenPdf::1 0
-system.mem_ctrl.wrQLenPdf::2 0
-system.mem_ctrl.wrQLenPdf::3 0
-system.mem_ctrl.wrQLenPdf::4 0
-system.mem_ctrl.wrQLenPdf::5 0
-system.mem_ctrl.wrQLenPdf::6 0
-system.mem_ctrl.wrQLenPdf::7 0
-system.mem_ctrl.wrQLenPdf::8 0
-system.mem_ctrl.wrQLenPdf::9 0
-system.mem_ctrl.wrQLenPdf::10 0
-system.mem_ctrl.wrQLenPdf::11 0
-system.mem_ctrl.wrQLenPdf::12 0
-system.mem_ctrl.wrQLenPdf::13 0
-system.mem_ctrl.wrQLenPdf::14 0
-system.mem_ctrl.wrQLenPdf::15 0
-system.mem_ctrl.wrQLenPdf::16 0
-system.mem_ctrl.wrQLenPdf::17 0
-system.mem_ctrl.wrQLenPdf::18 0
-system.mem_ctrl.wrQLenPdf::19 0
-system.mem_ctrl.wrQLenPdf::20 0
-system.mem_ctrl.wrQLenPdf::21 0
-system.mem_ctrl.wrQLenPdf::22 0
-system.mem_ctrl.wrQLenPdf::23 0
-system.mem_ctrl.wrQLenPdf::24 0
-system.mem_ctrl.wrQLenPdf::25 0
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-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu dvfs_handler mem_ctrl membus
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:536870911:0:0:0:0
-memories=system.mem_ctrl
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[2]
-
-[system.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.clk_domain.voltage_domain
-
-[system.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dtb interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.clk_domain
-cpu_id=-1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.membus.slave[1]
-icache_port=system.membus.slave[0]
-
-[system.cpu.dtb]
-type=MipsTLB
-eventq_index=0
-size=64
-
-[system.cpu.interrupts]
-type=MipsInterrupts
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-
-[system.cpu.isa]
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-num_threads=1
-num_vpes=1
-system=system
-
-[system.cpu.itb]
-type=MipsTLB
-eventq_index=0
-size=64
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=tests/test-progs/hello/bin/mips/linux/hello
-cwd=
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=
-gid=100
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.mem_ctrl]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:536870911:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.mem_ctrl.port
-slave=system.cpu.icache_port system.cpu.dcache_port system.system_port
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+++ /dev/null
-Redirecting stdout to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple/simout
-Redirecting stderr to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 13 2016 20:36:34
-gem5 started Oct 13 2016 20:36:59
-gem5 executing on e108600-lin, pid 36838
-command line: /work/curdun01/gem5-external.hg/build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple
-
-Global frequency set at 1000000000000 ticks per second
-Beginning simulation!
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-Hello World!
-Exiting @ tick 423127000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000423 # Number of seconds simulated
-sim_ticks 423127000 # Number of ticks simulated
-final_tick 423127000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 225323 # Simulator instruction rate (inst/s)
-host_op_rate 225118 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 16871799532 # Simulator tick rate (ticks/s)
-host_mem_usage 632064 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
-sim_insts 5641 # Number of instructions simulated
-sim_ops 5641 # Number of ops (including micro ops) simulated
-system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 423127000 # Cumulative time (in ticks) in various power states
-system.mem_ctrl.bytes_read::cpu.inst 22568 # Number of bytes read from this memory
-system.mem_ctrl.bytes_read::cpu.data 4301 # Number of bytes read from this memory
-system.mem_ctrl.bytes_read::total 26869 # Number of bytes read from this memory
-system.mem_ctrl.bytes_inst_read::cpu.inst 22568 # Number of instructions bytes read from this memory
-system.mem_ctrl.bytes_inst_read::total 22568 # Number of instructions bytes read from this memory
-system.mem_ctrl.bytes_written::cpu.data 3601 # Number of bytes written to this memory
-system.mem_ctrl.bytes_written::total 3601 # Number of bytes written to this memory
-system.mem_ctrl.num_reads::cpu.inst 5642 # Number of read requests responded to by this memory
-system.mem_ctrl.num_reads::cpu.data 1135 # Number of read requests responded to by this memory
-system.mem_ctrl.num_reads::total 6777 # Number of read requests responded to by this memory
-system.mem_ctrl.num_writes::cpu.data 901 # Number of write requests responded to by this memory
-system.mem_ctrl.num_writes::total 901 # Number of write requests responded to by this memory
-system.mem_ctrl.bw_read::cpu.inst 53336232 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::cpu.data 10164797 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::total 63501029 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::cpu.inst 53336232 # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::total 53336232 # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_write::cpu.data 8510447 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_write::total 8510447 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.inst 53336232 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.data 18675244 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::total 72011476 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.readReqs 6778 # Number of read requests accepted
-system.mem_ctrl.writeReqs 901 # Number of write requests accepted
-system.mem_ctrl.readBursts 6778 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrl.writeBursts 901 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrl.bytesReadDRAM 427712 # Total number of bytes read from DRAM
-system.mem_ctrl.bytesReadWrQ 6080 # Total number of bytes read from write queue
-system.mem_ctrl.bytesWritten 4096 # Total number of bytes written to DRAM
-system.mem_ctrl.bytesReadSys 26873 # Total read bytes from the system interface side
-system.mem_ctrl.bytesWrittenSys 3601 # Total written bytes from the system interface side
-system.mem_ctrl.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrl.mergedWrBursts 808 # Number of DRAM write bursts merged with an existing one
-system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrl.perBankRdBursts::0 275 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::1 0 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::2 0 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::3 0 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::4 215 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::5 18 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::6 105 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::7 516 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::8 543 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::9 1212 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::10 899 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::11 350 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::12 677 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::13 398 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::14 1426 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::15 49 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::7 5 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::9 7 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::11 2 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::12 30 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::14 19 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::15 1 # Per bank write bursts
-system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry
-system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrl.totGap 423050000 # Total gap between requests
-system.mem_ctrl.readPktSize::0 79 # Read request sizes (log2)
-system.mem_ctrl.readPktSize::1 1 # Read request sizes (log2)
-system.mem_ctrl.readPktSize::2 6698 # Read request sizes (log2)
-system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2)
-system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2)
-system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrl.readPktSize::6 0 # Read request sizes (log2)
-system.mem_ctrl.writePktSize::0 1 # Write request sizes (log2)
-system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2)
-system.mem_ctrl.writePktSize::2 900 # Write request sizes (log2)
-system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2)
-system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2)
-system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2)
-system.mem_ctrl.rdQLenPdf::0 6683 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::17 5 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::18 5 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::19 5 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::20 5 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::21 5 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::22 5 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::23 5 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::24 5 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::25 5 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::26 5 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::27 5 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::28 5 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::29 4 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::30 4 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::31 4 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::32 4 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrl.bytesPerActivate::samples 846 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::mean 508.141844 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::gmean 296.960814 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::stdev 409.521445 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::0-127 262 30.97% 30.97% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::128-255 81 9.57% 40.54% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::256-383 50 5.91% 46.45% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::384-511 56 6.62% 53.07% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::512-639 41 4.85% 57.92% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::640-767 45 5.32% 63.24% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::768-895 28 3.31% 66.55% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::896-1023 22 2.60% 69.15% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::1024-1151 261 30.85% 100.00% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::total 846 # Bytes accessed per row activation
-system.mem_ctrl.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::mean 1385.500000 # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::gmean 1320.719140 # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::stdev 457.578044 # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::768-831 1 25.00% 25.00% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::1216-1279 1 25.00% 50.00% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::1664-1727 1 25.00% 75.00% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::1792-1855 1 25.00% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::total 4 # Reads before turning the bus around for writes
-system.mem_ctrl.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads
-system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads
-system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads
-system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrl.wrPerTurnAround::total 4 # Writes before turning the bus around for reads
-system.mem_ctrl.totQLat 74613750 # Total ticks spent queuing
-system.mem_ctrl.totMemAccLat 199920000 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrl.totBusLat 33415000 # Total ticks spent in databus transfers
-system.mem_ctrl.avgQLat 11164.71 # Average queueing delay per DRAM burst
-system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.mem_ctrl.avgMemAccLat 29914.71 # Average memory access latency per DRAM burst
-system.mem_ctrl.avgRdBW 1010.84 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrl.avgWrBW 9.68 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrl.avgRdBWSys 63.51 # Average system read bandwidth in MiByte/s
-system.mem_ctrl.avgWrBWSys 8.51 # Average system write bandwidth in MiByte/s
-system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrl.busUtil 7.97 # Data bus utilization in percentage
-system.mem_ctrl.busUtilRead 7.90 # Data bus utilization in percentage for reads
-system.mem_ctrl.busUtilWrite 0.08 # Data bus utilization in percentage for writes
-system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrl.avgWrQLen 22.62 # Average write queue length when enqueuing
-system.mem_ctrl.readRowHits 5839 # Number of row buffer hits during reads
-system.mem_ctrl.writeRowHits 57 # Number of row buffer hits during writes
-system.mem_ctrl.readRowHitRate 87.37 # Row buffer hit rate for reads
-system.mem_ctrl.writeRowHitRate 61.29 # Row buffer hit rate for writes
-system.mem_ctrl.avgGap 55091.81 # Average gap between requests
-system.mem_ctrl.pageHitRate 87.01 # Row buffer hit rate, read and write combined
-system.mem_ctrl_0.actEnergy 985320 # Energy for activate commands per rank (pJ)
-system.mem_ctrl_0.preEnergy 519915 # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_0.readEnergy 8061060 # Energy for read commands per rank (pJ)
-system.mem_ctrl_0.writeEnergy 26100 # Energy for write commands per rank (pJ)
-system.mem_ctrl_0.refreshEnergy 33190560.000000 # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_0.actBackEnergy 21232500 # Energy for active background per rank (pJ)
-system.mem_ctrl_0.preBackEnergy 1932000 # Energy for precharge background per rank (pJ)
-system.mem_ctrl_0.actPowerDownEnergy 84890100 # Energy for active power-down per rank (pJ)
-system.mem_ctrl_0.prePowerDownEnergy 43723680 # Energy for precharge power-down per rank (pJ)
-system.mem_ctrl_0.selfRefreshEnergy 22684200 # Energy for self refresh per rank (pJ)
-system.mem_ctrl_0.totalEnergy 217245435 # Total energy per rank (pJ)
-system.mem_ctrl_0.averagePower 513.427832 # Core power per rank (mW)
-system.mem_ctrl_0.totalIdleTime 369366500 # Total Idle time Per DRAM Rank
-system.mem_ctrl_0.memoryStateTime::IDLE 2976000 # Time in different power states
-system.mem_ctrl_0.memoryStateTime::REF 14106000 # Time in different power states
-system.mem_ctrl_0.memoryStateTime::SREF 71507250 # Time in different power states
-system.mem_ctrl_0.memoryStateTime::PRE_PDN 113857500 # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT 34569250 # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT_PDN 186111000 # Time in different power states
-system.mem_ctrl_1.actEnergy 5090820 # Energy for activate commands per rank (pJ)
-system.mem_ctrl_1.preEnergy 2690655 # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_1.readEnergy 39648420 # Energy for read commands per rank (pJ)
-system.mem_ctrl_1.writeEnergy 307980 # Energy for write commands per rank (pJ)
-system.mem_ctrl_1.refreshEnergy 33190560.000000 # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_1.actBackEnergy 77391750 # Energy for active background per rank (pJ)
-system.mem_ctrl_1.preBackEnergy 1169760 # Energy for precharge background per rank (pJ)
-system.mem_ctrl_1.actPowerDownEnergy 113578770 # Energy for active power-down per rank (pJ)
-system.mem_ctrl_1.prePowerDownEnergy 493920 # Energy for precharge power-down per rank (pJ)
-system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
-system.mem_ctrl_1.totalEnergy 273562635 # Total energy per rank (pJ)
-system.mem_ctrl_1.averagePower 646.525303 # Core power per rank (mW)
-system.mem_ctrl_1.totalIdleTime 250424500 # Total Idle time Per DRAM Rank
-system.mem_ctrl_1.memoryStateTime::IDLE 900000 # Time in different power states
-system.mem_ctrl_1.memoryStateTime::REF 14040000 # Time in different power states
-system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states
-system.mem_ctrl_1.memoryStateTime::PRE_PDN 1291250 # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT 157762500 # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT_PDN 249133250 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 423127000 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 7 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 423127000 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 423127 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 5641 # Number of instructions committed
-system.cpu.committedOps 5641 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
-system.cpu.num_func_calls 191 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls
-system.cpu.num_int_insts 4957 # number of integer instructions
-system.cpu.num_fp_insts 2 # number of float instructions
-system.cpu.num_int_register_reads 7072 # number of times the integer registers were read
-system.cpu.num_int_register_writes 3291 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
-system.cpu.num_mem_refs 2037 # number of memory refs
-system.cpu.num_load_insts 1135 # Number of load instructions
-system.cpu.num_store_insts 902 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 423127 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 886 # Number of branches fetched
-system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction
-system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction
-system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction
-system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction
-system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 5642 # Class of executed instruction
-system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 423127000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 6778 # Transaction distribution
-system.membus.trans_dist::ReadResp 6777 # Transaction distribution
-system.membus.trans_dist::WriteReq 901 # Transaction distribution
-system.membus.trans_dist::WriteResp 901 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 11285 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4072 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 15357 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 22568 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 7902 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 30470 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 7679 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 7679 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 7679 # Request fanout histogram
-system.membus.reqLayer0.occupancy 8580000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 2.0 # Layer utilization (%)
-system.membus.respLayer0.occupancy 12855500 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 3.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 3550250 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.8 # Layer utilization (%)
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:536870911:0:0:0:0
-memories=system.mem_ctrl
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.clk_domain.voltage_domain
-
-[system.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dtb icache interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.clk_domain
-cpu_id=-1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=65536
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.l2bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=65536
-
-[system.cpu.dtb]
-type=MipsTLB
-eventq_index=0
-size=64
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=16384
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.icache_port
-mem_side=system.l2bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=16384
-
-[system.cpu.interrupts]
-type=MipsInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=MipsISA
-eventq_index=0
-num_threads=1
-num_vpes=1
-system=system
-
-[system.cpu.itb]
-type=MipsTLB
-eventq_index=0
-size=64
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=tests/test-progs/hello/bin/mips/linux/hello
-cwd=
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=
-gid=100
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.l2bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.l2bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.l2bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=262144
-system=system
-tags=system.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.l2bus.master[0]
-mem_side=system.membus.slave[0]
-
-[system.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-
-[system.mem_ctrl]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:536870911:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.mem_ctrl.port
-slave=system.l2cache.mem_side system.system_port
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+++ /dev/null
-Redirecting stdout to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level/simout
-Redirecting stderr to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 13 2016 20:36:34
-gem5 started Oct 13 2016 20:36:59
-gem5 executing on e108600-lin, pid 36839
-command line: /work/curdun01/gem5-external.hg/build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level
-
-Global frequency set at 1000000000000 ticks per second
-Beginning simulation!
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-Hello World!
-Exiting @ tick 62333000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000062 # Number of seconds simulated
-sim_ticks 62333000 # Number of ticks simulated
-final_tick 62333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 472885 # Simulator instruction rate (inst/s)
-host_op_rate 471880 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5205204018 # Simulator tick rate (ticks/s)
-host_mem_usage 636424 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-sim_insts 5641 # Number of instructions simulated
-sim_ops 5641 # Number of ops (including micro ops) simulated
-system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
-system.mem_ctrl.bytes_read::cpu.inst 18752 # Number of bytes read from this memory
-system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory
-system.mem_ctrl.bytes_read::total 27520 # Number of bytes read from this memory
-system.mem_ctrl.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory
-system.mem_ctrl.bytes_inst_read::total 18752 # Number of instructions bytes read from this memory
-system.mem_ctrl.num_reads::cpu.inst 293 # Number of read requests responded to by this memory
-system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory
-system.mem_ctrl.num_reads::total 430 # Number of read requests responded to by this memory
-system.mem_ctrl.bw_read::cpu.inst 300835833 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::cpu.data 140663854 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::total 441499687 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::cpu.inst 300835833 # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::total 300835833 # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.inst 300835833 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.data 140663854 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::total 441499687 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.readReqs 430 # Number of read requests accepted
-system.mem_ctrl.writeReqs 0 # Number of write requests accepted
-system.mem_ctrl.readBursts 430 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrl.bytesReadDRAM 27520 # Total number of bytes read from DRAM
-system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue
-system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM
-system.mem_ctrl.bytesReadSys 27520 # Total read bytes from the system interface side
-system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side
-system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrl.perBankRdBursts::0 25 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::1 0 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::2 0 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::3 0 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::4 6 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::5 3 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::6 11 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::7 49 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::8 53 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::9 74 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::10 34 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::11 19 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::12 50 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::13 27 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::14 72 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::15 7 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts
-system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry
-system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrl.totGap 62196000 # Total gap between requests
-system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2)
-system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2)
-system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2)
-system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2)
-system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2)
-system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrl.readPktSize::6 430 # Read request sizes (log2)
-system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2)
-system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2)
-system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2)
-system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2)
-system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2)
-system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2)
-system.mem_ctrl.rdQLenPdf::0 430 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrl.bytesPerActivate::samples 113 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::mean 241.840708 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::gmean 173.064480 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::stdev 223.138673 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::0-127 30 26.55% 26.55% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::128-255 41 36.28% 62.83% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::256-383 20 17.70% 80.53% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::384-511 8 7.08% 87.61% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::512-639 5 4.42% 92.04% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::640-767 2 1.77% 93.81% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::768-895 3 2.65% 96.46% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::896-1023 1 0.88% 97.35% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::1024-1151 3 2.65% 100.00% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::total 113 # Bytes accessed per row activation
-system.mem_ctrl.totQLat 6850250 # Total ticks spent queuing
-system.mem_ctrl.totMemAccLat 14912750 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrl.totBusLat 2150000 # Total ticks spent in databus transfers
-system.mem_ctrl.avgQLat 15930.81 # Average queueing delay per DRAM burst
-system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.mem_ctrl.avgMemAccLat 34680.81 # Average memory access latency per DRAM burst
-system.mem_ctrl.avgRdBW 441.50 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrl.avgRdBWSys 441.50 # Average system read bandwidth in MiByte/s
-system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
-system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrl.busUtil 3.45 # Data bus utilization in percentage
-system.mem_ctrl.busUtilRead 3.45 # Data bus utilization in percentage for reads
-system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.mem_ctrl.readRowHits 316 # Number of row buffer hits during reads
-system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes
-system.mem_ctrl.readRowHitRate 73.49 # Row buffer hit rate for reads
-system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes
-system.mem_ctrl.avgGap 144641.86 # Average gap between requests
-system.mem_ctrl.pageHitRate 73.49 # Row buffer hit rate, read and write combined
-system.mem_ctrl_0.actEnergy 192780 # Energy for activate commands per rank (pJ)
-system.mem_ctrl_0.preEnergy 98670 # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_0.readEnergy 671160 # Energy for read commands per rank (pJ)
-system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrl_0.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_0.actBackEnergy 2176830 # Energy for active background per rank (pJ)
-system.mem_ctrl_0.preBackEnergy 210240 # Energy for precharge background per rank (pJ)
-system.mem_ctrl_0.actPowerDownEnergy 19527630 # Energy for active power-down per rank (pJ)
-system.mem_ctrl_0.prePowerDownEnergy 3815040 # Energy for precharge power-down per rank (pJ)
-system.mem_ctrl_0.selfRefreshEnergy 1573140 # Energy for self refresh per rank (pJ)
-system.mem_ctrl_0.totalEnergy 33182610 # Total energy per rank (pJ)
-system.mem_ctrl_0.averagePower 532.337778 # Core power per rank (mW)
-system.mem_ctrl_0.totalIdleTime 56494000 # Total Idle time Per DRAM Rank
-system.mem_ctrl_0.memoryStateTime::IDLE 323000 # Time in different power states
-system.mem_ctrl_0.memoryStateTime::REF 2086000 # Time in different power states
-system.mem_ctrl_0.memoryStateTime::SREF 4253250 # Time in different power states
-system.mem_ctrl_0.memoryStateTime::PRE_PDN 9935000 # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT 2911750 # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT_PDN 42824000 # Time in different power states
-system.mem_ctrl_1.actEnergy 621180 # Energy for activate commands per rank (pJ)
-system.mem_ctrl_1.preEnergy 330165 # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_1.readEnergy 2399040 # Energy for read commands per rank (pJ)
-system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrl_1.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_1.actBackEnergy 5632170 # Energy for active background per rank (pJ)
-system.mem_ctrl_1.preBackEnergy 168480 # Energy for precharge background per rank (pJ)
-system.mem_ctrl_1.actPowerDownEnergy 22617030 # Energy for active power-down per rank (pJ)
-system.mem_ctrl_1.prePowerDownEnergy 64320 # Energy for precharge power-down per rank (pJ)
-system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
-system.mem_ctrl_1.totalEnergy 36749505 # Total energy per rank (pJ)
-system.mem_ctrl_1.averagePower 587.463363 # Core power per rank (mW)
-system.mem_ctrl_1.totalIdleTime 49768000 # Total Idle time Per DRAM Rank
-system.mem_ctrl_1.memoryStateTime::IDLE 176000 # Time in different power states
-system.mem_ctrl_1.memoryStateTime::REF 1843250 # Time in different power states
-system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states
-system.mem_ctrl_1.memoryStateTime::PRE_PDN 167500 # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT 10545750 # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT_PDN 49600500 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 7 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 62333000 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 62333 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 5641 # Number of instructions committed
-system.cpu.committedOps 5641 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
-system.cpu.num_func_calls 191 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls
-system.cpu.num_int_insts 4957 # number of integer instructions
-system.cpu.num_fp_insts 2 # number of float instructions
-system.cpu.num_int_register_reads 7072 # number of times the integer registers were read
-system.cpu.num_int_register_writes 3291 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
-system.cpu.num_mem_refs 2037 # number of memory refs
-system.cpu.num_load_insts 1135 # Number of load instructions
-system.cpu.num_store_insts 902 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 62333 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 886 # Number of branches fetched
-system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction
-system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction
-system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction
-system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction
-system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction
-system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 5642 # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 86.045434 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 86.045434 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.084029 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.084029 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits
-system.cpu.dcache.overall_hits::total 1899 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses
-system.cpu.dcache.overall_misses::total 137 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 10089000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 10089000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 5605000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 5605000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 15694000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 15694000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 15694000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 15694000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1135 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1135 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2036 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2036 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2036 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2036 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076652 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.076652 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.067289 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.067289 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.067289 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.067289 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115965.517241 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 115965.517241 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 112100 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 112100 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 114554.744526 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 114554.744526 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 114554.744526 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 114554.744526 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9915000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 9915000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5505000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 5505000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15420000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 15420000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15420000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 15420000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076652 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076652 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.067289 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.067289 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 113965.517241 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 113965.517241 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 110100 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 110100 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 112554.744526 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 112554.744526 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 112554.744526 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 112554.744526 # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements 94 # number of replacements
-system.cpu.icache.tags.tagsinuse 109.768952 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 5346 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 297 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 18 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 109.768952 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.428785 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.428785 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 203 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 11583 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 11583 # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst 5346 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 5346 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 5346 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 5346 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 5346 # number of overall hits
-system.cpu.icache.overall_hits::total 5346 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 297 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 297 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 297 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 297 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 297 # number of overall misses
-system.cpu.icache.overall_misses::total 297 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 32151000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 32151000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 32151000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 32151000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 32151000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 32151000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 5643 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 5643 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 5643 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 5643 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 5643 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 5643 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052632 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.052632 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.052632 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.052632 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.052632 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.052632 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 108252.525253 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 108252.525253 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 108252.525253 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 108252.525253 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 108252.525253 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 108252.525253 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 297 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 297 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31557000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 31557000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31557000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 31557000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31557000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 31557000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052632 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.052632 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.052632 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 106252.525253 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 106252.525253 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 106252.525253 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 106252.525253 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 106252.525253 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 106252.525253 # average overall mshr miss latency
-system.l2bus.snoop_filter.tot_requests 528 # Total number of requests made to the snoop filter.
-system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.l2bus.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
-system.l2bus.trans_dist::ReadResp 384 # Transaction distribution
-system.l2bus.trans_dist::CleanEvict 94 # Transaction distribution
-system.l2bus.trans_dist::ReadExReq 50 # Transaction distribution
-system.l2bus.trans_dist::ReadExResp 50 # Transaction distribution
-system.l2bus.trans_dist::ReadSharedReq 384 # Transaction distribution
-system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 688 # Packet count per connected master and slave (bytes)
-system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes)
-system.l2bus.pkt_count::total 962 # Packet count per connected master and slave (bytes)
-system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 19008 # Cumulative packet size per connected master and slave (bytes)
-system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes)
-system.l2bus.pkt_size::total 27776 # Cumulative packet size per connected master and slave (bytes)
-system.l2bus.snoops 0 # Total snoops (count)
-system.l2bus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.l2bus.snoop_fanout::samples 434 # Request fanout histogram
-system.l2bus.snoop_fanout::mean 0 # Request fanout histogram
-system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram
-system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.l2bus.snoop_fanout::0 434 100.00% 100.00% # Request fanout histogram
-system.l2bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.l2bus.snoop_fanout::max_value 0 # Request fanout histogram
-system.l2bus.snoop_fanout::total 434 # Request fanout histogram
-system.l2bus.reqLayer0.occupancy 528000 # Layer occupancy (ticks)
-system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%)
-system.l2bus.respLayer0.occupancy 891000 # Layer occupancy (ticks)
-system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%)
-system.l2bus.respLayer1.occupancy 411000 # Layer occupancy (ticks)
-system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%)
-system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
-system.l2cache.tags.replacements 0 # number of replacements
-system.l2cache.tags.tagsinuse 215.766788 # Cycle average of tags in use
-system.l2cache.tags.total_refs 98 # Total number of references to valid blocks.
-system.l2cache.tags.sampled_refs 430 # Sample count of references to valid blocks.
-system.l2cache.tags.avg_refs 0.227907 # Average number of references to valid blocks.
-system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2cache.tags.occ_blocks::cpu.inst 129.675199 # Average occupied blocks per requestor
-system.l2cache.tags.occ_blocks::cpu.data 86.091590 # Average occupied blocks per requestor
-system.l2cache.tags.occ_percent::cpu.inst 0.031659 # Average percentage of cache occupancy
-system.l2cache.tags.occ_percent::cpu.data 0.021018 # Average percentage of cache occupancy
-system.l2cache.tags.occ_percent::total 0.052677 # Average percentage of cache occupancy
-system.l2cache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id
-system.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id
-system.l2cache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id
-system.l2cache.tags.occ_task_id_percent::1024 0.104980 # Percentage of cache occupancy per task id
-system.l2cache.tags.tag_accesses 4654 # Number of tag accesses
-system.l2cache.tags.data_accesses 4654 # Number of data accesses
-system.l2cache.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
-system.l2cache.ReadSharedReq_hits::cpu.inst 4 # number of ReadSharedReq hits
-system.l2cache.ReadSharedReq_hits::total 4 # number of ReadSharedReq hits
-system.l2cache.demand_hits::cpu.inst 4 # number of demand (read+write) hits
-system.l2cache.demand_hits::total 4 # number of demand (read+write) hits
-system.l2cache.overall_hits::cpu.inst 4 # number of overall hits
-system.l2cache.overall_hits::total 4 # number of overall hits
-system.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses
-system.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses
-system.l2cache.ReadSharedReq_misses::cpu.inst 293 # number of ReadSharedReq misses
-system.l2cache.ReadSharedReq_misses::cpu.data 87 # number of ReadSharedReq misses
-system.l2cache.ReadSharedReq_misses::total 380 # number of ReadSharedReq misses
-system.l2cache.demand_misses::cpu.inst 293 # number of demand (read+write) misses
-system.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses
-system.l2cache.demand_misses::total 430 # number of demand (read+write) misses
-system.l2cache.overall_misses::cpu.inst 293 # number of overall misses
-system.l2cache.overall_misses::cpu.data 137 # number of overall misses
-system.l2cache.overall_misses::total 430 # number of overall misses
-system.l2cache.ReadExReq_miss_latency::cpu.data 5355000 # number of ReadExReq miss cycles
-system.l2cache.ReadExReq_miss_latency::total 5355000 # number of ReadExReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::cpu.inst 30582000 # number of ReadSharedReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::cpu.data 9654000 # number of ReadSharedReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::total 40236000 # number of ReadSharedReq miss cycles
-system.l2cache.demand_miss_latency::cpu.inst 30582000 # number of demand (read+write) miss cycles
-system.l2cache.demand_miss_latency::cpu.data 15009000 # number of demand (read+write) miss cycles
-system.l2cache.demand_miss_latency::total 45591000 # number of demand (read+write) miss cycles
-system.l2cache.overall_miss_latency::cpu.inst 30582000 # number of overall miss cycles
-system.l2cache.overall_miss_latency::cpu.data 15009000 # number of overall miss cycles
-system.l2cache.overall_miss_latency::total 45591000 # number of overall miss cycles
-system.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses)
-system.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses)
-system.l2cache.ReadSharedReq_accesses::cpu.inst 297 # number of ReadSharedReq accesses(hits+misses)
-system.l2cache.ReadSharedReq_accesses::cpu.data 87 # number of ReadSharedReq accesses(hits+misses)
-system.l2cache.ReadSharedReq_accesses::total 384 # number of ReadSharedReq accesses(hits+misses)
-system.l2cache.demand_accesses::cpu.inst 297 # number of demand (read+write) accesses
-system.l2cache.demand_accesses::cpu.data 137 # number of demand (read+write) accesses
-system.l2cache.demand_accesses::total 434 # number of demand (read+write) accesses
-system.l2cache.overall_accesses::cpu.inst 297 # number of overall (read+write) accesses
-system.l2cache.overall_accesses::cpu.data 137 # number of overall (read+write) accesses
-system.l2cache.overall_accesses::total 434 # number of overall (read+write) accesses
-system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
-system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.986532 # miss rate for ReadSharedReq accesses
-system.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
-system.l2cache.ReadSharedReq_miss_rate::total 0.989583 # miss rate for ReadSharedReq accesses
-system.l2cache.demand_miss_rate::cpu.inst 0.986532 # miss rate for demand accesses
-system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
-system.l2cache.demand_miss_rate::total 0.990783 # miss rate for demand accesses
-system.l2cache.overall_miss_rate::cpu.inst 0.986532 # miss rate for overall accesses
-system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
-system.l2cache.overall_miss_rate::total 0.990783 # miss rate for overall accesses
-system.l2cache.ReadExReq_avg_miss_latency::cpu.data 107100 # average ReadExReq miss latency
-system.l2cache.ReadExReq_avg_miss_latency::total 107100 # average ReadExReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 104375.426621 # average ReadSharedReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 110965.517241 # average ReadSharedReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::total 105884.210526 # average ReadSharedReq miss latency
-system.l2cache.demand_avg_miss_latency::cpu.inst 104375.426621 # average overall miss latency
-system.l2cache.demand_avg_miss_latency::cpu.data 109554.744526 # average overall miss latency
-system.l2cache.demand_avg_miss_latency::total 106025.581395 # average overall miss latency
-system.l2cache.overall_avg_miss_latency::cpu.inst 104375.426621 # average overall miss latency
-system.l2cache.overall_avg_miss_latency::cpu.data 109554.744526 # average overall miss latency
-system.l2cache.overall_avg_miss_latency::total 106025.581395 # average overall miss latency
-system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses
-system.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses
-system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 293 # number of ReadSharedReq MSHR misses
-system.l2cache.ReadSharedReq_mshr_misses::cpu.data 87 # number of ReadSharedReq MSHR misses
-system.l2cache.ReadSharedReq_mshr_misses::total 380 # number of ReadSharedReq MSHR misses
-system.l2cache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses
-system.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses
-system.l2cache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses
-system.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses
-system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses
-system.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses
-system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4355000 # number of ReadExReq MSHR miss cycles
-system.l2cache.ReadExReq_mshr_miss_latency::total 4355000 # number of ReadExReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 24722000 # number of ReadSharedReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7914000 # number of ReadSharedReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::total 32636000 # number of ReadSharedReq MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::cpu.inst 24722000 # number of demand (read+write) MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::cpu.data 12269000 # number of demand (read+write) MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::total 36991000 # number of demand (read+write) MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::cpu.inst 24722000 # number of overall MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::cpu.data 12269000 # number of overall MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::total 36991000 # number of overall MSHR miss cycles
-system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
-system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for ReadSharedReq accesses
-system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
-system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.989583 # mshr miss rate for ReadSharedReq accesses
-system.l2cache.demand_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for demand accesses
-system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.l2cache.demand_mshr_miss_rate::total 0.990783 # mshr miss rate for demand accesses
-system.l2cache.overall_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for overall accesses
-system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.l2cache.overall_mshr_miss_rate::total 0.990783 # mshr miss rate for overall accesses
-system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87100 # average ReadExReq mshr miss latency
-system.l2cache.ReadExReq_avg_mshr_miss_latency::total 87100 # average ReadExReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 84375.426621 # average ReadSharedReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90965.517241 # average ReadSharedReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 85884.210526 # average ReadSharedReq mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84375.426621 # average overall mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::cpu.data 89554.744526 # average overall mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::total 86025.581395 # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84375.426621 # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::cpu.data 89554.744526 # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::total 86025.581395 # average overall mshr miss latency
-system.membus.snoop_filter.tot_requests 430 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 380 # Transaction distribution
-system.membus.trans_dist::ReadExReq 50 # Transaction distribution
-system.membus.trans_dist::ReadExResp 50 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 380 # Transaction distribution
-system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 860 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 27520 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 430 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 430 # Request fanout histogram
-system.membus.reqLayer0.occupancy 430000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
-system.membus.respLayer0.occupancy 2298250 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 3.7 # Layer utilization (%)
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu dvfs_handler mem_ctrl membus
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:536870911:0:0:0:0
-memories=system.mem_ctrl
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[2]
-
-[system.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.clk_domain.voltage_domain
-
-[system.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dtb interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.clk_domain
-cpu_id=-1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.membus.slave[1]
-icache_port=system.membus.slave[0]
-
-[system.cpu.dtb]
-type=SparcTLB
-eventq_index=0
-size=64
-
-[system.cpu.interrupts]
-type=SparcInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=SparcISA
-eventq_index=0
-
-[system.cpu.itb]
-type=SparcTLB
-eventq_index=0
-size=64
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=Process
-cmd=tests/test-progs/hello/bin/sparc/linux/hello
-cwd=
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=
-gid=100
-input=cin
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.mem_ctrl]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:536870911:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.mem_ctrl.port
-slave=system.cpu.icache_port system.cpu.dcache_port system.system_port
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Entering event queue @ 0. Starting simulation...
+++ /dev/null
-Redirecting stdout to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Apr 3 2017 18:41:19
-gem5 started Apr 3 2017 18:41:38
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64860
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple
-
-Global frequency set at 1000000000000 ticks per second
-Beginning simulation!
-Hello World!Exiting @ tick 380341000 because exiting with last active thread context
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000380
-sim_ticks 380341000
-final_tick 380341000
-sim_freq 1000000000000
-host_inst_rate 164409
-host_op_rate 164322
-host_tick_rate 11259796640
-host_mem_usage 644796
-host_seconds 0.03
-sim_insts 5548
-sim_ops 5548
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 380341000
-system.mem_ctrl.bytes_read::cpu.inst 22364
-system.mem_ctrl.bytes_read::cpu.data 4640
-system.mem_ctrl.bytes_read::total 27004
-system.mem_ctrl.bytes_inst_read::cpu.inst 22364
-system.mem_ctrl.bytes_inst_read::total 22364
-system.mem_ctrl.bytes_written::cpu.data 5065
-system.mem_ctrl.bytes_written::total 5065
-system.mem_ctrl.num_reads::cpu.inst 5591
-system.mem_ctrl.num_reads::cpu.data 718
-system.mem_ctrl.num_reads::total 6309
-system.mem_ctrl.num_writes::cpu.data 673
-system.mem_ctrl.num_writes::total 673
-system.mem_ctrl.bw_read::cpu.inst 58799866
-system.mem_ctrl.bw_read::cpu.data 12199579
-system.mem_ctrl.bw_read::total 70999445
-system.mem_ctrl.bw_inst_read::cpu.inst 58799866
-system.mem_ctrl.bw_inst_read::total 58799866
-system.mem_ctrl.bw_write::cpu.data 13316997
-system.mem_ctrl.bw_write::total 13316997
-system.mem_ctrl.bw_total::cpu.inst 58799866
-system.mem_ctrl.bw_total::cpu.data 25516576
-system.mem_ctrl.bw_total::total 84316442
-system.mem_ctrl.readReqs 6310
-system.mem_ctrl.writeReqs 673
-system.mem_ctrl.readBursts 6310
-system.mem_ctrl.writeBursts 673
-system.mem_ctrl.bytesReadDRAM 397760
-system.mem_ctrl.bytesReadWrQ 6080
-system.mem_ctrl.bytesWritten 6144
-system.mem_ctrl.bytesReadSys 27008
-system.mem_ctrl.bytesWrittenSys 5065
-system.mem_ctrl.servicedByWrQ 95
-system.mem_ctrl.mergedWrBursts 548
-system.mem_ctrl.neitherReadNorWriteReqs 0
-system.mem_ctrl.perBankRdBursts::0 220
-system.mem_ctrl.perBankRdBursts::1 84
-system.mem_ctrl.perBankRdBursts::2 2
-system.mem_ctrl.perBankRdBursts::3 199
-system.mem_ctrl.perBankRdBursts::4 0
-system.mem_ctrl.perBankRdBursts::5 1004
-system.mem_ctrl.perBankRdBursts::6 1555
-system.mem_ctrl.perBankRdBursts::7 875
-system.mem_ctrl.perBankRdBursts::8 710
-system.mem_ctrl.perBankRdBursts::9 348
-system.mem_ctrl.perBankRdBursts::10 99
-system.mem_ctrl.perBankRdBursts::11 623
-system.mem_ctrl.perBankRdBursts::12 56
-system.mem_ctrl.perBankRdBursts::13 162
-system.mem_ctrl.perBankRdBursts::14 200
-system.mem_ctrl.perBankRdBursts::15 78
-system.mem_ctrl.perBankWrBursts::0 0
-system.mem_ctrl.perBankWrBursts::1 0
-system.mem_ctrl.perBankWrBursts::2 0
-system.mem_ctrl.perBankWrBursts::3 0
-system.mem_ctrl.perBankWrBursts::4 0
-system.mem_ctrl.perBankWrBursts::5 16
-system.mem_ctrl.perBankWrBursts::6 42
-system.mem_ctrl.perBankWrBursts::7 19
-system.mem_ctrl.perBankWrBursts::8 0
-system.mem_ctrl.perBankWrBursts::9 5
-system.mem_ctrl.perBankWrBursts::10 0
-system.mem_ctrl.perBankWrBursts::11 0
-system.mem_ctrl.perBankWrBursts::12 4
-system.mem_ctrl.perBankWrBursts::13 10
-system.mem_ctrl.perBankWrBursts::14 0
-system.mem_ctrl.perBankWrBursts::15 0
-system.mem_ctrl.numRdRetry 0
-system.mem_ctrl.numWrRetry 0
-system.mem_ctrl.totGap 380264000
-system.mem_ctrl.readPktSize::0 88
-system.mem_ctrl.readPktSize::1 2
-system.mem_ctrl.readPktSize::2 5711
-system.mem_ctrl.readPktSize::3 509
-system.mem_ctrl.readPktSize::4 0
-system.mem_ctrl.readPktSize::5 0
-system.mem_ctrl.readPktSize::6 0
-system.mem_ctrl.writePktSize::0 13
-system.mem_ctrl.writePktSize::1 2
-system.mem_ctrl.writePktSize::2 54
-system.mem_ctrl.writePktSize::3 604
-system.mem_ctrl.writePktSize::4 0
-system.mem_ctrl.writePktSize::5 0
-system.mem_ctrl.writePktSize::6 0
-system.mem_ctrl.rdQLenPdf::0 6215
-system.mem_ctrl.rdQLenPdf::1 0
-system.mem_ctrl.rdQLenPdf::2 0
-system.mem_ctrl.rdQLenPdf::3 0
-system.mem_ctrl.rdQLenPdf::4 0
-system.mem_ctrl.rdQLenPdf::5 0
-system.mem_ctrl.rdQLenPdf::6 0
-system.mem_ctrl.rdQLenPdf::7 0
-system.mem_ctrl.rdQLenPdf::8 0
-system.mem_ctrl.rdQLenPdf::9 0
-system.mem_ctrl.rdQLenPdf::10 0
-system.mem_ctrl.rdQLenPdf::11 0
-system.mem_ctrl.rdQLenPdf::12 0
-system.mem_ctrl.rdQLenPdf::13 0
-system.mem_ctrl.rdQLenPdf::14 0
-system.mem_ctrl.rdQLenPdf::15 0
-system.mem_ctrl.rdQLenPdf::16 0
-system.mem_ctrl.rdQLenPdf::17 0
-system.mem_ctrl.rdQLenPdf::18 0
-system.mem_ctrl.rdQLenPdf::19 0
-system.mem_ctrl.rdQLenPdf::20 0
-system.mem_ctrl.rdQLenPdf::21 0
-system.mem_ctrl.rdQLenPdf::22 0
-system.mem_ctrl.rdQLenPdf::23 0
-system.mem_ctrl.rdQLenPdf::24 0
-system.mem_ctrl.rdQLenPdf::25 0
-system.mem_ctrl.rdQLenPdf::26 0
-system.mem_ctrl.rdQLenPdf::27 0
-system.mem_ctrl.rdQLenPdf::28 0
-system.mem_ctrl.rdQLenPdf::29 0
-system.mem_ctrl.rdQLenPdf::30 0
-system.mem_ctrl.rdQLenPdf::31 0
-system.mem_ctrl.wrQLenPdf::0 1
-system.mem_ctrl.wrQLenPdf::1 1
-system.mem_ctrl.wrQLenPdf::2 1
-system.mem_ctrl.wrQLenPdf::3 1
-system.mem_ctrl.wrQLenPdf::4 1
-system.mem_ctrl.wrQLenPdf::5 1
-system.mem_ctrl.wrQLenPdf::6 1
-system.mem_ctrl.wrQLenPdf::7 1
-system.mem_ctrl.wrQLenPdf::8 1
-system.mem_ctrl.wrQLenPdf::9 1
-system.mem_ctrl.wrQLenPdf::10 1
-system.mem_ctrl.wrQLenPdf::11 1
-system.mem_ctrl.wrQLenPdf::12 1
-system.mem_ctrl.wrQLenPdf::13 1
-system.mem_ctrl.wrQLenPdf::14 1
-system.mem_ctrl.wrQLenPdf::15 1
-system.mem_ctrl.wrQLenPdf::16 1
-system.mem_ctrl.wrQLenPdf::17 7
-system.mem_ctrl.wrQLenPdf::18 7
-system.mem_ctrl.wrQLenPdf::19 7
-system.mem_ctrl.wrQLenPdf::20 7
-system.mem_ctrl.wrQLenPdf::21 7
-system.mem_ctrl.wrQLenPdf::22 7
-system.mem_ctrl.wrQLenPdf::23 7
-system.mem_ctrl.wrQLenPdf::24 7
-system.mem_ctrl.wrQLenPdf::25 7
-system.mem_ctrl.wrQLenPdf::26 7
-system.mem_ctrl.wrQLenPdf::27 7
-system.mem_ctrl.wrQLenPdf::28 7
-system.mem_ctrl.wrQLenPdf::29 6
-system.mem_ctrl.wrQLenPdf::30 6
-system.mem_ctrl.wrQLenPdf::31 6
-system.mem_ctrl.wrQLenPdf::32 6
-system.mem_ctrl.wrQLenPdf::33 0
-system.mem_ctrl.wrQLenPdf::34 0
-system.mem_ctrl.wrQLenPdf::35 0
-system.mem_ctrl.wrQLenPdf::36 0
-system.mem_ctrl.wrQLenPdf::37 0
-system.mem_ctrl.wrQLenPdf::38 0
-system.mem_ctrl.wrQLenPdf::39 0
-system.mem_ctrl.wrQLenPdf::40 0
-system.mem_ctrl.wrQLenPdf::41 0
-system.mem_ctrl.wrQLenPdf::42 0
-system.mem_ctrl.wrQLenPdf::43 0
-system.mem_ctrl.wrQLenPdf::44 0
-system.mem_ctrl.wrQLenPdf::45 0
-system.mem_ctrl.wrQLenPdf::46 0
-system.mem_ctrl.wrQLenPdf::47 0
-system.mem_ctrl.wrQLenPdf::48 0
-system.mem_ctrl.wrQLenPdf::49 0
-system.mem_ctrl.wrQLenPdf::50 0
-system.mem_ctrl.wrQLenPdf::51 0
-system.mem_ctrl.wrQLenPdf::52 0
-system.mem_ctrl.wrQLenPdf::53 0
-system.mem_ctrl.wrQLenPdf::54 0
-system.mem_ctrl.wrQLenPdf::55 0
-system.mem_ctrl.wrQLenPdf::56 0
-system.mem_ctrl.wrQLenPdf::57 0
-system.mem_ctrl.wrQLenPdf::58 0
-system.mem_ctrl.wrQLenPdf::59 0
-system.mem_ctrl.wrQLenPdf::60 0
-system.mem_ctrl.wrQLenPdf::61 0
-system.mem_ctrl.wrQLenPdf::62 0
-system.mem_ctrl.wrQLenPdf::63 0
-system.mem_ctrl.bytesPerActivate::samples 575
-system.mem_ctrl.bytesPerActivate::mean 700.438261
-system.mem_ctrl.bytesPerActivate::gmean 528.229400
-system.mem_ctrl.bytesPerActivate::stdev 375.888489
-system.mem_ctrl.bytesPerActivate::0-127 45 7.83% 7.83%
-system.mem_ctrl.bytesPerActivate::128-255 73 12.70% 20.52%
-system.mem_ctrl.bytesPerActivate::256-383 37 6.43% 26.96%
-system.mem_ctrl.bytesPerActivate::384-511 35 6.09% 33.04%
-system.mem_ctrl.bytesPerActivate::512-639 26 4.52% 37.57%
-system.mem_ctrl.bytesPerActivate::640-767 27 4.70% 42.26%
-system.mem_ctrl.bytesPerActivate::768-895 26 4.52% 46.78%
-system.mem_ctrl.bytesPerActivate::896-1023 27 4.70% 51.48%
-system.mem_ctrl.bytesPerActivate::1024-1151 279 48.52% 100.00%
-system.mem_ctrl.bytesPerActivate::total 575
-system.mem_ctrl.rdPerTurnAround::samples 6
-system.mem_ctrl.rdPerTurnAround::mean 772.166667
-system.mem_ctrl.rdPerTurnAround::gmean 643.154197
-system.mem_ctrl.rdPerTurnAround::stdev 524.176084
-system.mem_ctrl.rdPerTurnAround::256-319 2 33.33% 33.33%
-system.mem_ctrl.rdPerTurnAround::640-703 1 16.67% 50.00%
-system.mem_ctrl.rdPerTurnAround::704-767 1 16.67% 66.67%
-system.mem_ctrl.rdPerTurnAround::896-959 1 16.67% 83.33%
-system.mem_ctrl.rdPerTurnAround::1664-1727 1 16.67% 100.00%
-system.mem_ctrl.rdPerTurnAround::total 6
-system.mem_ctrl.wrPerTurnAround::samples 6
-system.mem_ctrl.wrPerTurnAround::mean 16
-system.mem_ctrl.wrPerTurnAround::gmean 16.000000
-system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00%
-system.mem_ctrl.wrPerTurnAround::total 6
-system.mem_ctrl.totQLat 59680000
-system.mem_ctrl.totMemAccLat 176211250
-system.mem_ctrl.totBusLat 31075000
-system.mem_ctrl.avgQLat 9602.57
-system.mem_ctrl.avgBusLat 5000.00
-system.mem_ctrl.avgMemAccLat 28352.57
-system.mem_ctrl.avgRdBW 1045.80
-system.mem_ctrl.avgWrBW 16.15
-system.mem_ctrl.avgRdBWSys 71.01
-system.mem_ctrl.avgWrBWSys 13.32
-system.mem_ctrl.peakBW 12800.00
-system.mem_ctrl.busUtil 8.30
-system.mem_ctrl.busUtilRead 8.17
-system.mem_ctrl.busUtilWrite 0.13
-system.mem_ctrl.avgRdQLen 1.00
-system.mem_ctrl.avgWrQLen 23.12
-system.mem_ctrl.readRowHits 5650
-system.mem_ctrl.writeRowHits 83
-system.mem_ctrl.readRowHitRate 90.91
-system.mem_ctrl.writeRowHitRate 66.40
-system.mem_ctrl.avgGap 54455.68
-system.mem_ctrl.pageHitRate 90.43
-system.mem_ctrl_0.actEnergy 2598960
-system.mem_ctrl_0.preEnergy 1377585
-system.mem_ctrl_0.readEnergy 28124460
-system.mem_ctrl_0.writeEnergy 401940
-system.mem_ctrl_0.refreshEnergy 29502720.000000
-system.mem_ctrl_0.actBackEnergy 55884510
-system.mem_ctrl_0.preBackEnergy 903360
-system.mem_ctrl_0.actPowerDownEnergy 108619200
-system.mem_ctrl_0.prePowerDownEnergy 6618240
-system.mem_ctrl_0.selfRefreshEnergy 0
-system.mem_ctrl_0.totalEnergy 234030975
-system.mem_ctrl_0.averagePower 615.318415
-system.mem_ctrl_0.totalIdleTime 255286000
-system.mem_ctrl_0.memoryStateTime::IDLE 462000
-system.mem_ctrl_0.memoryStateTime::REF 12480000
-system.mem_ctrl_0.memoryStateTime::SREF 0
-system.mem_ctrl_0.memoryStateTime::PRE_PDN 17232500
-system.mem_ctrl_0.memoryStateTime::ACT 111848750
-system.mem_ctrl_0.memoryStateTime::ACT_PDN 238317750
-system.mem_ctrl_1.actEnergy 1527960
-system.mem_ctrl_1.preEnergy 804540
-system.mem_ctrl_1.readEnergy 16243500
-system.mem_ctrl_1.writeEnergy 99180
-system.mem_ctrl_1.refreshEnergy 28273440.000000
-system.mem_ctrl_1.actBackEnergy 35538930
-system.mem_ctrl_1.preBackEnergy 1997760
-system.mem_ctrl_1.actPowerDownEnergy 96272430
-system.mem_ctrl_1.prePowerDownEnergy 16892160
-system.mem_ctrl_1.selfRefreshEnergy 11758020
-system.mem_ctrl_1.totalEnergy 209407920
-system.mem_ctrl_1.averagePower 550.579039
-system.mem_ctrl_1.totalIdleTime 297220000
-system.mem_ctrl_1.memoryStateTime::IDLE 3473000
-system.mem_ctrl_1.memoryStateTime::REF 11978000
-system.mem_ctrl_1.memoryStateTime::SREF 42087750
-system.mem_ctrl_1.memoryStateTime::PRE_PDN 43986250
-system.mem_ctrl_1.memoryStateTime::ACT 67670000
-system.mem_ctrl_1.memoryStateTime::ACT_PDN 211146000
-system.pwrStateResidencyTicks::UNDEFINED 380341000
-system.cpu.workload.numSyscalls 11
-system.cpu.pwrStateResidencyTicks::ON 380341000
-system.cpu.numCycles 380341
-system.cpu.numWorkItemsStarted 0
-system.cpu.numWorkItemsCompleted 0
-system.cpu.committedInsts 5548
-system.cpu.committedOps 5548
-system.cpu.num_int_alu_accesses 4660
-system.cpu.num_fp_alu_accesses 0
-system.cpu.num_func_calls 146
-system.cpu.num_conditional_control_insts 835
-system.cpu.num_int_insts 4660
-system.cpu.num_fp_insts 0
-system.cpu.num_int_register_reads 10977
-system.cpu.num_int_register_writes 5062
-system.cpu.num_fp_register_reads 0
-system.cpu.num_fp_register_writes 0
-system.cpu.num_mem_refs 1404
-system.cpu.num_load_insts 726
-system.cpu.num_store_insts 678
-system.cpu.num_idle_cycles 0
-system.cpu.num_busy_cycles 380341
-system.cpu.not_idle_fraction 1
-system.cpu.idle_fraction 0
-system.cpu.Branches 1187
-system.cpu.op_class::No_OpClass 173 3.09% 3.09%
-system.cpu.op_class::IntAlu 4014 71.79% 74.89%
-system.cpu.op_class::IntMult 0 0.00% 74.89%
-system.cpu.op_class::IntDiv 0 0.00% 74.89%
-system.cpu.op_class::FloatAdd 0 0.00% 74.89%
-system.cpu.op_class::FloatCmp 0 0.00% 74.89%
-system.cpu.op_class::FloatCvt 0 0.00% 74.89%
-system.cpu.op_class::FloatMult 0 0.00% 74.89%
-system.cpu.op_class::FloatMultAcc 0 0.00% 74.89%
-system.cpu.op_class::FloatDiv 0 0.00% 74.89%
-system.cpu.op_class::FloatMisc 0 0.00% 74.89%
-system.cpu.op_class::FloatSqrt 0 0.00% 74.89%
-system.cpu.op_class::SimdAdd 0 0.00% 74.89%
-system.cpu.op_class::SimdAddAcc 0 0.00% 74.89%
-system.cpu.op_class::SimdAlu 0 0.00% 74.89%
-system.cpu.op_class::SimdCmp 0 0.00% 74.89%
-system.cpu.op_class::SimdCvt 0 0.00% 74.89%
-system.cpu.op_class::SimdMisc 0 0.00% 74.89%
-system.cpu.op_class::SimdMult 0 0.00% 74.89%
-system.cpu.op_class::SimdMultAcc 0 0.00% 74.89%
-system.cpu.op_class::SimdShift 0 0.00% 74.89%
-system.cpu.op_class::SimdShiftAcc 0 0.00% 74.89%
-system.cpu.op_class::SimdSqrt 0 0.00% 74.89%
-system.cpu.op_class::SimdFloatAdd 0 0.00% 74.89%
-system.cpu.op_class::SimdFloatAlu 0 0.00% 74.89%
-system.cpu.op_class::SimdFloatCmp 0 0.00% 74.89%
-system.cpu.op_class::SimdFloatCvt 0 0.00% 74.89%
-system.cpu.op_class::SimdFloatDiv 0 0.00% 74.89%
-system.cpu.op_class::SimdFloatMisc 0 0.00% 74.89%
-system.cpu.op_class::SimdFloatMult 0 0.00% 74.89%
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 74.89%
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 74.89%
-system.cpu.op_class::MemRead 726 12.99% 87.87%
-system.cpu.op_class::MemWrite 678 12.13% 100.00%
-system.cpu.op_class::FloatMemRead 0 0.00% 100.00%
-system.cpu.op_class::FloatMemWrite 0 0.00% 100.00%
-system.cpu.op_class::IprAccess 0 0.00% 100.00%
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
-system.cpu.op_class::total 5591
-system.membus.snoop_filter.tot_requests 0
-system.membus.snoop_filter.hit_single_requests 0
-system.membus.snoop_filter.hit_multi_requests 0
-system.membus.snoop_filter.tot_snoops 0
-system.membus.snoop_filter.hit_single_snoops 0
-system.membus.snoop_filter.hit_multi_snoops 0
-system.membus.pwrStateResidencyTicks::UNDEFINED 380341000
-system.membus.trans_dist::ReadReq 6310
-system.membus.trans_dist::ReadResp 6309
-system.membus.trans_dist::WriteReq 673
-system.membus.trans_dist::WriteResp 673
-system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 11183
-system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 2782
-system.membus.pkt_count::total 13965
-system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 22364
-system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 9705
-system.membus.pkt_size::total 32069
-system.membus.snoops 0
-system.membus.snoopTraffic 0
-system.membus.snoop_fanout::samples 6983
-system.membus.snoop_fanout::mean 0
-system.membus.snoop_fanout::stdev 0
-system.membus.snoop_fanout::underflows 0 0.00% 0.00%
-system.membus.snoop_fanout::0 6983 100.00% 100.00%
-system.membus.snoop_fanout::1 0 0.00% 100.00%
-system.membus.snoop_fanout::overflows 0 0.00% 100.00%
-system.membus.snoop_fanout::min_value 0
-system.membus.snoop_fanout::max_value 0
-system.membus.snoop_fanout::total 6983
-system.membus.reqLayer0.occupancy 7656000
-system.membus.reqLayer0.utilization 2.0
-system.membus.respLayer0.occupancy 12691750
-system.membus.respLayer0.utilization 3.3
-system.membus.respLayer1.occupancy 2300750
-system.membus.respLayer1.utilization 0.6
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:536870911:0:0:0:0
-memories=system.mem_ctrl
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.clk_domain.voltage_domain
-
-[system.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dtb icache interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.clk_domain
-cpu_id=-1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=65536
-system=system
-tag_latency=2
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.l2bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=65536
-tag_latency=2
-
-[system.cpu.dtb]
-type=SparcTLB
-eventq_index=0
-size=64
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=16384
-system=system
-tag_latency=2
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.icache_port
-mem_side=system.l2bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=16384
-tag_latency=2
-
-[system.cpu.interrupts]
-type=SparcInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=SparcISA
-eventq_index=0
-
-[system.cpu.itb]
-type=SparcTLB
-eventq_index=0
-size=64
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=Process
-cmd=tests/test-progs/hello/bin/sparc/linux/hello
-cwd=
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=
-gid=100
-input=cin
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.l2bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.l2bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.l2bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-data_latency=20
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=262144
-system=system
-tag_latency=20
-tags=system.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.l2bus.master[0]
-mem_side=system.membus.slave[0]
-
-[system.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-data_latency=20
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-tag_latency=20
-
-[system.mem_ctrl]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:536870911:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.mem_ctrl.port
-slave=system.l2cache.mem_side system.system_port
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Entering event queue @ 0. Starting simulation...
+++ /dev/null
-Redirecting stdout to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Apr 3 2017 18:41:19
-gem5 started Apr 3 2017 18:43:32
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 66465
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level
-
-Global frequency set at 1000000000000 ticks per second
-Beginning simulation!
-Hello World!Exiting @ tick 56511000 because exiting with last active thread context
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000057
-sim_ticks 56511000
-final_tick 56511000
-sim_freq 1000000000000
-host_inst_rate 336003
-host_op_rate 335612
-host_tick_rate 3415114336
-host_mem_usage 648892
-host_seconds 0.02
-sim_insts 5548
-sim_ops 5548
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 56511000
-system.mem_ctrl.bytes_read::cpu.inst 16448
-system.mem_ctrl.bytes_read::cpu.data 8768
-system.mem_ctrl.bytes_read::total 25216
-system.mem_ctrl.bytes_inst_read::cpu.inst 16448
-system.mem_ctrl.bytes_inst_read::total 16448
-system.mem_ctrl.num_reads::cpu.inst 257
-system.mem_ctrl.num_reads::cpu.data 137
-system.mem_ctrl.num_reads::total 394
-system.mem_ctrl.bw_read::cpu.inst 291058378
-system.mem_ctrl.bw_read::cpu.data 155155633
-system.mem_ctrl.bw_read::total 446214011
-system.mem_ctrl.bw_inst_read::cpu.inst 291058378
-system.mem_ctrl.bw_inst_read::total 291058378
-system.mem_ctrl.bw_total::cpu.inst 291058378
-system.mem_ctrl.bw_total::cpu.data 155155633
-system.mem_ctrl.bw_total::total 446214011
-system.mem_ctrl.readReqs 394
-system.mem_ctrl.writeReqs 0
-system.mem_ctrl.readBursts 394
-system.mem_ctrl.writeBursts 0
-system.mem_ctrl.bytesReadDRAM 25216
-system.mem_ctrl.bytesReadWrQ 0
-system.mem_ctrl.bytesWritten 0
-system.mem_ctrl.bytesReadSys 25216
-system.mem_ctrl.bytesWrittenSys 0
-system.mem_ctrl.servicedByWrQ 0
-system.mem_ctrl.mergedWrBursts 0
-system.mem_ctrl.neitherReadNorWriteReqs 0
-system.mem_ctrl.perBankRdBursts::0 21
-system.mem_ctrl.perBankRdBursts::1 7
-system.mem_ctrl.perBankRdBursts::2 1
-system.mem_ctrl.perBankRdBursts::3 7
-system.mem_ctrl.perBankRdBursts::4 0
-system.mem_ctrl.perBankRdBursts::5 69
-system.mem_ctrl.perBankRdBursts::6 79
-system.mem_ctrl.perBankRdBursts::7 62
-system.mem_ctrl.perBankRdBursts::8 32
-system.mem_ctrl.perBankRdBursts::9 17
-system.mem_ctrl.perBankRdBursts::10 9
-system.mem_ctrl.perBankRdBursts::11 47
-system.mem_ctrl.perBankRdBursts::12 10
-system.mem_ctrl.perBankRdBursts::13 21
-system.mem_ctrl.perBankRdBursts::14 5
-system.mem_ctrl.perBankRdBursts::15 7
-system.mem_ctrl.perBankWrBursts::0 0
-system.mem_ctrl.perBankWrBursts::1 0
-system.mem_ctrl.perBankWrBursts::2 0
-system.mem_ctrl.perBankWrBursts::3 0
-system.mem_ctrl.perBankWrBursts::4 0
-system.mem_ctrl.perBankWrBursts::5 0
-system.mem_ctrl.perBankWrBursts::6 0
-system.mem_ctrl.perBankWrBursts::7 0
-system.mem_ctrl.perBankWrBursts::8 0
-system.mem_ctrl.perBankWrBursts::9 0
-system.mem_ctrl.perBankWrBursts::10 0
-system.mem_ctrl.perBankWrBursts::11 0
-system.mem_ctrl.perBankWrBursts::12 0
-system.mem_ctrl.perBankWrBursts::13 0
-system.mem_ctrl.perBankWrBursts::14 0
-system.mem_ctrl.perBankWrBursts::15 0
-system.mem_ctrl.numRdRetry 0
-system.mem_ctrl.numWrRetry 0
-system.mem_ctrl.totGap 56394000
-system.mem_ctrl.readPktSize::0 0
-system.mem_ctrl.readPktSize::1 0
-system.mem_ctrl.readPktSize::2 0
-system.mem_ctrl.readPktSize::3 0
-system.mem_ctrl.readPktSize::4 0
-system.mem_ctrl.readPktSize::5 0
-system.mem_ctrl.readPktSize::6 394
-system.mem_ctrl.writePktSize::0 0
-system.mem_ctrl.writePktSize::1 0
-system.mem_ctrl.writePktSize::2 0
-system.mem_ctrl.writePktSize::3 0
-system.mem_ctrl.writePktSize::4 0
-system.mem_ctrl.writePktSize::5 0
-system.mem_ctrl.writePktSize::6 0
-system.mem_ctrl.rdQLenPdf::0 394
-system.mem_ctrl.rdQLenPdf::1 0
-system.mem_ctrl.rdQLenPdf::2 0
-system.mem_ctrl.rdQLenPdf::3 0
-system.mem_ctrl.rdQLenPdf::4 0
-system.mem_ctrl.rdQLenPdf::5 0
-system.mem_ctrl.rdQLenPdf::6 0
-system.mem_ctrl.rdQLenPdf::7 0
-system.mem_ctrl.rdQLenPdf::8 0
-system.mem_ctrl.rdQLenPdf::9 0
-system.mem_ctrl.rdQLenPdf::10 0
-system.mem_ctrl.rdQLenPdf::11 0
-system.mem_ctrl.rdQLenPdf::12 0
-system.mem_ctrl.rdQLenPdf::13 0
-system.mem_ctrl.rdQLenPdf::14 0
-system.mem_ctrl.rdQLenPdf::15 0
-system.mem_ctrl.rdQLenPdf::16 0
-system.mem_ctrl.rdQLenPdf::17 0
-system.mem_ctrl.rdQLenPdf::18 0
-system.mem_ctrl.rdQLenPdf::19 0
-system.mem_ctrl.rdQLenPdf::20 0
-system.mem_ctrl.rdQLenPdf::21 0
-system.mem_ctrl.rdQLenPdf::22 0
-system.mem_ctrl.rdQLenPdf::23 0
-system.mem_ctrl.rdQLenPdf::24 0
-system.mem_ctrl.rdQLenPdf::25 0
-system.mem_ctrl.rdQLenPdf::26 0
-system.mem_ctrl.rdQLenPdf::27 0
-system.mem_ctrl.rdQLenPdf::28 0
-system.mem_ctrl.rdQLenPdf::29 0
-system.mem_ctrl.rdQLenPdf::30 0
-system.mem_ctrl.rdQLenPdf::31 0
-system.mem_ctrl.wrQLenPdf::0 0
-system.mem_ctrl.wrQLenPdf::1 0
-system.mem_ctrl.wrQLenPdf::2 0
-system.mem_ctrl.wrQLenPdf::3 0
-system.mem_ctrl.wrQLenPdf::4 0
-system.mem_ctrl.wrQLenPdf::5 0
-system.mem_ctrl.wrQLenPdf::6 0
-system.mem_ctrl.wrQLenPdf::7 0
-system.mem_ctrl.wrQLenPdf::8 0
-system.mem_ctrl.wrQLenPdf::9 0
-system.mem_ctrl.wrQLenPdf::10 0
-system.mem_ctrl.wrQLenPdf::11 0
-system.mem_ctrl.wrQLenPdf::12 0
-system.mem_ctrl.wrQLenPdf::13 0
-system.mem_ctrl.wrQLenPdf::14 0
-system.mem_ctrl.wrQLenPdf::15 0
-system.mem_ctrl.wrQLenPdf::16 0
-system.mem_ctrl.wrQLenPdf::17 0
-system.mem_ctrl.wrQLenPdf::18 0
-system.mem_ctrl.wrQLenPdf::19 0
-system.mem_ctrl.wrQLenPdf::20 0
-system.mem_ctrl.wrQLenPdf::21 0
-system.mem_ctrl.wrQLenPdf::22 0
-system.mem_ctrl.wrQLenPdf::23 0
-system.mem_ctrl.wrQLenPdf::24 0
-system.mem_ctrl.wrQLenPdf::25 0
-system.mem_ctrl.wrQLenPdf::26 0
-system.mem_ctrl.wrQLenPdf::27 0
-system.mem_ctrl.wrQLenPdf::28 0
-system.mem_ctrl.wrQLenPdf::29 0
-system.mem_ctrl.wrQLenPdf::30 0
-system.mem_ctrl.wrQLenPdf::31 0
-system.mem_ctrl.wrQLenPdf::32 0
-system.mem_ctrl.wrQLenPdf::33 0
-system.mem_ctrl.wrQLenPdf::34 0
-system.mem_ctrl.wrQLenPdf::35 0
-system.mem_ctrl.wrQLenPdf::36 0
-system.mem_ctrl.wrQLenPdf::37 0
-system.mem_ctrl.wrQLenPdf::38 0
-system.mem_ctrl.wrQLenPdf::39 0
-system.mem_ctrl.wrQLenPdf::40 0
-system.mem_ctrl.wrQLenPdf::41 0
-system.mem_ctrl.wrQLenPdf::42 0
-system.mem_ctrl.wrQLenPdf::43 0
-system.mem_ctrl.wrQLenPdf::44 0
-system.mem_ctrl.wrQLenPdf::45 0
-system.mem_ctrl.wrQLenPdf::46 0
-system.mem_ctrl.wrQLenPdf::47 0
-system.mem_ctrl.wrQLenPdf::48 0
-system.mem_ctrl.wrQLenPdf::49 0
-system.mem_ctrl.wrQLenPdf::50 0
-system.mem_ctrl.wrQLenPdf::51 0
-system.mem_ctrl.wrQLenPdf::52 0
-system.mem_ctrl.wrQLenPdf::53 0
-system.mem_ctrl.wrQLenPdf::54 0
-system.mem_ctrl.wrQLenPdf::55 0
-system.mem_ctrl.wrQLenPdf::56 0
-system.mem_ctrl.wrQLenPdf::57 0
-system.mem_ctrl.wrQLenPdf::58 0
-system.mem_ctrl.wrQLenPdf::59 0
-system.mem_ctrl.wrQLenPdf::60 0
-system.mem_ctrl.wrQLenPdf::61 0
-system.mem_ctrl.wrQLenPdf::62 0
-system.mem_ctrl.wrQLenPdf::63 0
-system.mem_ctrl.bytesPerActivate::samples 98
-system.mem_ctrl.bytesPerActivate::mean 248.816327
-system.mem_ctrl.bytesPerActivate::gmean 183.748429
-system.mem_ctrl.bytesPerActivate::stdev 196.431638
-system.mem_ctrl.bytesPerActivate::0-127 26 26.53% 26.53%
-system.mem_ctrl.bytesPerActivate::128-255 31 31.63% 58.16%
-system.mem_ctrl.bytesPerActivate::256-383 15 15.31% 73.47%
-system.mem_ctrl.bytesPerActivate::384-511 13 13.27% 86.73%
-system.mem_ctrl.bytesPerActivate::512-639 9 9.18% 95.92%
-system.mem_ctrl.bytesPerActivate::640-767 2 2.04% 97.96%
-system.mem_ctrl.bytesPerActivate::896-1023 1 1.02% 98.98%
-system.mem_ctrl.bytesPerActivate::1024-1151 1 1.02% 100.00%
-system.mem_ctrl.bytesPerActivate::total 98
-system.mem_ctrl.totQLat 5793000
-system.mem_ctrl.totMemAccLat 13180500
-system.mem_ctrl.totBusLat 1970000
-system.mem_ctrl.avgQLat 14703.05
-system.mem_ctrl.avgBusLat 5000.00
-system.mem_ctrl.avgMemAccLat 33453.05
-system.mem_ctrl.avgRdBW 446.21
-system.mem_ctrl.avgWrBW 0.00
-system.mem_ctrl.avgRdBWSys 446.21
-system.mem_ctrl.avgWrBWSys 0.00
-system.mem_ctrl.peakBW 12800.00
-system.mem_ctrl.busUtil 3.49
-system.mem_ctrl.busUtilRead 3.49
-system.mem_ctrl.busUtilWrite 0.00
-system.mem_ctrl.avgRdQLen 1.00
-system.mem_ctrl.avgWrQLen 0.00
-system.mem_ctrl.readRowHits 292
-system.mem_ctrl.writeRowHits 0
-system.mem_ctrl.readRowHitRate 74.11
-system.mem_ctrl.writeRowHitRate nan
-system.mem_ctrl.avgGap 143131.98
-system.mem_ctrl.pageHitRate 74.11
-system.mem_ctrl_0.actEnergy 421260
-system.mem_ctrl_0.preEnergy 216315
-system.mem_ctrl_0.readEnergy 1756440
-system.mem_ctrl_0.writeEnergy 0
-system.mem_ctrl_0.refreshEnergy 4302480.000000
-system.mem_ctrl_0.actBackEnergy 4075500
-system.mem_ctrl_0.preBackEnergy 122880
-system.mem_ctrl_0.actPowerDownEnergy 21123630
-system.mem_ctrl_0.prePowerDownEnergy 357120
-system.mem_ctrl_0.selfRefreshEnergy 0
-system.mem_ctrl_0.totalEnergy 32375625
-system.mem_ctrl_0.averagePower 572.905837
-system.mem_ctrl_0.totalIdleTime 47002000
-system.mem_ctrl_0.memoryStateTime::IDLE 71000
-system.mem_ctrl_0.memoryStateTime::REF 1820000
-system.mem_ctrl_0.memoryStateTime::SREF 0
-system.mem_ctrl_0.memoryStateTime::PRE_PDN 929250
-system.mem_ctrl_0.memoryStateTime::ACT 7357750
-system.mem_ctrl_0.memoryStateTime::ACT_PDN 46333000
-system.mem_ctrl_1.actEnergy 307020
-system.mem_ctrl_1.preEnergy 155595
-system.mem_ctrl_1.readEnergy 1056720
-system.mem_ctrl_1.writeEnergy 0
-system.mem_ctrl_1.refreshEnergy 4302480.000000
-system.mem_ctrl_1.actBackEnergy 2785590
-system.mem_ctrl_1.preBackEnergy 293760
-system.mem_ctrl_1.actPowerDownEnergy 20523420
-system.mem_ctrl_1.prePowerDownEnergy 1777920
-system.mem_ctrl_1.selfRefreshEnergy 0
-system.mem_ctrl_1.totalEnergy 31202505
-system.mem_ctrl_1.averagePower 552.146785
-system.mem_ctrl_1.totalIdleTime 49582750
-system.mem_ctrl_1.memoryStateTime::IDLE 557000
-system.mem_ctrl_1.memoryStateTime::REF 1820000
-system.mem_ctrl_1.memoryStateTime::SREF 0
-system.mem_ctrl_1.memoryStateTime::PRE_PDN 4629500
-system.mem_ctrl_1.memoryStateTime::ACT 4495750
-system.mem_ctrl_1.memoryStateTime::ACT_PDN 45008750
-system.pwrStateResidencyTicks::UNDEFINED 56511000
-system.cpu.workload.numSyscalls 11
-system.cpu.pwrStateResidencyTicks::ON 56511000
-system.cpu.numCycles 56511
-system.cpu.numWorkItemsStarted 0
-system.cpu.numWorkItemsCompleted 0
-system.cpu.committedInsts 5548
-system.cpu.committedOps 5548
-system.cpu.num_int_alu_accesses 4660
-system.cpu.num_fp_alu_accesses 0
-system.cpu.num_func_calls 146
-system.cpu.num_conditional_control_insts 835
-system.cpu.num_int_insts 4660
-system.cpu.num_fp_insts 0
-system.cpu.num_int_register_reads 10977
-system.cpu.num_int_register_writes 5062
-system.cpu.num_fp_register_reads 0
-system.cpu.num_fp_register_writes 0
-system.cpu.num_mem_refs 1404
-system.cpu.num_load_insts 726
-system.cpu.num_store_insts 678
-system.cpu.num_idle_cycles 0
-system.cpu.num_busy_cycles 56511
-system.cpu.not_idle_fraction 1
-system.cpu.idle_fraction 0
-system.cpu.Branches 1187
-system.cpu.op_class::No_OpClass 173 3.09% 3.09%
-system.cpu.op_class::IntAlu 4014 71.79% 74.89%
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-system.l2cache.demand_mshr_miss_latency::total 33407000
-system.l2cache.overall_mshr_miss_latency::cpu.inst 21347000
-system.l2cache.overall_mshr_miss_latency::cpu.data 12060000
-system.l2cache.overall_mshr_miss_latency::total 33407000
-system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1
-system.l2cache.ReadExReq_mshr_miss_rate::total 1
-system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.992278
-system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.982143
-system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.990476
-system.l2cache.demand_mshr_miss_rate::cpu.inst 0.992278
-system.l2cache.demand_mshr_miss_rate::cpu.data 0.992754
-system.l2cache.demand_mshr_miss_rate::total 0.992443
-system.l2cache.overall_mshr_miss_rate::cpu.inst 0.992278
-system.l2cache.overall_mshr_miss_rate::cpu.data 0.992754
-system.l2cache.overall_mshr_miss_rate::total 0.992443
-system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83987.804878
-system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83987.804878
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 83062.256809
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 94054.545455
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 85000
-system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83062.256809
-system.l2cache.demand_avg_mshr_miss_latency::cpu.data 88029.197080
-system.l2cache.demand_avg_mshr_miss_latency::total 84789.340102
-system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83062.256809
-system.l2cache.overall_avg_mshr_miss_latency::cpu.data 88029.197080
-system.l2cache.overall_avg_mshr_miss_latency::total 84789.340102
-system.membus.snoop_filter.tot_requests 394
-system.membus.snoop_filter.hit_single_requests 0
-system.membus.snoop_filter.hit_multi_requests 0
-system.membus.snoop_filter.tot_snoops 0
-system.membus.snoop_filter.hit_single_snoops 0
-system.membus.snoop_filter.hit_multi_snoops 0
-system.membus.pwrStateResidencyTicks::UNDEFINED 56511000
-system.membus.trans_dist::ReadResp 312
-system.membus.trans_dist::ReadExReq 82
-system.membus.trans_dist::ReadExResp 82
-system.membus.trans_dist::ReadSharedReq 312
-system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 788
-system.membus.pkt_count::total 788
-system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 25216
-system.membus.pkt_size::total 25216
-system.membus.snoops 0
-system.membus.snoopTraffic 0
-system.membus.snoop_fanout::samples 394
-system.membus.snoop_fanout::mean 0
-system.membus.snoop_fanout::stdev 0
-system.membus.snoop_fanout::underflows 0 0.00% 0.00%
-system.membus.snoop_fanout::0 394 100.00% 100.00%
-system.membus.snoop_fanout::1 0 0.00% 100.00%
-system.membus.snoop_fanout::overflows 0 0.00% 100.00%
-system.membus.snoop_fanout::min_value 0
-system.membus.snoop_fanout::max_value 0
-system.membus.snoop_fanout::total 394
-system.membus.reqLayer0.occupancy 394000
-system.membus.reqLayer0.utilization 0.7
-system.membus.respLayer0.occupancy 2102500
-system.membus.respLayer0.utilization 3.7
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu dvfs_handler mem_ctrl membus
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-kvm_vm=Null
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:536870911:0:0:0:0
-memories=system.mem_ctrl
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[3]
-
-[system.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.clk_domain.voltage_domain
-
-[system.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.cpu]
-type=TimingSimpleCPU
-children=apic_clk_domain dtb interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.clk_domain
-cpu_id=-1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.membus.slave[1]
-icache_port=system.membus.slave[0]
-
-[system.cpu.apic_clk_domain]
-type=DerivedClockDomain
-clk_divider=16
-clk_domain=system.clk_domain
-eventq_index=0
-
-[system.cpu.dtb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-num_squash_per_cycle=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-system=system
-
-[system.cpu.interrupts]
-type=X86LocalApic
-clk_domain=system.cpu.apic_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-int_latency=1000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=2305843009213693952
-pio_latency=100000
-power_model=Null
-system=system
-int_master=system.membus.slave[2]
-int_slave=system.membus.master[1]
-pio=system.membus.master[0]
-
-[system.cpu.isa]
-type=X86ISA
-eventq_index=0
-
-[system.cpu.itb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-num_squash_per_cycle=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=Process
-cmd=tests/test-progs/hello/bin/x86/linux/hello
-cwd=
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=
-gid=100
-input=cin
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.mem_ctrl]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:536870911:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[2]
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.mem_ctrl.port
-slave=system.cpu.icache_port system.cpu.dcache_port system.cpu.interrupts.int_master system.system_port
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Entering event queue @ 0. Starting simulation...
+++ /dev/null
-Redirecting stdout to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple/simout
-Redirecting stderr to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Apr 3 2017 19:05:53
-gem5 started Apr 3 2017 19:06:23
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87205
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple
-
-Global frequency set at 1000000000000 ticks per second
-Beginning simulation!
-Hello world!
-Exiting @ tick 507841000 because exiting with last active thread context
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000508
-sim_ticks 507841000
-final_tick 507841000
-sim_freq 1000000000000
-host_inst_rate 110016
-host_op_rate 198569
-host_tick_rate 9773316243
-host_mem_usage 663056
-host_seconds 0.05
-sim_insts 5712
-sim_ops 10314
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 507841000
-system.mem_ctrl.bytes_read::cpu.inst 58264
-system.mem_ctrl.bytes_read::cpu.data 7167
-system.mem_ctrl.bytes_read::total 65431
-system.mem_ctrl.bytes_inst_read::cpu.inst 58264
-system.mem_ctrl.bytes_inst_read::total 58264
-system.mem_ctrl.bytes_written::cpu.data 7160
-system.mem_ctrl.bytes_written::total 7160
-system.mem_ctrl.num_reads::cpu.inst 7283
-system.mem_ctrl.num_reads::cpu.data 1084
-system.mem_ctrl.num_reads::total 8367
-system.mem_ctrl.num_writes::cpu.data 941
-system.mem_ctrl.num_writes::total 941
-system.mem_ctrl.bw_read::cpu.inst 114728823
-system.mem_ctrl.bw_read::cpu.data 14112685
-system.mem_ctrl.bw_read::total 128841507
-system.mem_ctrl.bw_inst_read::cpu.inst 114728823
-system.mem_ctrl.bw_inst_read::total 114728823
-system.mem_ctrl.bw_write::cpu.data 14098901
-system.mem_ctrl.bw_write::total 14098901
-system.mem_ctrl.bw_total::cpu.inst 114728823
-system.mem_ctrl.bw_total::cpu.data 28211586
-system.mem_ctrl.bw_total::total 142940409
-system.mem_ctrl.readReqs 8368
-system.mem_ctrl.writeReqs 941
-system.mem_ctrl.readBursts 8368
-system.mem_ctrl.writeBursts 941
-system.mem_ctrl.bytesReadDRAM 525248
-system.mem_ctrl.bytesReadWrQ 10304
-system.mem_ctrl.bytesWritten 7168
-system.mem_ctrl.bytesReadSys 65439
-system.mem_ctrl.bytesWrittenSys 7160
-system.mem_ctrl.servicedByWrQ 161
-system.mem_ctrl.mergedWrBursts 810
-system.mem_ctrl.neitherReadNorWriteReqs 0
-system.mem_ctrl.perBankRdBursts::0 277
-system.mem_ctrl.perBankRdBursts::1 4
-system.mem_ctrl.perBankRdBursts::2 227
-system.mem_ctrl.perBankRdBursts::3 102
-system.mem_ctrl.perBankRdBursts::4 1619
-system.mem_ctrl.perBankRdBursts::5 965
-system.mem_ctrl.perBankRdBursts::6 1103
-system.mem_ctrl.perBankRdBursts::7 906
-system.mem_ctrl.perBankRdBursts::8 703
-system.mem_ctrl.perBankRdBursts::9 491
-system.mem_ctrl.perBankRdBursts::10 1059
-system.mem_ctrl.perBankRdBursts::11 59
-system.mem_ctrl.perBankRdBursts::12 11
-system.mem_ctrl.perBankRdBursts::13 489
-system.mem_ctrl.perBankRdBursts::14 78
-system.mem_ctrl.perBankRdBursts::15 114
-system.mem_ctrl.perBankWrBursts::0 10
-system.mem_ctrl.perBankWrBursts::1 0
-system.mem_ctrl.perBankWrBursts::2 0
-system.mem_ctrl.perBankWrBursts::3 0
-system.mem_ctrl.perBankWrBursts::4 0
-system.mem_ctrl.perBankWrBursts::5 0
-system.mem_ctrl.perBankWrBursts::6 0
-system.mem_ctrl.perBankWrBursts::7 0
-system.mem_ctrl.perBankWrBursts::8 3
-system.mem_ctrl.perBankWrBursts::9 54
-system.mem_ctrl.perBankWrBursts::10 34
-system.mem_ctrl.perBankWrBursts::11 7
-system.mem_ctrl.perBankWrBursts::12 0
-system.mem_ctrl.perBankWrBursts::13 0
-system.mem_ctrl.perBankWrBursts::14 0
-system.mem_ctrl.perBankWrBursts::15 4
-system.mem_ctrl.numRdRetry 0
-system.mem_ctrl.numWrRetry 0
-system.mem_ctrl.totGap 507764000
-system.mem_ctrl.readPktSize::0 135
-system.mem_ctrl.readPktSize::1 14
-system.mem_ctrl.readPktSize::2 119
-system.mem_ctrl.readPktSize::3 8100
-system.mem_ctrl.readPktSize::4 0
-system.mem_ctrl.readPktSize::5 0
-system.mem_ctrl.readPktSize::6 0
-system.mem_ctrl.writePktSize::0 14
-system.mem_ctrl.writePktSize::1 3
-system.mem_ctrl.writePktSize::2 63
-system.mem_ctrl.writePktSize::3 861
-system.mem_ctrl.writePktSize::4 0
-system.mem_ctrl.writePktSize::5 0
-system.mem_ctrl.writePktSize::6 0
-system.mem_ctrl.rdQLenPdf::0 8207
-system.mem_ctrl.rdQLenPdf::1 0
-system.mem_ctrl.rdQLenPdf::2 0
-system.mem_ctrl.rdQLenPdf::3 0
-system.mem_ctrl.rdQLenPdf::4 0
-system.mem_ctrl.rdQLenPdf::5 0
-system.mem_ctrl.rdQLenPdf::6 0
-system.mem_ctrl.rdQLenPdf::7 0
-system.mem_ctrl.rdQLenPdf::8 0
-system.mem_ctrl.rdQLenPdf::9 0
-system.mem_ctrl.rdQLenPdf::10 0
-system.mem_ctrl.rdQLenPdf::11 0
-system.mem_ctrl.rdQLenPdf::12 0
-system.mem_ctrl.rdQLenPdf::13 0
-system.mem_ctrl.rdQLenPdf::14 0
-system.mem_ctrl.rdQLenPdf::15 0
-system.mem_ctrl.rdQLenPdf::16 0
-system.mem_ctrl.rdQLenPdf::17 0
-system.mem_ctrl.rdQLenPdf::18 0
-system.mem_ctrl.rdQLenPdf::19 0
-system.mem_ctrl.rdQLenPdf::20 0
-system.mem_ctrl.rdQLenPdf::21 0
-system.mem_ctrl.rdQLenPdf::22 0
-system.mem_ctrl.rdQLenPdf::23 0
-system.mem_ctrl.rdQLenPdf::24 0
-system.mem_ctrl.rdQLenPdf::25 0
-system.mem_ctrl.rdQLenPdf::26 0
-system.mem_ctrl.rdQLenPdf::27 0
-system.mem_ctrl.rdQLenPdf::28 0
-system.mem_ctrl.rdQLenPdf::29 0
-system.mem_ctrl.rdQLenPdf::30 0
-system.mem_ctrl.rdQLenPdf::31 0
-system.mem_ctrl.wrQLenPdf::0 1
-system.mem_ctrl.wrQLenPdf::1 1
-system.mem_ctrl.wrQLenPdf::2 1
-system.mem_ctrl.wrQLenPdf::3 1
-system.mem_ctrl.wrQLenPdf::4 1
-system.mem_ctrl.wrQLenPdf::5 1
-system.mem_ctrl.wrQLenPdf::6 1
-system.mem_ctrl.wrQLenPdf::7 1
-system.mem_ctrl.wrQLenPdf::8 1
-system.mem_ctrl.wrQLenPdf::9 1
-system.mem_ctrl.wrQLenPdf::10 1
-system.mem_ctrl.wrQLenPdf::11 1
-system.mem_ctrl.wrQLenPdf::12 1
-system.mem_ctrl.wrQLenPdf::13 1
-system.mem_ctrl.wrQLenPdf::14 1
-system.mem_ctrl.wrQLenPdf::15 1
-system.mem_ctrl.wrQLenPdf::16 1
-system.mem_ctrl.wrQLenPdf::17 8
-system.mem_ctrl.wrQLenPdf::18 8
-system.mem_ctrl.wrQLenPdf::19 7
-system.mem_ctrl.wrQLenPdf::20 7
-system.mem_ctrl.wrQLenPdf::21 7
-system.mem_ctrl.wrQLenPdf::22 7
-system.mem_ctrl.wrQLenPdf::23 7
-system.mem_ctrl.wrQLenPdf::24 7
-system.mem_ctrl.wrQLenPdf::25 7
-system.mem_ctrl.wrQLenPdf::26 7
-system.mem_ctrl.wrQLenPdf::27 7
-system.mem_ctrl.wrQLenPdf::28 7
-system.mem_ctrl.wrQLenPdf::29 7
-system.mem_ctrl.wrQLenPdf::30 7
-system.mem_ctrl.wrQLenPdf::31 7
-system.mem_ctrl.wrQLenPdf::32 7
-system.mem_ctrl.wrQLenPdf::33 0
-system.mem_ctrl.wrQLenPdf::34 0
-system.mem_ctrl.wrQLenPdf::35 0
-system.mem_ctrl.wrQLenPdf::36 0
-system.mem_ctrl.wrQLenPdf::37 0
-system.mem_ctrl.wrQLenPdf::38 0
-system.mem_ctrl.wrQLenPdf::39 0
-system.mem_ctrl.wrQLenPdf::40 0
-system.mem_ctrl.wrQLenPdf::41 0
-system.mem_ctrl.wrQLenPdf::42 0
-system.mem_ctrl.wrQLenPdf::43 0
-system.mem_ctrl.wrQLenPdf::44 0
-system.mem_ctrl.wrQLenPdf::45 0
-system.mem_ctrl.wrQLenPdf::46 0
-system.mem_ctrl.wrQLenPdf::47 0
-system.mem_ctrl.wrQLenPdf::48 0
-system.mem_ctrl.wrQLenPdf::49 0
-system.mem_ctrl.wrQLenPdf::50 0
-system.mem_ctrl.wrQLenPdf::51 0
-system.mem_ctrl.wrQLenPdf::52 0
-system.mem_ctrl.wrQLenPdf::53 0
-system.mem_ctrl.wrQLenPdf::54 0
-system.mem_ctrl.wrQLenPdf::55 0
-system.mem_ctrl.wrQLenPdf::56 0
-system.mem_ctrl.wrQLenPdf::57 0
-system.mem_ctrl.wrQLenPdf::58 0
-system.mem_ctrl.wrQLenPdf::59 0
-system.mem_ctrl.wrQLenPdf::60 0
-system.mem_ctrl.wrQLenPdf::61 0
-system.mem_ctrl.wrQLenPdf::62 0
-system.mem_ctrl.wrQLenPdf::63 0
-system.mem_ctrl.bytesPerActivate::samples 856
-system.mem_ctrl.bytesPerActivate::mean 618.018692
-system.mem_ctrl.bytesPerActivate::gmean 421.107711
-system.mem_ctrl.bytesPerActivate::stdev 393.969749
-system.mem_ctrl.bytesPerActivate::0-127 148 17.29% 17.29%
-system.mem_ctrl.bytesPerActivate::128-255 75 8.76% 26.05%
-system.mem_ctrl.bytesPerActivate::256-383 73 8.53% 34.58%
-system.mem_ctrl.bytesPerActivate::384-511 52 6.07% 40.65%
-system.mem_ctrl.bytesPerActivate::512-639 57 6.66% 47.31%
-system.mem_ctrl.bytesPerActivate::640-767 49 5.72% 53.04%
-system.mem_ctrl.bytesPerActivate::768-895 36 4.21% 57.24%
-system.mem_ctrl.bytesPerActivate::896-1023 15 1.75% 59.00%
-system.mem_ctrl.bytesPerActivate::1024-1151 351 41.00% 100.00%
-system.mem_ctrl.bytesPerActivate::total 856
-system.mem_ctrl.rdPerTurnAround::samples 7
-system.mem_ctrl.rdPerTurnAround::mean 1165.285714
-system.mem_ctrl.rdPerTurnAround::gmean 941.793638
-system.mem_ctrl.rdPerTurnAround::stdev 714.559471
-system.mem_ctrl.rdPerTurnAround::256-383 1 14.29% 14.29%
-system.mem_ctrl.rdPerTurnAround::384-511 1 14.29% 28.57%
-system.mem_ctrl.rdPerTurnAround::640-767 1 14.29% 42.86%
-system.mem_ctrl.rdPerTurnAround::1280-1407 1 14.29% 57.14%
-system.mem_ctrl.rdPerTurnAround::1408-1535 1 14.29% 71.43%
-system.mem_ctrl.rdPerTurnAround::1920-2047 1 14.29% 85.71%
-system.mem_ctrl.rdPerTurnAround::2048-2175 1 14.29% 100.00%
-system.mem_ctrl.rdPerTurnAround::total 7
-system.mem_ctrl.wrPerTurnAround::samples 7
-system.mem_ctrl.wrPerTurnAround::mean 16
-system.mem_ctrl.wrPerTurnAround::gmean 16.000000
-system.mem_ctrl.wrPerTurnAround::16 7 100.00% 100.00%
-system.mem_ctrl.wrPerTurnAround::total 7
-system.mem_ctrl.totQLat 82521500
-system.mem_ctrl.totMemAccLat 236402750
-system.mem_ctrl.totBusLat 41035000
-system.mem_ctrl.avgQLat 10055.01
-system.mem_ctrl.avgBusLat 5000.00
-system.mem_ctrl.avgMemAccLat 28805.01
-system.mem_ctrl.avgRdBW 1034.28
-system.mem_ctrl.avgWrBW 14.11
-system.mem_ctrl.avgRdBWSys 128.86
-system.mem_ctrl.avgWrBWSys 14.10
-system.mem_ctrl.peakBW 12800.00
-system.mem_ctrl.busUtil 8.19
-system.mem_ctrl.busUtilRead 8.08
-system.mem_ctrl.busUtilWrite 0.11
-system.mem_ctrl.avgRdQLen 1.00
-system.mem_ctrl.avgWrQLen 23.79
-system.mem_ctrl.readRowHits 7358
-system.mem_ctrl.writeRowHits 98
-system.mem_ctrl.readRowHitRate 89.66
-system.mem_ctrl.writeRowHitRate 74.81
-system.mem_ctrl.avgGap 54545.49
-system.mem_ctrl.pageHitRate 89.42
-system.mem_ctrl_0.actEnergy 3127320
-system.mem_ctrl_0.preEnergy 1647030
-system.mem_ctrl_0.readEnergy 37149420
-system.mem_ctrl_0.writeEnergy 52200
-system.mem_ctrl_0.refreshEnergy 36263760.000000
-system.mem_ctrl_0.actBackEnergy 70559160
-system.mem_ctrl_0.preBackEnergy 1716480
-system.mem_ctrl_0.actPowerDownEnergy 113314290
-system.mem_ctrl_0.prePowerDownEnergy 13222080
-system.mem_ctrl_0.selfRefreshEnergy 17426520
-system.mem_ctrl_0.totalEnergy 294478260
-system.mem_ctrl_0.averagePower 579.862821
-system.mem_ctrl_0.totalIdleTime 347720500
-system.mem_ctrl_0.memoryStateTime::IDLE 1584000
-system.mem_ctrl_0.memoryStateTime::REF 15358000
-system.mem_ctrl_0.memoryStateTime::SREF 65707000
-system.mem_ctrl_0.memoryStateTime::PRE_PDN 34427500
-system.mem_ctrl_0.memoryStateTime::ACT 142245250
-system.mem_ctrl_0.memoryStateTime::ACT_PDN 248519250
-system.mem_ctrl_1.actEnergy 3034500
-system.mem_ctrl_1.preEnergy 1601490
-system.mem_ctrl_1.readEnergy 21441420
-system.mem_ctrl_1.writeEnergy 532440
-system.mem_ctrl_1.refreshEnergy 39336960.000000
-system.mem_ctrl_1.actBackEnergy 51598110
-system.mem_ctrl_1.preBackEnergy 1155360
-system.mem_ctrl_1.actPowerDownEnergy 151289970
-system.mem_ctrl_1.prePowerDownEnergy 18740160
-system.mem_ctrl_1.selfRefreshEnergy 3216240
-system.mem_ctrl_1.totalEnergy 291946650
-system.mem_ctrl_1.averagePower 574.877779
-system.mem_ctrl_1.totalIdleTime 391725750
-system.mem_ctrl_1.memoryStateTime::IDLE 757000
-system.mem_ctrl_1.memoryStateTime::REF 16646000
-system.mem_ctrl_1.memoryStateTime::SREF 11100000
-system.mem_ctrl_1.memoryStateTime::PRE_PDN 48800500
-system.mem_ctrl_1.memoryStateTime::ACT 98712250
-system.mem_ctrl_1.memoryStateTime::ACT_PDN 331825250
-system.pwrStateResidencyTicks::UNDEFINED 507841000
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 507841000
-system.cpu.apic_clk_domain.clock 16000
-system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 507841000
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 507841000
-system.cpu.workload.numSyscalls 11
-system.cpu.pwrStateResidencyTicks::ON 507841000
-system.cpu.numCycles 507841
-system.cpu.numWorkItemsStarted 0
-system.cpu.numWorkItemsCompleted 0
-system.cpu.committedInsts 5712
-system.cpu.committedOps 10314
-system.cpu.num_int_alu_accesses 10205
-system.cpu.num_fp_alu_accesses 0
-system.cpu.num_func_calls 221
-system.cpu.num_conditional_control_insts 986
-system.cpu.num_int_insts 10205
-system.cpu.num_fp_insts 0
-system.cpu.num_int_register_reads 19296
-system.cpu.num_int_register_writes 7977
-system.cpu.num_fp_register_reads 0
-system.cpu.num_fp_register_writes 0
-system.cpu.num_cc_register_reads 7020
-system.cpu.num_cc_register_writes 3825
-system.cpu.num_mem_refs 2025
-system.cpu.num_load_insts 1084
-system.cpu.num_store_insts 941
-system.cpu.num_idle_cycles 0
-system.cpu.num_busy_cycles 507841
-system.cpu.not_idle_fraction 1
-system.cpu.idle_fraction 0
-system.cpu.Branches 1306
-system.cpu.op_class::No_OpClass 1 0.01% 0.01%
-system.cpu.op_class::IntAlu 8275 80.23% 80.24%
-system.cpu.op_class::IntMult 6 0.06% 80.30%
-system.cpu.op_class::IntDiv 7 0.07% 80.37%
-system.cpu.op_class::FloatAdd 0 0.00% 80.37%
-system.cpu.op_class::FloatCmp 0 0.00% 80.37%
-system.cpu.op_class::FloatCvt 0 0.00% 80.37%
-system.cpu.op_class::FloatMult 0 0.00% 80.37%
-system.cpu.op_class::FloatMultAcc 0 0.00% 80.37%
-system.cpu.op_class::FloatDiv 0 0.00% 80.37%
-system.cpu.op_class::FloatMisc 0 0.00% 80.37%
-system.cpu.op_class::FloatSqrt 0 0.00% 80.37%
-system.cpu.op_class::SimdAdd 0 0.00% 80.37%
-system.cpu.op_class::SimdAddAcc 0 0.00% 80.37%
-system.cpu.op_class::SimdAlu 0 0.00% 80.37%
-system.cpu.op_class::SimdCmp 0 0.00% 80.37%
-system.cpu.op_class::SimdCvt 0 0.00% 80.37%
-system.cpu.op_class::SimdMisc 0 0.00% 80.37%
-system.cpu.op_class::SimdMult 0 0.00% 80.37%
-system.cpu.op_class::SimdMultAcc 0 0.00% 80.37%
-system.cpu.op_class::SimdShift 0 0.00% 80.37%
-system.cpu.op_class::SimdShiftAcc 0 0.00% 80.37%
-system.cpu.op_class::SimdSqrt 0 0.00% 80.37%
-system.cpu.op_class::SimdFloatAdd 0 0.00% 80.37%
-system.cpu.op_class::SimdFloatAlu 0 0.00% 80.37%
-system.cpu.op_class::SimdFloatCmp 0 0.00% 80.37%
-system.cpu.op_class::SimdFloatCvt 0 0.00% 80.37%
-system.cpu.op_class::SimdFloatDiv 0 0.00% 80.37%
-system.cpu.op_class::SimdFloatMisc 0 0.00% 80.37%
-system.cpu.op_class::SimdFloatMult 0 0.00% 80.37%
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37%
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37%
-system.cpu.op_class::MemRead 1084 10.51% 90.88%
-system.cpu.op_class::MemWrite 941 9.12% 100.00%
-system.cpu.op_class::FloatMemRead 0 0.00% 100.00%
-system.cpu.op_class::FloatMemWrite 0 0.00% 100.00%
-system.cpu.op_class::IprAccess 0 0.00% 100.00%
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
-system.cpu.op_class::total 10314
-system.membus.snoop_filter.tot_requests 0
-system.membus.snoop_filter.hit_single_requests 0
-system.membus.snoop_filter.hit_multi_requests 0
-system.membus.snoop_filter.tot_snoops 0
-system.membus.snoop_filter.hit_single_snoops 0
-system.membus.snoop_filter.hit_multi_snoops 0
-system.membus.pwrStateResidencyTicks::UNDEFINED 507841000
-system.membus.trans_dist::ReadReq 8368
-system.membus.trans_dist::ReadResp 8367
-system.membus.trans_dist::WriteReq 941
-system.membus.trans_dist::WriteResp 941
-system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 14567
-system.membus.pkt_count_system.cpu.icache_port::total 14567
-system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4050
-system.membus.pkt_count_system.cpu.dcache_port::total 4050
-system.membus.pkt_count::total 18617
-system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 58264
-system.membus.pkt_size_system.cpu.icache_port::total 58264
-system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 14327
-system.membus.pkt_size_system.cpu.dcache_port::total 14327
-system.membus.pkt_size::total 72591
-system.membus.snoops 0
-system.membus.snoopTraffic 0
-system.membus.snoop_fanout::samples 9309
-system.membus.snoop_fanout::mean 0
-system.membus.snoop_fanout::stdev 0
-system.membus.snoop_fanout::underflows 0 0.00% 0.00%
-system.membus.snoop_fanout::0 9309 100.00% 100.00%
-system.membus.snoop_fanout::1 0 0.00% 100.00%
-system.membus.snoop_fanout::overflows 0 0.00% 100.00%
-system.membus.snoop_fanout::min_value 0
-system.membus.snoop_fanout::max_value 0
-system.membus.snoop_fanout::total 9309
-system.membus.reqLayer2.occupancy 10250000
-system.membus.reqLayer2.utilization 2.0
-system.membus.respLayer0.occupancy 16544750
-system.membus.respLayer0.utilization 3.3
-system.membus.respLayer1.occupancy 3432250
-system.membus.respLayer1.utilization 0.7
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-kvm_vm=Null
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:536870911:0:0:0:0
-memories=system.mem_ctrl
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[2]
-
-[system.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.clk_domain.voltage_domain
-
-[system.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.cpu]
-type=TimingSimpleCPU
-children=apic_clk_domain dcache dtb icache interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.clk_domain
-cpu_id=-1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.apic_clk_domain]
-type=DerivedClockDomain
-clk_divider=16
-clk_domain=system.clk_domain
-eventq_index=0
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=65536
-system=system
-tag_latency=2
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.l2bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=65536
-tag_latency=2
-
-[system.cpu.dtb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-num_squash_per_cycle=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-system=system
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=16384
-system=system
-tag_latency=2
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.icache_port
-mem_side=system.l2bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=16384
-tag_latency=2
-
-[system.cpu.interrupts]
-type=X86LocalApic
-clk_domain=system.cpu.apic_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-int_latency=1000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=2305843009213693952
-pio_latency=100000
-power_model=Null
-system=system
-int_master=system.membus.slave[1]
-int_slave=system.membus.master[1]
-pio=system.membus.master[0]
-
-[system.cpu.isa]
-type=X86ISA
-eventq_index=0
-
-[system.cpu.itb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-num_squash_per_cycle=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=Process
-cmd=tests/test-progs/hello/bin/x86/linux/hello
-cwd=
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=
-gid=100
-input=cin
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.l2bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.l2bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.l2bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-data_latency=20
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=262144
-system=system
-tag_latency=20
-tags=system.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.l2bus.master[0]
-mem_side=system.membus.slave[0]
-
-[system.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-data_latency=20
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-tag_latency=20
-
-[system.mem_ctrl]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:536870911:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[2]
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.mem_ctrl.port
-slave=system.l2cache.mem_side system.cpu.interrupts.int_master system.system_port
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Entering event queue @ 0. Starting simulation...
+++ /dev/null
-Redirecting stdout to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level/simout
-Redirecting stderr to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Apr 3 2017 19:05:53
-gem5 started Apr 3 2017 19:06:21
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87157
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level
-
-Global frequency set at 1000000000000 ticks per second
-Beginning simulation!
-Hello world!
-Exiting @ tick 58513000 because exiting with last active thread context
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000059
-sim_ticks 58513000
-final_tick 58513000
-sim_freq 1000000000000
-host_inst_rate 157408
-host_op_rate 284057
-host_tick_rate 1610644917
-host_mem_usage 667152
-host_seconds 0.04
-sim_insts 5712
-sim_ops 10314
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 58513000
-system.mem_ctrl.bytes_read::cpu.inst 14656
-system.mem_ctrl.bytes_read::cpu.data 8640
-system.mem_ctrl.bytes_read::total 23296
-system.mem_ctrl.bytes_inst_read::cpu.inst 14656
-system.mem_ctrl.bytes_inst_read::total 14656
-system.mem_ctrl.num_reads::cpu.inst 229
-system.mem_ctrl.num_reads::cpu.data 135
-system.mem_ctrl.num_reads::total 364
-system.mem_ctrl.bw_read::cpu.inst 250474254
-system.mem_ctrl.bw_read::cpu.data 147659494
-system.mem_ctrl.bw_read::total 398133748
-system.mem_ctrl.bw_inst_read::cpu.inst 250474254
-system.mem_ctrl.bw_inst_read::total 250474254
-system.mem_ctrl.bw_total::cpu.inst 250474254
-system.mem_ctrl.bw_total::cpu.data 147659494
-system.mem_ctrl.bw_total::total 398133748
-system.mem_ctrl.readReqs 364
-system.mem_ctrl.writeReqs 0
-system.mem_ctrl.readBursts 364
-system.mem_ctrl.writeBursts 0
-system.mem_ctrl.bytesReadDRAM 23296
-system.mem_ctrl.bytesReadWrQ 0
-system.mem_ctrl.bytesWritten 0
-system.mem_ctrl.bytesReadSys 23296
-system.mem_ctrl.bytesWrittenSys 0
-system.mem_ctrl.servicedByWrQ 0
-system.mem_ctrl.mergedWrBursts 0
-system.mem_ctrl.neitherReadNorWriteReqs 0
-system.mem_ctrl.perBankRdBursts::0 30
-system.mem_ctrl.perBankRdBursts::1 1
-system.mem_ctrl.perBankRdBursts::2 5
-system.mem_ctrl.perBankRdBursts::3 8
-system.mem_ctrl.perBankRdBursts::4 43
-system.mem_ctrl.perBankRdBursts::5 40
-system.mem_ctrl.perBankRdBursts::6 13
-system.mem_ctrl.perBankRdBursts::7 24
-system.mem_ctrl.perBankRdBursts::8 17
-system.mem_ctrl.perBankRdBursts::9 71
-system.mem_ctrl.perBankRdBursts::10 62
-system.mem_ctrl.perBankRdBursts::11 14
-system.mem_ctrl.perBankRdBursts::12 2
-system.mem_ctrl.perBankRdBursts::13 14
-system.mem_ctrl.perBankRdBursts::14 4
-system.mem_ctrl.perBankRdBursts::15 16
-system.mem_ctrl.perBankWrBursts::0 0
-system.mem_ctrl.perBankWrBursts::1 0
-system.mem_ctrl.perBankWrBursts::2 0
-system.mem_ctrl.perBankWrBursts::3 0
-system.mem_ctrl.perBankWrBursts::4 0
-system.mem_ctrl.perBankWrBursts::5 0
-system.mem_ctrl.perBankWrBursts::6 0
-system.mem_ctrl.perBankWrBursts::7 0
-system.mem_ctrl.perBankWrBursts::8 0
-system.mem_ctrl.perBankWrBursts::9 0
-system.mem_ctrl.perBankWrBursts::10 0
-system.mem_ctrl.perBankWrBursts::11 0
-system.mem_ctrl.perBankWrBursts::12 0
-system.mem_ctrl.perBankWrBursts::13 0
-system.mem_ctrl.perBankWrBursts::14 0
-system.mem_ctrl.perBankWrBursts::15 0
-system.mem_ctrl.numRdRetry 0
-system.mem_ctrl.numWrRetry 0
-system.mem_ctrl.totGap 58376000
-system.mem_ctrl.readPktSize::0 0
-system.mem_ctrl.readPktSize::1 0
-system.mem_ctrl.readPktSize::2 0
-system.mem_ctrl.readPktSize::3 0
-system.mem_ctrl.readPktSize::4 0
-system.mem_ctrl.readPktSize::5 0
-system.mem_ctrl.readPktSize::6 364
-system.mem_ctrl.writePktSize::0 0
-system.mem_ctrl.writePktSize::1 0
-system.mem_ctrl.writePktSize::2 0
-system.mem_ctrl.writePktSize::3 0
-system.mem_ctrl.writePktSize::4 0
-system.mem_ctrl.writePktSize::5 0
-system.mem_ctrl.writePktSize::6 0
-system.mem_ctrl.rdQLenPdf::0 364
-system.mem_ctrl.rdQLenPdf::1 0
-system.mem_ctrl.rdQLenPdf::2 0
-system.mem_ctrl.rdQLenPdf::3 0
-system.mem_ctrl.rdQLenPdf::4 0
-system.mem_ctrl.rdQLenPdf::5 0
-system.mem_ctrl.rdQLenPdf::6 0
-system.mem_ctrl.rdQLenPdf::7 0
-system.mem_ctrl.rdQLenPdf::8 0
-system.mem_ctrl.rdQLenPdf::9 0
-system.mem_ctrl.rdQLenPdf::10 0
-system.mem_ctrl.rdQLenPdf::11 0
-system.mem_ctrl.rdQLenPdf::12 0
-system.mem_ctrl.rdQLenPdf::13 0
-system.mem_ctrl.rdQLenPdf::14 0
-system.mem_ctrl.rdQLenPdf::15 0
-system.mem_ctrl.rdQLenPdf::16 0
-system.mem_ctrl.rdQLenPdf::17 0
-system.mem_ctrl.rdQLenPdf::18 0
-system.mem_ctrl.rdQLenPdf::19 0
-system.mem_ctrl.rdQLenPdf::20 0
-system.mem_ctrl.rdQLenPdf::21 0
-system.mem_ctrl.rdQLenPdf::22 0
-system.mem_ctrl.rdQLenPdf::23 0
-system.mem_ctrl.rdQLenPdf::24 0
-system.mem_ctrl.rdQLenPdf::25 0
-system.mem_ctrl.rdQLenPdf::26 0
-system.mem_ctrl.rdQLenPdf::27 0
-system.mem_ctrl.rdQLenPdf::28 0
-system.mem_ctrl.rdQLenPdf::29 0
-system.mem_ctrl.rdQLenPdf::30 0
-system.mem_ctrl.rdQLenPdf::31 0
-system.mem_ctrl.wrQLenPdf::0 0
-system.mem_ctrl.wrQLenPdf::1 0
-system.mem_ctrl.wrQLenPdf::2 0
-system.mem_ctrl.wrQLenPdf::3 0
-system.mem_ctrl.wrQLenPdf::4 0
-system.mem_ctrl.wrQLenPdf::5 0
-system.mem_ctrl.wrQLenPdf::6 0
-system.mem_ctrl.wrQLenPdf::7 0
-system.mem_ctrl.wrQLenPdf::8 0
-system.mem_ctrl.wrQLenPdf::9 0
-system.mem_ctrl.wrQLenPdf::10 0
-system.mem_ctrl.wrQLenPdf::11 0
-system.mem_ctrl.wrQLenPdf::12 0
-system.mem_ctrl.wrQLenPdf::13 0
-system.mem_ctrl.wrQLenPdf::14 0
-system.mem_ctrl.wrQLenPdf::15 0
-system.mem_ctrl.wrQLenPdf::16 0
-system.mem_ctrl.wrQLenPdf::17 0
-system.mem_ctrl.wrQLenPdf::18 0
-system.mem_ctrl.wrQLenPdf::19 0
-system.mem_ctrl.wrQLenPdf::20 0
-system.mem_ctrl.wrQLenPdf::21 0
-system.mem_ctrl.wrQLenPdf::22 0
-system.mem_ctrl.wrQLenPdf::23 0
-system.mem_ctrl.wrQLenPdf::24 0
-system.mem_ctrl.wrQLenPdf::25 0
-system.mem_ctrl.wrQLenPdf::26 0
-system.mem_ctrl.wrQLenPdf::27 0
-system.mem_ctrl.wrQLenPdf::28 0
-system.mem_ctrl.wrQLenPdf::29 0
-system.mem_ctrl.wrQLenPdf::30 0
-system.mem_ctrl.wrQLenPdf::31 0
-system.mem_ctrl.wrQLenPdf::32 0
-system.mem_ctrl.wrQLenPdf::33 0
-system.mem_ctrl.wrQLenPdf::34 0
-system.mem_ctrl.wrQLenPdf::35 0
-system.mem_ctrl.wrQLenPdf::36 0
-system.mem_ctrl.wrQLenPdf::37 0
-system.mem_ctrl.wrQLenPdf::38 0
-system.mem_ctrl.wrQLenPdf::39 0
-system.mem_ctrl.wrQLenPdf::40 0
-system.mem_ctrl.wrQLenPdf::41 0
-system.mem_ctrl.wrQLenPdf::42 0
-system.mem_ctrl.wrQLenPdf::43 0
-system.mem_ctrl.wrQLenPdf::44 0
-system.mem_ctrl.wrQLenPdf::45 0
-system.mem_ctrl.wrQLenPdf::46 0
-system.mem_ctrl.wrQLenPdf::47 0
-system.mem_ctrl.wrQLenPdf::48 0
-system.mem_ctrl.wrQLenPdf::49 0
-system.mem_ctrl.wrQLenPdf::50 0
-system.mem_ctrl.wrQLenPdf::51 0
-system.mem_ctrl.wrQLenPdf::52 0
-system.mem_ctrl.wrQLenPdf::53 0
-system.mem_ctrl.wrQLenPdf::54 0
-system.mem_ctrl.wrQLenPdf::55 0
-system.mem_ctrl.wrQLenPdf::56 0
-system.mem_ctrl.wrQLenPdf::57 0
-system.mem_ctrl.wrQLenPdf::58 0
-system.mem_ctrl.wrQLenPdf::59 0
-system.mem_ctrl.wrQLenPdf::60 0
-system.mem_ctrl.wrQLenPdf::61 0
-system.mem_ctrl.wrQLenPdf::62 0
-system.mem_ctrl.wrQLenPdf::63 0
-system.mem_ctrl.bytesPerActivate::samples 108
-system.mem_ctrl.bytesPerActivate::mean 199.703704
-system.mem_ctrl.bytesPerActivate::gmean 135.091179
-system.mem_ctrl.bytesPerActivate::stdev 199.282229
-system.mem_ctrl.bytesPerActivate::0-127 52 48.15% 48.15%
-system.mem_ctrl.bytesPerActivate::128-255 21 19.44% 67.59%
-system.mem_ctrl.bytesPerActivate::256-383 15 13.89% 81.48%
-system.mem_ctrl.bytesPerActivate::384-511 8 7.41% 88.89%
-system.mem_ctrl.bytesPerActivate::512-639 7 6.48% 95.37%
-system.mem_ctrl.bytesPerActivate::640-767 2 1.85% 97.22%
-system.mem_ctrl.bytesPerActivate::768-895 1 0.93% 98.15%
-system.mem_ctrl.bytesPerActivate::896-1023 1 0.93% 99.07%
-system.mem_ctrl.bytesPerActivate::1024-1151 1 0.93% 100.00%
-system.mem_ctrl.bytesPerActivate::total 108
-system.mem_ctrl.totQLat 5858750
-system.mem_ctrl.totMemAccLat 12683750
-system.mem_ctrl.totBusLat 1820000
-system.mem_ctrl.avgQLat 16095.47
-system.mem_ctrl.avgBusLat 5000.00
-system.mem_ctrl.avgMemAccLat 34845.47
-system.mem_ctrl.avgRdBW 398.13
-system.mem_ctrl.avgWrBW 0.00
-system.mem_ctrl.avgRdBWSys 398.13
-system.mem_ctrl.avgWrBWSys 0.00
-system.mem_ctrl.peakBW 12800.00
-system.mem_ctrl.busUtil 3.11
-system.mem_ctrl.busUtilRead 3.11
-system.mem_ctrl.busUtilWrite 0.00
-system.mem_ctrl.avgRdQLen 1.00
-system.mem_ctrl.avgWrQLen 0.00
-system.mem_ctrl.readRowHits 248
-system.mem_ctrl.writeRowHits 0
-system.mem_ctrl.readRowHitRate 68.13
-system.mem_ctrl.writeRowHitRate nan
-system.mem_ctrl.avgGap 160373.63
-system.mem_ctrl.pageHitRate 68.13
-system.mem_ctrl_0.actEnergy 292740
-system.mem_ctrl_0.preEnergy 136620
-system.mem_ctrl_0.readEnergy 1170960
-system.mem_ctrl_0.writeEnergy 0
-system.mem_ctrl_0.refreshEnergy 4302480.000000
-system.mem_ctrl_0.actBackEnergy 2975970
-system.mem_ctrl_0.preBackEnergy 96960
-system.mem_ctrl_0.actPowerDownEnergy 20164320
-system.mem_ctrl_0.prePowerDownEnergy 2885760
-system.mem_ctrl_0.selfRefreshEnergy 0
-system.mem_ctrl_0.totalEnergy 32025810
-system.mem_ctrl_0.averagePower 547.321100
-system.mem_ctrl_0.totalIdleTime 51467750
-system.mem_ctrl_0.memoryStateTime::IDLE 59000
-system.mem_ctrl_0.memoryStateTime::REF 1820000
-system.mem_ctrl_0.memoryStateTime::SREF 0
-system.mem_ctrl_0.memoryStateTime::PRE_PDN 7513000
-system.mem_ctrl_0.memoryStateTime::ACT 4902000
-system.mem_ctrl_0.memoryStateTime::ACT_PDN 44219000
-system.mem_ctrl_1.actEnergy 535500
-system.mem_ctrl_1.preEnergy 273240
-system.mem_ctrl_1.readEnergy 1428000
-system.mem_ctrl_1.writeEnergy 0
-system.mem_ctrl_1.refreshEnergy 4302480.000000
-system.mem_ctrl_1.actBackEnergy 3735210
-system.mem_ctrl_1.preBackEnergy 150720
-system.mem_ctrl_1.actPowerDownEnergy 22328040
-system.mem_ctrl_1.prePowerDownEnergy 370560
-system.mem_ctrl_1.selfRefreshEnergy 0
-system.mem_ctrl_1.totalEnergy 33123750
-system.mem_ctrl_1.averagePower 566.084895
-system.mem_ctrl_1.totalIdleTime 49870500
-system.mem_ctrl_1.memoryStateTime::IDLE 184000
-system.mem_ctrl_1.memoryStateTime::REF 1820000
-system.mem_ctrl_1.memoryStateTime::SREF 0
-system.mem_ctrl_1.memoryStateTime::PRE_PDN 965000
-system.mem_ctrl_1.memoryStateTime::ACT 6563000
-system.mem_ctrl_1.memoryStateTime::ACT_PDN 48981000
-system.pwrStateResidencyTicks::UNDEFINED 58513000
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58513000
-system.cpu.apic_clk_domain.clock 16000
-system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 58513000
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58513000
-system.cpu.workload.numSyscalls 11
-system.cpu.pwrStateResidencyTicks::ON 58513000
-system.cpu.numCycles 58513
-system.cpu.numWorkItemsStarted 0
-system.cpu.numWorkItemsCompleted 0
-system.cpu.committedInsts 5712
-system.cpu.committedOps 10314
-system.cpu.num_int_alu_accesses 10205
-system.cpu.num_fp_alu_accesses 0
-system.cpu.num_func_calls 221
-system.cpu.num_conditional_control_insts 986
-system.cpu.num_int_insts 10205
-system.cpu.num_fp_insts 0
-system.cpu.num_int_register_reads 19296
-system.cpu.num_int_register_writes 7977
-system.cpu.num_fp_register_reads 0
-system.cpu.num_fp_register_writes 0
-system.cpu.num_cc_register_reads 7020
-system.cpu.num_cc_register_writes 3825
-system.cpu.num_mem_refs 2025
-system.cpu.num_load_insts 1084
-system.cpu.num_store_insts 941
-system.cpu.num_idle_cycles 0
-system.cpu.num_busy_cycles 58513
-system.cpu.not_idle_fraction 1
-system.cpu.idle_fraction 0
-system.cpu.Branches 1306
-system.cpu.op_class::No_OpClass 1 0.01% 0.01%
-system.cpu.op_class::IntAlu 8275 80.23% 80.24%
-system.cpu.op_class::IntMult 6 0.06% 80.30%
-system.cpu.op_class::IntDiv 7 0.07% 80.37%
-system.cpu.op_class::FloatAdd 0 0.00% 80.37%
-system.cpu.op_class::FloatCmp 0 0.00% 80.37%
-system.cpu.op_class::FloatCvt 0 0.00% 80.37%
-system.cpu.op_class::FloatMult 0 0.00% 80.37%
-system.cpu.op_class::FloatMultAcc 0 0.00% 80.37%
-system.cpu.op_class::FloatDiv 0 0.00% 80.37%
-system.cpu.op_class::FloatMisc 0 0.00% 80.37%
-system.cpu.op_class::FloatSqrt 0 0.00% 80.37%
-system.cpu.op_class::SimdAdd 0 0.00% 80.37%
-system.cpu.op_class::SimdAddAcc 0 0.00% 80.37%
-system.cpu.op_class::SimdAlu 0 0.00% 80.37%
-system.cpu.op_class::SimdCmp 0 0.00% 80.37%
-system.cpu.op_class::SimdCvt 0 0.00% 80.37%
-system.cpu.op_class::SimdMisc 0 0.00% 80.37%
-system.cpu.op_class::SimdMult 0 0.00% 80.37%
-system.cpu.op_class::SimdMultAcc 0 0.00% 80.37%
-system.cpu.op_class::SimdShift 0 0.00% 80.37%
-system.cpu.op_class::SimdShiftAcc 0 0.00% 80.37%
-system.cpu.op_class::SimdSqrt 0 0.00% 80.37%
-system.cpu.op_class::SimdFloatAdd 0 0.00% 80.37%
-system.cpu.op_class::SimdFloatAlu 0 0.00% 80.37%
-system.cpu.op_class::SimdFloatCmp 0 0.00% 80.37%
-system.cpu.op_class::SimdFloatCvt 0 0.00% 80.37%
-system.cpu.op_class::SimdFloatDiv 0 0.00% 80.37%
-system.cpu.op_class::SimdFloatMisc 0 0.00% 80.37%
-system.cpu.op_class::SimdFloatMult 0 0.00% 80.37%
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37%
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37%
-system.cpu.op_class::MemRead 1084 10.51% 90.88%
-system.cpu.op_class::MemWrite 941 9.12% 100.00%
-system.cpu.op_class::FloatMemRead 0 0.00% 100.00%
-system.cpu.op_class::FloatMemWrite 0 0.00% 100.00%
-system.cpu.op_class::IprAccess 0 0.00% 100.00%
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
-system.cpu.op_class::total 10314
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58513000
-system.cpu.dcache.tags.replacements 0
-system.cpu.dcache.tags.tagsinuse 81.299644
-system.cpu.dcache.tags.total_refs 1890
-system.cpu.dcache.tags.sampled_refs 135
-system.cpu.dcache.tags.avg_refs 14
-system.cpu.dcache.tags.warmup_cycle 0
-system.cpu.dcache.tags.occ_blocks::cpu.data 81.299644
-system.cpu.dcache.tags.occ_percent::cpu.data 0.079394
-system.cpu.dcache.tags.occ_percent::total 0.079394
-system.cpu.dcache.tags.occ_task_id_blocks::1024 135
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 12
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 123
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.131836
-system.cpu.dcache.tags.tag_accesses 4185
-system.cpu.dcache.tags.data_accesses 4185
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58513000
-system.cpu.dcache.ReadReq_hits::cpu.data 1028
-system.cpu.dcache.ReadReq_hits::total 1028
-system.cpu.dcache.WriteReq_hits::cpu.data 862
-system.cpu.dcache.WriteReq_hits::total 862
-system.cpu.dcache.demand_hits::cpu.data 1890
-system.cpu.dcache.demand_hits::total 1890
-system.cpu.dcache.overall_hits::cpu.data 1890
-system.cpu.dcache.overall_hits::total 1890
-system.cpu.dcache.ReadReq_misses::cpu.data 56
-system.cpu.dcache.ReadReq_misses::total 56
-system.cpu.dcache.WriteReq_misses::cpu.data 79
-system.cpu.dcache.WriteReq_misses::total 79
-system.cpu.dcache.demand_misses::cpu.data 135
-system.cpu.dcache.demand_misses::total 135
-system.cpu.dcache.overall_misses::cpu.data 135
-system.cpu.dcache.overall_misses::total 135
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 6406000
-system.cpu.dcache.ReadReq_miss_latency::total 6406000
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 8602000
-system.cpu.dcache.WriteReq_miss_latency::total 8602000
-system.cpu.dcache.demand_miss_latency::cpu.data 15008000
-system.cpu.dcache.demand_miss_latency::total 15008000
-system.cpu.dcache.overall_miss_latency::cpu.data 15008000
-system.cpu.dcache.overall_miss_latency::total 15008000
-system.cpu.dcache.ReadReq_accesses::cpu.data 1084
-system.cpu.dcache.ReadReq_accesses::total 1084
-system.cpu.dcache.WriteReq_accesses::cpu.data 941
-system.cpu.dcache.WriteReq_accesses::total 941
-system.cpu.dcache.demand_accesses::cpu.data 2025
-system.cpu.dcache.demand_accesses::total 2025
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-
----------- End Simulation Statistics ----------
+++ /dev/null
-
-# Empty to satisfy run.py
\ No newline at end of file
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
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-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cp_cntrl0 cpu0 cpu1 cpu2 dir_cntrl0 dispatcher_coalescer dispatcher_tlb dvfs_handler l1_coalescer0 l1_coalescer1 l1_tlb0 l1_tlb1 l2_coalescer l2_tlb l3_coalescer l3_tlb mem_ctrls piobus ruby sqc_cntrl0 sqc_coalescer sqc_tlb sys_port_proxy tcc_cntrl0 tccdir_cntrl0 tcp_cntrl0 tcp_cntrl1 voltage_domain
-boot_osflags=a
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-memories=system.mem_ctrls system.ruby.phys_mem
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-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.sys_port_proxy.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cp_cntrl0]
-type=CorePair_Controller
-children=L1D0cache L1D1cache L1Icache L2cache mandatoryQueue probeToCore requestFromCore responseFromCore responseToCore sequencer sequencer1 triggerQueue unblockFromCore
-L1D0cache=system.cp_cntrl0.L1D0cache
-L1D1cache=system.cp_cntrl0.L1D1cache
-L1Icache=system.cp_cntrl0.L1Icache
-L2cache=system.cp_cntrl0.L2cache
-buffer_size=0
-clk_domain=system.clk_domain
-cluster_id=0
-default_p_state=UNDEFINED
-eventq_index=0
-issue_latency=15
-l2_hit_latency=18
-mandatoryQueue=system.cp_cntrl0.mandatoryQueue
-number_of_TBEs=256
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-probeToCore=system.cp_cntrl0.probeToCore
-recycle_latency=10
-requestFromCore=system.cp_cntrl0.requestFromCore
-responseFromCore=system.cp_cntrl0.responseFromCore
-responseToCore=system.cp_cntrl0.responseToCore
-ruby_system=system.ruby
-send_evictions=true
-sequencer=system.cp_cntrl0.sequencer
-sequencer1=system.cp_cntrl0.sequencer1
-system=system
-transitions_per_cycle=32
-triggerQueue=system.cp_cntrl0.triggerQueue
-unblockFromCore=system.cp_cntrl0.unblockFromCore
-version=0
-
-[system.cp_cntrl0.L1D0cache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.cp_cntrl0.L1D0cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=65536
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.cp_cntrl0.L1D0cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=65536
-
-[system.cp_cntrl0.L1D1cache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.cp_cntrl0.L1D1cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=65536
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.cp_cntrl0.L1D1cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=65536
-
-[system.cp_cntrl0.L1Icache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.cp_cntrl0.L1Icache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=32768
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.cp_cntrl0.L1Icache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=32768
-
-[system.cp_cntrl0.L2cache]
-type=RubyCache
-children=replacement_policy
-assoc=8
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.cp_cntrl0.L2cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=2097152
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.cp_cntrl0.L2cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=8
-block_size=64
-eventq_index=0
-size=2097152
-
-[system.cp_cntrl0.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.cp_cntrl0.probeToCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[3]
-
-[system.cp_cntrl0.requestFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[2]
-
-[system.cp_cntrl0.responseFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[3]
-
-[system.cp_cntrl0.responseToCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[4]
-
-[system.cp_cntrl0.sequencer]
-type=RubySequencer
-clk_domain=system.clk_domain
-coreid=0
-dcache=system.cp_cntrl0.L1D0cache
-dcache_hit_latency=2
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.cp_cntrl0.L1Icache
-icache_hit_latency=2
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=0
-master=system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave
-mem_master_port=system.piobus.slave[0]
-slave=system.cpu0.icache_port system.cpu0.dcache_port system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.interrupts.int_master
-
-[system.cp_cntrl0.sequencer1]
-type=RubySequencer
-clk_domain=system.clk_domain
-coreid=1
-dcache=system.cp_cntrl0.L1D1cache
-dcache_hit_latency=2
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.cp_cntrl0.L1Icache
-icache_hit_latency=2
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=1
-
-[system.cp_cntrl0.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.cp_cntrl0.unblockFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[4]
-
-[system.cpu0]
-type=TimingSimpleCPU
-children=apic_clk_domain clk_domain dtb interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu0.clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu0.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu0.tracer
-workload=system.cpu0.workload
-dcache_port=system.cp_cntrl0.sequencer.slave[1]
-icache_port=system.cp_cntrl0.sequencer.slave[0]
-
-[system.cpu0.apic_clk_domain]
-type=DerivedClockDomain
-clk_divider=16
-clk_domain=system.cpu0.clk_domain
-eventq_index=0
-
-[system.cpu0.clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0.dtb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu0.dtb.walker
-
-[system.cpu0.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu0.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-num_squash_per_cycle=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-system=system
-port=system.cp_cntrl0.sequencer.slave[3]
-
-[system.cpu0.interrupts]
-type=X86LocalApic
-clk_domain=system.cpu0.apic_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-int_latency=1000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=2305843009213693952
-pio_latency=100000
-power_model=Null
-system=system
-int_master=system.cp_cntrl0.sequencer.slave[4]
-int_slave=system.cp_cntrl0.sequencer.master[1]
-pio=system.cp_cntrl0.sequencer.master[0]
-
-[system.cpu0.isa]
-type=X86ISA
-eventq_index=0
-
-[system.cpu0.itb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu0.itb.walker
-
-[system.cpu0.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu0.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-num_squash_per_cycle=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-system=system
-port=system.cp_cntrl0.sequencer.slave[2]
-
-[system.cpu0.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu0.workload]
-type=Process
-cmd=gpu-hello
-cwd=
-drivers=system.cpu2.cl_driver
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello
-gid=100
-input=cin
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu1]
-type=Shader
-children=CUs0 CUs1 clk_domain
-CUs=system.cpu1.CUs0 system.cpu1.CUs1
-clk_domain=system.cpu1.clk_domain
-cpu_pointer=system.cpu0
-default_p_state=UNDEFINED
-eventq_index=0
-globalmem=65536
-impl_kern_boundary_sync=false
-n_wf=8
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-separate_acquire_release=false
-timing=true
-translation=false
-
-[system.cpu1.CUs0]
-type=ComputeUnit
-children=ldsBus localDataStore vector_register_file0 vector_register_file1 vector_register_file2 vector_register_file3 wavefronts00 wavefronts01 wavefronts02 wavefronts03 wavefronts04 wavefronts05 wavefronts06 wavefronts07 wavefronts08 wavefronts09 wavefronts10 wavefronts11 wavefronts12 wavefronts13 wavefronts14 wavefronts15 wavefronts16 wavefronts17 wavefronts18 wavefronts19 wavefronts20 wavefronts21 wavefronts22 wavefronts23 wavefronts24 wavefronts25 wavefronts26 wavefronts27 wavefronts28 wavefronts29 wavefronts30 wavefronts31
-clk_domain=system.cpu1.clk_domain
-coalescer_to_vrf_bus_width=32
-countPages=false
-cu_id=0
-debugSegFault=false
-default_p_state=UNDEFINED
-dpbypass_pipe_length=4
-eventq_index=0
-execPolicy=OLDEST-FIRST
-functionalTLB=true
-global_mem_queue_size=256
-issue_period=4
-localDataStore=system.cpu1.CUs0.localDataStore
-localMemBarrier=false
-local_mem_queue_size=256
-mem_req_latency=9
-mem_resp_latency=9
-n_wf=8
-num_SIMDs=4
-num_global_mem_pipes=1
-num_shared_mem_pipes=1
-out_of_order_data_delivery=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-perLaneTLB=false
-power_model=Null
-prefetch_depth=0
-prefetch_prev_type=PF_PHASE
-prefetch_stride=1
-spbypass_pipe_length=4
-system=system
-vector_register_file=system.cpu1.CUs0.vector_register_file0 system.cpu1.CUs0.vector_register_file1 system.cpu1.CUs0.vector_register_file2 system.cpu1.CUs0.vector_register_file3
-vrf_to_coalescer_bus_width=32
-wavefronts=system.cpu1.CUs0.wavefronts00 system.cpu1.CUs0.wavefronts01 system.cpu1.CUs0.wavefronts02 system.cpu1.CUs0.wavefronts03 system.cpu1.CUs0.wavefronts04 system.cpu1.CUs0.wavefronts05 system.cpu1.CUs0.wavefronts06 system.cpu1.CUs0.wavefronts07 system.cpu1.CUs0.wavefronts08 system.cpu1.CUs0.wavefronts09 system.cpu1.CUs0.wavefronts10 system.cpu1.CUs0.wavefronts11 system.cpu1.CUs0.wavefronts12 system.cpu1.CUs0.wavefronts13 system.cpu1.CUs0.wavefronts14 system.cpu1.CUs0.wavefronts15 system.cpu1.CUs0.wavefronts16 system.cpu1.CUs0.wavefronts17 system.cpu1.CUs0.wavefronts18 system.cpu1.CUs0.wavefronts19 system.cpu1.CUs0.wavefronts20 system.cpu1.CUs0.wavefronts21 system.cpu1.CUs0.wavefronts22 system.cpu1.CUs0.wavefronts23 system.cpu1.CUs0.wavefronts24 system.cpu1.CUs0.wavefronts25 system.cpu1.CUs0.wavefronts26 system.cpu1.CUs0.wavefronts27 system.cpu1.CUs0.wavefronts28 system.cpu1.CUs0.wavefronts29 system.cpu1.CUs0.wavefronts30 system.cpu1.CUs0.wavefronts31
-wfSize=64
-xactCasMode=false
-ldsPort=system.cpu1.CUs0.ldsBus.slave
-memory_port=system.tcp_cntrl0.coalescer.slave[0] system.tcp_cntrl0.coalescer.slave[1] system.tcp_cntrl0.coalescer.slave[2] system.tcp_cntrl0.coalescer.slave[3] system.tcp_cntrl0.coalescer.slave[4] system.tcp_cntrl0.coalescer.slave[5] system.tcp_cntrl0.coalescer.slave[6] system.tcp_cntrl0.coalescer.slave[7] system.tcp_cntrl0.coalescer.slave[8] system.tcp_cntrl0.coalescer.slave[9] system.tcp_cntrl0.coalescer.slave[10] system.tcp_cntrl0.coalescer.slave[11] system.tcp_cntrl0.coalescer.slave[12] system.tcp_cntrl0.coalescer.slave[13] system.tcp_cntrl0.coalescer.slave[14] system.tcp_cntrl0.coalescer.slave[15] system.tcp_cntrl0.coalescer.slave[16] system.tcp_cntrl0.coalescer.slave[17] system.tcp_cntrl0.coalescer.slave[18] system.tcp_cntrl0.coalescer.slave[19] system.tcp_cntrl0.coalescer.slave[20] system.tcp_cntrl0.coalescer.slave[21] system.tcp_cntrl0.coalescer.slave[22] system.tcp_cntrl0.coalescer.slave[23] system.tcp_cntrl0.coalescer.slave[24] system.tcp_cntrl0.coalescer.slave[25] system.tcp_cntrl0.coalescer.slave[26] system.tcp_cntrl0.coalescer.slave[27] system.tcp_cntrl0.coalescer.slave[28] system.tcp_cntrl0.coalescer.slave[29] system.tcp_cntrl0.coalescer.slave[30] system.tcp_cntrl0.coalescer.slave[31] system.tcp_cntrl0.coalescer.slave[32] system.tcp_cntrl0.coalescer.slave[33] system.tcp_cntrl0.coalescer.slave[34] system.tcp_cntrl0.coalescer.slave[35] system.tcp_cntrl0.coalescer.slave[36] system.tcp_cntrl0.coalescer.slave[37] system.tcp_cntrl0.coalescer.slave[38] system.tcp_cntrl0.coalescer.slave[39] system.tcp_cntrl0.coalescer.slave[40] system.tcp_cntrl0.coalescer.slave[41] system.tcp_cntrl0.coalescer.slave[42] system.tcp_cntrl0.coalescer.slave[43] system.tcp_cntrl0.coalescer.slave[44] system.tcp_cntrl0.coalescer.slave[45] system.tcp_cntrl0.coalescer.slave[46] system.tcp_cntrl0.coalescer.slave[47] system.tcp_cntrl0.coalescer.slave[48] system.tcp_cntrl0.coalescer.slave[49] system.tcp_cntrl0.coalescer.slave[50] system.tcp_cntrl0.coalescer.slave[51] system.tcp_cntrl0.coalescer.slave[52] system.tcp_cntrl0.coalescer.slave[53] system.tcp_cntrl0.coalescer.slave[54] system.tcp_cntrl0.coalescer.slave[55] system.tcp_cntrl0.coalescer.slave[56] system.tcp_cntrl0.coalescer.slave[57] system.tcp_cntrl0.coalescer.slave[58] system.tcp_cntrl0.coalescer.slave[59] system.tcp_cntrl0.coalescer.slave[60] system.tcp_cntrl0.coalescer.slave[61] system.tcp_cntrl0.coalescer.slave[62] system.tcp_cntrl0.coalescer.slave[63]
-sqc_port=system.sqc_cntrl0.sequencer.slave[0]
-sqc_tlb_port=system.sqc_coalescer.slave[0]
-translation_port=system.l1_coalescer0.slave[0]
-
-[system.cpu1.CUs0.ldsBus]
-type=Bridge
-clk_domain=system.cpu1.clk_domain
-default_p_state=UNDEFINED
-delay=0
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=0:18446744073709551615:0:0:0:0
-req_size=16
-resp_size=16
-master=system.cpu1.CUs0.localDataStore.cuPort
-slave=system.cpu1.CUs0.ldsPort
-
-[system.cpu1.CUs0.localDataStore]
-type=LdsState
-bankConflictPenalty=1
-banks=32
-clk_domain=system.cpu1.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:65535:0:0:0:0
-size=65536
-cuPort=system.cpu1.CUs0.ldsBus.master
-
-[system.cpu1.CUs0.vector_register_file0]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=0
-wfSize=64
-
-[system.cpu1.CUs0.vector_register_file1]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=1
-wfSize=64
-
-[system.cpu1.CUs0.vector_register_file2]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=2
-wfSize=64
-
-[system.cpu1.CUs0.vector_register_file3]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=3
-wfSize=64
-
-[system.cpu1.CUs0.wavefronts00]
-type=Wavefront
-eventq_index=0
-simdId=0
-wfSize=64
-wf_slot_id=0
-
-[system.cpu1.CUs0.wavefronts01]
-type=Wavefront
-eventq_index=0
-simdId=0
-wfSize=64
-wf_slot_id=1
-
-[system.cpu1.CUs0.wavefronts02]
-type=Wavefront
-eventq_index=0
-simdId=0
-wfSize=64
-wf_slot_id=2
-
-[system.cpu1.CUs0.wavefronts03]
-type=Wavefront
-eventq_index=0
-simdId=0
-wfSize=64
-wf_slot_id=3
-
-[system.cpu1.CUs0.wavefronts04]
-type=Wavefront
-eventq_index=0
-simdId=0
-wfSize=64
-wf_slot_id=4
-
-[system.cpu1.CUs0.wavefronts05]
-type=Wavefront
-eventq_index=0
-simdId=0
-wfSize=64
-wf_slot_id=5
-
-[system.cpu1.CUs0.wavefronts06]
-type=Wavefront
-eventq_index=0
-simdId=0
-wfSize=64
-wf_slot_id=6
-
-[system.cpu1.CUs0.wavefronts07]
-type=Wavefront
-eventq_index=0
-simdId=0
-wfSize=64
-wf_slot_id=7
-
-[system.cpu1.CUs0.wavefronts08]
-type=Wavefront
-eventq_index=0
-simdId=1
-wfSize=64
-wf_slot_id=0
-
-[system.cpu1.CUs0.wavefronts09]
-type=Wavefront
-eventq_index=0
-simdId=1
-wfSize=64
-wf_slot_id=1
-
-[system.cpu1.CUs0.wavefronts10]
-type=Wavefront
-eventq_index=0
-simdId=1
-wfSize=64
-wf_slot_id=2
-
-[system.cpu1.CUs0.wavefronts11]
-type=Wavefront
-eventq_index=0
-simdId=1
-wfSize=64
-wf_slot_id=3
-
-[system.cpu1.CUs0.wavefronts12]
-type=Wavefront
-eventq_index=0
-simdId=1
-wfSize=64
-wf_slot_id=4
-
-[system.cpu1.CUs0.wavefronts13]
-type=Wavefront
-eventq_index=0
-simdId=1
-wfSize=64
-wf_slot_id=5
-
-[system.cpu1.CUs0.wavefronts14]
-type=Wavefront
-eventq_index=0
-simdId=1
-wfSize=64
-wf_slot_id=6
-
-[system.cpu1.CUs0.wavefronts15]
-type=Wavefront
-eventq_index=0
-simdId=1
-wfSize=64
-wf_slot_id=7
-
-[system.cpu1.CUs0.wavefronts16]
-type=Wavefront
-eventq_index=0
-simdId=2
-wfSize=64
-wf_slot_id=0
-
-[system.cpu1.CUs0.wavefronts17]
-type=Wavefront
-eventq_index=0
-simdId=2
-wfSize=64
-wf_slot_id=1
-
-[system.cpu1.CUs0.wavefronts18]
-type=Wavefront
-eventq_index=0
-simdId=2
-wfSize=64
-wf_slot_id=2
-
-[system.cpu1.CUs0.wavefronts19]
-type=Wavefront
-eventq_index=0
-simdId=2
-wfSize=64
-wf_slot_id=3
-
-[system.cpu1.CUs0.wavefronts20]
-type=Wavefront
-eventq_index=0
-simdId=2
-wfSize=64
-wf_slot_id=4
-
-[system.cpu1.CUs0.wavefronts21]
-type=Wavefront
-eventq_index=0
-simdId=2
-wfSize=64
-wf_slot_id=5
-
-[system.cpu1.CUs0.wavefronts22]
-type=Wavefront
-eventq_index=0
-simdId=2
-wfSize=64
-wf_slot_id=6
-
-[system.cpu1.CUs0.wavefronts23]
-type=Wavefront
-eventq_index=0
-simdId=2
-wfSize=64
-wf_slot_id=7
-
-[system.cpu1.CUs0.wavefronts24]
-type=Wavefront
-eventq_index=0
-simdId=3
-wfSize=64
-wf_slot_id=0
-
-[system.cpu1.CUs0.wavefronts25]
-type=Wavefront
-eventq_index=0
-simdId=3
-wfSize=64
-wf_slot_id=1
-
-[system.cpu1.CUs0.wavefronts26]
-type=Wavefront
-eventq_index=0
-simdId=3
-wfSize=64
-wf_slot_id=2
-
-[system.cpu1.CUs0.wavefronts27]
-type=Wavefront
-eventq_index=0
-simdId=3
-wfSize=64
-wf_slot_id=3
-
-[system.cpu1.CUs0.wavefronts28]
-type=Wavefront
-eventq_index=0
-simdId=3
-wfSize=64
-wf_slot_id=4
-
-[system.cpu1.CUs0.wavefronts29]
-type=Wavefront
-eventq_index=0
-simdId=3
-wfSize=64
-wf_slot_id=5
-
-[system.cpu1.CUs0.wavefronts30]
-type=Wavefront
-eventq_index=0
-simdId=3
-wfSize=64
-wf_slot_id=6
-
-[system.cpu1.CUs0.wavefronts31]
-type=Wavefront
-eventq_index=0
-simdId=3
-wfSize=64
-wf_slot_id=7
-
-[system.cpu1.CUs1]
-type=ComputeUnit
-children=ldsBus localDataStore vector_register_file0 vector_register_file1 vector_register_file2 vector_register_file3 wavefronts00 wavefronts01 wavefronts02 wavefronts03 wavefronts04 wavefronts05 wavefronts06 wavefronts07 wavefronts08 wavefronts09 wavefronts10 wavefronts11 wavefronts12 wavefronts13 wavefronts14 wavefronts15 wavefronts16 wavefronts17 wavefronts18 wavefronts19 wavefronts20 wavefronts21 wavefronts22 wavefronts23 wavefronts24 wavefronts25 wavefronts26 wavefronts27 wavefronts28 wavefronts29 wavefronts30 wavefronts31
-clk_domain=system.cpu1.clk_domain
-coalescer_to_vrf_bus_width=32
-countPages=false
-cu_id=1
-debugSegFault=false
-default_p_state=UNDEFINED
-dpbypass_pipe_length=4
-eventq_index=0
-execPolicy=OLDEST-FIRST
-functionalTLB=true
-global_mem_queue_size=256
-issue_period=4
-localDataStore=system.cpu1.CUs1.localDataStore
-localMemBarrier=false
-local_mem_queue_size=256
-mem_req_latency=9
-mem_resp_latency=9
-n_wf=8
-num_SIMDs=4
-num_global_mem_pipes=1
-num_shared_mem_pipes=1
-out_of_order_data_delivery=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-perLaneTLB=false
-power_model=Null
-prefetch_depth=0
-prefetch_prev_type=PF_PHASE
-prefetch_stride=1
-spbypass_pipe_length=4
-system=system
-vector_register_file=system.cpu1.CUs1.vector_register_file0 system.cpu1.CUs1.vector_register_file1 system.cpu1.CUs1.vector_register_file2 system.cpu1.CUs1.vector_register_file3
-vrf_to_coalescer_bus_width=32
-wavefronts=system.cpu1.CUs1.wavefronts00 system.cpu1.CUs1.wavefronts01 system.cpu1.CUs1.wavefronts02 system.cpu1.CUs1.wavefronts03 system.cpu1.CUs1.wavefronts04 system.cpu1.CUs1.wavefronts05 system.cpu1.CUs1.wavefronts06 system.cpu1.CUs1.wavefronts07 system.cpu1.CUs1.wavefronts08 system.cpu1.CUs1.wavefronts09 system.cpu1.CUs1.wavefronts10 system.cpu1.CUs1.wavefronts11 system.cpu1.CUs1.wavefronts12 system.cpu1.CUs1.wavefronts13 system.cpu1.CUs1.wavefronts14 system.cpu1.CUs1.wavefronts15 system.cpu1.CUs1.wavefronts16 system.cpu1.CUs1.wavefronts17 system.cpu1.CUs1.wavefronts18 system.cpu1.CUs1.wavefronts19 system.cpu1.CUs1.wavefronts20 system.cpu1.CUs1.wavefronts21 system.cpu1.CUs1.wavefronts22 system.cpu1.CUs1.wavefronts23 system.cpu1.CUs1.wavefronts24 system.cpu1.CUs1.wavefronts25 system.cpu1.CUs1.wavefronts26 system.cpu1.CUs1.wavefronts27 system.cpu1.CUs1.wavefronts28 system.cpu1.CUs1.wavefronts29 system.cpu1.CUs1.wavefronts30 system.cpu1.CUs1.wavefronts31
-wfSize=64
-xactCasMode=false
-ldsPort=system.cpu1.CUs1.ldsBus.slave
-memory_port=system.tcp_cntrl1.coalescer.slave[0] system.tcp_cntrl1.coalescer.slave[1] system.tcp_cntrl1.coalescer.slave[2] system.tcp_cntrl1.coalescer.slave[3] system.tcp_cntrl1.coalescer.slave[4] system.tcp_cntrl1.coalescer.slave[5] system.tcp_cntrl1.coalescer.slave[6] system.tcp_cntrl1.coalescer.slave[7] system.tcp_cntrl1.coalescer.slave[8] system.tcp_cntrl1.coalescer.slave[9] system.tcp_cntrl1.coalescer.slave[10] system.tcp_cntrl1.coalescer.slave[11] system.tcp_cntrl1.coalescer.slave[12] system.tcp_cntrl1.coalescer.slave[13] system.tcp_cntrl1.coalescer.slave[14] system.tcp_cntrl1.coalescer.slave[15] system.tcp_cntrl1.coalescer.slave[16] system.tcp_cntrl1.coalescer.slave[17] system.tcp_cntrl1.coalescer.slave[18] system.tcp_cntrl1.coalescer.slave[19] system.tcp_cntrl1.coalescer.slave[20] system.tcp_cntrl1.coalescer.slave[21] system.tcp_cntrl1.coalescer.slave[22] system.tcp_cntrl1.coalescer.slave[23] system.tcp_cntrl1.coalescer.slave[24] system.tcp_cntrl1.coalescer.slave[25] system.tcp_cntrl1.coalescer.slave[26] system.tcp_cntrl1.coalescer.slave[27] system.tcp_cntrl1.coalescer.slave[28] system.tcp_cntrl1.coalescer.slave[29] system.tcp_cntrl1.coalescer.slave[30] system.tcp_cntrl1.coalescer.slave[31] system.tcp_cntrl1.coalescer.slave[32] system.tcp_cntrl1.coalescer.slave[33] system.tcp_cntrl1.coalescer.slave[34] system.tcp_cntrl1.coalescer.slave[35] system.tcp_cntrl1.coalescer.slave[36] system.tcp_cntrl1.coalescer.slave[37] system.tcp_cntrl1.coalescer.slave[38] system.tcp_cntrl1.coalescer.slave[39] system.tcp_cntrl1.coalescer.slave[40] system.tcp_cntrl1.coalescer.slave[41] system.tcp_cntrl1.coalescer.slave[42] system.tcp_cntrl1.coalescer.slave[43] system.tcp_cntrl1.coalescer.slave[44] system.tcp_cntrl1.coalescer.slave[45] system.tcp_cntrl1.coalescer.slave[46] system.tcp_cntrl1.coalescer.slave[47] system.tcp_cntrl1.coalescer.slave[48] system.tcp_cntrl1.coalescer.slave[49] system.tcp_cntrl1.coalescer.slave[50] system.tcp_cntrl1.coalescer.slave[51] system.tcp_cntrl1.coalescer.slave[52] system.tcp_cntrl1.coalescer.slave[53] system.tcp_cntrl1.coalescer.slave[54] system.tcp_cntrl1.coalescer.slave[55] system.tcp_cntrl1.coalescer.slave[56] system.tcp_cntrl1.coalescer.slave[57] system.tcp_cntrl1.coalescer.slave[58] system.tcp_cntrl1.coalescer.slave[59] system.tcp_cntrl1.coalescer.slave[60] system.tcp_cntrl1.coalescer.slave[61] system.tcp_cntrl1.coalescer.slave[62] system.tcp_cntrl1.coalescer.slave[63]
-sqc_port=system.sqc_cntrl0.sequencer.slave[1]
-sqc_tlb_port=system.sqc_coalescer.slave[1]
-translation_port=system.l1_coalescer1.slave[0]
-
-[system.cpu1.CUs1.ldsBus]
-type=Bridge
-clk_domain=system.cpu1.clk_domain
-default_p_state=UNDEFINED
-delay=0
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=0:18446744073709551615:0:0:0:0
-req_size=16
-resp_size=16
-master=system.cpu1.CUs1.localDataStore.cuPort
-slave=system.cpu1.CUs1.ldsPort
-
-[system.cpu1.CUs1.localDataStore]
-type=LdsState
-bankConflictPenalty=1
-banks=32
-clk_domain=system.cpu1.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:65535:0:0:0:0
-size=65536
-cuPort=system.cpu1.CUs1.ldsBus.master
-
-[system.cpu1.CUs1.vector_register_file0]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=0
-wfSize=64
-
-[system.cpu1.CUs1.vector_register_file1]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=1
-wfSize=64
-
-[system.cpu1.CUs1.vector_register_file2]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=2
-wfSize=64
-
-[system.cpu1.CUs1.vector_register_file3]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=3
-wfSize=64
-
-[system.cpu1.CUs1.wavefronts00]
-type=Wavefront
-eventq_index=0
-simdId=0
-wfSize=64
-wf_slot_id=0
-
-[system.cpu1.CUs1.wavefronts01]
-type=Wavefront
-eventq_index=0
-simdId=0
-wfSize=64
-wf_slot_id=1
-
-[system.cpu1.CUs1.wavefronts02]
-type=Wavefront
-eventq_index=0
-simdId=0
-wfSize=64
-wf_slot_id=2
-
-[system.cpu1.CUs1.wavefronts03]
-type=Wavefront
-eventq_index=0
-simdId=0
-wfSize=64
-wf_slot_id=3
-
-[system.cpu1.CUs1.wavefronts04]
-type=Wavefront
-eventq_index=0
-simdId=0
-wfSize=64
-wf_slot_id=4
-
-[system.cpu1.CUs1.wavefronts05]
-type=Wavefront
-eventq_index=0
-simdId=0
-wfSize=64
-wf_slot_id=5
-
-[system.cpu1.CUs1.wavefronts06]
-type=Wavefront
-eventq_index=0
-simdId=0
-wfSize=64
-wf_slot_id=6
-
-[system.cpu1.CUs1.wavefronts07]
-type=Wavefront
-eventq_index=0
-simdId=0
-wfSize=64
-wf_slot_id=7
-
-[system.cpu1.CUs1.wavefronts08]
-type=Wavefront
-eventq_index=0
-simdId=1
-wfSize=64
-wf_slot_id=0
-
-[system.cpu1.CUs1.wavefronts09]
-type=Wavefront
-eventq_index=0
-simdId=1
-wfSize=64
-wf_slot_id=1
-
-[system.cpu1.CUs1.wavefronts10]
-type=Wavefront
-eventq_index=0
-simdId=1
-wfSize=64
-wf_slot_id=2
-
-[system.cpu1.CUs1.wavefronts11]
-type=Wavefront
-eventq_index=0
-simdId=1
-wfSize=64
-wf_slot_id=3
-
-[system.cpu1.CUs1.wavefronts12]
-type=Wavefront
-eventq_index=0
-simdId=1
-wfSize=64
-wf_slot_id=4
-
-[system.cpu1.CUs1.wavefronts13]
-type=Wavefront
-eventq_index=0
-simdId=1
-wfSize=64
-wf_slot_id=5
-
-[system.cpu1.CUs1.wavefronts14]
-type=Wavefront
-eventq_index=0
-simdId=1
-wfSize=64
-wf_slot_id=6
-
-[system.cpu1.CUs1.wavefronts15]
-type=Wavefront
-eventq_index=0
-simdId=1
-wfSize=64
-wf_slot_id=7
-
-[system.cpu1.CUs1.wavefronts16]
-type=Wavefront
-eventq_index=0
-simdId=2
-wfSize=64
-wf_slot_id=0
-
-[system.cpu1.CUs1.wavefronts17]
-type=Wavefront
-eventq_index=0
-simdId=2
-wfSize=64
-wf_slot_id=1
-
-[system.cpu1.CUs1.wavefronts18]
-type=Wavefront
-eventq_index=0
-simdId=2
-wfSize=64
-wf_slot_id=2
-
-[system.cpu1.CUs1.wavefronts19]
-type=Wavefront
-eventq_index=0
-simdId=2
-wfSize=64
-wf_slot_id=3
-
-[system.cpu1.CUs1.wavefronts20]
-type=Wavefront
-eventq_index=0
-simdId=2
-wfSize=64
-wf_slot_id=4
-
-[system.cpu1.CUs1.wavefronts21]
-type=Wavefront
-eventq_index=0
-simdId=2
-wfSize=64
-wf_slot_id=5
-
-[system.cpu1.CUs1.wavefronts22]
-type=Wavefront
-eventq_index=0
-simdId=2
-wfSize=64
-wf_slot_id=6
-
-[system.cpu1.CUs1.wavefronts23]
-type=Wavefront
-eventq_index=0
-simdId=2
-wfSize=64
-wf_slot_id=7
-
-[system.cpu1.CUs1.wavefronts24]
-type=Wavefront
-eventq_index=0
-simdId=3
-wfSize=64
-wf_slot_id=0
-
-[system.cpu1.CUs1.wavefronts25]
-type=Wavefront
-eventq_index=0
-simdId=3
-wfSize=64
-wf_slot_id=1
-
-[system.cpu1.CUs1.wavefronts26]
-type=Wavefront
-eventq_index=0
-simdId=3
-wfSize=64
-wf_slot_id=2
-
-[system.cpu1.CUs1.wavefronts27]
-type=Wavefront
-eventq_index=0
-simdId=3
-wfSize=64
-wf_slot_id=3
-
-[system.cpu1.CUs1.wavefronts28]
-type=Wavefront
-eventq_index=0
-simdId=3
-wfSize=64
-wf_slot_id=4
-
-[system.cpu1.CUs1.wavefronts29]
-type=Wavefront
-eventq_index=0
-simdId=3
-wfSize=64
-wf_slot_id=5
-
-[system.cpu1.CUs1.wavefronts30]
-type=Wavefront
-eventq_index=0
-simdId=3
-wfSize=64
-wf_slot_id=6
-
-[system.cpu1.CUs1.wavefronts31]
-type=Wavefront
-eventq_index=0
-simdId=3
-wfSize=64
-wf_slot_id=7
-
-[system.cpu1.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.cpu1.clk_domain.voltage_domain
-
-[system.cpu1.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.cpu2]
-type=GpuDispatcher
-children=cl_driver
-cl_driver=system.cpu2.cl_driver
-clk_domain=system.clk_domain
-cpu=system.cpu0
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8589934592
-pio_latency=1000
-power_model=Null
-shader_pointer=system.cpu1
-system=system
-dma=system.piobus.slave[1]
-pio=system.piobus.master[0]
-translation_port=system.dispatcher_coalescer.slave[0]
-
-[system.cpu2.cl_driver]
-type=ClDriver
-codefile=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm
-eventq_index=0
-filename=hsa
-
-[system.dir_cntrl0]
-type=Directory_Controller
-children=L3CacheMemory L3triggerQueue directory probeToCore requestFromCores responseFromCores responseFromMemory responseToCore triggerQueue unblockFromCores
-CPUonly=false
-L3CacheMemory=system.dir_cntrl0.L3CacheMemory
-L3triggerQueue=system.dir_cntrl0.L3triggerQueue
-TCC_select_num_bits=0
-buffer_size=0
-clk_domain=system.clk_domain
-cluster_id=0
-default_p_state=UNDEFINED
-directory=system.dir_cntrl0.directory
-eventq_index=0
-l3_hit_latency=15
-noTCCdir=false
-number_of_TBEs=5120
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-probeToCore=system.dir_cntrl0.probeToCore
-recycle_latency=10
-requestFromCores=system.dir_cntrl0.requestFromCores
-responseFromCores=system.dir_cntrl0.responseFromCores
-responseFromMemory=system.dir_cntrl0.responseFromMemory
-responseToCore=system.dir_cntrl0.responseToCore
-response_latency=30
-ruby_system=system.ruby
-system=system
-to_memory_controller_latency=1
-transitions_per_cycle=32
-triggerQueue=system.dir_cntrl0.triggerQueue
-unblockFromCores=system.dir_cntrl0.unblockFromCores
-useL3OnWT=false
-version=0
-memory=system.mem_ctrls.port
-
-[system.dir_cntrl0.L3CacheMemory]
-type=RubyCache
-children=replacement_policy
-assoc=8
-block_size=0
-dataAccessLatency=20
-dataArrayBanks=256.0
-eventq_index=0
-is_icache=false
-replacement_policy=system.dir_cntrl0.L3CacheMemory.replacement_policy
-resourceStalls=true
-ruby_system=system.ruby
-size=16777216
-start_index_bit=6
-tagAccessLatency=15
-tagArrayBanks=256.0
-
-[system.dir_cntrl0.L3CacheMemory.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=8
-block_size=64
-eventq_index=0
-size=16777216
-
-[system.dir_cntrl0.L3triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.dir_cntrl0.directory]
-type=RubyDirectoryMemory
-eventq_index=0
-numa_high_bit=5
-size=536870912
-system=system
-version=0
-
-[system.dir_cntrl0.probeToCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[0]
-
-[system.dir_cntrl0.requestFromCores]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[0]
-
-[system.dir_cntrl0.responseFromCores]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[1]
-
-[system.dir_cntrl0.responseFromMemory]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.dir_cntrl0.responseToCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[1]
-
-[system.dir_cntrl0.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.dir_cntrl0.unblockFromCores]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[2]
-
-[system.dispatcher_coalescer]
-type=TLBCoalescer
-children=clk_domain
-clk_domain=system.dispatcher_coalescer.clk_domain
-coalescingWindow=1
-default_p_state=UNDEFINED
-disableCoalescing=false
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-probesPerCycle=2
-master=system.dispatcher_tlb.slave[0]
-slave=system.cpu2.translation_port
-
-[system.dispatcher_coalescer.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.dispatcher_coalescer.clk_domain.voltage_domain
-
-[system.dispatcher_coalescer.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.dispatcher_tlb]
-type=X86GPUTLB
-children=clk_domain
-accessDistance=false
-allocationPolicy=true
-assoc=32
-clk_domain=system.dispatcher_tlb.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hitLatency=1
-maxOutstandingReqs=64
-missLatency1=5
-missLatency2=750
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-size=32
-master=system.l2_coalescer.slave[1]
-slave=system.dispatcher_coalescer.master[0]
-
-[system.dispatcher_tlb.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.dispatcher_tlb.clk_domain.voltage_domain
-
-[system.dispatcher_tlb.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.l1_coalescer0]
-type=TLBCoalescer
-children=clk_domain
-clk_domain=system.l1_coalescer0.clk_domain
-coalescingWindow=1
-default_p_state=UNDEFINED
-disableCoalescing=false
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-probesPerCycle=2
-master=system.l1_tlb0.slave[0]
-slave=system.cpu1.CUs0.translation_port[0]
-
-[system.l1_coalescer0.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l1_coalescer0.clk_domain.voltage_domain
-
-[system.l1_coalescer0.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l1_coalescer1]
-type=TLBCoalescer
-children=clk_domain
-clk_domain=system.l1_coalescer1.clk_domain
-coalescingWindow=1
-default_p_state=UNDEFINED
-disableCoalescing=false
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-probesPerCycle=2
-master=system.l1_tlb1.slave[0]
-slave=system.cpu1.CUs1.translation_port[0]
-
-[system.l1_coalescer1.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l1_coalescer1.clk_domain.voltage_domain
-
-[system.l1_coalescer1.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l1_tlb0]
-type=X86GPUTLB
-children=clk_domain
-accessDistance=false
-allocationPolicy=true
-assoc=32
-clk_domain=system.l1_tlb0.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hitLatency=1
-maxOutstandingReqs=64
-missLatency1=5
-missLatency2=750
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-size=32
-master=system.l2_coalescer.slave[2]
-slave=system.l1_coalescer0.master[0]
-
-[system.l1_tlb0.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l1_tlb0.clk_domain.voltage_domain
-
-[system.l1_tlb0.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l1_tlb1]
-type=X86GPUTLB
-children=clk_domain
-accessDistance=false
-allocationPolicy=true
-assoc=32
-clk_domain=system.l1_tlb1.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hitLatency=1
-maxOutstandingReqs=64
-missLatency1=5
-missLatency2=750
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-size=32
-master=system.l2_coalescer.slave[3]
-slave=system.l1_coalescer1.master[0]
-
-[system.l1_tlb1.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l1_tlb1.clk_domain.voltage_domain
-
-[system.l1_tlb1.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l2_coalescer]
-type=TLBCoalescer
-children=clk_domain
-clk_domain=system.l2_coalescer.clk_domain
-coalescingWindow=1
-default_p_state=UNDEFINED
-disableCoalescing=false
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-probesPerCycle=2
-master=system.l2_tlb.slave[0]
-slave=system.sqc_tlb.master[0] system.dispatcher_tlb.master[0] system.l1_tlb0.master[0] system.l1_tlb1.master[0]
-
-[system.l2_coalescer.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l2_coalescer.clk_domain.voltage_domain
-
-[system.l2_coalescer.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l2_tlb]
-type=X86GPUTLB
-children=clk_domain
-accessDistance=false
-allocationPolicy=true
-assoc=32
-clk_domain=system.l2_tlb.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hitLatency=69
-maxOutstandingReqs=64
-missLatency1=5
-missLatency2=750
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-size=4096
-master=system.l3_coalescer.slave[0]
-slave=system.l2_coalescer.master[0]
-
-[system.l2_tlb.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l2_tlb.clk_domain.voltage_domain
-
-[system.l2_tlb.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l3_coalescer]
-type=TLBCoalescer
-children=clk_domain
-clk_domain=system.l3_coalescer.clk_domain
-coalescingWindow=1
-default_p_state=UNDEFINED
-disableCoalescing=false
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-probesPerCycle=2
-master=system.l3_tlb.slave[0]
-slave=system.l2_tlb.master[0]
-
-[system.l3_coalescer.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l3_coalescer.clk_domain.voltage_domain
-
-[system.l3_coalescer.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l3_tlb]
-type=X86GPUTLB
-children=clk_domain
-accessDistance=false
-allocationPolicy=true
-assoc=32
-clk_domain=system.l3_tlb.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hitLatency=150
-maxOutstandingReqs=64
-missLatency1=5
-missLatency2=750
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-size=8192
-slave=system.l3_coalescer.master[0]
-
-[system.l3_tlb.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l3_tlb.clk_domain.voltage_domain
-
-[system.l3_tlb.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.mem_ctrls]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=false
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:536870911:5:19:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.dir_cntrl0.memory
-
-[system.piobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=0
-use_default_range=false
-width=32
-master=system.cpu2.pio
-slave=system.cp_cntrl0.sequencer.mem_master_port system.cpu2.dma
-
-[system.ruby]
-type=RubySystem
-children=clk_domain network phys_mem
-access_backing_store=true
-all_instructions=false
-block_size_bytes=64
-clk_domain=system.ruby.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hot_lines=false
-memory_size_bits=48
-num_of_sequencers=5
-number_of_virtual_networks=10
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-phys_mem=system.ruby.phys_mem
-power_model=Null
-randomization=false
-
-[system.ruby.clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.ruby.network]
-type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_link_buffers48 int_link_buffers49 int_link_buffers50 int_link_buffers51 int_link_buffers52 int_link_buffers53 int_link_buffers54 int_link_buffers55 int_link_buffers56 int_link_buffers57 int_link_buffers58 int_link_buffers59 int_link_buffers60 int_link_buffers61 int_link_buffers62 int_link_buffers63 int_link_buffers64 int_link_buffers65 int_link_buffers66 int_link_buffers67 int_link_buffers68 int_link_buffers69 int_link_buffers70 int_link_buffers71 int_link_buffers72 int_link_buffers73 int_link_buffers74 int_link_buffers75 int_link_buffers76 int_link_buffers77 int_link_buffers78 int_link_buffers79 int_links0 int_links1 int_links2 int_links3
-adaptive_routing=false
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-control_msg_size=8
-default_p_state=UNDEFINED
-endpoint_bandwidth=1000
-eventq_index=0
-ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4 system.ruby.network.ext_links5 system.ruby.network.ext_links6
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 system.ruby.network.int_link_buffers48 system.ruby.network.int_link_buffers49 system.ruby.network.int_link_buffers50 system.ruby.network.int_link_buffers51 system.ruby.network.int_link_buffers52 system.ruby.network.int_link_buffers53 system.ruby.network.int_link_buffers54 system.ruby.network.int_link_buffers55 system.ruby.network.int_link_buffers56 system.ruby.network.int_link_buffers57 system.ruby.network.int_link_buffers58 system.ruby.network.int_link_buffers59 system.ruby.network.int_link_buffers60 system.ruby.network.int_link_buffers61 system.ruby.network.int_link_buffers62 system.ruby.network.int_link_buffers63 system.ruby.network.int_link_buffers64 system.ruby.network.int_link_buffers65 system.ruby.network.int_link_buffers66 system.ruby.network.int_link_buffers67 system.ruby.network.int_link_buffers68 system.ruby.network.int_link_buffers69 system.ruby.network.int_link_buffers70 system.ruby.network.int_link_buffers71 system.ruby.network.int_link_buffers72 system.ruby.network.int_link_buffers73 system.ruby.network.int_link_buffers74 system.ruby.network.int_link_buffers75 system.ruby.network.int_link_buffers76 system.ruby.network.int_link_buffers77 system.ruby.network.int_link_buffers78 system.ruby.network.int_link_buffers79
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3
-netifs=
-number_of_virtual_networks=10
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-routers=system.ruby.network.ext_links0.int_node system.ruby.network.ext_links1.int_node system.ruby.network.ext_links2.int_node
-ruby_system=system.ruby
-topology=Crossbar
-master=system.dir_cntrl0.requestFromCores.slave system.dir_cntrl0.responseFromCores.slave system.dir_cntrl0.unblockFromCores.slave system.cp_cntrl0.probeToCore.slave system.cp_cntrl0.responseToCore.slave system.tcp_cntrl0.probeToTCP.slave system.tcp_cntrl0.responseToTCP.slave system.tcp_cntrl1.probeToTCP.slave system.tcp_cntrl1.responseToTCP.slave system.sqc_cntrl0.probeToSQC.slave system.sqc_cntrl0.responseToSQC.slave system.tcc_cntrl0.responseToTCC.slave system.tccdir_cntrl0.requestFromTCP.slave system.tccdir_cntrl0.responseFromTCP.slave system.tccdir_cntrl0.unblockFromTCP.slave system.tccdir_cntrl0.probeFromNB.slave system.tccdir_cntrl0.responseFromNB.slave
-slave=system.dir_cntrl0.probeToCore.master system.dir_cntrl0.responseToCore.master system.cp_cntrl0.requestFromCore.master system.cp_cntrl0.responseFromCore.master system.cp_cntrl0.unblockFromCore.master system.tcp_cntrl0.requestFromTCP.master system.tcp_cntrl0.responseFromTCP.master system.tcp_cntrl0.unblockFromCore.master system.tcp_cntrl1.requestFromTCP.master system.tcp_cntrl1.responseFromTCP.master system.tcp_cntrl1.unblockFromCore.master system.sqc_cntrl0.requestFromSQC.master system.sqc_cntrl0.responseFromSQC.master system.sqc_cntrl0.unblockFromCore.master system.tcc_cntrl0.responseFromTCC.master system.tccdir_cntrl0.probeToCore.master system.tccdir_cntrl0.responseToCore.master system.tccdir_cntrl0.requestToNB.master system.tccdir_cntrl0.responseToNB.master system.tccdir_cntrl0.unblockToNB.master
-
-[system.ruby.network.ext_links0]
-type=SimpleExtLink
-children=int_node
-bandwidth_factor=512
-eventq_index=0
-ext_node=system.dir_cntrl0
-int_node=system.ruby.network.ext_links0.int_node
-latency=1
-link_id=0
-weight=1
-
-[system.ruby.network.ext_links0.int_node]
-type=Switch
-children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 port_buffers24 port_buffers25 port_buffers26 port_buffers27 port_buffers28 port_buffers29 port_buffers30 port_buffers31 port_buffers32 port_buffers33 port_buffers34 port_buffers35 port_buffers36 port_buffers37 port_buffers38 port_buffers39 port_buffers40 port_buffers41 port_buffers42 port_buffers43 port_buffers44 port_buffers45 port_buffers46 port_buffers47 port_buffers48 port_buffers49 port_buffers50 port_buffers51 port_buffers52 port_buffers53 port_buffers54 port_buffers55 port_buffers56 port_buffers57 port_buffers58 port_buffers59 port_buffers60 port_buffers61 port_buffers62 port_buffers63 port_buffers64 port_buffers65 port_buffers66 port_buffers67 port_buffers68 port_buffers69 port_buffers70 port_buffers71 port_buffers72 port_buffers73 port_buffers74 port_buffers75 port_buffers76 port_buffers77 port_buffers78 port_buffers79 port_buffers80 port_buffers81 port_buffers82 port_buffers83 port_buffers84 port_buffers85 port_buffers86 port_buffers87 port_buffers88 port_buffers89
-clk_domain=system.ruby.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-latency=1
-p_state_clk_gate_bins=20
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-
-[system.ruby.network.int_link_buffers18]
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-
-[system.ruby.network.int_link_buffers19]
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-
-[system.ruby.network.int_link_buffers20]
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-
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-
-[system.ruby.network.int_link_buffers22]
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-
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-
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-
-[system.ruby.network.int_link_buffers25]
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-
-[system.ruby.network.int_link_buffers26]
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-
-[system.ruby.network.int_link_buffers27]
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-
-[system.ruby.network.int_link_buffers28]
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-
-[system.ruby.network.int_link_buffers29]
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-
-[system.ruby.network.int_link_buffers30]
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-
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-
-[system.ruby.network.int_link_buffers32]
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-
-[system.ruby.network.int_link_buffers33]
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-
-[system.ruby.network.int_link_buffers34]
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-
-[system.ruby.network.int_link_buffers35]
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-
-[system.ruby.network.int_link_buffers36]
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-
-[system.ruby.network.int_link_buffers37]
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-
-[system.ruby.network.int_link_buffers38]
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-
-[system.ruby.network.int_link_buffers39]
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-
-[system.ruby.network.int_link_buffers40]
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-
-[system.ruby.network.int_link_buffers41]
-type=MessageBuffer
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-
-[system.ruby.network.int_link_buffers42]
-type=MessageBuffer
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-
-[system.ruby.network.int_link_buffers43]
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-
-[system.ruby.network.int_link_buffers44]
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-
-[system.ruby.network.int_link_buffers45]
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-
-[system.ruby.network.int_link_buffers46]
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-
-[system.ruby.network.int_link_buffers47]
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-
-[system.ruby.network.int_link_buffers48]
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-
-[system.ruby.network.int_link_buffers49]
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-
-[system.ruby.network.int_link_buffers50]
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-
-[system.ruby.network.int_link_buffers51]
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-
-[system.ruby.network.int_link_buffers52]
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-
-[system.ruby.network.int_link_buffers53]
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-
-[system.ruby.network.int_link_buffers54]
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-
-[system.ruby.network.int_link_buffers55]
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-
-[system.ruby.network.int_link_buffers56]
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-
-[system.ruby.network.int_link_buffers57]
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-
-[system.ruby.network.int_link_buffers58]
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-
-[system.ruby.network.int_link_buffers59]
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-
-[system.ruby.network.int_link_buffers60]
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-
-[system.ruby.network.int_link_buffers61]
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-
-[system.ruby.network.int_link_buffers62]
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-
-[system.ruby.network.int_link_buffers63]
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-
-[system.ruby.network.int_link_buffers64]
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-
-[system.ruby.network.int_link_buffers65]
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-
-[system.ruby.network.int_link_buffers66]
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-
-[system.ruby.network.int_link_buffers67]
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-
-[system.ruby.network.int_link_buffers68]
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-
-[system.ruby.network.int_link_buffers69]
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-
-[system.ruby.network.int_link_buffers70]
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-
-[system.ruby.network.int_link_buffers71]
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-
-[system.ruby.network.int_link_buffers72]
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-
-[system.ruby.network.int_link_buffers73]
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-
-[system.ruby.network.int_link_buffers74]
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-
-[system.ruby.network.int_link_buffers75]
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-
-[system.ruby.network.int_link_buffers76]
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-
-[system.ruby.network.int_link_buffers77]
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-
-[system.ruby.network.int_link_buffers78]
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-
-[system.ruby.network.int_link_buffers79]
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-
-[system.ruby.network.int_links0]
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-src_outport=
-weight=1
-
-[system.ruby.network.int_links1]
-type=SimpleIntLink
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-dst_node=system.ruby.network.ext_links0.int_node
-eventq_index=0
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-src_node=system.ruby.network.ext_links1.int_node
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-weight=1
-
-[system.ruby.network.int_links2]
-type=SimpleIntLink
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-weight=1
-
-[system.ruby.network.int_links3]
-type=SimpleIntLink
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-eventq_index=0
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-weight=1
-
-[system.ruby.phys_mem]
-type=SimpleMemory
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-
-[system.sqc_cntrl0]
-type=SQC_Controller
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-mandatoryQueue=system.sqc_cntrl0.mandatoryQueue
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-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-probeToSQC=system.sqc_cntrl0.probeToSQC
-recycle_latency=10
-requestFromSQC=system.sqc_cntrl0.requestFromSQC
-responseFromSQC=system.sqc_cntrl0.responseFromSQC
-responseToSQC=system.sqc_cntrl0.responseToSQC
-ruby_system=system.ruby
-sequencer=system.sqc_cntrl0.sequencer
-system=system
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-unblockFromCore=system.sqc_cntrl0.unblockFromCore
-version=0
-
-[system.sqc_cntrl0.L1cache]
-type=RubyCache
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-replacement_policy=system.sqc_cntrl0.L1cache.replacement_policy
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-ruby_system=system.ruby
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-tagAccessLatency=1
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-
-[system.sqc_cntrl0.L1cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
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-
-[system.sqc_cntrl0.mandatoryQueue]
-type=MessageBuffer
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-
-[system.sqc_cntrl0.probeToSQC]
-type=MessageBuffer
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-slave=system.ruby.network.master[9]
-
-[system.sqc_cntrl0.requestFromSQC]
-type=MessageBuffer
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-ordered=true
-randomization=false
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-
-[system.sqc_cntrl0.responseFromSQC]
-type=MessageBuffer
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-ordered=true
-randomization=false
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-
-[system.sqc_cntrl0.responseToSQC]
-type=MessageBuffer
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-ordered=true
-randomization=false
-slave=system.ruby.network.master[10]
-
-[system.sqc_cntrl0.sequencer]
-type=RubySequencer
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-default_p_state=UNDEFINED
-eventq_index=0
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-icache=system.sqc_cntrl0.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=false
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-no_retry_on_stall=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=false
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=6
-slave=system.cpu1.CUs0.sqc_port system.cpu1.CUs1.sqc_port
-
-[system.sqc_cntrl0.unblockFromCore]
-type=MessageBuffer
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-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[13]
-
-[system.sqc_coalescer]
-type=TLBCoalescer
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-coalescingWindow=1
-default_p_state=UNDEFINED
-disableCoalescing=false
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-probesPerCycle=2
-master=system.sqc_tlb.slave[0]
-slave=system.cpu1.CUs0.sqc_tlb_port system.cpu1.CUs1.sqc_tlb_port
-
-[system.sqc_coalescer.clk_domain]
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-domain_id=-1
-eventq_index=0
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-voltage_domain=system.sqc_coalescer.clk_domain.voltage_domain
-
-[system.sqc_coalescer.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.sqc_tlb]
-type=X86GPUTLB
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-default_p_state=UNDEFINED
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-hitLatency=1
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-missLatency1=5
-missLatency2=750
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-size=32
-master=system.l2_coalescer.slave[0]
-slave=system.sqc_coalescer.master[0]
-
-[system.sqc_tlb.clk_domain]
-type=SrcClockDomain
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-domain_id=-1
-eventq_index=0
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-voltage_domain=system.sqc_tlb.clk_domain.voltage_domain
-
-[system.sqc_tlb.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.sys_port_proxy]
-type=RubyPortProxy
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-eventq_index=0
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-no_retry_on_stall=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=0
-slave=system.system_port
-
-[system.tcc_cntrl0]
-type=TCC_Controller
-children=L2cache responseFromTCC responseToTCC w_TCCUnblockToTCCDir w_probeToTCC w_reqToTCC w_reqToTCCDir w_respToTCC w_respToTCCDir
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-clk_domain=system.clk_domain
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-default_p_state=UNDEFINED
-eventq_index=0
-l2_request_latency=1
-l2_response_latency=16
-number_of_TBEs=2048
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-recycle_latency=10
-responseFromTCC=system.tcc_cntrl0.responseFromTCC
-responseToTCC=system.tcc_cntrl0.responseToTCC
-ruby_system=system.ruby
-system=system
-transitions_per_cycle=32
-version=0
-w_TCCUnblockToTCCDir=system.tcc_cntrl0.w_TCCUnblockToTCCDir
-w_probeToTCC=system.tcc_cntrl0.w_probeToTCC
-w_reqToTCC=system.tcc_cntrl0.w_reqToTCC
-w_reqToTCCDir=system.tcc_cntrl0.w_reqToTCCDir
-w_respToTCC=system.tcc_cntrl0.w_respToTCC
-w_respToTCCDir=system.tcc_cntrl0.w_respToTCCDir
-
-[system.tcc_cntrl0.L2cache]
-type=RubyCache
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-dataAccessLatency=8
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-eventq_index=0
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-replacement_policy=system.tcc_cntrl0.L2cache.replacement_policy
-resourceStalls=true
-ruby_system=system.ruby
-size=262144.0
-start_index_bit=6
-tagAccessLatency=2
-tagArrayBanks=256
-
-[system.tcc_cntrl0.L2cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
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-eventq_index=0
-size=262144.0
-
-[system.tcc_cntrl0.responseFromTCC]
-type=MessageBuffer
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-ordered=true
-randomization=false
-master=system.ruby.network.slave[14]
-
-[system.tcc_cntrl0.responseToTCC]
-type=MessageBuffer
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-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[11]
-
-[system.tcc_cntrl0.w_TCCUnblockToTCCDir]
-type=RubyWireBuffer
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-ruby_system=system.ruby
-
-[system.tcc_cntrl0.w_probeToTCC]
-type=RubyWireBuffer
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-ruby_system=system.ruby
-
-[system.tcc_cntrl0.w_reqToTCC]
-type=RubyWireBuffer
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-ruby_system=system.ruby
-
-[system.tcc_cntrl0.w_reqToTCCDir]
-type=RubyWireBuffer
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-ruby_system=system.ruby
-
-[system.tcc_cntrl0.w_respToTCC]
-type=RubyWireBuffer
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-ruby_system=system.ruby
-
-[system.tcc_cntrl0.w_respToTCCDir]
-type=RubyWireBuffer
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-ruby_system=system.ruby
-
-[system.tccdir_cntrl0]
-type=TCCdir_Controller
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-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-probeFromNB=system.tccdir_cntrl0.probeFromNB
-probeToCore=system.tccdir_cntrl0.probeToCore
-recycle_latency=10
-requestFromTCP=system.tccdir_cntrl0.requestFromTCP
-requestToNB=system.tccdir_cntrl0.requestToNB
-responseFromNB=system.tccdir_cntrl0.responseFromNB
-responseFromTCP=system.tccdir_cntrl0.responseFromTCP
-responseToCore=system.tccdir_cntrl0.responseToCore
-responseToNB=system.tccdir_cntrl0.responseToNB
-response_latency=5
-ruby_system=system.ruby
-system=system
-transitions_per_cycle=32
-triggerQueue=system.tccdir_cntrl0.triggerQueue
-unblockFromTCP=system.tccdir_cntrl0.unblockFromTCP
-unblockToNB=system.tccdir_cntrl0.unblockToNB
-version=0
-w_TCCUnblockToTCCDir=system.tcc_cntrl0.w_TCCUnblockToTCCDir
-w_probeToTCC=system.tcc_cntrl0.w_probeToTCC
-w_reqToTCC=system.tcc_cntrl0.w_reqToTCC
-w_reqToTCCDir=system.tcc_cntrl0.w_reqToTCCDir
-w_respToTCC=system.tcc_cntrl0.w_respToTCC
-w_respToTCCDir=system.tcc_cntrl0.w_respToTCCDir
-
-[system.tccdir_cntrl0.directory]
-type=RubyCache
-children=replacement_policy
-assoc=16
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.tccdir_cntrl0.directory.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=393216
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.tccdir_cntrl0.directory.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=16
-block_size=64
-eventq_index=0
-size=393216
-
-[system.tccdir_cntrl0.probeFromNB]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[15]
-
-[system.tccdir_cntrl0.probeToCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[15]
-
-[system.tccdir_cntrl0.requestFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[12]
-
-[system.tccdir_cntrl0.requestToNB]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[17]
-
-[system.tccdir_cntrl0.responseFromNB]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[16]
-
-[system.tccdir_cntrl0.responseFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[13]
-
-[system.tccdir_cntrl0.responseToCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[16]
-
-[system.tccdir_cntrl0.responseToNB]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[18]
-
-[system.tccdir_cntrl0.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.tccdir_cntrl0.unblockFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[14]
-
-[system.tccdir_cntrl0.unblockToNB]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[19]
-
-[system.tcp_cntrl0]
-type=TCP_Controller
-children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore
-L1cache=system.tcp_cntrl0.L1cache
-TCC_select_num_bits=0
-buffer_size=0
-clk_domain=system.clk_domain
-cluster_id=0
-coalescer=system.tcp_cntrl0.coalescer
-default_p_state=UNDEFINED
-eventq_index=0
-issue_latency=40
-l2_hit_latency=18
-mandatoryQueue=system.tcp_cntrl0.mandatoryQueue
-number_of_TBEs=2560
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-probeToTCP=system.tcp_cntrl0.probeToTCP
-recycle_latency=10
-requestFromTCP=system.tcp_cntrl0.requestFromTCP
-responseFromTCP=system.tcp_cntrl0.responseFromTCP
-responseToTCP=system.tcp_cntrl0.responseToTCP
-ruby_system=system.ruby
-sequencer=system.tcp_cntrl0.sequencer
-system=system
-transitions_per_cycle=32
-unblockFromCore=system.tcp_cntrl0.unblockFromCore
-use_seq_not_coal=false
-version=0
-
-[system.tcp_cntrl0.L1cache]
-type=RubyCache
-children=replacement_policy
-assoc=8
-block_size=0
-dataAccessLatency=4
-dataArrayBanks=16
-eventq_index=0
-is_icache=false
-replacement_policy=system.tcp_cntrl0.L1cache.replacement_policy
-resourceStalls=true
-ruby_system=system.ruby
-size=16384
-start_index_bit=6
-tagAccessLatency=4
-tagArrayBanks=4
-
-[system.tcp_cntrl0.L1cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=8
-block_size=64
-eventq_index=0
-size=16384
-
-[system.tcp_cntrl0.coalescer]
-type=RubyGPUCoalescer
-assume_rfo=true
-clk_domain=system.clk_domain
-dcache=system.tcp_cntrl0.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.tcp_cntrl0.L1cache
-is_cpu_sequencer=false
-max_outstanding_requests=2048
-no_retry_on_stall=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=false
-system=system
-using_ruby_tester=false
-version=2
-slave=system.cpu1.CUs0.memory_port[0] system.cpu1.CUs0.memory_port[1] system.cpu1.CUs0.memory_port[2] system.cpu1.CUs0.memory_port[3] system.cpu1.CUs0.memory_port[4] system.cpu1.CUs0.memory_port[5] system.cpu1.CUs0.memory_port[6] system.cpu1.CUs0.memory_port[7] system.cpu1.CUs0.memory_port[8] system.cpu1.CUs0.memory_port[9] system.cpu1.CUs0.memory_port[10] system.cpu1.CUs0.memory_port[11] system.cpu1.CUs0.memory_port[12] system.cpu1.CUs0.memory_port[13] system.cpu1.CUs0.memory_port[14] system.cpu1.CUs0.memory_port[15] system.cpu1.CUs0.memory_port[16] system.cpu1.CUs0.memory_port[17] system.cpu1.CUs0.memory_port[18] system.cpu1.CUs0.memory_port[19] system.cpu1.CUs0.memory_port[20] system.cpu1.CUs0.memory_port[21] system.cpu1.CUs0.memory_port[22] system.cpu1.CUs0.memory_port[23] system.cpu1.CUs0.memory_port[24] system.cpu1.CUs0.memory_port[25] system.cpu1.CUs0.memory_port[26] system.cpu1.CUs0.memory_port[27] system.cpu1.CUs0.memory_port[28] system.cpu1.CUs0.memory_port[29] system.cpu1.CUs0.memory_port[30] system.cpu1.CUs0.memory_port[31] system.cpu1.CUs0.memory_port[32] system.cpu1.CUs0.memory_port[33] system.cpu1.CUs0.memory_port[34] system.cpu1.CUs0.memory_port[35] system.cpu1.CUs0.memory_port[36] system.cpu1.CUs0.memory_port[37] system.cpu1.CUs0.memory_port[38] system.cpu1.CUs0.memory_port[39] system.cpu1.CUs0.memory_port[40] system.cpu1.CUs0.memory_port[41] system.cpu1.CUs0.memory_port[42] system.cpu1.CUs0.memory_port[43] system.cpu1.CUs0.memory_port[44] system.cpu1.CUs0.memory_port[45] system.cpu1.CUs0.memory_port[46] system.cpu1.CUs0.memory_port[47] system.cpu1.CUs0.memory_port[48] system.cpu1.CUs0.memory_port[49] system.cpu1.CUs0.memory_port[50] system.cpu1.CUs0.memory_port[51] system.cpu1.CUs0.memory_port[52] system.cpu1.CUs0.memory_port[53] system.cpu1.CUs0.memory_port[54] system.cpu1.CUs0.memory_port[55] system.cpu1.CUs0.memory_port[56] system.cpu1.CUs0.memory_port[57] system.cpu1.CUs0.memory_port[58] system.cpu1.CUs0.memory_port[59] system.cpu1.CUs0.memory_port[60] system.cpu1.CUs0.memory_port[61] system.cpu1.CUs0.memory_port[62] system.cpu1.CUs0.memory_port[63]
-
-[system.tcp_cntrl0.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.tcp_cntrl0.probeToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[5]
-
-[system.tcp_cntrl0.requestFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[5]
-
-[system.tcp_cntrl0.responseFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[6]
-
-[system.tcp_cntrl0.responseToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[6]
-
-[system.tcp_cntrl0.sequencer]
-type=RubySequencer
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.tcp_cntrl0.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.tcp_cntrl0.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=3
-
-[system.tcp_cntrl0.unblockFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[7]
-
-[system.tcp_cntrl1]
-type=TCP_Controller
-children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore
-L1cache=system.tcp_cntrl1.L1cache
-TCC_select_num_bits=0
-buffer_size=0
-clk_domain=system.clk_domain
-cluster_id=0
-coalescer=system.tcp_cntrl1.coalescer
-default_p_state=UNDEFINED
-eventq_index=0
-issue_latency=40
-l2_hit_latency=18
-mandatoryQueue=system.tcp_cntrl1.mandatoryQueue
-number_of_TBEs=2560
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-probeToTCP=system.tcp_cntrl1.probeToTCP
-recycle_latency=10
-requestFromTCP=system.tcp_cntrl1.requestFromTCP
-responseFromTCP=system.tcp_cntrl1.responseFromTCP
-responseToTCP=system.tcp_cntrl1.responseToTCP
-ruby_system=system.ruby
-sequencer=system.tcp_cntrl1.sequencer
-system=system
-transitions_per_cycle=32
-unblockFromCore=system.tcp_cntrl1.unblockFromCore
-use_seq_not_coal=false
-version=1
-
-[system.tcp_cntrl1.L1cache]
-type=RubyCache
-children=replacement_policy
-assoc=8
-block_size=0
-dataAccessLatency=4
-dataArrayBanks=16
-eventq_index=0
-is_icache=false
-replacement_policy=system.tcp_cntrl1.L1cache.replacement_policy
-resourceStalls=true
-ruby_system=system.ruby
-size=16384
-start_index_bit=6
-tagAccessLatency=4
-tagArrayBanks=4
-
-[system.tcp_cntrl1.L1cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=8
-block_size=64
-eventq_index=0
-size=16384
-
-[system.tcp_cntrl1.coalescer]
-type=RubyGPUCoalescer
-assume_rfo=true
-clk_domain=system.clk_domain
-dcache=system.tcp_cntrl1.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.tcp_cntrl1.L1cache
-is_cpu_sequencer=false
-max_outstanding_requests=2048
-no_retry_on_stall=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=false
-system=system
-using_ruby_tester=false
-version=4
-slave=system.cpu1.CUs1.memory_port[0] system.cpu1.CUs1.memory_port[1] system.cpu1.CUs1.memory_port[2] system.cpu1.CUs1.memory_port[3] system.cpu1.CUs1.memory_port[4] system.cpu1.CUs1.memory_port[5] system.cpu1.CUs1.memory_port[6] system.cpu1.CUs1.memory_port[7] system.cpu1.CUs1.memory_port[8] system.cpu1.CUs1.memory_port[9] system.cpu1.CUs1.memory_port[10] system.cpu1.CUs1.memory_port[11] system.cpu1.CUs1.memory_port[12] system.cpu1.CUs1.memory_port[13] system.cpu1.CUs1.memory_port[14] system.cpu1.CUs1.memory_port[15] system.cpu1.CUs1.memory_port[16] system.cpu1.CUs1.memory_port[17] system.cpu1.CUs1.memory_port[18] system.cpu1.CUs1.memory_port[19] system.cpu1.CUs1.memory_port[20] system.cpu1.CUs1.memory_port[21] system.cpu1.CUs1.memory_port[22] system.cpu1.CUs1.memory_port[23] system.cpu1.CUs1.memory_port[24] system.cpu1.CUs1.memory_port[25] system.cpu1.CUs1.memory_port[26] system.cpu1.CUs1.memory_port[27] system.cpu1.CUs1.memory_port[28] system.cpu1.CUs1.memory_port[29] system.cpu1.CUs1.memory_port[30] system.cpu1.CUs1.memory_port[31] system.cpu1.CUs1.memory_port[32] system.cpu1.CUs1.memory_port[33] system.cpu1.CUs1.memory_port[34] system.cpu1.CUs1.memory_port[35] system.cpu1.CUs1.memory_port[36] system.cpu1.CUs1.memory_port[37] system.cpu1.CUs1.memory_port[38] system.cpu1.CUs1.memory_port[39] system.cpu1.CUs1.memory_port[40] system.cpu1.CUs1.memory_port[41] system.cpu1.CUs1.memory_port[42] system.cpu1.CUs1.memory_port[43] system.cpu1.CUs1.memory_port[44] system.cpu1.CUs1.memory_port[45] system.cpu1.CUs1.memory_port[46] system.cpu1.CUs1.memory_port[47] system.cpu1.CUs1.memory_port[48] system.cpu1.CUs1.memory_port[49] system.cpu1.CUs1.memory_port[50] system.cpu1.CUs1.memory_port[51] system.cpu1.CUs1.memory_port[52] system.cpu1.CUs1.memory_port[53] system.cpu1.CUs1.memory_port[54] system.cpu1.CUs1.memory_port[55] system.cpu1.CUs1.memory_port[56] system.cpu1.CUs1.memory_port[57] system.cpu1.CUs1.memory_port[58] system.cpu1.CUs1.memory_port[59] system.cpu1.CUs1.memory_port[60] system.cpu1.CUs1.memory_port[61] system.cpu1.CUs1.memory_port[62] system.cpu1.CUs1.memory_port[63]
-
-[system.tcp_cntrl1.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.tcp_cntrl1.probeToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[7]
-
-[system.tcp_cntrl1.requestFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[8]
-
-[system.tcp_cntrl1.responseFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[9]
-
-[system.tcp_cntrl1.responseToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[8]
-
-[system.tcp_cntrl1.sequencer]
-type=RubySequencer
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.tcp_cntrl1.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.tcp_cntrl1.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=5
-
-[system.tcp_cntrl1.unblockFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[10]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: system.ruby.network adopting orphan SimObject param 'int_links'
-warn: system.ruby.network adopting orphan SimObject param 'ext_links'
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Entering event queue @ 0. Starting simulation...
-warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
+++ /dev/null
-Redirecting stdout to build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO/simout
-Redirecting stderr to build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Mar 29 2017 16:09:06
-gem5 started Mar 29 2017 16:09:22
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54093
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO
-
-Using GPU kernel code file(s) /usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm
-Global frequency set at 1000000000000 ticks per second
-Forcing maxCoalescedReqs to 32 (TLB assoc.)
-Forcing maxCoalescedReqs to 32 (TLB assoc.)
-Forcing maxCoalescedReqs to 32 (TLB assoc.)
-Forcing maxCoalescedReqs to 32 (TLB assoc.)
-Forcing maxCoalescedReqs to 32 (TLB assoc.)
-Forcing maxCoalescedReqs to 32 (TLB assoc.)
-keys = 0x7b2bc0, &keys = 0x798998, keys[0] = 23
-the gpu says:
-\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fe
-Exiting @ tick 667407500 because exiting with last active thread context
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000667
-sim_ticks 667407500
-final_tick 667407500
-sim_freq 1000000000000
-host_inst_rate 212660
-host_op_rate 437306
-host_tick_rate 2119397283
-host_mem_usage 1336868
-host_seconds 0.32
-sim_insts 66963
-sim_ops 137705
-system.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 667407500
-system.mem_ctrls.bytes_read::dir_cntrl0 99136
-system.mem_ctrls.bytes_read::total 99136
-system.mem_ctrls.num_reads::dir_cntrl0 1549
-system.mem_ctrls.num_reads::total 1549
-system.mem_ctrls.bw_read::dir_cntrl0 148538936
-system.mem_ctrls.bw_read::total 148538936
-system.mem_ctrls.bw_total::dir_cntrl0 148538936
-system.mem_ctrls.bw_total::total 148538936
-system.mem_ctrls.readReqs 1549
-system.mem_ctrls.writeReqs 0
-system.mem_ctrls.readBursts 1549
-system.mem_ctrls.writeBursts 0
-system.mem_ctrls.bytesReadDRAM 99136
-system.mem_ctrls.bytesReadWrQ 0
-system.mem_ctrls.bytesWritten 0
-system.mem_ctrls.bytesReadSys 99136
-system.mem_ctrls.bytesWrittenSys 0
-system.mem_ctrls.servicedByWrQ 0
-system.mem_ctrls.mergedWrBursts 0
-system.mem_ctrls.neitherReadNorWriteReqs 0
-system.mem_ctrls.perBankRdBursts::0 122
-system.mem_ctrls.perBankRdBursts::1 192
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-system.cpu1.CUs1.ExecStage.spc::total 2840
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-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 8 8.79% 92.31%
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 92.31%
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 0 0.00% 92.31%
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 0 0.00% 92.31%
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-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 93.41%
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 93.41%
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 93.41%
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 93.41%
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 93.41%
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-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 93.41%
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 93.41%
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 93.41%
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 93.41%
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-system.cpu1.CUs1.lds_bank_conflicts::46-47 0 0.00% 100.00%
-system.cpu1.CUs1.lds_bank_conflicts::48-49 0 0.00% 100.00%
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-system.ruby.CorePair_Controller.C0_Store_L1hit 10448 0.00% 0.00%
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-system.ruby.CorePair_Controller.NB_AckM 326 0.00% 0.00%
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-system.ruby.CorePair_Controller.PrbShrData 5 0.00% 0.00%
-system.ruby.CorePair_Controller.I.C0_Load_L1miss 175 0.00% 0.00%
-system.ruby.CorePair_Controller.I.Ifetch0_L1miss 1034 0.00% 0.00%
-system.ruby.CorePair_Controller.I.C0_Store_L1miss 325 0.00% 0.00%
-system.ruby.CorePair_Controller.I.PrbInvData 8 0.00% 0.00%
-system.ruby.CorePair_Controller.I.PrbShrData 3 0.00% 0.00%
-system.ruby.CorePair_Controller.S.C0_Load_L1hit 635 0.00% 0.00%
-system.ruby.CorePair_Controller.S.Ifetch0_L1hit 86007 0.00% 0.00%
-system.ruby.CorePair_Controller.S.Ifetch0_L1miss 54 0.00% 0.00%
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-system.ruby.CorePair_Controller.E0.C0_Load_L1miss 2 0.00% 0.00%
-system.ruby.CorePair_Controller.E0.C0_Load_L1hit 2721 0.00% 0.00%
-system.ruby.CorePair_Controller.E0.C0_Store_L1hit 46 0.00% 0.00%
-system.ruby.CorePair_Controller.E0.L1D0_Repl 16 0.00% 0.00%
-system.ruby.CorePair_Controller.E0.PrbShrData 1 0.00% 0.00%
-system.ruby.CorePair_Controller.O.C0_Load_L1hit 3 0.00% 0.00%
-system.ruby.CorePair_Controller.O.C0_Store_L1hit 1 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.C0_Load_L1miss 3 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.C0_Load_L1hit 12796 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.C0_Store_L1hit 10401 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.L1D0_Repl 8 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.PrbInvData 1 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.PrbShrData 1 0.00% 0.00%
-system.ruby.CorePair_Controller.I_M0.NB_AckM 325 0.00% 0.00%
-system.ruby.CorePair_Controller.I_E0S.NB_AckS 9 0.00% 0.00%
-system.ruby.CorePair_Controller.I_E0S.NB_AckE 166 0.00% 0.00%
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-system.ruby.CorePair_Controller.O_M0.NB_AckM 1 0.00% 0.00%
-system.ruby.CorePair_Controller.S0.NB_AckS 1034 0.00% 0.00%
-system.ruby.CorePair_Controller.E0_F.L2_to_L1D0 2 0.00% 0.00%
-system.ruby.CorePair_Controller.M0_F.L2_to_L1D0 3 0.00% 0.00%
-system.ruby.Directory_Controller.RdBlkS 1037 0.00% 0.00%
-system.ruby.Directory_Controller.RdBlkM 335 0.00% 0.00%
-system.ruby.Directory_Controller.RdBlk 177 0.00% 0.00%
-system.ruby.Directory_Controller.CPUPrbResp 1549 0.00% 0.00%
-system.ruby.Directory_Controller.ProbeAcksComplete 1549 0.00% 0.00%
-system.ruby.Directory_Controller.MemData 1549 0.00% 0.00%
-system.ruby.Directory_Controller.CoreUnblock 1549 0.00% 0.00%
-system.ruby.Directory_Controller.U.RdBlkS 1037 0.00% 0.00%
-system.ruby.Directory_Controller.U.RdBlkM 335 0.00% 0.00%
-system.ruby.Directory_Controller.U.RdBlk 177 0.00% 0.00%
-system.ruby.Directory_Controller.BS_M.MemData 35 0.00% 0.00%
-system.ruby.Directory_Controller.BM_M.MemData 18 0.00% 0.00%
-system.ruby.Directory_Controller.B_M.MemData 11 0.00% 0.00%
-system.ruby.Directory_Controller.BS_PM.CPUPrbResp 35 0.00% 0.00%
-system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 35 0.00% 0.00%
-system.ruby.Directory_Controller.BS_PM.MemData 1002 0.00% 0.00%
-system.ruby.Directory_Controller.BM_PM.CPUPrbResp 18 0.00% 0.00%
-system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 18 0.00% 0.00%
-system.ruby.Directory_Controller.BM_PM.MemData 317 0.00% 0.00%
-system.ruby.Directory_Controller.B_PM.CPUPrbResp 11 0.00% 0.00%
-system.ruby.Directory_Controller.B_PM.ProbeAcksComplete 11 0.00% 0.00%
-system.ruby.Directory_Controller.B_PM.MemData 166 0.00% 0.00%
-system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 1002 0.00% 0.00%
-system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 1002 0.00% 0.00%
-system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 317 0.00% 0.00%
-system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 317 0.00% 0.00%
-system.ruby.Directory_Controller.B_Pm.CPUPrbResp 166 0.00% 0.00%
-system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 166 0.00% 0.00%
-system.ruby.Directory_Controller.B.CoreUnblock 1549 0.00% 0.00%
-system.ruby.LD.latency_hist_seqr::bucket_size 64
-system.ruby.LD.latency_hist_seqr::max_bucket 639
-system.ruby.LD.latency_hist_seqr::samples 16335
-system.ruby.LD.latency_hist_seqr::mean 4.314539
-system.ruby.LD.latency_hist_seqr::gmean 2.104196
-system.ruby.LD.latency_hist_seqr::stdev 22.794494
-system.ruby.LD.latency_hist_seqr | 16160 98.93% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 166 1.02% 99.94% | 6 0.04% 99.98% | 1 0.01% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 2 0.01% 100.00%
-system.ruby.LD.latency_hist_seqr::total 16335
-system.ruby.LD.latency_hist_coalsr::bucket_size 64
-system.ruby.LD.latency_hist_coalsr::max_bucket 639
-system.ruby.LD.latency_hist_coalsr::samples 9
-system.ruby.LD.latency_hist_coalsr::mean 133.666667
-system.ruby.LD.latency_hist_coalsr::gmean 19.860866
-system.ruby.LD.latency_hist_coalsr::stdev 158.801763
-system.ruby.LD.latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.latency_hist_coalsr::total 9
-system.ruby.LD.hit_latency_hist_seqr::bucket_size 64
-system.ruby.LD.hit_latency_hist_seqr::max_bucket 639
-system.ruby.LD.hit_latency_hist_seqr::samples 175
-system.ruby.LD.hit_latency_hist_seqr::mean 217.531429
-system.ruby.LD.hit_latency_hist_seqr::gmean 214.409561
-system.ruby.LD.hit_latency_hist_seqr::stdev 50.482703
-system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 166 94.86% 94.86% | 6 3.43% 98.29% | 1 0.57% 98.86% | 0 0.00% 98.86% | 0 0.00% 98.86% | 0 0.00% 98.86% | 2 1.14% 100.00%
-system.ruby.LD.hit_latency_hist_seqr::total 175
-system.ruby.LD.miss_latency_hist_seqr::bucket_size 4
-system.ruby.LD.miss_latency_hist_seqr::max_bucket 39
-system.ruby.LD.miss_latency_hist_seqr::samples 16160
-system.ruby.LD.miss_latency_hist_seqr::mean 2.005569
-system.ruby.LD.miss_latency_hist_seqr::gmean 2.001425
-system.ruby.LD.miss_latency_hist_seqr::stdev 0.316580
-system.ruby.LD.miss_latency_hist_seqr | 16155 99.97% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 5 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.miss_latency_hist_seqr::total 16160
-system.ruby.LD.miss_latency_hist_coalsr::bucket_size 64
-system.ruby.LD.miss_latency_hist_coalsr::max_bucket 639
-system.ruby.LD.miss_latency_hist_coalsr::samples 9
-system.ruby.LD.miss_latency_hist_coalsr::mean 133.666667
-system.ruby.LD.miss_latency_hist_coalsr::gmean 19.860866
-system.ruby.LD.miss_latency_hist_coalsr::stdev 158.801763
-system.ruby.LD.miss_latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.miss_latency_hist_coalsr::total 9
-system.ruby.ST.latency_hist_seqr::bucket_size 64
-system.ruby.ST.latency_hist_seqr::max_bucket 639
-system.ruby.ST.latency_hist_seqr::samples 10412
-system.ruby.ST.latency_hist_seqr::mean 8.469939
-system.ruby.ST.latency_hist_seqr::gmean 2.309412
-system.ruby.ST.latency_hist_seqr::stdev 36.833690
-system.ruby.ST.latency_hist_seqr | 10090 96.91% 96.91% | 0 0.00% 96.91% | 0 0.00% 96.91% | 314 3.02% 99.92% | 1 0.01% 99.93% | 5 0.05% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 2 0.02% 100.00%
-system.ruby.ST.latency_hist_seqr::total 10412
-system.ruby.ST.latency_hist_coalsr::bucket_size 64
-system.ruby.ST.latency_hist_coalsr::max_bucket 639
-system.ruby.ST.latency_hist_coalsr::samples 16
-system.ruby.ST.latency_hist_coalsr::mean 184.500000
-system.ruby.ST.latency_hist_coalsr::gmean 27.004823
-system.ruby.ST.latency_hist_coalsr::stdev 190.921974
-system.ruby.ST.latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 4 25.00% 75.00% | 4 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.latency_hist_coalsr::total 16
-system.ruby.ST.hit_latency_hist_seqr::bucket_size 64
-system.ruby.ST.hit_latency_hist_seqr::max_bucket 639
-system.ruby.ST.hit_latency_hist_seqr::samples 322
-system.ruby.ST.hit_latency_hist_seqr::mean 211.208075
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-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::samples 10090
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::mean 2
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::total 10090
-system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::bucket_size 64
-system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::max_bucket 639
-system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::samples 322
-system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::mean 211.208075
-system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::gmean 209.444324
-system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::stdev 38.157121
-system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 314 97.52% 97.52% | 1 0.31% 97.83% | 5 1.55% 99.38% | 0 0.00% 99.38% | 0 0.00% 99.38% | 0 0.00% 99.38% | 2 0.62% 100.00%
-system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::total 322
-system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1
-system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9
-system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::samples 8
-system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean 2
-system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean 2
-system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::total 8
-system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 64
-system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 639
-system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::samples 8
-system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 367
-system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 364.630235
-system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 44.510031
-system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 50.00% 50.00% | 4 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::total 8
-system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64
-system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639
-system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 1
-system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 332
-system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 332.000000
-system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev nan
-system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 1
-system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32
-system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319
-system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::samples 1
-system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::mean 259
-system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 259.000000
-system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::stdev nan
-system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::total 1
-system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1
-system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9
-system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::samples 86007
-system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::mean 2
-system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000
-system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 86007 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist_seqr::total 86007
-system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::bucket_size 4
-system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::max_bucket 39
-system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::samples 54
-system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::mean 20
-system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::gmean 20.000000
-system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 54 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::total 54
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::bucket_size 64
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::max_bucket 639
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::samples 1034
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean 210.386847
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean 209.145816
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::stdev 30.434753
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1006 97.29% 97.29% | 11 1.06% 98.36% | 12 1.16% 99.52% | 2 0.19% 99.71% | 0 0.00% 99.71% | 0 0.00% 99.71% | 3 0.29% 100.00%
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::total 1034
-system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1
-system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9
-system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::samples 337
-system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::mean 2
-system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2.000000
-system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::total 337
-system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::bucket_size 32
-system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::max_bucket 319
-system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::samples 4
-system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::mean 206
-system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::gmean 206.000000
-system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist_seqr::total 4
-system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1
-system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9
-system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::samples 10
-system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::mean 2
-system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2
-system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::total 10
-system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1
-system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9
-system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::samples 10
-system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::mean 2
-system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2
-system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::total 10
-system.ruby.SQC_Controller.Fetch 70 0.00% 0.00%
-system.ruby.SQC_Controller.TCC_AckS 3 0.00% 0.00%
-system.ruby.SQC_Controller.I.Fetch 3 0.00% 0.00%
-system.ruby.SQC_Controller.S.Fetch 67 0.00% 0.00%
-system.ruby.SQC_Controller.I_S.TCC_AckS 3 0.00% 0.00%
-system.ruby.TCCdir_Controller.RdBlk 54 0.00% 0.00%
-system.ruby.TCCdir_Controller.RdBlkM 34 0.00% 0.00%
-system.ruby.TCCdir_Controller.RdBlkS 3 0.00% 0.00%
-system.ruby.TCCdir_Controller.CPUPrbResp 14 0.00% 0.00%
-system.ruby.TCCdir_Controller.ProbeAcksComplete 13 0.00% 0.00%
-system.ruby.TCCdir_Controller.CoreUnblock 15 0.00% 0.00%
-system.ruby.TCCdir_Controller.LastCoreUnblock 2 0.00% 0.00%
-system.ruby.TCCdir_Controller.NB_AckS 5 0.00% 0.00%
-system.ruby.TCCdir_Controller.NB_AckM 9 0.00% 0.00%
-system.ruby.TCCdir_Controller.PrbInvData 326 0.00% 0.00%
-system.ruby.TCCdir_Controller.PrbShrData 1209 0.00% 0.00%
-system.ruby.TCCdir_Controller.I.RdBlk 2 0.00% 0.00%
-system.ruby.TCCdir_Controller.I.RdBlkM 9 0.00% 0.00%
-system.ruby.TCCdir_Controller.I.RdBlkS 3 0.00% 0.00%
-system.ruby.TCCdir_Controller.I.PrbInvData 325 0.00% 0.00%
-system.ruby.TCCdir_Controller.I.PrbShrData 1200 0.00% 0.00%
-system.ruby.TCCdir_Controller.S.RdBlk 2 0.00% 0.00%
-system.ruby.TCCdir_Controller.S.PrbInvData 1 0.00% 0.00%
-system.ruby.TCCdir_Controller.M.RdBlkM 1 0.00% 0.00%
-system.ruby.TCCdir_Controller.M.PrbShrData 9 0.00% 0.00%
-system.ruby.TCCdir_Controller.CP_I.CPUPrbResp 2 0.00% 0.00%
-system.ruby.TCCdir_Controller.CP_I.ProbeAcksComplete 1 0.00% 0.00%
-system.ruby.TCCdir_Controller.CP_O.CPUPrbResp 9 0.00% 0.00%
-system.ruby.TCCdir_Controller.CP_O.ProbeAcksComplete 9 0.00% 0.00%
-system.ruby.TCCdir_Controller.I_M.RdBlkM 20 0.00% 0.00%
-system.ruby.TCCdir_Controller.I_M.NB_AckM 9 0.00% 0.00%
-system.ruby.TCCdir_Controller.I_ES.RdBlk 41 0.00% 0.00%
-system.ruby.TCCdir_Controller.I_ES.NB_AckS 2 0.00% 0.00%
-system.ruby.TCCdir_Controller.I_S.NB_AckS 3 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBS_S.CPUPrbResp 2 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBS_S.ProbeAcksComplete 2 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBM_M.CPUPrbResp 1 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBM_M.ProbeAcksComplete 1 0.00% 0.00%
-system.ruby.TCCdir_Controller.BB_M.CoreUnblock 1 0.00% 0.00%
-system.ruby.TCCdir_Controller.BB_S.LastCoreUnblock 2 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBB_S.RdBlk 9 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBB_S.CoreUnblock 5 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBB_M.RdBlkM 4 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBB_M.CoreUnblock 9 0.00% 0.00%
-system.ruby.TCP_Controller.Load | 4 44.44% 44.44% | 5 55.56% 100.00%
-system.ruby.TCP_Controller.Load::total 9
-system.ruby.TCP_Controller.Store | 9 50.00% 50.00% | 9 50.00% 100.00%
-system.ruby.TCP_Controller.Store::total 18
-system.ruby.TCP_Controller.TCC_AckS | 2 50.00% 50.00% | 2 50.00% 100.00%
-system.ruby.TCP_Controller.TCC_AckS::total 4
-system.ruby.TCP_Controller.TCC_AckM | 5 50.00% 50.00% | 5 50.00% 100.00%
-system.ruby.TCP_Controller.TCC_AckM::total 10
-system.ruby.TCP_Controller.PrbInvData | 2 66.67% 66.67% | 1 33.33% 100.00%
-system.ruby.TCP_Controller.PrbInvData::total 3
-system.ruby.TCP_Controller.PrbShrData | 6 54.55% 54.55% | 5 45.45% 100.00%
-system.ruby.TCP_Controller.PrbShrData::total 11
-system.ruby.TCP_Controller.I.Load | 2 50.00% 50.00% | 2 50.00% 100.00%
-system.ruby.TCP_Controller.I.Load::total 4
-system.ruby.TCP_Controller.I.Store | 5 50.00% 50.00% | 5 50.00% 100.00%
-system.ruby.TCP_Controller.I.Store::total 10
-system.ruby.TCP_Controller.S.Load | 2 40.00% 40.00% | 3 60.00% 100.00%
-system.ruby.TCP_Controller.S.Load::total 5
-system.ruby.TCP_Controller.S.PrbInvData | 1 50.00% 50.00% | 1 50.00% 100.00%
-system.ruby.TCP_Controller.S.PrbInvData::total 2
-system.ruby.TCP_Controller.S.PrbShrData | 2 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.TCP_Controller.S.PrbShrData::total 2
-system.ruby.TCP_Controller.M.Store | 4 50.00% 50.00% | 4 50.00% 100.00%
-system.ruby.TCP_Controller.M.Store::total 8
-system.ruby.TCP_Controller.M.PrbInvData | 1 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.TCP_Controller.M.PrbInvData::total 1
-system.ruby.TCP_Controller.M.PrbShrData | 4 44.44% 44.44% | 5 55.56% 100.00%
-system.ruby.TCP_Controller.M.PrbShrData::total 9
-system.ruby.TCP_Controller.I_M.TCC_AckM | 5 50.00% 50.00% | 5 50.00% 100.00%
-system.ruby.TCP_Controller.I_M.TCC_AckM::total 10
-system.ruby.TCP_Controller.I_ES.TCC_AckS | 2 50.00% 50.00% | 2 50.00% 100.00%
-system.ruby.TCP_Controller.I_ES.TCC_AckS::total 4
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu0 cpu1 cpu2 dispatcher_coalescer dispatcher_tlb dvfs_handler l1_coalescer0 l1_coalescer1 l1_tlb0 l1_tlb1 l2_coalescer l2_tlb l3_coalescer l3_tlb mem_ctrls piobus ruby sqc_coalescer sqc_tlb sys_port_proxy voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:536870911
-memories=system.mem_ctrls system.ruby.phys_mem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.sys_port_proxy.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=TimingSimpleCPU
-children=apic_clk_domain clk_domain dtb interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu0.clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu0.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu0.tracer
-workload=system.cpu0.workload
-dcache_port=system.ruby.cp_cntrl0.sequencer.slave[1]
-icache_port=system.ruby.cp_cntrl0.sequencer.slave[0]
-
-[system.cpu0.apic_clk_domain]
-type=DerivedClockDomain
-clk_divider=16
-clk_domain=system.cpu0.clk_domain
-eventq_index=0
-
-[system.cpu0.clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0.dtb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu0.dtb.walker
-
-[system.cpu0.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu0.clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-port=system.ruby.cp_cntrl0.sequencer.slave[3]
-
-[system.cpu0.interrupts]
-type=X86LocalApic
-clk_domain=system.cpu0.apic_clk_domain
-eventq_index=0
-int_latency=1000
-pio_addr=2305843009213693952
-pio_latency=100000
-system=system
-int_master=system.ruby.cp_cntrl0.sequencer.slave[4]
-int_slave=system.ruby.cp_cntrl0.sequencer.master[1]
-pio=system.ruby.cp_cntrl0.sequencer.master[0]
-
-[system.cpu0.isa]
-type=X86ISA
-eventq_index=0
-
-[system.cpu0.itb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu0.itb.walker
-
-[system.cpu0.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu0.clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-port=system.ruby.cp_cntrl0.sequencer.slave[2]
-
-[system.cpu0.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu0.workload]
-type=LiveProcess
-cmd=gpu-hello
-cwd=
-drivers=system.cpu2.cl_driver
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello
-gid=100
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu1]
-type=Shader
-children=CUs0 CUs1 clk_domain
-CUs=system.cpu1.CUs0 system.cpu1.CUs1
-clk_domain=system.cpu1.clk_domain
-cpu_pointer=system.cpu0
-eventq_index=0
-globalmem=65536
-impl_kern_boundary_sync=true
-n_wf=8
-separate_acquire_release=false
-timing=true
-translation=false
-
-[system.cpu1.CUs0]
-type=ComputeUnit
-children=ldsBus localDataStore vector_register_file0 vector_register_file1 vector_register_file2 vector_register_file3 wavefronts00 wavefronts01 wavefronts02 wavefronts03 wavefronts04 wavefronts05 wavefronts06 wavefronts07 wavefronts08 wavefronts09 wavefronts10 wavefronts11 wavefronts12 wavefronts13 wavefronts14 wavefronts15 wavefronts16 wavefronts17 wavefronts18 wavefronts19 wavefronts20 wavefronts21 wavefronts22 wavefronts23 wavefronts24 wavefronts25 wavefronts26 wavefronts27 wavefronts28 wavefronts29 wavefronts30 wavefronts31
-clk_domain=system.cpu1.clk_domain
-coalescer_to_vrf_bus_width=32
-countPages=false
-cu_id=0
-debugSegFault=false
-dpbypass_pipe_length=4
-eventq_index=0
-execPolicy=OLDEST-FIRST
-functionalTLB=true
-global_mem_queue_size=256
-issue_period=4
-localDataStore=system.cpu1.CUs0.localDataStore
-localMemBarrier=false
-local_mem_queue_size=256
-mem_req_latency=9
-mem_resp_latency=9
-n_wf=8
-num_SIMDs=4
-num_global_mem_pipes=1
-num_shared_mem_pipes=1
-perLaneTLB=false
-prefetch_depth=0
-prefetch_prev_type=PF_PHASE
-prefetch_stride=1
-spbypass_pipe_length=4
-system=system
-vector_register_file=system.cpu1.CUs0.vector_register_file0 system.cpu1.CUs0.vector_register_file1 system.cpu1.CUs0.vector_register_file2 system.cpu1.CUs0.vector_register_file3
-vrf_to_coalescer_bus_width=32
-wavefronts=system.cpu1.CUs0.wavefronts00 system.cpu1.CUs0.wavefronts01 system.cpu1.CUs0.wavefronts02 system.cpu1.CUs0.wavefronts03 system.cpu1.CUs0.wavefronts04 system.cpu1.CUs0.wavefronts05 system.cpu1.CUs0.wavefronts06 system.cpu1.CUs0.wavefronts07 system.cpu1.CUs0.wavefronts08 system.cpu1.CUs0.wavefronts09 system.cpu1.CUs0.wavefronts10 system.cpu1.CUs0.wavefronts11 system.cpu1.CUs0.wavefronts12 system.cpu1.CUs0.wavefronts13 system.cpu1.CUs0.wavefronts14 system.cpu1.CUs0.wavefronts15 system.cpu1.CUs0.wavefronts16 system.cpu1.CUs0.wavefronts17 system.cpu1.CUs0.wavefronts18 system.cpu1.CUs0.wavefronts19 system.cpu1.CUs0.wavefronts20 system.cpu1.CUs0.wavefronts21 system.cpu1.CUs0.wavefronts22 system.cpu1.CUs0.wavefronts23 system.cpu1.CUs0.wavefronts24 system.cpu1.CUs0.wavefronts25 system.cpu1.CUs0.wavefronts26 system.cpu1.CUs0.wavefronts27 system.cpu1.CUs0.wavefronts28 system.cpu1.CUs0.wavefronts29 system.cpu1.CUs0.wavefronts30 system.cpu1.CUs0.wavefronts31
-wfSize=64
-xactCasMode=false
-ldsPort=system.cpu1.CUs0.ldsBus.slave
-memory_port=system.ruby.tcp_cntrl0.coalescer.slave[0] system.ruby.tcp_cntrl0.coalescer.slave[1] system.ruby.tcp_cntrl0.coalescer.slave[2] system.ruby.tcp_cntrl0.coalescer.slave[3] system.ruby.tcp_cntrl0.coalescer.slave[4] system.ruby.tcp_cntrl0.coalescer.slave[5] system.ruby.tcp_cntrl0.coalescer.slave[6] system.ruby.tcp_cntrl0.coalescer.slave[7] system.ruby.tcp_cntrl0.coalescer.slave[8] system.ruby.tcp_cntrl0.coalescer.slave[9] system.ruby.tcp_cntrl0.coalescer.slave[10] system.ruby.tcp_cntrl0.coalescer.slave[11] system.ruby.tcp_cntrl0.coalescer.slave[12] system.ruby.tcp_cntrl0.coalescer.slave[13] system.ruby.tcp_cntrl0.coalescer.slave[14] system.ruby.tcp_cntrl0.coalescer.slave[15] system.ruby.tcp_cntrl0.coalescer.slave[16] system.ruby.tcp_cntrl0.coalescer.slave[17] system.ruby.tcp_cntrl0.coalescer.slave[18] system.ruby.tcp_cntrl0.coalescer.slave[19] system.ruby.tcp_cntrl0.coalescer.slave[20] system.ruby.tcp_cntrl0.coalescer.slave[21] system.ruby.tcp_cntrl0.coalescer.slave[22] system.ruby.tcp_cntrl0.coalescer.slave[23] system.ruby.tcp_cntrl0.coalescer.slave[24] system.ruby.tcp_cntrl0.coalescer.slave[25] system.ruby.tcp_cntrl0.coalescer.slave[26] system.ruby.tcp_cntrl0.coalescer.slave[27] system.ruby.tcp_cntrl0.coalescer.slave[28] system.ruby.tcp_cntrl0.coalescer.slave[29] system.ruby.tcp_cntrl0.coalescer.slave[30] system.ruby.tcp_cntrl0.coalescer.slave[31] system.ruby.tcp_cntrl0.coalescer.slave[32] system.ruby.tcp_cntrl0.coalescer.slave[33] system.ruby.tcp_cntrl0.coalescer.slave[34] system.ruby.tcp_cntrl0.coalescer.slave[35] system.ruby.tcp_cntrl0.coalescer.slave[36] system.ruby.tcp_cntrl0.coalescer.slave[37] system.ruby.tcp_cntrl0.coalescer.slave[38] system.ruby.tcp_cntrl0.coalescer.slave[39] system.ruby.tcp_cntrl0.coalescer.slave[40] system.ruby.tcp_cntrl0.coalescer.slave[41] system.ruby.tcp_cntrl0.coalescer.slave[42] system.ruby.tcp_cntrl0.coalescer.slave[43] system.ruby.tcp_cntrl0.coalescer.slave[44] system.ruby.tcp_cntrl0.coalescer.slave[45] system.ruby.tcp_cntrl0.coalescer.slave[46] system.ruby.tcp_cntrl0.coalescer.slave[47] system.ruby.tcp_cntrl0.coalescer.slave[48] system.ruby.tcp_cntrl0.coalescer.slave[49] system.ruby.tcp_cntrl0.coalescer.slave[50] system.ruby.tcp_cntrl0.coalescer.slave[51] system.ruby.tcp_cntrl0.coalescer.slave[52] system.ruby.tcp_cntrl0.coalescer.slave[53] system.ruby.tcp_cntrl0.coalescer.slave[54] system.ruby.tcp_cntrl0.coalescer.slave[55] system.ruby.tcp_cntrl0.coalescer.slave[56] system.ruby.tcp_cntrl0.coalescer.slave[57] system.ruby.tcp_cntrl0.coalescer.slave[58] system.ruby.tcp_cntrl0.coalescer.slave[59] system.ruby.tcp_cntrl0.coalescer.slave[60] system.ruby.tcp_cntrl0.coalescer.slave[61] system.ruby.tcp_cntrl0.coalescer.slave[62] system.ruby.tcp_cntrl0.coalescer.slave[63]
-sqc_port=system.ruby.sqc_cntrl0.sequencer.slave[0]
-sqc_tlb_port=system.sqc_coalescer.slave[0]
-translation_port=system.l1_coalescer0.slave[0]
-
-[system.cpu1.CUs0.ldsBus]
-type=Bridge
-clk_domain=system.cpu1.clk_domain
-delay=0
-eventq_index=0
-ranges=0:18446744073709551615
-req_size=16
-resp_size=16
-master=system.cpu1.CUs0.localDataStore.cuPort
-slave=system.cpu1.CUs0.ldsPort
-
-[system.cpu1.CUs0.localDataStore]
-type=LdsState
-bankConflictPenalty=1
-banks=32
-clk_domain=system.cpu1.clk_domain
-eventq_index=0
-range=0:65535
-size=65536
-cuPort=system.cpu1.CUs0.ldsBus.master
-
-[system.cpu1.CUs0.vector_register_file0]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=0
-
-[system.cpu1.CUs0.vector_register_file1]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=1
-
-[system.cpu1.CUs0.vector_register_file2]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=2
-
-[system.cpu1.CUs0.vector_register_file3]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=3
-
-[system.cpu1.CUs0.wavefronts00]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=0
-
-[system.cpu1.CUs0.wavefronts01]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=1
-
-[system.cpu1.CUs0.wavefronts02]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=2
-
-[system.cpu1.CUs0.wavefronts03]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=3
-
-[system.cpu1.CUs0.wavefronts04]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=4
-
-[system.cpu1.CUs0.wavefronts05]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=5
-
-[system.cpu1.CUs0.wavefronts06]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=6
-
-[system.cpu1.CUs0.wavefronts07]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=7
-
-[system.cpu1.CUs0.wavefronts08]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=0
-
-[system.cpu1.CUs0.wavefronts09]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=1
-
-[system.cpu1.CUs0.wavefronts10]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=2
-
-[system.cpu1.CUs0.wavefronts11]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=3
-
-[system.cpu1.CUs0.wavefronts12]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=4
-
-[system.cpu1.CUs0.wavefronts13]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=5
-
-[system.cpu1.CUs0.wavefronts14]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=6
-
-[system.cpu1.CUs0.wavefronts15]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=7
-
-[system.cpu1.CUs0.wavefronts16]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=0
-
-[system.cpu1.CUs0.wavefronts17]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=1
-
-[system.cpu1.CUs0.wavefronts18]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=2
-
-[system.cpu1.CUs0.wavefronts19]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=3
-
-[system.cpu1.CUs0.wavefronts20]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=4
-
-[system.cpu1.CUs0.wavefronts21]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=5
-
-[system.cpu1.CUs0.wavefronts22]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=6
-
-[system.cpu1.CUs0.wavefronts23]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=7
-
-[system.cpu1.CUs0.wavefronts24]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=0
-
-[system.cpu1.CUs0.wavefronts25]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=1
-
-[system.cpu1.CUs0.wavefronts26]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=2
-
-[system.cpu1.CUs0.wavefronts27]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=3
-
-[system.cpu1.CUs0.wavefronts28]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=4
-
-[system.cpu1.CUs0.wavefronts29]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=5
-
-[system.cpu1.CUs0.wavefronts30]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=6
-
-[system.cpu1.CUs0.wavefronts31]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=7
-
-[system.cpu1.CUs1]
-type=ComputeUnit
-children=ldsBus localDataStore vector_register_file0 vector_register_file1 vector_register_file2 vector_register_file3 wavefronts00 wavefronts01 wavefronts02 wavefronts03 wavefronts04 wavefronts05 wavefronts06 wavefronts07 wavefronts08 wavefronts09 wavefronts10 wavefronts11 wavefronts12 wavefronts13 wavefronts14 wavefronts15 wavefronts16 wavefronts17 wavefronts18 wavefronts19 wavefronts20 wavefronts21 wavefronts22 wavefronts23 wavefronts24 wavefronts25 wavefronts26 wavefronts27 wavefronts28 wavefronts29 wavefronts30 wavefronts31
-clk_domain=system.cpu1.clk_domain
-coalescer_to_vrf_bus_width=32
-countPages=false
-cu_id=1
-debugSegFault=false
-dpbypass_pipe_length=4
-eventq_index=0
-execPolicy=OLDEST-FIRST
-functionalTLB=true
-global_mem_queue_size=256
-issue_period=4
-localDataStore=system.cpu1.CUs1.localDataStore
-localMemBarrier=false
-local_mem_queue_size=256
-mem_req_latency=9
-mem_resp_latency=9
-n_wf=8
-num_SIMDs=4
-num_global_mem_pipes=1
-num_shared_mem_pipes=1
-perLaneTLB=false
-prefetch_depth=0
-prefetch_prev_type=PF_PHASE
-prefetch_stride=1
-spbypass_pipe_length=4
-system=system
-vector_register_file=system.cpu1.CUs1.vector_register_file0 system.cpu1.CUs1.vector_register_file1 system.cpu1.CUs1.vector_register_file2 system.cpu1.CUs1.vector_register_file3
-vrf_to_coalescer_bus_width=32
-wavefronts=system.cpu1.CUs1.wavefronts00 system.cpu1.CUs1.wavefronts01 system.cpu1.CUs1.wavefronts02 system.cpu1.CUs1.wavefronts03 system.cpu1.CUs1.wavefronts04 system.cpu1.CUs1.wavefronts05 system.cpu1.CUs1.wavefronts06 system.cpu1.CUs1.wavefronts07 system.cpu1.CUs1.wavefronts08 system.cpu1.CUs1.wavefronts09 system.cpu1.CUs1.wavefronts10 system.cpu1.CUs1.wavefronts11 system.cpu1.CUs1.wavefronts12 system.cpu1.CUs1.wavefronts13 system.cpu1.CUs1.wavefronts14 system.cpu1.CUs1.wavefronts15 system.cpu1.CUs1.wavefronts16 system.cpu1.CUs1.wavefronts17 system.cpu1.CUs1.wavefronts18 system.cpu1.CUs1.wavefronts19 system.cpu1.CUs1.wavefronts20 system.cpu1.CUs1.wavefronts21 system.cpu1.CUs1.wavefronts22 system.cpu1.CUs1.wavefronts23 system.cpu1.CUs1.wavefronts24 system.cpu1.CUs1.wavefronts25 system.cpu1.CUs1.wavefronts26 system.cpu1.CUs1.wavefronts27 system.cpu1.CUs1.wavefronts28 system.cpu1.CUs1.wavefronts29 system.cpu1.CUs1.wavefronts30 system.cpu1.CUs1.wavefronts31
-wfSize=64
-xactCasMode=false
-ldsPort=system.cpu1.CUs1.ldsBus.slave
-memory_port=system.ruby.tcp_cntrl1.coalescer.slave[0] system.ruby.tcp_cntrl1.coalescer.slave[1] system.ruby.tcp_cntrl1.coalescer.slave[2] system.ruby.tcp_cntrl1.coalescer.slave[3] system.ruby.tcp_cntrl1.coalescer.slave[4] system.ruby.tcp_cntrl1.coalescer.slave[5] system.ruby.tcp_cntrl1.coalescer.slave[6] system.ruby.tcp_cntrl1.coalescer.slave[7] system.ruby.tcp_cntrl1.coalescer.slave[8] system.ruby.tcp_cntrl1.coalescer.slave[9] system.ruby.tcp_cntrl1.coalescer.slave[10] system.ruby.tcp_cntrl1.coalescer.slave[11] system.ruby.tcp_cntrl1.coalescer.slave[12] system.ruby.tcp_cntrl1.coalescer.slave[13] system.ruby.tcp_cntrl1.coalescer.slave[14] system.ruby.tcp_cntrl1.coalescer.slave[15] system.ruby.tcp_cntrl1.coalescer.slave[16] system.ruby.tcp_cntrl1.coalescer.slave[17] system.ruby.tcp_cntrl1.coalescer.slave[18] system.ruby.tcp_cntrl1.coalescer.slave[19] system.ruby.tcp_cntrl1.coalescer.slave[20] system.ruby.tcp_cntrl1.coalescer.slave[21] system.ruby.tcp_cntrl1.coalescer.slave[22] system.ruby.tcp_cntrl1.coalescer.slave[23] system.ruby.tcp_cntrl1.coalescer.slave[24] system.ruby.tcp_cntrl1.coalescer.slave[25] system.ruby.tcp_cntrl1.coalescer.slave[26] system.ruby.tcp_cntrl1.coalescer.slave[27] system.ruby.tcp_cntrl1.coalescer.slave[28] system.ruby.tcp_cntrl1.coalescer.slave[29] system.ruby.tcp_cntrl1.coalescer.slave[30] system.ruby.tcp_cntrl1.coalescer.slave[31] system.ruby.tcp_cntrl1.coalescer.slave[32] system.ruby.tcp_cntrl1.coalescer.slave[33] system.ruby.tcp_cntrl1.coalescer.slave[34] system.ruby.tcp_cntrl1.coalescer.slave[35] system.ruby.tcp_cntrl1.coalescer.slave[36] system.ruby.tcp_cntrl1.coalescer.slave[37] system.ruby.tcp_cntrl1.coalescer.slave[38] system.ruby.tcp_cntrl1.coalescer.slave[39] system.ruby.tcp_cntrl1.coalescer.slave[40] system.ruby.tcp_cntrl1.coalescer.slave[41] system.ruby.tcp_cntrl1.coalescer.slave[42] system.ruby.tcp_cntrl1.coalescer.slave[43] system.ruby.tcp_cntrl1.coalescer.slave[44] system.ruby.tcp_cntrl1.coalescer.slave[45] system.ruby.tcp_cntrl1.coalescer.slave[46] system.ruby.tcp_cntrl1.coalescer.slave[47] system.ruby.tcp_cntrl1.coalescer.slave[48] system.ruby.tcp_cntrl1.coalescer.slave[49] system.ruby.tcp_cntrl1.coalescer.slave[50] system.ruby.tcp_cntrl1.coalescer.slave[51] system.ruby.tcp_cntrl1.coalescer.slave[52] system.ruby.tcp_cntrl1.coalescer.slave[53] system.ruby.tcp_cntrl1.coalescer.slave[54] system.ruby.tcp_cntrl1.coalescer.slave[55] system.ruby.tcp_cntrl1.coalescer.slave[56] system.ruby.tcp_cntrl1.coalescer.slave[57] system.ruby.tcp_cntrl1.coalescer.slave[58] system.ruby.tcp_cntrl1.coalescer.slave[59] system.ruby.tcp_cntrl1.coalescer.slave[60] system.ruby.tcp_cntrl1.coalescer.slave[61] system.ruby.tcp_cntrl1.coalescer.slave[62] system.ruby.tcp_cntrl1.coalescer.slave[63]
-sqc_port=system.ruby.sqc_cntrl0.sequencer.slave[1]
-sqc_tlb_port=system.sqc_coalescer.slave[1]
-translation_port=system.l1_coalescer1.slave[0]
-
-[system.cpu1.CUs1.ldsBus]
-type=Bridge
-clk_domain=system.cpu1.clk_domain
-delay=0
-eventq_index=0
-ranges=0:18446744073709551615
-req_size=16
-resp_size=16
-master=system.cpu1.CUs1.localDataStore.cuPort
-slave=system.cpu1.CUs1.ldsPort
-
-[system.cpu1.CUs1.localDataStore]
-type=LdsState
-bankConflictPenalty=1
-banks=32
-clk_domain=system.cpu1.clk_domain
-eventq_index=0
-range=0:65535
-size=65536
-cuPort=system.cpu1.CUs1.ldsBus.master
-
-[system.cpu1.CUs1.vector_register_file0]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=0
-
-[system.cpu1.CUs1.vector_register_file1]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=1
-
-[system.cpu1.CUs1.vector_register_file2]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=2
-
-[system.cpu1.CUs1.vector_register_file3]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=3
-
-[system.cpu1.CUs1.wavefronts00]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=0
-
-[system.cpu1.CUs1.wavefronts01]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=1
-
-[system.cpu1.CUs1.wavefronts02]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=2
-
-[system.cpu1.CUs1.wavefronts03]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=3
-
-[system.cpu1.CUs1.wavefronts04]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=4
-
-[system.cpu1.CUs1.wavefronts05]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=5
-
-[system.cpu1.CUs1.wavefronts06]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=6
-
-[system.cpu1.CUs1.wavefronts07]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=7
-
-[system.cpu1.CUs1.wavefronts08]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=0
-
-[system.cpu1.CUs1.wavefronts09]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=1
-
-[system.cpu1.CUs1.wavefronts10]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=2
-
-[system.cpu1.CUs1.wavefronts11]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=3
-
-[system.cpu1.CUs1.wavefronts12]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=4
-
-[system.cpu1.CUs1.wavefronts13]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=5
-
-[system.cpu1.CUs1.wavefronts14]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=6
-
-[system.cpu1.CUs1.wavefronts15]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=7
-
-[system.cpu1.CUs1.wavefronts16]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=0
-
-[system.cpu1.CUs1.wavefronts17]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=1
-
-[system.cpu1.CUs1.wavefronts18]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=2
-
-[system.cpu1.CUs1.wavefronts19]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=3
-
-[system.cpu1.CUs1.wavefronts20]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=4
-
-[system.cpu1.CUs1.wavefronts21]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=5
-
-[system.cpu1.CUs1.wavefronts22]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=6
-
-[system.cpu1.CUs1.wavefronts23]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=7
-
-[system.cpu1.CUs1.wavefronts24]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=0
-
-[system.cpu1.CUs1.wavefronts25]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=1
-
-[system.cpu1.CUs1.wavefronts26]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=2
-
-[system.cpu1.CUs1.wavefronts27]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=3
-
-[system.cpu1.CUs1.wavefronts28]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=4
-
-[system.cpu1.CUs1.wavefronts29]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=5
-
-[system.cpu1.CUs1.wavefronts30]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=6
-
-[system.cpu1.CUs1.wavefronts31]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=7
-
-[system.cpu1.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.cpu1.clk_domain.voltage_domain
-
-[system.cpu1.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.cpu2]
-type=GpuDispatcher
-children=cl_driver
-cl_driver=system.cpu2.cl_driver
-clk_domain=system.clk_domain
-cpu=system.cpu0
-eventq_index=0
-pio_addr=8589934592
-pio_latency=1000
-shader_pointer=system.cpu1
-system=system
-dma=system.piobus.slave[1]
-pio=system.piobus.master[0]
-translation_port=system.dispatcher_coalescer.slave[0]
-
-[system.cpu2.cl_driver]
-type=ClDriver
-codefile=/dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm
-eventq_index=0
-filename=hsa
-
-[system.dispatcher_coalescer]
-type=TLBCoalescer
-children=clk_domain
-clk_domain=system.dispatcher_coalescer.clk_domain
-coalescingWindow=1
-disableCoalescing=false
-eventq_index=0
-probesPerCycle=2
-master=system.dispatcher_tlb.slave[0]
-slave=system.cpu2.translation_port
-
-[system.dispatcher_coalescer.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.dispatcher_coalescer.clk_domain.voltage_domain
-
-[system.dispatcher_coalescer.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.dispatcher_tlb]
-type=X86GPUTLB
-children=clk_domain
-accessDistance=false
-allocationPolicy=true
-assoc=32
-clk_domain=system.dispatcher_tlb.clk_domain
-eventq_index=0
-hitLatency=1
-maxOutstandingReqs=64
-missLatency1=5
-missLatency2=750
-size=32
-master=system.l2_coalescer.slave[1]
-slave=system.dispatcher_coalescer.master[0]
-
-[system.dispatcher_tlb.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.dispatcher_tlb.clk_domain.voltage_domain
-
-[system.dispatcher_tlb.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.l1_coalescer0]
-type=TLBCoalescer
-children=clk_domain
-clk_domain=system.l1_coalescer0.clk_domain
-coalescingWindow=1
-disableCoalescing=false
-eventq_index=0
-probesPerCycle=2
-master=system.l1_tlb0.slave[0]
-slave=system.cpu1.CUs0.translation_port[0]
-
-[system.l1_coalescer0.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l1_coalescer0.clk_domain.voltage_domain
-
-[system.l1_coalescer0.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l1_coalescer1]
-type=TLBCoalescer
-children=clk_domain
-clk_domain=system.l1_coalescer1.clk_domain
-coalescingWindow=1
-disableCoalescing=false
-eventq_index=0
-probesPerCycle=2
-master=system.l1_tlb1.slave[0]
-slave=system.cpu1.CUs1.translation_port[0]
-
-[system.l1_coalescer1.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l1_coalescer1.clk_domain.voltage_domain
-
-[system.l1_coalescer1.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l1_tlb0]
-type=X86GPUTLB
-children=clk_domain
-accessDistance=false
-allocationPolicy=true
-assoc=32
-clk_domain=system.l1_tlb0.clk_domain
-eventq_index=0
-hitLatency=1
-maxOutstandingReqs=64
-missLatency1=5
-missLatency2=750
-size=32
-master=system.l2_coalescer.slave[2]
-slave=system.l1_coalescer0.master[0]
-
-[system.l1_tlb0.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l1_tlb0.clk_domain.voltage_domain
-
-[system.l1_tlb0.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l1_tlb1]
-type=X86GPUTLB
-children=clk_domain
-accessDistance=false
-allocationPolicy=true
-assoc=32
-clk_domain=system.l1_tlb1.clk_domain
-eventq_index=0
-hitLatency=1
-maxOutstandingReqs=64
-missLatency1=5
-missLatency2=750
-size=32
-master=system.l2_coalescer.slave[3]
-slave=system.l1_coalescer1.master[0]
-
-[system.l1_tlb1.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l1_tlb1.clk_domain.voltage_domain
-
-[system.l1_tlb1.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l2_coalescer]
-type=TLBCoalescer
-children=clk_domain
-clk_domain=system.l2_coalescer.clk_domain
-coalescingWindow=1
-disableCoalescing=false
-eventq_index=0
-probesPerCycle=2
-master=system.l2_tlb.slave[0]
-slave=system.sqc_tlb.master[0] system.dispatcher_tlb.master[0] system.l1_tlb0.master[0] system.l1_tlb1.master[0]
-
-[system.l2_coalescer.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l2_coalescer.clk_domain.voltage_domain
-
-[system.l2_coalescer.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l2_tlb]
-type=X86GPUTLB
-children=clk_domain
-accessDistance=false
-allocationPolicy=true
-assoc=32
-clk_domain=system.l2_tlb.clk_domain
-eventq_index=0
-hitLatency=69
-maxOutstandingReqs=64
-missLatency1=5
-missLatency2=750
-size=4096
-master=system.l3_coalescer.slave[0]
-slave=system.l2_coalescer.master[0]
-
-[system.l2_tlb.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l2_tlb.clk_domain.voltage_domain
-
-[system.l2_tlb.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l3_coalescer]
-type=TLBCoalescer
-children=clk_domain
-clk_domain=system.l3_coalescer.clk_domain
-coalescingWindow=1
-disableCoalescing=false
-eventq_index=0
-probesPerCycle=2
-master=system.l3_tlb.slave[0]
-slave=system.l2_tlb.master[0]
-
-[system.l3_coalescer.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l3_coalescer.clk_domain.voltage_domain
-
-[system.l3_coalescer.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l3_tlb]
-type=X86GPUTLB
-children=clk_domain
-accessDistance=false
-allocationPolicy=true
-assoc=32
-clk_domain=system.l3_tlb.clk_domain
-eventq_index=0
-hitLatency=150
-maxOutstandingReqs=64
-missLatency1=5
-missLatency2=750
-size=8192
-slave=system.l3_coalescer.master[0]
-
-[system.l3_tlb.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l3_tlb.clk_domain.voltage_domain
-
-[system.l3_tlb.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.mem_ctrls]
-type=DRAMCtrl
-IDD0=0.075000
-IDD02=0.000000
-IDD2N=0.050000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.000000
-IDD2P12=0.000000
-IDD3N=0.057000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.000000
-IDD3P12=0.000000
-IDD4R=0.187000
-IDD4R2=0.000000
-IDD4W=0.165000
-IDD4W2=0.000000
-IDD5=0.220000
-IDD52=0.000000
-IDD6=0.000000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-page_policy=open_adaptive
-range=0:536870911
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=0
-tXPDLL=0
-tXS=0
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.ruby.dir_cntrl0.memory
-
-[system.piobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-forward_latency=0
-frontend_latency=0
-response_latency=0
-use_default_range=false
-width=32
-master=system.cpu2.pio
-slave=system.ruby.cp_cntrl0.sequencer.mem_master_port system.cpu2.dma
-
-[system.ruby]
-type=RubySystem
-children=clk_domain cp_cntrl0 dir_cntrl0 network phys_mem sqc_cntrl0 tcc_cntrl0 tcp_cntrl0 tcp_cntrl1
-access_backing_store=true
-all_instructions=false
-block_size_bytes=64
-clk_domain=system.ruby.clk_domain
-eventq_index=0
-hot_lines=false
-memory_size_bits=48
-num_of_sequencers=5
-number_of_virtual_networks=10
-phys_mem=system.ruby.phys_mem
-randomization=false
-
-[system.ruby.clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.ruby.cp_cntrl0]
-type=CorePair_Controller
-children=L1D0cache L1D1cache L1Icache L2cache mandatoryQueue probeToCore requestFromCore responseFromCore responseToCore sequencer sequencer1 triggerQueue unblockFromCore
-L1D0cache=system.ruby.cp_cntrl0.L1D0cache
-L1D1cache=system.ruby.cp_cntrl0.L1D1cache
-L1Icache=system.ruby.cp_cntrl0.L1Icache
-L2cache=system.ruby.cp_cntrl0.L2cache
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-eventq_index=0
-issue_latency=120
-l2_hit_latency=18
-mandatoryQueue=system.ruby.cp_cntrl0.mandatoryQueue
-number_of_TBEs=256
-probeToCore=system.ruby.cp_cntrl0.probeToCore
-recycle_latency=10
-requestFromCore=system.ruby.cp_cntrl0.requestFromCore
-responseFromCore=system.ruby.cp_cntrl0.responseFromCore
-responseToCore=system.ruby.cp_cntrl0.responseToCore
-ruby_system=system.ruby
-send_evictions=true
-sequencer=system.ruby.cp_cntrl0.sequencer
-sequencer1=system.ruby.cp_cntrl0.sequencer1
-system=system
-transitions_per_cycle=32
-triggerQueue=system.ruby.cp_cntrl0.triggerQueue
-unblockFromCore=system.ruby.cp_cntrl0.unblockFromCore
-version=0
-
-[system.ruby.cp_cntrl0.L1D0cache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=2
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.cp_cntrl0.L1D0cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=65536
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=2
-
-[system.ruby.cp_cntrl0.L1D0cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=65536
-
-[system.ruby.cp_cntrl0.L1D1cache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=2
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.cp_cntrl0.L1D1cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=65536
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=2
-
-[system.ruby.cp_cntrl0.L1D1cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=65536
-
-[system.ruby.cp_cntrl0.L1Icache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=2
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.cp_cntrl0.L1Icache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=32768
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=2
-
-[system.ruby.cp_cntrl0.L1Icache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=32768
-
-[system.ruby.cp_cntrl0.L2cache]
-type=RubyCache
-children=replacement_policy
-assoc=8
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=16
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.cp_cntrl0.L2cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=2097152
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=16
-
-[system.ruby.cp_cntrl0.L2cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=8
-block_size=64
-eventq_index=0
-size=2097152
-
-[system.ruby.cp_cntrl0.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.cp_cntrl0.probeToCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[3]
-
-[system.ruby.cp_cntrl0.requestFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[2]
-
-[system.ruby.cp_cntrl0.responseFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[3]
-
-[system.ruby.cp_cntrl0.responseToCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[4]
-
-[system.ruby.cp_cntrl0.sequencer]
-type=RubySequencer
-clk_domain=system.ruby.clk_domain
-coreid=0
-dcache=system.ruby.cp_cntrl0.L1D0cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-eventq_index=0
-icache=system.ruby.cp_cntrl0.L1Icache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=0
-master=system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave
-mem_master_port=system.piobus.slave[0]
-slave=system.cpu0.icache_port system.cpu0.dcache_port system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.interrupts.int_master
-
-[system.ruby.cp_cntrl0.sequencer1]
-type=RubySequencer
-clk_domain=system.ruby.clk_domain
-coreid=1
-dcache=system.ruby.cp_cntrl0.L1D1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-eventq_index=0
-icache=system.ruby.cp_cntrl0.L1Icache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=1
-
-[system.ruby.cp_cntrl0.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.cp_cntrl0.unblockFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[4]
-
-[system.ruby.dir_cntrl0]
-type=Directory_Controller
-children=L3CacheMemory L3triggerQueue directory probeToCore requestFromCores responseFromCores responseFromMemory responseToCore triggerQueue unblockFromCores
-CPUonly=false
-L3CacheMemory=system.ruby.dir_cntrl0.L3CacheMemory
-L3triggerQueue=system.ruby.dir_cntrl0.L3triggerQueue
-TCC_select_num_bits=0
-buffer_size=0
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-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers23]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers24]
-type=MessageBuffer
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-eventq_index=0
-ordered=true
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-
-[system.ruby.network.int_link_buffers25]
-type=MessageBuffer
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-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers26]
-type=MessageBuffer
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-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers27]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers28]
-type=MessageBuffer
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-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers29]
-type=MessageBuffer
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-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers30]
-type=MessageBuffer
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-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers31]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers32]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers33]
-type=MessageBuffer
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-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers34]
-type=MessageBuffer
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-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers35]
-type=MessageBuffer
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-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers36]
-type=MessageBuffer
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-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers37]
-type=MessageBuffer
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-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers38]
-type=MessageBuffer
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-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers39]
-type=MessageBuffer
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-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_links0]
-type=SimpleIntLink
-bandwidth_factor=8
-eventq_index=0
-latency=1
-link_id=0
-node_a=system.ruby.network.ext_links0.int_node
-node_b=system.ruby.network.ext_links1.int_node
-weight=1
-
-[system.ruby.network.int_links1]
-type=SimpleIntLink
-bandwidth_factor=8
-eventq_index=0
-latency=1
-link_id=1
-node_a=system.ruby.network.ext_links0.int_node
-node_b=system.ruby.network.ext_links2.int_node
-weight=1
-
-[system.ruby.phys_mem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.ruby.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=false
-latency=30000
-latency_var=0
-null=false
-range=0:536870911
-
-[system.ruby.sqc_cntrl0]
-type=SQC_Controller
-children=L1cache mandatoryQueue probeToSQC requestFromSQC responseToSQC sequencer
-L1cache=system.ruby.sqc_cntrl0.L1cache
-TCC_select_num_bits=0
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-eventq_index=0
-issue_latency=80
-l2_hit_latency=18
-mandatoryQueue=system.ruby.sqc_cntrl0.mandatoryQueue
-number_of_TBEs=256
-probeToSQC=system.ruby.sqc_cntrl0.probeToSQC
-recycle_latency=10
-requestFromSQC=system.ruby.sqc_cntrl0.requestFromSQC
-responseToSQC=system.ruby.sqc_cntrl0.responseToSQC
-ruby_system=system.ruby
-sequencer=system.ruby.sqc_cntrl0.sequencer
-system=system
-transitions_per_cycle=32
-version=0
-
-[system.ruby.sqc_cntrl0.L1cache]
-type=RubyCache
-children=replacement_policy
-assoc=8
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=8
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.sqc_cntrl0.L1cache.replacement_policy
-resourceStalls=true
-ruby_system=system.ruby
-size=32768
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=8
-
-[system.ruby.sqc_cntrl0.L1cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
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-block_size=64
-eventq_index=0
-size=32768
-
-[system.ruby.sqc_cntrl0.mandatoryQueue]
-type=MessageBuffer
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-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.sqc_cntrl0.probeToSQC]
-type=MessageBuffer
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-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[9]
-
-[system.ruby.sqc_cntrl0.requestFromSQC]
-type=MessageBuffer
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-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[11]
-
-[system.ruby.sqc_cntrl0.responseToSQC]
-type=MessageBuffer
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-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[10]
-
-[system.ruby.sqc_cntrl0.sequencer]
-type=RubySequencer
-clk_domain=system.ruby.clk_domain
-coreid=99
-dcache=system.ruby.sqc_cntrl0.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-eventq_index=0
-icache=system.ruby.sqc_cntrl0.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=false
-max_outstanding_requests=16
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=false
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=6
-slave=system.cpu1.CUs0.sqc_port system.cpu1.CUs1.sqc_port
-
-[system.ruby.tcc_cntrl0]
-type=TCC_Controller
-children=L2cache probeFromNB requestFromTCP requestToNB responseFromNB responseToCore responseToNB triggerQueue unblockToNB
-L2cache=system.ruby.tcc_cntrl0.L2cache
-WB=false
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-eventq_index=0
-l2_request_latency=120
-l2_response_latency=16
-number_of_TBEs=5120
-probeFromNB=system.ruby.tcc_cntrl0.probeFromNB
-recycle_latency=10
-requestFromTCP=system.ruby.tcc_cntrl0.requestFromTCP
-requestToNB=system.ruby.tcc_cntrl0.requestToNB
-responseFromNB=system.ruby.tcc_cntrl0.responseFromNB
-responseToCore=system.ruby.tcc_cntrl0.responseToCore
-responseToNB=system.ruby.tcc_cntrl0.responseToNB
-ruby_system=system.ruby
-system=system
-transitions_per_cycle=32
-triggerQueue=system.ruby.tcc_cntrl0.triggerQueue
-unblockToNB=system.ruby.tcc_cntrl0.unblockToNB
-version=0
-
-[system.ruby.tcc_cntrl0.L2cache]
-type=RubyCache
-children=replacement_policy
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-block_size=0
-dataAccessLatency=8
-dataArrayBanks=256
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.tcc_cntrl0.L2cache.replacement_policy
-resourceStalls=true
-ruby_system=system.ruby
-size=262144
-start_index_bit=6
-tagAccessLatency=2
-tagArrayBanks=256
-
-[system.ruby.tcc_cntrl0.L2cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
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-block_size=64
-eventq_index=0
-size=262144
-
-[system.ruby.tcc_cntrl0.probeFromNB]
-type=MessageBuffer
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-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[12]
-
-[system.ruby.tcc_cntrl0.requestFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[11]
-
-[system.ruby.tcc_cntrl0.requestToNB]
-type=MessageBuffer
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-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[13]
-
-[system.ruby.tcc_cntrl0.responseFromNB]
-type=MessageBuffer
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-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[13]
-
-[system.ruby.tcc_cntrl0.responseToCore]
-type=MessageBuffer
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-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[12]
-
-[system.ruby.tcc_cntrl0.responseToNB]
-type=MessageBuffer
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-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[14]
-
-[system.ruby.tcc_cntrl0.triggerQueue]
-type=MessageBuffer
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-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.tcc_cntrl0.unblockToNB]
-type=MessageBuffer
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-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[15]
-
-[system.ruby.tcp_cntrl0]
-type=TCP_Controller
-children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore
-L1cache=system.ruby.tcp_cntrl0.L1cache
-TCC_select_num_bits=0
-WB=false
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-coalescer=system.ruby.tcp_cntrl0.coalescer
-disableL1=false
-eventq_index=0
-issue_latency=1
-l2_hit_latency=18
-mandatoryQueue=system.ruby.tcp_cntrl0.mandatoryQueue
-number_of_TBEs=2560
-probeToTCP=system.ruby.tcp_cntrl0.probeToTCP
-recycle_latency=10
-requestFromTCP=system.ruby.tcp_cntrl0.requestFromTCP
-responseFromTCP=system.ruby.tcp_cntrl0.responseFromTCP
-responseToTCP=system.ruby.tcp_cntrl0.responseToTCP
-ruby_system=system.ruby
-sequencer=system.ruby.tcp_cntrl0.sequencer
-system=system
-transitions_per_cycle=32
-unblockFromCore=system.ruby.tcp_cntrl0.unblockFromCore
-use_seq_not_coal=false
-version=0
-
-[system.ruby.tcp_cntrl0.L1cache]
-type=RubyCache
-children=replacement_policy
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-block_size=0
-dataAccessLatency=4
-dataArrayBanks=16
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.tcp_cntrl0.L1cache.replacement_policy
-resourceStalls=true
-ruby_system=system.ruby
-size=16384
-start_index_bit=6
-tagAccessLatency=4
-tagArrayBanks=16
-
-[system.ruby.tcp_cntrl0.L1cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
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-block_size=64
-eventq_index=0
-size=16384
-
-[system.ruby.tcp_cntrl0.coalescer]
-type=VIPERCoalescer
-assume_rfo=false
-clk_domain=system.ruby.clk_domain
-coreid=99
-dcache=system.ruby.tcp_cntrl0.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-eventq_index=0
-icache=system.ruby.tcp_cntrl0.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=false
-max_inv_per_cycle=32
-max_outstanding_requests=2560
-max_wb_per_cycle=32
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=false
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=2
-slave=system.cpu1.CUs0.memory_port[0] system.cpu1.CUs0.memory_port[1] system.cpu1.CUs0.memory_port[2] system.cpu1.CUs0.memory_port[3] system.cpu1.CUs0.memory_port[4] system.cpu1.CUs0.memory_port[5] system.cpu1.CUs0.memory_port[6] system.cpu1.CUs0.memory_port[7] system.cpu1.CUs0.memory_port[8] system.cpu1.CUs0.memory_port[9] system.cpu1.CUs0.memory_port[10] system.cpu1.CUs0.memory_port[11] system.cpu1.CUs0.memory_port[12] system.cpu1.CUs0.memory_port[13] system.cpu1.CUs0.memory_port[14] system.cpu1.CUs0.memory_port[15] system.cpu1.CUs0.memory_port[16] system.cpu1.CUs0.memory_port[17] system.cpu1.CUs0.memory_port[18] system.cpu1.CUs0.memory_port[19] system.cpu1.CUs0.memory_port[20] system.cpu1.CUs0.memory_port[21] system.cpu1.CUs0.memory_port[22] system.cpu1.CUs0.memory_port[23] system.cpu1.CUs0.memory_port[24] system.cpu1.CUs0.memory_port[25] system.cpu1.CUs0.memory_port[26] system.cpu1.CUs0.memory_port[27] system.cpu1.CUs0.memory_port[28] system.cpu1.CUs0.memory_port[29] system.cpu1.CUs0.memory_port[30] system.cpu1.CUs0.memory_port[31] system.cpu1.CUs0.memory_port[32] system.cpu1.CUs0.memory_port[33] system.cpu1.CUs0.memory_port[34] system.cpu1.CUs0.memory_port[35] system.cpu1.CUs0.memory_port[36] system.cpu1.CUs0.memory_port[37] system.cpu1.CUs0.memory_port[38] system.cpu1.CUs0.memory_port[39] system.cpu1.CUs0.memory_port[40] system.cpu1.CUs0.memory_port[41] system.cpu1.CUs0.memory_port[42] system.cpu1.CUs0.memory_port[43] system.cpu1.CUs0.memory_port[44] system.cpu1.CUs0.memory_port[45] system.cpu1.CUs0.memory_port[46] system.cpu1.CUs0.memory_port[47] system.cpu1.CUs0.memory_port[48] system.cpu1.CUs0.memory_port[49] system.cpu1.CUs0.memory_port[50] system.cpu1.CUs0.memory_port[51] system.cpu1.CUs0.memory_port[52] system.cpu1.CUs0.memory_port[53] system.cpu1.CUs0.memory_port[54] system.cpu1.CUs0.memory_port[55] system.cpu1.CUs0.memory_port[56] system.cpu1.CUs0.memory_port[57] system.cpu1.CUs0.memory_port[58] system.cpu1.CUs0.memory_port[59] system.cpu1.CUs0.memory_port[60] system.cpu1.CUs0.memory_port[61] system.cpu1.CUs0.memory_port[62] system.cpu1.CUs0.memory_port[63]
-
-[system.ruby.tcp_cntrl0.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.tcp_cntrl0.probeToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[5]
-
-[system.ruby.tcp_cntrl0.requestFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[5]
-
-[system.ruby.tcp_cntrl0.responseFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[6]
-
-[system.ruby.tcp_cntrl0.responseToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[6]
-
-[system.ruby.tcp_cntrl0.sequencer]
-type=RubySequencer
-clk_domain=system.ruby.clk_domain
-coreid=99
-dcache=system.ruby.tcp_cntrl0.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-eventq_index=0
-icache=system.ruby.tcp_cntrl0.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=3
-
-[system.ruby.tcp_cntrl0.unblockFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[7]
-
-[system.ruby.tcp_cntrl1]
-type=TCP_Controller
-children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore
-L1cache=system.ruby.tcp_cntrl1.L1cache
-TCC_select_num_bits=0
-WB=false
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-coalescer=system.ruby.tcp_cntrl1.coalescer
-disableL1=false
-eventq_index=0
-issue_latency=1
-l2_hit_latency=18
-mandatoryQueue=system.ruby.tcp_cntrl1.mandatoryQueue
-number_of_TBEs=2560
-probeToTCP=system.ruby.tcp_cntrl1.probeToTCP
-recycle_latency=10
-requestFromTCP=system.ruby.tcp_cntrl1.requestFromTCP
-responseFromTCP=system.ruby.tcp_cntrl1.responseFromTCP
-responseToTCP=system.ruby.tcp_cntrl1.responseToTCP
-ruby_system=system.ruby
-sequencer=system.ruby.tcp_cntrl1.sequencer
-system=system
-transitions_per_cycle=32
-unblockFromCore=system.ruby.tcp_cntrl1.unblockFromCore
-use_seq_not_coal=false
-version=1
-
-[system.ruby.tcp_cntrl1.L1cache]
-type=RubyCache
-children=replacement_policy
-assoc=16
-block_size=0
-dataAccessLatency=4
-dataArrayBanks=16
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.tcp_cntrl1.L1cache.replacement_policy
-resourceStalls=true
-ruby_system=system.ruby
-size=16384
-start_index_bit=6
-tagAccessLatency=4
-tagArrayBanks=16
-
-[system.ruby.tcp_cntrl1.L1cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=16
-block_size=64
-eventq_index=0
-size=16384
-
-[system.ruby.tcp_cntrl1.coalescer]
-type=VIPERCoalescer
-assume_rfo=false
-clk_domain=system.ruby.clk_domain
-coreid=99
-dcache=system.ruby.tcp_cntrl1.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-eventq_index=0
-icache=system.ruby.tcp_cntrl1.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=false
-max_inv_per_cycle=32
-max_outstanding_requests=2560
-max_wb_per_cycle=32
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=false
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=4
-slave=system.cpu1.CUs1.memory_port[0] system.cpu1.CUs1.memory_port[1] system.cpu1.CUs1.memory_port[2] system.cpu1.CUs1.memory_port[3] system.cpu1.CUs1.memory_port[4] system.cpu1.CUs1.memory_port[5] system.cpu1.CUs1.memory_port[6] system.cpu1.CUs1.memory_port[7] system.cpu1.CUs1.memory_port[8] system.cpu1.CUs1.memory_port[9] system.cpu1.CUs1.memory_port[10] system.cpu1.CUs1.memory_port[11] system.cpu1.CUs1.memory_port[12] system.cpu1.CUs1.memory_port[13] system.cpu1.CUs1.memory_port[14] system.cpu1.CUs1.memory_port[15] system.cpu1.CUs1.memory_port[16] system.cpu1.CUs1.memory_port[17] system.cpu1.CUs1.memory_port[18] system.cpu1.CUs1.memory_port[19] system.cpu1.CUs1.memory_port[20] system.cpu1.CUs1.memory_port[21] system.cpu1.CUs1.memory_port[22] system.cpu1.CUs1.memory_port[23] system.cpu1.CUs1.memory_port[24] system.cpu1.CUs1.memory_port[25] system.cpu1.CUs1.memory_port[26] system.cpu1.CUs1.memory_port[27] system.cpu1.CUs1.memory_port[28] system.cpu1.CUs1.memory_port[29] system.cpu1.CUs1.memory_port[30] system.cpu1.CUs1.memory_port[31] system.cpu1.CUs1.memory_port[32] system.cpu1.CUs1.memory_port[33] system.cpu1.CUs1.memory_port[34] system.cpu1.CUs1.memory_port[35] system.cpu1.CUs1.memory_port[36] system.cpu1.CUs1.memory_port[37] system.cpu1.CUs1.memory_port[38] system.cpu1.CUs1.memory_port[39] system.cpu1.CUs1.memory_port[40] system.cpu1.CUs1.memory_port[41] system.cpu1.CUs1.memory_port[42] system.cpu1.CUs1.memory_port[43] system.cpu1.CUs1.memory_port[44] system.cpu1.CUs1.memory_port[45] system.cpu1.CUs1.memory_port[46] system.cpu1.CUs1.memory_port[47] system.cpu1.CUs1.memory_port[48] system.cpu1.CUs1.memory_port[49] system.cpu1.CUs1.memory_port[50] system.cpu1.CUs1.memory_port[51] system.cpu1.CUs1.memory_port[52] system.cpu1.CUs1.memory_port[53] system.cpu1.CUs1.memory_port[54] system.cpu1.CUs1.memory_port[55] system.cpu1.CUs1.memory_port[56] system.cpu1.CUs1.memory_port[57] system.cpu1.CUs1.memory_port[58] system.cpu1.CUs1.memory_port[59] system.cpu1.CUs1.memory_port[60] system.cpu1.CUs1.memory_port[61] system.cpu1.CUs1.memory_port[62] system.cpu1.CUs1.memory_port[63]
-
-[system.ruby.tcp_cntrl1.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.tcp_cntrl1.probeToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[7]
-
-[system.ruby.tcp_cntrl1.requestFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[8]
-
-[system.ruby.tcp_cntrl1.responseFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[9]
-
-[system.ruby.tcp_cntrl1.responseToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[8]
-
-[system.ruby.tcp_cntrl1.sequencer]
-type=RubySequencer
-clk_domain=system.ruby.clk_domain
-coreid=99
-dcache=system.ruby.tcp_cntrl1.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-eventq_index=0
-icache=system.ruby.tcp_cntrl1.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=5
-
-[system.ruby.tcp_cntrl1.unblockFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[10]
-
-[system.sqc_coalescer]
-type=TLBCoalescer
-children=clk_domain
-clk_domain=system.sqc_coalescer.clk_domain
-coalescingWindow=1
-disableCoalescing=false
-eventq_index=0
-probesPerCycle=2
-master=system.sqc_tlb.slave[0]
-slave=system.cpu1.CUs0.sqc_tlb_port system.cpu1.CUs1.sqc_tlb_port
-
-[system.sqc_coalescer.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.sqc_coalescer.clk_domain.voltage_domain
-
-[system.sqc_coalescer.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.sqc_tlb]
-type=X86GPUTLB
-children=clk_domain
-accessDistance=false
-allocationPolicy=true
-assoc=32
-clk_domain=system.sqc_tlb.clk_domain
-eventq_index=0
-hitLatency=1
-maxOutstandingReqs=64
-missLatency1=5
-missLatency2=750
-size=32
-master=system.l2_coalescer.slave[0]
-slave=system.sqc_coalescer.master[0]
-
-[system.sqc_tlb.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.sqc_tlb.clk_domain.voltage_domain
-
-[system.sqc_tlb.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.sys_port_proxy]
-type=RubyPortProxy
-clk_domain=system.clk_domain
-eventq_index=0
-is_cpu_sequencer=true
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=0
-slave=system.system_port
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: system.ruby.network adopting orphan SimObject param 'int_links'
-warn: system.ruby.network adopting orphan SimObject param 'ext_links'
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 19 2016 13:36:44
-gem5 started Jan 19 2016 13:37:09
-gem5 executing on zizzer, pid 49676
-command line: build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_VIPER -re /z/atgutier/gem5/gem5-commit/tests/run.py build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_VIPER
-
-Using GPU kernel code file(s) /dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm
-Global frequency set at 1000000000000 ticks per second
-Forcing maxCoalescedReqs to 32 (TLB assoc.)
-Forcing maxCoalescedReqs to 32 (TLB assoc.)
-Forcing maxCoalescedReqs to 32 (TLB assoc.)
-Forcing maxCoalescedReqs to 32 (TLB assoc.)
-Forcing maxCoalescedReqs to 32 (TLB assoc.)
-Forcing maxCoalescedReqs to 32 (TLB assoc.)
-info: Entering event queue @ 0. Starting simulation...
-keys = 0x7b2bc0, &keys = 0x798998, keys[0] = 23
-the gpu says:
-\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fe
-Exiting @ tick 314399500 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000314 # Number of seconds simulated
-sim_ticks 314399500 # Number of ticks simulated
-final_tick 314399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 59851 # Simulator instruction rate (inst/s)
-host_op_rate 123077 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 280996968 # Simulator tick rate (ticks/s)
-host_mem_usage 1296852 # Number of bytes of host memory used
-host_seconds 1.12 # Real time elapsed on the host
-sim_insts 66963 # Number of instructions simulated
-sim_ops 137705 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 99840 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 99840 # Number of bytes read from this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 1560 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 1560 # Number of read requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 317557757 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 317557757 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 317557757 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 317557757 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 1560 # Number of read requests accepted
-system.mem_ctrls.writeReqs 0 # Number of write requests accepted
-system.mem_ctrls.readBursts 1560 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 99840 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 99840 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 122 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 192 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 93 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 44 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 61 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 79 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 52 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 42 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8 54 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9 56 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 182 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11 90 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12 223 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 125 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 51 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 94 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
-system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
-system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 314257000 # Total gap between requests
-system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 1560 # Read request sizes (log2)
-system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 1544 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 3 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2 2 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3 2 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4 4 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5 3 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7 1 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 398 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 247.798995 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 164.777646 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 248.151006 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 138 34.67% 34.67% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 115 28.89% 63.57% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 55 13.82% 77.39% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 30 7.54% 84.92% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 19 4.77% 89.70% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 13 3.27% 92.96% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 7 1.76% 94.72% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 7 1.76% 96.48% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 14 3.52% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 398 # Bytes accessed per row activation
-system.mem_ctrls.totQLat 12586250 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 41836250 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 7800000 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 8068.11 # Average queueing delay per DRAM burst
-system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 26818.11 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 317.56 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 317.56 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
-system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 2.48 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 2.48 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 1.04 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 1157 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 74.17 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 201446.79 # Average gap between requests
-system.mem_ctrls.pageHitRate 74.17 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 1141560 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 622875 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 5335200 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 20342400 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 179243055 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 29795250 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 236480340 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 758.654968 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 51073000 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 10400000 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 252847000 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls_1.actEnergy 1867320 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 1018875 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 6684600 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 20342400 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 198048780 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 13299000 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 241260975 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 773.991771 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 20941500 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 10400000 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 280382250 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.ruby.clk_domain.clock 500 # Clock period in ticks
-system.ruby.phys_mem.bytes_read::cpu0.inst 696760 # Number of bytes read from this memory
-system.ruby.phys_mem.bytes_read::cpu0.data 119832 # Number of bytes read from this memory
-system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 3280 # Number of bytes read from this memory
-system.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit 3280 # Number of bytes read from this memory
-system.ruby.phys_mem.bytes_read::total 823152 # Number of bytes read from this memory
-system.ruby.phys_mem.bytes_inst_read::cpu0.inst 696760 # Number of instructions bytes read from this memory
-system.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit 2000 # Number of instructions bytes read from this memory
-system.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit 2000 # Number of instructions bytes read from this memory
-system.ruby.phys_mem.bytes_inst_read::total 700760 # Number of instructions bytes read from this memory
-system.ruby.phys_mem.bytes_written::cpu0.data 72767 # Number of bytes written to this memory
-system.ruby.phys_mem.bytes_written::cpu1.CUs0.ComputeUnit 256 # Number of bytes written to this memory
-system.ruby.phys_mem.bytes_written::cpu1.CUs1.ComputeUnit 256 # Number of bytes written to this memory
-system.ruby.phys_mem.bytes_written::total 73279 # Number of bytes written to this memory
-system.ruby.phys_mem.num_reads::cpu0.inst 87095 # Number of read requests responded to by this memory
-system.ruby.phys_mem.num_reads::cpu0.data 16686 # Number of read requests responded to by this memory
-system.ruby.phys_mem.num_reads::cpu1.CUs0.ComputeUnit 555 # Number of read requests responded to by this memory
-system.ruby.phys_mem.num_reads::cpu1.CUs1.ComputeUnit 555 # Number of read requests responded to by this memory
-system.ruby.phys_mem.num_reads::total 104891 # Number of read requests responded to by this memory
-system.ruby.phys_mem.num_writes::cpu0.data 10422 # Number of write requests responded to by this memory
-system.ruby.phys_mem.num_writes::cpu1.CUs0.ComputeUnit 256 # Number of write requests responded to by this memory
-system.ruby.phys_mem.num_writes::cpu1.CUs1.ComputeUnit 256 # Number of write requests responded to by this memory
-system.ruby.phys_mem.num_writes::total 10934 # Number of write requests responded to by this memory
-system.ruby.phys_mem.bw_read::cpu0.inst 2216161285 # Total read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_read::cpu0.data 381145644 # Total read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit 10432587 # Total read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit 10432587 # Total read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_read::total 2618172103 # Total read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_inst_read::cpu0.inst 2216161285 # Instruction read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit 6361333 # Instruction read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit 6361333 # Instruction read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_inst_read::total 2228883952 # Instruction read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_write::cpu0.data 231447569 # Write bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 814251 # Write bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 814251 # Write bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_write::total 233076070 # Write bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_total::cpu0.inst 2216161285 # Total bandwidth to/from this memory (bytes/s)
-system.ruby.phys_mem.bw_total::cpu0.data 612593213 # Total bandwidth to/from this memory (bytes/s)
-system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 11246837 # Total bandwidth to/from this memory (bytes/s)
-system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 11246837 # Total bandwidth to/from this memory (bytes/s)
-system.ruby.phys_mem.bw_total::total 2851248173 # Total bandwidth to/from this memory (bytes/s)
-system.cpu0.clk_domain.clock 500 # Clock period in ticks
-system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu0.workload.numSyscalls 21 # Number of system calls
-system.cpu0.numCycles 628799 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 66963 # Number of instructions committed
-system.cpu0.committedOps 137705 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 136380 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 1279 # Number of float alu accesses
-system.cpu0.num_func_calls 3196 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 12151 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 136380 # number of integer instructions
-system.cpu0.num_fp_insts 1279 # number of float instructions
-system.cpu0.num_int_register_reads 257490 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 110039 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 1981 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 981 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 78262 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 42183 # number of times the CC registers were written
-system.cpu0.num_mem_refs 27198 # number of memory refs
-system.cpu0.num_load_insts 16684 # Number of load instructions
-system.cpu0.num_store_insts 10514 # Number of store instructions
-system.cpu0.num_idle_cycles 8671.003972 # Number of idle cycles
-system.cpu0.num_busy_cycles 620127.996028 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.986210 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.013790 # Percentage of idle cycles
-system.cpu0.Branches 16199 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 615 0.45% 0.45% # Class of executed instruction
-system.cpu0.op_class::IntAlu 108791 79.00% 79.45% # Class of executed instruction
-system.cpu0.op_class::IntMult 13 0.01% 79.46% # Class of executed instruction
-system.cpu0.op_class::IntDiv 138 0.10% 79.56% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 950 0.69% 80.25% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::MemRead 16684 12.12% 92.36% # Class of executed instruction
-system.cpu0.op_class::MemWrite 10514 7.64% 100.00% # Class of executed instruction
-system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 137705 # Class of executed instruction
-system.cpu1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.cpu1.clk_domain.clock 1000 # Clock period in ticks
-system.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 216 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::total 39 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts01.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts01.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts02.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts02.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts02.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts03.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts03.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts04.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts04.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts04.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts05.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts05.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts05.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts06.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts06.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts07.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts07.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts07.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 195 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 194 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 177 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 4663 # number of cycles the CU issues nothing
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 102 # number of cycles the CU issued at least one instruction
-system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 1993 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 288 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 325 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 248 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 341 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 27 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.spc::samples 4765 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::mean 0.029591 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::stdev 0.214321 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::0 4663 97.86% 97.86% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::1 65 1.36% 99.22% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::2 35 0.73% 99.96% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::3 2 0.04% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::total 4765 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 66 # number of CU transitions from active to idle
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 66 # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 61.575758 # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 253.572448 # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 45 68.18% 68.18% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 10 15.15% 83.33% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 83.33% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 1 1.52% 84.85% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 2 3.03% 87.88% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.52% 89.39% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 89.39% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 89.39% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 89.39% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 89.39% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 89.39% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 89.39% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 89.39% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 89.39% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 89.39% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 89.39% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 7 10.61% 100.00% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value 1685 # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 66 # duration of idle periods in cycles
-system.cpu1.CUs0.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF
-system.cpu1.CUs0.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF
-system.cpu1.CUs0.tlb_requests 769 # number of uncoalesced requests
-system.cpu1.CUs0.tlb_cycles -212991640500 # total number of cycles for all uncoalesced requests
-system.cpu1.CUs0.avg_translation_latency -276972224.317295 # Avg. translation latency for data translations
-system.cpu1.CUs0.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs0.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs0.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs0.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs0.lds_bank_access_cnt 54 # Total number of LDS bank accesses
-system.cpu1.CUs0.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::mean 8 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::stdev 6.196773 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::10-11 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::12-13 4 66.67% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.global_mem_instr_cnt 17 # dynamic global memory instructions count
-system.cpu1.CUs0.local_mem_instr_cnt 6 # dynamic local memory intruction count
-system.cpu1.CUs0.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity
-system.cpu1.CUs0.num_instr_executed 141 # number of instructions executed
-system.cpu1.CUs0.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::mean 81.602837 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::stdev 244.924445 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::0-1 1 0.71% 0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::4-5 57 40.43% 49.65% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::6-7 28 19.86% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::8-9 2 1.42% 70.92% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::10 1 0.71% 71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::overflows 40 28.37% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::min_value 1 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::max_value 1686 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.num_vec_ops_executed 6769 # number of vec ops executed (e.g. VSZ/inst)
-system.cpu1.CUs0.num_total_cycles 4765 # number of cycles the CU ran for
-system.cpu1.CUs0.vpc 1.420567 # Vector Operations per cycle (this CU only)
-system.cpu1.CUs0.ipc 0.029591 # Instructions per cycle (this CU only)
-system.cpu1.CUs0.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::mean 48.007092 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::stdev 23.719942 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::9-12 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::13-16 36 25.53% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::mean 37.833333 # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::stdev 27.064737 # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::9-12 0 0.00% 5.56% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::13-16 8 44.44% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::mean 19.500000 # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::stdev 22.322634 # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::9-12 0 0.00% 16.67% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::13-16 4 66.67% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction
-system.cpu1.CUs0.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed
-system.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD
-system.cpu1.CUs0.num_CAS_ops 0 # number of compare and swap operations
-system.cpu1.CUs0.num_failed_CAS_ops 0 # number of compare and swap operations that failed
-system.cpu1.CUs0.num_completed_wfs 4 # number of completed wavefronts
-system.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 216 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::total 39 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts01.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts01.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts02.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts02.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts03.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts03.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts04.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts04.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts05.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts05.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts06.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts06.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts07.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts07.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 195 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 190 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 176 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 4667 # number of cycles the CU issues nothing
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 98 # number of cycles the CU issued at least one instruction
-system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 2052 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 327 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 265 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 285 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 341 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 32 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.spc::samples 4765 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::mean 0.029591 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::stdev 0.218204 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::0 4667 97.94% 97.94% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::1 57 1.20% 99.14% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::2 39 0.82% 99.96% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::3 2 0.04% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::total 4765 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 68 # number of CU transitions from active to idle
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 68 # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 61 # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 257.808908 # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 49 72.06% 72.06% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 8 11.76% 83.82% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 83.82% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 2 2.94% 86.76% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 1 1.47% 88.24% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 1 1.47% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 7 10.29% 100.00% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value 1764 # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 68 # duration of idle periods in cycles
-system.cpu1.CUs1.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF
-system.cpu1.CUs1.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF
-system.cpu1.CUs1.tlb_requests 769 # number of uncoalesced requests
-system.cpu1.CUs1.tlb_cycles -212991830500 # total number of cycles for all uncoalesced requests
-system.cpu1.CUs1.avg_translation_latency -276972471.391417 # Avg. translation latency for data translations
-system.cpu1.CUs1.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs1.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs1.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs1.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs1.lds_bank_access_cnt 53 # Total number of LDS bank accesses
-system.cpu1.CUs1.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::mean 7.833333 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::stdev 6.080022 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::10-11 1 16.67% 50.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::12-13 3 50.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.global_mem_instr_cnt 17 # dynamic global memory instructions count
-system.cpu1.CUs1.local_mem_instr_cnt 6 # dynamic local memory intruction count
-system.cpu1.CUs1.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity
-system.cpu1.CUs1.num_instr_executed 141 # number of instructions executed
-system.cpu1.CUs1.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::mean 82.212766 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::stdev 248.914352 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::0-1 1 0.71% 0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::2-3 12 8.51% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::4-5 53 37.59% 46.81% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::6-7 28 19.86% 66.67% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::8-9 5 3.55% 70.21% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::10 1 0.71% 70.92% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::overflows 41 29.08% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::min_value 1 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::max_value 1765 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.num_vec_ops_executed 6762 # number of vec ops executed (e.g. VSZ/inst)
-system.cpu1.CUs1.num_total_cycles 4765 # number of cycles the CU ran for
-system.cpu1.CUs1.vpc 1.419098 # Vector Operations per cycle (this CU only)
-system.cpu1.CUs1.ipc 0.029591 # Instructions per cycle (this CU only)
-system.cpu1.CUs1.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::mean 47.957447 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::stdev 23.818022 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::9-12 9 6.38% 9.93% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::13-16 27 19.15% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::mean 37.722222 # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::stdev 27.174394 # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::9-12 2 11.11% 16.67% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::13-16 6 33.33% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::mean 19.333333 # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::stdev 22.384518 # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::9-12 1 16.67% 33.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::13-16 3 50.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction
-system.cpu1.CUs1.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed
-system.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD
-system.cpu1.CUs1.num_CAS_ops 0 # number of compare and swap operations
-system.cpu1.CUs1.num_failed_CAS_ops 0 # number of compare and swap operations that failed
-system.cpu1.CUs1.num_completed_wfs 4 # number of completed wavefronts
-system.cpu2.num_kernel_launched 1 # number of kernel launched
-system.dispatcher_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.dispatcher_coalescer.clk_domain.clock 1000 # Clock period in ticks
-system.dispatcher_coalescer.uncoalesced_accesses 0 # Number of uncoalesced TLB accesses
-system.dispatcher_coalescer.coalesced_accesses 0 # Number of coalesced TLB accesses
-system.dispatcher_coalescer.queuing_cycles 0 # Number of cycles spent in queue
-system.dispatcher_coalescer.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs
-system.dispatcher_coalescer.local_latency nan # Avg. latency over all incoming pkts
-system.dispatcher_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.dispatcher_tlb.clk_domain.clock 1000 # Clock period in ticks
-system.dispatcher_tlb.local_TLB_accesses 0 # Number of TLB accesses
-system.dispatcher_tlb.local_TLB_hits 0 # Number of TLB hits
-system.dispatcher_tlb.local_TLB_misses 0 # Number of TLB misses
-system.dispatcher_tlb.local_TLB_miss_rate nan # TLB miss rate
-system.dispatcher_tlb.global_TLB_accesses 0 # Number of TLB accesses
-system.dispatcher_tlb.global_TLB_hits 0 # Number of TLB hits
-system.dispatcher_tlb.global_TLB_misses 0 # Number of TLB misses
-system.dispatcher_tlb.global_TLB_miss_rate nan # TLB miss rate
-system.dispatcher_tlb.access_cycles 0 # Cycles spent accessing this TLB level
-system.dispatcher_tlb.page_table_cycles 0 # Cycles spent accessing the page table
-system.dispatcher_tlb.unique_pages 0 # Number of unique pages touched
-system.dispatcher_tlb.local_cycles 0 # Number of cycles spent in queue for all incoming reqs
-system.dispatcher_tlb.local_latency nan # Avg. latency over incoming coalesced reqs
-system.dispatcher_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
-system.l1_coalescer0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l1_coalescer0.clk_domain.clock 1000 # Clock period in ticks
-system.l1_coalescer0.uncoalesced_accesses 778 # Number of uncoalesced TLB accesses
-system.l1_coalescer0.coalesced_accesses 0 # Number of coalesced TLB accesses
-system.l1_coalescer0.queuing_cycles 0 # Number of cycles spent in queue
-system.l1_coalescer0.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs
-system.l1_coalescer0.local_latency 0 # Avg. latency over all incoming pkts
-system.l1_coalescer1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l1_coalescer1.clk_domain.clock 1000 # Clock period in ticks
-system.l1_coalescer1.uncoalesced_accesses 769 # Number of uncoalesced TLB accesses
-system.l1_coalescer1.coalesced_accesses 0 # Number of coalesced TLB accesses
-system.l1_coalescer1.queuing_cycles 0 # Number of cycles spent in queue
-system.l1_coalescer1.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs
-system.l1_coalescer1.local_latency 0 # Avg. latency over all incoming pkts
-system.l1_tlb0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l1_tlb0.clk_domain.clock 1000 # Clock period in ticks
-system.l1_tlb0.local_TLB_accesses 778 # Number of TLB accesses
-system.l1_tlb0.local_TLB_hits 774 # Number of TLB hits
-system.l1_tlb0.local_TLB_misses 4 # Number of TLB misses
-system.l1_tlb0.local_TLB_miss_rate 0.514139 # TLB miss rate
-system.l1_tlb0.global_TLB_accesses 778 # Number of TLB accesses
-system.l1_tlb0.global_TLB_hits 774 # Number of TLB hits
-system.l1_tlb0.global_TLB_misses 4 # Number of TLB misses
-system.l1_tlb0.global_TLB_miss_rate 0.514139 # TLB miss rate
-system.l1_tlb0.access_cycles 0 # Cycles spent accessing this TLB level
-system.l1_tlb0.page_table_cycles 0 # Cycles spent accessing the page table
-system.l1_tlb0.unique_pages 4 # Number of unique pages touched
-system.l1_tlb0.local_cycles 0 # Number of cycles spent in queue for all incoming reqs
-system.l1_tlb0.local_latency 0 # Avg. latency over incoming coalesced reqs
-system.l1_tlb0.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
-system.l1_tlb1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l1_tlb1.clk_domain.clock 1000 # Clock period in ticks
-system.l1_tlb1.local_TLB_accesses 769 # Number of TLB accesses
-system.l1_tlb1.local_TLB_hits 766 # Number of TLB hits
-system.l1_tlb1.local_TLB_misses 3 # Number of TLB misses
-system.l1_tlb1.local_TLB_miss_rate 0.390117 # TLB miss rate
-system.l1_tlb1.global_TLB_accesses 769 # Number of TLB accesses
-system.l1_tlb1.global_TLB_hits 766 # Number of TLB hits
-system.l1_tlb1.global_TLB_misses 3 # Number of TLB misses
-system.l1_tlb1.global_TLB_miss_rate 0.390117 # TLB miss rate
-system.l1_tlb1.access_cycles 0 # Cycles spent accessing this TLB level
-system.l1_tlb1.page_table_cycles 0 # Cycles spent accessing the page table
-system.l1_tlb1.unique_pages 3 # Number of unique pages touched
-system.l1_tlb1.local_cycles 0 # Number of cycles spent in queue for all incoming reqs
-system.l1_tlb1.local_latency 0 # Avg. latency over incoming coalesced reqs
-system.l1_tlb1.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
-system.l2_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l2_coalescer.clk_domain.clock 1000 # Clock period in ticks
-system.l2_coalescer.uncoalesced_accesses 8 # Number of uncoalesced TLB accesses
-system.l2_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses
-system.l2_coalescer.queuing_cycles 8000 # Number of cycles spent in queue
-system.l2_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs
-system.l2_coalescer.local_latency 125 # Avg. latency over all incoming pkts
-system.l2_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l2_tlb.clk_domain.clock 1000 # Clock period in ticks
-system.l2_tlb.local_TLB_accesses 8 # Number of TLB accesses
-system.l2_tlb.local_TLB_hits 3 # Number of TLB hits
-system.l2_tlb.local_TLB_misses 5 # Number of TLB misses
-system.l2_tlb.local_TLB_miss_rate 62.500000 # TLB miss rate
-system.l2_tlb.global_TLB_accesses 15 # Number of TLB accesses
-system.l2_tlb.global_TLB_hits 3 # Number of TLB hits
-system.l2_tlb.global_TLB_misses 12 # Number of TLB misses
-system.l2_tlb.global_TLB_miss_rate 80 # TLB miss rate
-system.l2_tlb.access_cycles 552008 # Cycles spent accessing this TLB level
-system.l2_tlb.page_table_cycles 0 # Cycles spent accessing the page table
-system.l2_tlb.unique_pages 5 # Number of unique pages touched
-system.l2_tlb.local_cycles 69001 # Number of cycles spent in queue for all incoming reqs
-system.l2_tlb.local_latency 8625.125000 # Avg. latency over incoming coalesced reqs
-system.l2_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
-system.l3_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l3_coalescer.clk_domain.clock 1000 # Clock period in ticks
-system.l3_coalescer.uncoalesced_accesses 5 # Number of uncoalesced TLB accesses
-system.l3_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses
-system.l3_coalescer.queuing_cycles 8000 # Number of cycles spent in queue
-system.l3_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs
-system.l3_coalescer.local_latency 200 # Avg. latency over all incoming pkts
-system.l3_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l3_tlb.clk_domain.clock 1000 # Clock period in ticks
-system.l3_tlb.local_TLB_accesses 5 # Number of TLB accesses
-system.l3_tlb.local_TLB_hits 0 # Number of TLB hits
-system.l3_tlb.local_TLB_misses 5 # Number of TLB misses
-system.l3_tlb.local_TLB_miss_rate 100 # TLB miss rate
-system.l3_tlb.global_TLB_accesses 12 # Number of TLB accesses
-system.l3_tlb.global_TLB_hits 0 # Number of TLB hits
-system.l3_tlb.global_TLB_misses 12 # Number of TLB misses
-system.l3_tlb.global_TLB_miss_rate 100 # TLB miss rate
-system.l3_tlb.access_cycles 1200000 # Cycles spent accessing this TLB level
-system.l3_tlb.page_table_cycles 6000000 # Cycles spent accessing the page table
-system.l3_tlb.unique_pages 5 # Number of unique pages touched
-system.l3_tlb.local_cycles 150000 # Number of cycles spent in queue for all incoming reqs
-system.l3_tlb.local_latency 30000 # Avg. latency over incoming coalesced reqs
-system.l3_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
-system.piobus.trans_dist::WriteReq 94 # Transaction distribution
-system.piobus.trans_dist::WriteResp 94 # Transaction distribution
-system.piobus.pkt_count_system.ruby.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 188 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::total 188 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_size_system.ruby.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 748 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.pkt_size::total 748 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.reqLayer0.occupancy 234500 # Layer occupancy (ticks)
-system.piobus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.piobus.respLayer0.occupancy 94000 # Layer occupancy (ticks)
-system.piobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.ruby.outstanding_req_hist::bucket_size 1
-system.ruby.outstanding_req_hist::max_bucket 9
-system.ruby.outstanding_req_hist::samples 114203
-system.ruby.outstanding_req_hist::mean 1.000035
-system.ruby.outstanding_req_hist::gmean 1.000024
-system.ruby.outstanding_req_hist::stdev 0.005918
-system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 114199 100.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist::total 114203
-system.ruby.latency_hist::bucket_size 128
-system.ruby.latency_hist::max_bucket 1279
-system.ruby.latency_hist::samples 114203
-system.ruby.latency_hist::mean 4.423518
-system.ruby.latency_hist::gmean 1.078765
-system.ruby.latency_hist::stdev 30.010569
-system.ruby.latency_hist | 112668 98.66% 98.66% | 1136 0.99% 99.65% | 372 0.33% 99.98% | 3 0.00% 99.98% | 8 0.01% 99.99% | 14 0.01% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist::total 114203
-system.ruby.hit_latency_hist::bucket_size 128
-system.ruby.hit_latency_hist::max_bucket 1279
-system.ruby.hit_latency_hist::samples 1535
-system.ruby.hit_latency_hist::mean 255.015635
-system.ruby.hit_latency_hist::gmean 251.519163
-system.ruby.hit_latency_hist::stdev 57.825523
-system.ruby.hit_latency_hist | 0 0.00% 0.00% | 1136 74.01% 74.01% | 372 24.23% 98.24% | 3 0.20% 98.44% | 8 0.52% 98.96% | 14 0.91% 99.87% | 2 0.13% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist::total 1535
-system.ruby.miss_latency_hist::bucket_size 2
-system.ruby.miss_latency_hist::max_bucket 19
-system.ruby.miss_latency_hist::samples 112668
-system.ruby.miss_latency_hist::mean 1.009426
-system.ruby.miss_latency_hist::gmean 1.001543
-system.ruby.miss_latency_hist::stdev 0.411800
-system.ruby.miss_latency_hist | 112609 99.95% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 59 0.05% 100.00%
-system.ruby.miss_latency_hist::total 112668
-system.ruby.L1Cache.incomplete_times 112609
-system.ruby.L2Cache.incomplete_times 59
-system.ruby.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits
-system.ruby.cp_cntrl0.L1D0cache.demand_misses 506 # Number of cache demand misses
-system.ruby.cp_cntrl0.L1D0cache.demand_accesses 506 # Number of cache demand accesses
-system.ruby.cp_cntrl0.L1D0cache.num_data_array_reads 16155 # number of data array reads
-system.ruby.cp_cntrl0.L1D0cache.num_data_array_writes 11985 # number of data array writes
-system.ruby.cp_cntrl0.L1D0cache.num_tag_array_reads 27132 # number of tag array reads
-system.ruby.cp_cntrl0.L1D0cache.num_tag_array_writes 1584 # number of tag array writes
-system.ruby.cp_cntrl0.L1D1cache.demand_hits 0 # Number of cache demand hits
-system.ruby.cp_cntrl0.L1D1cache.demand_misses 0 # Number of cache demand misses
-system.ruby.cp_cntrl0.L1D1cache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.cp_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.cp_cntrl0.L1Icache.demand_misses 1088 # Number of cache demand misses
-system.ruby.cp_cntrl0.L1Icache.demand_accesses 1088 # Number of cache demand accesses
-system.ruby.cp_cntrl0.L1Icache.num_data_array_reads 86007 # number of data array reads
-system.ruby.cp_cntrl0.L1Icache.num_data_array_writes 54 # number of data array writes
-system.ruby.cp_cntrl0.L1Icache.num_tag_array_reads 87684 # number of tag array reads
-system.ruby.cp_cntrl0.L1Icache.num_tag_array_writes 54 # number of tag array writes
-system.ruby.cp_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits
-system.ruby.cp_cntrl0.L2cache.demand_misses 1535 # Number of cache demand misses
-system.ruby.cp_cntrl0.L2cache.demand_accesses 1535 # Number of cache demand accesses
-system.ruby.cp_cntrl0.L2cache.num_data_array_reads 120 # number of data array reads
-system.ruby.cp_cntrl0.L2cache.num_data_array_writes 11982 # number of data array writes
-system.ruby.cp_cntrl0.L2cache.num_tag_array_reads 12068 # number of tag array reads
-system.ruby.cp_cntrl0.L2cache.num_tag_array_writes 1658 # number of tag array writes
-system.ruby.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits
-system.ruby.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses
-system.ruby.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses
-system.ruby.dir_cntrl0.L3CacheMemory.num_data_array_writes 1560 # number of data array writes
-system.ruby.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1560 # number of tag array reads
-system.ruby.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1578 # number of tag array writes
-system.ruby.network.ext_links0.int_node.percent_links_utilized 1.075754
-system.ruby.network.ext_links0.int_node.msg_count.Control::0 1560
-system.ruby.network.ext_links0.int_node.msg_count.Data::0 18
-system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1542
-system.ruby.network.ext_links0.int_node.msg_count.Response_Data::2 1546
-system.ruby.network.ext_links0.int_node.msg_count.Response_Control::2 1558
-system.ruby.network.ext_links0.int_node.msg_count.Writeback_Control::2 16
-system.ruby.network.ext_links0.int_node.msg_count.Unblock_Control::4 1541
-system.ruby.network.ext_links0.int_node.msg_bytes.Control::0 12480
-system.ruby.network.ext_links0.int_node.msg_bytes.Data::0 1296
-system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0 12336
-system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 111312
-system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 12464
-system.ruby.network.ext_links0.int_node.msg_bytes.Writeback_Control::2 128
-system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12328
-system.ruby.network.ext_links1.int_node.percent_links_utilized 1.347807
-system.ruby.network.ext_links1.int_node.msg_count.Control::0 25
-system.ruby.network.ext_links1.int_node.msg_count.Request_Control::0 1535
-system.ruby.network.ext_links1.int_node.msg_count.Response_Data::2 1537
-system.ruby.network.ext_links1.int_node.msg_count.Response_Control::2 23
-system.ruby.network.ext_links1.int_node.msg_count.Unblock_Control::4 1534
-system.ruby.network.ext_links1.int_node.msg_bytes.Control::0 200
-system.ruby.network.ext_links1.int_node.msg_bytes.Request_Control::0 12280
-system.ruby.network.ext_links1.int_node.msg_bytes.Response_Data::2 110664
-system.ruby.network.ext_links1.int_node.msg_bytes.Response_Control::2 184
-system.ruby.network.ext_links1.int_node.msg_bytes.Unblock_Control::4 12272
-system.ruby.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits
-system.ruby.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses
-system.ruby.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.tcp_cntrl0.L1cache.num_data_array_reads 6 # number of data array reads
-system.ruby.tcp_cntrl0.L1cache.num_data_array_writes 11 # number of data array writes
-system.ruby.tcp_cntrl0.L1cache.num_tag_array_reads 1297 # number of tag array reads
-system.ruby.tcp_cntrl0.L1cache.num_tag_array_writes 11 # number of tag array writes
-system.ruby.tcp_cntrl0.L1cache.num_tag_array_stalls 5082 # number of stalls caused by tag array
-system.ruby.tcp_cntrl0.L1cache.num_data_array_stalls 6 # number of stalls caused by data array
-system.ruby.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP
-system.ruby.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers
-system.ruby.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
-system.ruby.tcp_cntrl0.coalescer.gpu_ld_misses 5 # loads that miss in the GPU
-system.ruby.tcp_cntrl0.coalescer.gpu_tcp_st_hits 0 # stores that hit in the TCP
-system.ruby.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers
-system.ruby.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
-system.ruby.tcp_cntrl0.coalescer.gpu_st_misses 9 # stores that miss in the GPU
-system.ruby.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP
-system.ruby.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers
-system.ruby.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC
-system.ruby.tcp_cntrl0.coalescer.cp_ld_misses 0 # loads that miss in the GPU
-system.ruby.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP
-system.ruby.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
-system.ruby.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
-system.ruby.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU
-system.ruby.network.ext_links2.int_node.percent_links_utilized 0.115426
-system.ruby.network.ext_links2.int_node.msg_count.Control::0 1535
-system.ruby.network.ext_links2.int_node.msg_count.Data::0 18
-system.ruby.network.ext_links2.int_node.msg_count.Data::1 18
-system.ruby.network.ext_links2.int_node.msg_count.Request_Control::0 7
-system.ruby.network.ext_links2.int_node.msg_count.Request_Control::1 9
-system.ruby.network.ext_links2.int_node.msg_count.Response_Data::2 9
-system.ruby.network.ext_links2.int_node.msg_count.Response_Data::3 11
-system.ruby.network.ext_links2.int_node.msg_count.Response_Control::2 1535
-system.ruby.network.ext_links2.int_node.msg_count.Writeback_Control::2 16
-system.ruby.network.ext_links2.int_node.msg_count.Writeback_Control::3 16
-system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::4 7
-system.ruby.network.ext_links2.int_node.msg_bytes.Control::0 12280
-system.ruby.network.ext_links2.int_node.msg_bytes.Data::0 1296
-system.ruby.network.ext_links2.int_node.msg_bytes.Data::1 1296
-system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::0 56
-system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::1 72
-system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::2 648
-system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::3 792
-system.ruby.network.ext_links2.int_node.msg_bytes.Response_Control::2 12280
-system.ruby.network.ext_links2.int_node.msg_bytes.Writeback_Control::2 128
-system.ruby.network.ext_links2.int_node.msg_bytes.Writeback_Control::3 128
-system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::4 56
-system.ruby.tcp_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits
-system.ruby.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses
-system.ruby.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.tcp_cntrl1.L1cache.num_data_array_reads 6 # number of data array reads
-system.ruby.tcp_cntrl1.L1cache.num_data_array_writes 11 # number of data array writes
-system.ruby.tcp_cntrl1.L1cache.num_tag_array_reads 1297 # number of tag array reads
-system.ruby.tcp_cntrl1.L1cache.num_tag_array_writes 11 # number of tag array writes
-system.ruby.tcp_cntrl1.L1cache.num_tag_array_stalls 5082 # number of stalls caused by tag array
-system.ruby.tcp_cntrl1.L1cache.num_data_array_stalls 6 # number of stalls caused by data array
-system.ruby.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP
-system.ruby.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers
-system.ruby.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
-system.ruby.tcp_cntrl1.coalescer.gpu_ld_misses 5 # loads that miss in the GPU
-system.ruby.tcp_cntrl1.coalescer.gpu_tcp_st_hits 0 # stores that hit in the TCP
-system.ruby.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers
-system.ruby.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
-system.ruby.tcp_cntrl1.coalescer.gpu_st_misses 9 # stores that miss in the GPU
-system.ruby.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP
-system.ruby.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers
-system.ruby.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC
-system.ruby.tcp_cntrl1.coalescer.cp_ld_misses 0 # loads that miss in the GPU
-system.ruby.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP
-system.ruby.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
-system.ruby.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
-system.ruby.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU
-system.ruby.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits
-system.ruby.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses
-system.ruby.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.sqc_cntrl0.L1cache.num_data_array_reads 86 # number of data array reads
-system.ruby.sqc_cntrl0.L1cache.num_tag_array_reads 91 # number of tag array reads
-system.ruby.sqc_cntrl0.L1cache.num_tag_array_writes 10 # number of tag array writes
-system.ruby.sqc_cntrl0.sequencer.load_waiting_on_load 97 # Number of times a load aliased with a pending load
-system.ruby.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits
-system.ruby.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses
-system.ruby.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.tcc_cntrl0.L2cache.num_data_array_writes 9 # number of data array writes
-system.ruby.tcc_cntrl0.L2cache.num_tag_array_reads 1569 # number of tag array reads
-system.ruby.tcc_cntrl0.L2cache.num_tag_array_writes 1545 # number of tag array writes
-system.ruby.tcc_cntrl0.L2cache.num_tag_array_stalls 1 # number of stalls caused by tag array
-system.ruby.network.msg_count.Control 3120
-system.ruby.network.msg_count.Data 54
-system.ruby.network.msg_count.Request_Control 3093
-system.ruby.network.msg_count.Response_Data 3103
-system.ruby.network.msg_count.Response_Control 3116
-system.ruby.network.msg_count.Writeback_Control 48
-system.ruby.network.msg_count.Unblock_Control 3082
-system.ruby.network.msg_byte.Control 24960
-system.ruby.network.msg_byte.Data 3888
-system.ruby.network.msg_byte.Request_Control 24744
-system.ruby.network.msg_byte.Response_Data 223416
-system.ruby.network.msg_byte.Response_Control 24928
-system.ruby.network.msg_byte.Writeback_Control 384
-system.ruby.network.msg_byte.Unblock_Control 24656
-system.sqc_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.sqc_coalescer.clk_domain.clock 1000 # Clock period in ticks
-system.sqc_coalescer.uncoalesced_accesses 86 # Number of uncoalesced TLB accesses
-system.sqc_coalescer.coalesced_accesses 48 # Number of coalesced TLB accesses
-system.sqc_coalescer.queuing_cycles 211000 # Number of cycles spent in queue
-system.sqc_coalescer.local_queuing_cycles 211000 # Number of cycles spent in queue for all incoming reqs
-system.sqc_coalescer.local_latency 2453.488372 # Avg. latency over all incoming pkts
-system.sqc_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.sqc_tlb.clk_domain.clock 1000 # Clock period in ticks
-system.sqc_tlb.local_TLB_accesses 48 # Number of TLB accesses
-system.sqc_tlb.local_TLB_hits 47 # Number of TLB hits
-system.sqc_tlb.local_TLB_misses 1 # Number of TLB misses
-system.sqc_tlb.local_TLB_miss_rate 2.083333 # TLB miss rate
-system.sqc_tlb.global_TLB_accesses 86 # Number of TLB accesses
-system.sqc_tlb.global_TLB_hits 78 # Number of TLB hits
-system.sqc_tlb.global_TLB_misses 8 # Number of TLB misses
-system.sqc_tlb.global_TLB_miss_rate 9.302326 # TLB miss rate
-system.sqc_tlb.access_cycles 86008 # Cycles spent accessing this TLB level
-system.sqc_tlb.page_table_cycles 0 # Cycles spent accessing the page table
-system.sqc_tlb.unique_pages 1 # Number of unique pages touched
-system.sqc_tlb.local_cycles 48001 # Number of cycles spent in queue for all incoming reqs
-system.sqc_tlb.local_latency 1000.020833 # Avg. latency over incoming coalesced reqs
-system.sqc_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
-system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.766700
-system.ruby.network.ext_links0.int_node.throttle0.msg_count.Data::0 18
-system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1542
-system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2 2
-system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2 1558
-system.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4 1541
-system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Data::0 1296
-system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0 12336
-system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Data::2 144
-system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2 12464
-system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Unblock_Control::4 12328
-system.ruby.network.ext_links0.int_node.throttle1.link_utilization 2.201021
-system.ruby.network.ext_links0.int_node.throttle1.msg_count.Control::0 25
-system.ruby.network.ext_links0.int_node.throttle1.msg_count.Response_Data::2 1535
-system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Control::0 200
-system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Response_Data::2 110520
-system.ruby.network.ext_links0.int_node.throttle2.link_utilization 0.259542
-system.ruby.network.ext_links0.int_node.throttle2.msg_count.Control::0 1535
-system.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Data::2 9
-system.ruby.network.ext_links0.int_node.throttle2.msg_count.Writeback_Control::2 16
-system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Control::0 12280
-system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Data::2 648
-system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Writeback_Control::2 128
-system.ruby.network.ext_links1.int_node.throttle0.link_utilization 2.201021
-system.ruby.network.ext_links1.int_node.throttle0.msg_count.Control::0 25
-system.ruby.network.ext_links1.int_node.throttle0.msg_count.Response_Data::2 1535
-system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Control::0 200
-system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Response_Data::2 110520
-system.ruby.network.ext_links1.int_node.throttle1.link_utilization 0.494594
-system.ruby.network.ext_links1.int_node.throttle1.msg_count.Request_Control::0 1535
-system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Data::2 2
-system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Control::2 23
-system.ruby.network.ext_links1.int_node.throttle1.msg_count.Unblock_Control::4 1534
-system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Request_Control::0 12280
-system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Data::2 144
-system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Control::2 184
-system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Unblock_Control::4 12272
-system.ruby.network.ext_links2.int_node.throttle0.link_utilization 0.005566
-system.ruby.network.ext_links2.int_node.throttle0.msg_count.Response_Data::3 3
-system.ruby.network.ext_links2.int_node.throttle0.msg_count.Writeback_Control::3 8
-system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Response_Data::3 216
-system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Writeback_Control::3 64
-system.ruby.network.ext_links2.int_node.throttle1.link_utilization 0.005566
-system.ruby.network.ext_links2.int_node.throttle1.msg_count.Response_Data::3 3
-system.ruby.network.ext_links2.int_node.throttle1.msg_count.Writeback_Control::3 8
-system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Response_Data::3 216
-system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Writeback_Control::3 64
-system.ruby.network.ext_links2.int_node.throttle2.link_utilization 0.286737
-system.ruby.network.ext_links2.int_node.throttle2.msg_count.Control::0 1535
-system.ruby.network.ext_links2.int_node.throttle2.msg_count.Data::1 18
-system.ruby.network.ext_links2.int_node.throttle2.msg_count.Request_Control::1 9
-system.ruby.network.ext_links2.int_node.throttle2.msg_count.Response_Data::2 9
-system.ruby.network.ext_links2.int_node.throttle2.msg_count.Writeback_Control::2 16
-system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Control::0 12280
-system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Data::1 1296
-system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Request_Control::1 72
-system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Response_Data::2 648
-system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Writeback_Control::2 128
-system.ruby.network.ext_links2.int_node.throttle3.link_utilization 0.007156
-system.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::3 5
-system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::3 360
-system.ruby.network.ext_links2.int_node.throttle4.link_utilization 0.272106
-system.ruby.network.ext_links2.int_node.throttle4.msg_count.Data::0 18
-system.ruby.network.ext_links2.int_node.throttle4.msg_count.Request_Control::0 7
-system.ruby.network.ext_links2.int_node.throttle4.msg_count.Response_Control::2 1535
-system.ruby.network.ext_links2.int_node.throttle4.msg_count.Unblock_Control::4 7
-system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Data::0 1296
-system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Request_Control::0 56
-system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Response_Control::2 12280
-system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Unblock_Control::4 56
-system.ruby.LD.latency_hist::bucket_size 128
-system.ruby.LD.latency_hist::max_bucket 1279
-system.ruby.LD.latency_hist::samples 16335
-system.ruby.LD.latency_hist::mean 3.784451
-system.ruby.LD.latency_hist::gmean 1.062267
-system.ruby.LD.latency_hist::stdev 27.056562
-system.ruby.LD.latency_hist | 16160 98.93% 98.93% | 90 0.55% 99.48% | 84 0.51% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.latency_hist::total 16335
-system.ruby.LD.hit_latency_hist::bucket_size 128
-system.ruby.LD.hit_latency_hist::max_bucket 1279
-system.ruby.LD.hit_latency_hist::samples 175
-system.ruby.LD.hit_latency_hist::mean 260.394286
-system.ruby.LD.hit_latency_hist::gmean 258.339713
-system.ruby.LD.hit_latency_hist::stdev 42.039376
-system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 90 51.43% 51.43% | 84 48.00% 99.43% | 0 0.00% 99.43% | 0 0.00% 99.43% | 1 0.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.hit_latency_hist::total 175
-system.ruby.LD.miss_latency_hist::bucket_size 2
-system.ruby.LD.miss_latency_hist::max_bucket 19
-system.ruby.LD.miss_latency_hist::samples 16160
-system.ruby.LD.miss_latency_hist::mean 1.005569
-system.ruby.LD.miss_latency_hist::gmean 1.000911
-system.ruby.LD.miss_latency_hist::stdev 0.316580
-system.ruby.LD.miss_latency_hist | 16155 99.97% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 5 0.03% 100.00%
-system.ruby.LD.miss_latency_hist::total 16160
-system.ruby.ST.latency_hist::bucket_size 128
-system.ruby.ST.latency_hist::max_bucket 1279
-system.ruby.ST.latency_hist::samples 10412
-system.ruby.ST.latency_hist::mean 8.839992
-system.ruby.ST.latency_hist::gmean 1.186243
-system.ruby.ST.latency_hist::stdev 45.390081
-system.ruby.ST.latency_hist | 10090 96.91% 96.91% | 254 2.44% 99.35% | 62 0.60% 99.94% | 0 0.00% 99.94% | 1 0.01% 99.95% | 4 0.04% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.latency_hist::total 10412
-system.ruby.ST.hit_latency_hist::bucket_size 128
-system.ruby.ST.hit_latency_hist::max_bucket 1279
-system.ruby.ST.hit_latency_hist::samples 322
-system.ruby.ST.hit_latency_hist::mean 254.509317
-system.ruby.ST.hit_latency_hist::gmean 250.282441
-system.ruby.ST.hit_latency_hist::stdev 65.931487
-system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 254 78.88% 78.88% | 62 19.25% 98.14% | 0 0.00% 98.14% | 1 0.31% 98.45% | 4 1.24% 99.69% | 1 0.31% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.hit_latency_hist::total 322
-system.ruby.ST.miss_latency_hist::bucket_size 1
-system.ruby.ST.miss_latency_hist::max_bucket 9
-system.ruby.ST.miss_latency_hist::samples 10090
-system.ruby.ST.miss_latency_hist::mean 1
-system.ruby.ST.miss_latency_hist::gmean 1
-system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.miss_latency_hist::total 10090
-system.ruby.IFETCH.latency_hist::bucket_size 128
-system.ruby.IFETCH.latency_hist::max_bucket 1279
-system.ruby.IFETCH.latency_hist::samples 87095
-system.ruby.IFETCH.latency_hist::mean 4.017395
-system.ruby.IFETCH.latency_hist::gmean 1.069735
-system.ruby.IFETCH.latency_hist::stdev 28.134930
-system.ruby.IFETCH.latency_hist | 86061 98.81% 98.81% | 790 0.91% 99.72% | 224 0.26% 99.98% | 3 0.00% 99.98% | 7 0.01% 99.99% | 9 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.latency_hist::total 87095
-system.ruby.IFETCH.hit_latency_hist::bucket_size 128
-system.ruby.IFETCH.hit_latency_hist::max_bucket 1279
-system.ruby.IFETCH.hit_latency_hist::samples 1034
-system.ruby.IFETCH.hit_latency_hist::mean 254.218569
-system.ruby.IFETCH.hit_latency_hist::gmean 250.716467
-system.ruby.IFETCH.hit_latency_hist::stdev 57.514968
-system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 790 76.40% 76.40% | 224 21.66% 98.07% | 3 0.29% 98.36% | 7 0.68% 99.03% | 9 0.87% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.hit_latency_hist::total 1034
-system.ruby.IFETCH.miss_latency_hist::bucket_size 2
-system.ruby.IFETCH.miss_latency_hist::max_bucket 19
-system.ruby.IFETCH.miss_latency_hist::samples 86061
-system.ruby.IFETCH.miss_latency_hist::mean 1.011294
-system.ruby.IFETCH.miss_latency_hist::gmean 1.001849
-system.ruby.IFETCH.miss_latency_hist::stdev 0.450747
-system.ruby.IFETCH.miss_latency_hist | 86007 99.94% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 54 0.06% 100.00%
-system.ruby.IFETCH.miss_latency_hist::total 86061
-system.ruby.RMW_Read.latency_hist::bucket_size 32
-system.ruby.RMW_Read.latency_hist::max_bucket 319
-system.ruby.RMW_Read.latency_hist::samples 341
-system.ruby.RMW_Read.latency_hist::mean 4.114370
-system.ruby.RMW_Read.latency_hist::gmean 1.067644
-system.ruby.RMW_Read.latency_hist::stdev 28.783090
-system.ruby.RMW_Read.latency_hist | 337 98.83% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 2 0.59% 99.41% | 0 0.00% 99.41% | 2 0.59% 100.00%
-system.ruby.RMW_Read.latency_hist::total 341
-system.ruby.RMW_Read.hit_latency_hist::bucket_size 32
-system.ruby.RMW_Read.hit_latency_hist::max_bucket 319
-system.ruby.RMW_Read.hit_latency_hist::samples 4
-system.ruby.RMW_Read.hit_latency_hist::mean 266.500000
-system.ruby.RMW_Read.hit_latency_hist::gmean 265.077347
-system.ruby.RMW_Read.hit_latency_hist::stdev 31.754265
-system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 50.00% 50.00% | 0 0.00% 50.00% | 2 50.00% 100.00%
-system.ruby.RMW_Read.hit_latency_hist::total 4
-system.ruby.RMW_Read.miss_latency_hist::bucket_size 1
-system.ruby.RMW_Read.miss_latency_hist::max_bucket 9
-system.ruby.RMW_Read.miss_latency_hist::samples 337
-system.ruby.RMW_Read.miss_latency_hist::mean 1
-system.ruby.RMW_Read.miss_latency_hist::gmean 1
-system.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.RMW_Read.miss_latency_hist::total 337
-system.ruby.Locked_RMW_Read.latency_hist::bucket_size 1
-system.ruby.Locked_RMW_Read.latency_hist::max_bucket 9
-system.ruby.Locked_RMW_Read.latency_hist::samples 10
-system.ruby.Locked_RMW_Read.latency_hist::mean 1
-system.ruby.Locked_RMW_Read.latency_hist::gmean 1
-system.ruby.Locked_RMW_Read.latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Locked_RMW_Read.latency_hist::total 10
-system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 1
-system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 9
-system.ruby.Locked_RMW_Read.miss_latency_hist::samples 10
-system.ruby.Locked_RMW_Read.miss_latency_hist::mean 1
-system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 1
-system.ruby.Locked_RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Locked_RMW_Read.miss_latency_hist::total 10
-system.ruby.Locked_RMW_Write.latency_hist::bucket_size 1
-system.ruby.Locked_RMW_Write.latency_hist::max_bucket 9
-system.ruby.Locked_RMW_Write.latency_hist::samples 10
-system.ruby.Locked_RMW_Write.latency_hist::mean 1
-system.ruby.Locked_RMW_Write.latency_hist::gmean 1
-system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Locked_RMW_Write.latency_hist::total 10
-system.ruby.Locked_RMW_Write.miss_latency_hist::bucket_size 1
-system.ruby.Locked_RMW_Write.miss_latency_hist::max_bucket 9
-system.ruby.Locked_RMW_Write.miss_latency_hist::samples 10
-system.ruby.Locked_RMW_Write.miss_latency_hist::mean 1
-system.ruby.Locked_RMW_Write.miss_latency_hist::gmean 1
-system.ruby.Locked_RMW_Write.miss_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Locked_RMW_Write.miss_latency_hist::total 10
-system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 1
-system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 9
-system.ruby.L1Cache.miss_mach_latency_hist::samples 112609
-system.ruby.L1Cache.miss_mach_latency_hist::mean 1
-system.ruby.L1Cache.miss_mach_latency_hist::gmean 1
-system.ruby.L1Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 112609 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache.miss_mach_latency_hist::total 112609
-system.ruby.L2Cache.miss_mach_latency_hist::bucket_size 2
-system.ruby.L2Cache.miss_mach_latency_hist::max_bucket 19
-system.ruby.L2Cache.miss_mach_latency_hist::samples 59
-system.ruby.L2Cache.miss_mach_latency_hist::mean 19
-system.ruby.L2Cache.miss_mach_latency_hist::gmean 19.000000
-system.ruby.L2Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 59 100.00% 100.00%
-system.ruby.L2Cache.miss_mach_latency_hist::total 59
-system.ruby.Directory.hit_mach_latency_hist::bucket_size 128
-system.ruby.Directory.hit_mach_latency_hist::max_bucket 1279
-system.ruby.Directory.hit_mach_latency_hist::samples 1535
-system.ruby.Directory.hit_mach_latency_hist::mean 255.015635
-system.ruby.Directory.hit_mach_latency_hist::gmean 251.519163
-system.ruby.Directory.hit_mach_latency_hist::stdev 57.825523
-system.ruby.Directory.hit_mach_latency_hist | 0 0.00% 0.00% | 1136 74.01% 74.01% | 372 24.23% 98.24% | 3 0.20% 98.44% | 8 0.52% 98.96% | 14 0.91% 99.87% | 2 0.13% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory.hit_mach_latency_hist::total 1535
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 1
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 9
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 16155
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 1
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 16155 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 16155
-system.ruby.LD.L2Cache.miss_type_mach_latency_hist::bucket_size 2
-system.ruby.LD.L2Cache.miss_type_mach_latency_hist::max_bucket 19
-system.ruby.LD.L2Cache.miss_type_mach_latency_hist::samples 5
-system.ruby.LD.L2Cache.miss_type_mach_latency_hist::mean 19
-system.ruby.LD.L2Cache.miss_type_mach_latency_hist::gmean 19.000000
-system.ruby.LD.L2Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 100.00% 100.00%
-system.ruby.LD.L2Cache.miss_type_mach_latency_hist::total 5
-system.ruby.LD.Directory.hit_type_mach_latency_hist::bucket_size 128
-system.ruby.LD.Directory.hit_type_mach_latency_hist::max_bucket 1279
-system.ruby.LD.Directory.hit_type_mach_latency_hist::samples 175
-system.ruby.LD.Directory.hit_type_mach_latency_hist::mean 260.394286
-system.ruby.LD.Directory.hit_type_mach_latency_hist::gmean 258.339713
-system.ruby.LD.Directory.hit_type_mach_latency_hist::stdev 42.039376
-system.ruby.LD.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 90 51.43% 51.43% | 84 48.00% 99.43% | 0 0.00% 99.43% | 0 0.00% 99.43% | 1 0.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.Directory.hit_type_mach_latency_hist::total 175
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 1
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 9
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 10090
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 1
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 10090
-system.ruby.ST.Directory.hit_type_mach_latency_hist::bucket_size 128
-system.ruby.ST.Directory.hit_type_mach_latency_hist::max_bucket 1279
-system.ruby.ST.Directory.hit_type_mach_latency_hist::samples 322
-system.ruby.ST.Directory.hit_type_mach_latency_hist::mean 254.509317
-system.ruby.ST.Directory.hit_type_mach_latency_hist::gmean 250.282441
-system.ruby.ST.Directory.hit_type_mach_latency_hist::stdev 65.931487
-system.ruby.ST.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 254 78.88% 78.88% | 62 19.25% 98.14% | 0 0.00% 98.14% | 1 0.31% 98.45% | 4 1.24% 99.69% | 1 0.31% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.Directory.hit_type_mach_latency_hist::total 322
-system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::bucket_size 1
-system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::max_bucket 9
-system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::samples 86007
-system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::mean 1
-system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::gmean 1
-system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 86007 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::total 86007
-system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::bucket_size 2
-system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::max_bucket 19
-system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::samples 54
-system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::mean 19
-system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::gmean 19.000000
-system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 54 100.00% 100.00%
-system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::total 54
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::bucket_size 128
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::max_bucket 1279
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::samples 1034
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::mean 254.218569
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::gmean 250.716467
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::stdev 57.514968
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 790 76.40% 76.40% | 224 21.66% 98.07% | 3 0.29% 98.36% | 7 0.68% 99.03% | 9 0.87% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::total 1034
-system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::bucket_size 1
-system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::max_bucket 9
-system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::samples 337
-system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::mean 1
-system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::gmean 1
-system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::total 337
-system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::bucket_size 32
-system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::max_bucket 319
-system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::samples 4
-system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::mean 266.500000
-system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::gmean 265.077347
-system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::stdev 31.754265
-system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 50.00% 50.00% | 0 0.00% 50.00% | 2 50.00% 100.00%
-system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::total 4
-system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::bucket_size 1
-system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::max_bucket 9
-system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::samples 10
-system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::mean 1
-system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::gmean 1
-system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::total 10
-system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::bucket_size 1
-system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::max_bucket 9
-system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::samples 10
-system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::mean 1
-system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::gmean 1
-system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::total 10
-system.ruby.CorePair_Controller.C0_Load_L1miss 180 0.00% 0.00%
-system.ruby.CorePair_Controller.C0_Load_L1hit 16155 0.00% 0.00%
-system.ruby.CorePair_Controller.Ifetch0_L1hit 86007 0.00% 0.00%
-system.ruby.CorePair_Controller.Ifetch0_L1miss 1088 0.00% 0.00%
-system.ruby.CorePair_Controller.C0_Store_L1miss 325 0.00% 0.00%
-system.ruby.CorePair_Controller.C0_Store_L1hit 10448 0.00% 0.00%
-system.ruby.CorePair_Controller.NB_AckS 1034 0.00% 0.00%
-system.ruby.CorePair_Controller.NB_AckM 326 0.00% 0.00%
-system.ruby.CorePair_Controller.NB_AckE 175 0.00% 0.00%
-system.ruby.CorePair_Controller.L1I_Repl 589 0.00% 0.00%
-system.ruby.CorePair_Controller.L1D0_Repl 24 0.00% 0.00%
-system.ruby.CorePair_Controller.L2_to_L1D0 5 0.00% 0.00%
-system.ruby.CorePair_Controller.L2_to_L1I 54 0.00% 0.00%
-system.ruby.CorePair_Controller.PrbInvData 18 0.00% 0.00%
-system.ruby.CorePair_Controller.PrbShrData 7 0.00% 0.00%
-system.ruby.CorePair_Controller.I.C0_Load_L1miss 175 0.00% 0.00%
-system.ruby.CorePair_Controller.I.Ifetch0_L1miss 1034 0.00% 0.00%
-system.ruby.CorePair_Controller.I.C0_Store_L1miss 325 0.00% 0.00%
-system.ruby.CorePair_Controller.I.PrbInvData 17 0.00% 0.00%
-system.ruby.CorePair_Controller.I.PrbShrData 5 0.00% 0.00%
-system.ruby.CorePair_Controller.S.Ifetch0_L1hit 86007 0.00% 0.00%
-system.ruby.CorePair_Controller.S.Ifetch0_L1miss 54 0.00% 0.00%
-system.ruby.CorePair_Controller.S.L1I_Repl 589 0.00% 0.00%
-system.ruby.CorePair_Controller.E0.C0_Load_L1miss 2 0.00% 0.00%
-system.ruby.CorePair_Controller.E0.C0_Load_L1hit 3356 0.00% 0.00%
-system.ruby.CorePair_Controller.E0.C0_Store_L1hit 46 0.00% 0.00%
-system.ruby.CorePair_Controller.E0.L1D0_Repl 16 0.00% 0.00%
-system.ruby.CorePair_Controller.E0.PrbShrData 1 0.00% 0.00%
-system.ruby.CorePair_Controller.O.C0_Load_L1hit 3 0.00% 0.00%
-system.ruby.CorePair_Controller.O.C0_Store_L1hit 1 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.C0_Load_L1miss 3 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.C0_Load_L1hit 12796 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.C0_Store_L1hit 10401 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.L1D0_Repl 8 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.PrbInvData 1 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.PrbShrData 1 0.00% 0.00%
-system.ruby.CorePair_Controller.I_M0.NB_AckM 325 0.00% 0.00%
-system.ruby.CorePair_Controller.I_E0S.NB_AckE 175 0.00% 0.00%
-system.ruby.CorePair_Controller.Si_F0.L2_to_L1I 54 0.00% 0.00%
-system.ruby.CorePair_Controller.O_M0.NB_AckM 1 0.00% 0.00%
-system.ruby.CorePair_Controller.S0.NB_AckS 1034 0.00% 0.00%
-system.ruby.CorePair_Controller.E0_F.L2_to_L1D0 2 0.00% 0.00%
-system.ruby.CorePair_Controller.M0_F.L2_to_L1D0 3 0.00% 0.00%
-system.ruby.Directory_Controller.RdBlkS 1034 0.00% 0.00%
-system.ruby.Directory_Controller.RdBlkM 326 0.00% 0.00%
-system.ruby.Directory_Controller.RdBlk 182 0.00% 0.00%
-system.ruby.Directory_Controller.WriteThrough 16 0.00% 0.00%
-system.ruby.Directory_Controller.Atomic 3 0.00% 0.00%
-system.ruby.Directory_Controller.CPUPrbResp 1560 0.00% 0.00%
-system.ruby.Directory_Controller.ProbeAcksComplete 1560 0.00% 0.00%
-system.ruby.Directory_Controller.MemData 1560 0.00% 0.00%
-system.ruby.Directory_Controller.CoreUnblock 1541 0.00% 0.00%
-system.ruby.Directory_Controller.UnblockWriteThrough 18 0.00% 0.00%
-system.ruby.Directory_Controller.U.RdBlkS 1034 0.00% 0.00%
-system.ruby.Directory_Controller.U.RdBlkM 326 0.00% 0.00%
-system.ruby.Directory_Controller.U.RdBlk 182 0.00% 0.00%
-system.ruby.Directory_Controller.U.WriteThrough 16 0.00% 0.00%
-system.ruby.Directory_Controller.U.Atomic 2 0.00% 0.00%
-system.ruby.Directory_Controller.BS_M.MemData 1034 0.00% 0.00%
-system.ruby.Directory_Controller.BM_M.MemData 326 0.00% 0.00%
-system.ruby.Directory_Controller.B_M.MemData 175 0.00% 0.00%
-system.ruby.Directory_Controller.BS_PM.CPUPrbResp 1034 0.00% 0.00%
-system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 1034 0.00% 0.00%
-system.ruby.Directory_Controller.BM_PM.Atomic 1 0.00% 0.00%
-system.ruby.Directory_Controller.BM_PM.CPUPrbResp 326 0.00% 0.00%
-system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 326 0.00% 0.00%
-system.ruby.Directory_Controller.BM_PM.MemData 18 0.00% 0.00%
-system.ruby.Directory_Controller.B_PM.CPUPrbResp 175 0.00% 0.00%
-system.ruby.Directory_Controller.B_PM.ProbeAcksComplete 175 0.00% 0.00%
-system.ruby.Directory_Controller.B_PM.MemData 7 0.00% 0.00%
-system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 18 0.00% 0.00%
-system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 18 0.00% 0.00%
-system.ruby.Directory_Controller.B_Pm.CPUPrbResp 7 0.00% 0.00%
-system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 7 0.00% 0.00%
-system.ruby.Directory_Controller.B.CoreUnblock 1541 0.00% 0.00%
-system.ruby.Directory_Controller.B.UnblockWriteThrough 18 0.00% 0.00%
-system.ruby.SQC_Controller.Fetch 86 0.00% 0.00%
-system.ruby.SQC_Controller.Data 5 0.00% 0.00%
-system.ruby.SQC_Controller.I.Fetch 5 0.00% 0.00%
-system.ruby.SQC_Controller.I.Data 5 0.00% 0.00%
-system.ruby.SQC_Controller.V.Fetch 81 0.00% 0.00%
-system.ruby.TCC_Controller.RdBlk 9 0.00% 0.00%
-system.ruby.TCC_Controller.WrVicBlk 16 0.00% 0.00%
-system.ruby.TCC_Controller.Atomic 2 0.00% 0.00%
-system.ruby.TCC_Controller.AtomicDone 1 0.00% 0.00%
-system.ruby.TCC_Controller.Data 9 0.00% 0.00%
-system.ruby.TCC_Controller.PrbInv 1535 0.00% 0.00%
-system.ruby.TCC_Controller.WBAck 16 0.00% 0.00%
-system.ruby.TCC_Controller.V.PrbInv 1 0.00% 0.00%
-system.ruby.TCC_Controller.I.RdBlk 7 0.00% 0.00%
-system.ruby.TCC_Controller.I.WrVicBlk 16 0.00% 0.00%
-system.ruby.TCC_Controller.I.Atomic 1 0.00% 0.00%
-system.ruby.TCC_Controller.I.PrbInv 1534 0.00% 0.00%
-system.ruby.TCC_Controller.I.WBAck 16 0.00% 0.00%
-system.ruby.TCC_Controller.IV.RdBlk 2 0.00% 0.00%
-system.ruby.TCC_Controller.IV.Data 7 0.00% 0.00%
-system.ruby.TCC_Controller.A.Atomic 1 0.00% 0.00%
-system.ruby.TCC_Controller.A.AtomicDone 1 0.00% 0.00%
-system.ruby.TCC_Controller.A.Data 2 0.00% 0.00%
-system.ruby.TCP_Controller.Load | 5 50.00% 50.00% | 5 50.00% 100.00%
-system.ruby.TCP_Controller.Load::total 10
-system.ruby.TCP_Controller.StoreThrough | 8 50.00% 50.00% | 8 50.00% 100.00%
-system.ruby.TCP_Controller.StoreThrough::total 16
-system.ruby.TCP_Controller.Atomic | 1 50.00% 50.00% | 1 50.00% 100.00%
-system.ruby.TCP_Controller.Atomic::total 2
-system.ruby.TCP_Controller.Flush | 768 50.00% 50.00% | 768 50.00% 100.00%
-system.ruby.TCP_Controller.Flush::total 1536
-system.ruby.TCP_Controller.Evict | 512 50.00% 50.00% | 512 50.00% 100.00%
-system.ruby.TCP_Controller.Evict::total 1024
-system.ruby.TCP_Controller.TCC_Ack | 3 50.00% 50.00% | 3 50.00% 100.00%
-system.ruby.TCP_Controller.TCC_Ack::total 6
-system.ruby.TCP_Controller.TCC_AckWB | 8 50.00% 50.00% | 8 50.00% 100.00%
-system.ruby.TCP_Controller.TCC_AckWB::total 16
-system.ruby.TCP_Controller.I.Load | 2 50.00% 50.00% | 2 50.00% 100.00%
-system.ruby.TCP_Controller.I.Load::total 4
-system.ruby.TCP_Controller.I.StoreThrough | 8 50.00% 50.00% | 8 50.00% 100.00%
-system.ruby.TCP_Controller.I.StoreThrough::total 16
-system.ruby.TCP_Controller.I.Atomic | 1 50.00% 50.00% | 1 50.00% 100.00%
-system.ruby.TCP_Controller.I.Atomic::total 2
-system.ruby.TCP_Controller.I.Flush | 766 50.00% 50.00% | 766 50.00% 100.00%
-system.ruby.TCP_Controller.I.Flush::total 1532
-system.ruby.TCP_Controller.I.Evict | 510 50.00% 50.00% | 510 50.00% 100.00%
-system.ruby.TCP_Controller.I.Evict::total 1020
-system.ruby.TCP_Controller.I.TCC_Ack | 2 50.00% 50.00% | 2 50.00% 100.00%
-system.ruby.TCP_Controller.I.TCC_Ack::total 4
-system.ruby.TCP_Controller.I.TCC_AckWB | 8 50.00% 50.00% | 8 50.00% 100.00%
-system.ruby.TCP_Controller.I.TCC_AckWB::total 16
-system.ruby.TCP_Controller.V.Load | 3 50.00% 50.00% | 3 50.00% 100.00%
-system.ruby.TCP_Controller.V.Load::total 6
-system.ruby.TCP_Controller.V.Flush | 2 50.00% 50.00% | 2 50.00% 100.00%
-system.ruby.TCP_Controller.V.Flush::total 4
-system.ruby.TCP_Controller.V.Evict | 2 50.00% 50.00% | 2 50.00% 100.00%
-system.ruby.TCP_Controller.V.Evict::total 4
-system.ruby.TCP_Controller.A.TCC_Ack | 1 50.00% 50.00% | 1 50.00% 100.00%
-system.ruby.TCP_Controller.A.TCC_Ack::total 2
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cp_cntrl0 cpu0 cpu1 cpu2 dir_cntrl0 dispatcher_coalescer dispatcher_tlb dvfs_handler l1_coalescer0 l1_coalescer1 l1_tlb0 l1_tlb1 l2_coalescer l2_tlb l3_coalescer l3_tlb mem_ctrls piobus ruby sqc_cntrl0 sqc_coalescer sqc_tlb sys_port_proxy tcc_cntrl0 tcp_cntrl0 tcp_cntrl1 voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:536870911
-memories=system.mem_ctrls system.ruby.phys_mem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.sys_port_proxy.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cp_cntrl0]
-type=CorePair_Controller
-children=L1D0cache L1D1cache L1Icache L2cache mandatoryQueue probeToCore requestFromCore responseFromCore responseToCore sequencer sequencer1 triggerQueue unblockFromCore
-L1D0cache=system.cp_cntrl0.L1D0cache
-L1D1cache=system.cp_cntrl0.L1D1cache
-L1Icache=system.cp_cntrl0.L1Icache
-L2cache=system.cp_cntrl0.L2cache
-buffer_size=0
-clk_domain=system.clk_domain
-cluster_id=0
-eventq_index=0
-issue_latency=120
-l2_hit_latency=18
-mandatoryQueue=system.cp_cntrl0.mandatoryQueue
-number_of_TBEs=256
-probeToCore=system.cp_cntrl0.probeToCore
-recycle_latency=10
-requestFromCore=system.cp_cntrl0.requestFromCore
-responseFromCore=system.cp_cntrl0.responseFromCore
-responseToCore=system.cp_cntrl0.responseToCore
-ruby_system=system.ruby
-send_evictions=true
-sequencer=system.cp_cntrl0.sequencer
-sequencer1=system.cp_cntrl0.sequencer1
-system=system
-transitions_per_cycle=32
-triggerQueue=system.cp_cntrl0.triggerQueue
-unblockFromCore=system.cp_cntrl0.unblockFromCore
-version=0
-
-[system.cp_cntrl0.L1D0cache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=2
-eventq_index=0
-is_icache=false
-replacement_policy=system.cp_cntrl0.L1D0cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=65536
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=2
-
-[system.cp_cntrl0.L1D0cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=65536
-
-[system.cp_cntrl0.L1D1cache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=2
-eventq_index=0
-is_icache=false
-replacement_policy=system.cp_cntrl0.L1D1cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=65536
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=2
-
-[system.cp_cntrl0.L1D1cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=65536
-
-[system.cp_cntrl0.L1Icache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=2
-eventq_index=0
-is_icache=false
-replacement_policy=system.cp_cntrl0.L1Icache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=32768
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=2
-
-[system.cp_cntrl0.L1Icache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=32768
-
-[system.cp_cntrl0.L2cache]
-type=RubyCache
-children=replacement_policy
-assoc=8
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=16
-eventq_index=0
-is_icache=false
-replacement_policy=system.cp_cntrl0.L2cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=2097152
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=16
-
-[system.cp_cntrl0.L2cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=8
-block_size=64
-eventq_index=0
-size=2097152
-
-[system.cp_cntrl0.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.cp_cntrl0.probeToCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[3]
-
-[system.cp_cntrl0.requestFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[2]
-
-[system.cp_cntrl0.responseFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[3]
-
-[system.cp_cntrl0.responseToCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[4]
-
-[system.cp_cntrl0.sequencer]
-type=RubySequencer
-clk_domain=system.clk_domain
-coreid=0
-dcache=system.cp_cntrl0.L1D0cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-eventq_index=0
-icache=system.cp_cntrl0.L1Icache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=0
-master=system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave
-mem_master_port=system.piobus.slave[0]
-slave=system.cpu0.icache_port system.cpu0.dcache_port system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.interrupts.int_master
-
-[system.cp_cntrl0.sequencer1]
-type=RubySequencer
-clk_domain=system.clk_domain
-coreid=1
-dcache=system.cp_cntrl0.L1D1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-eventq_index=0
-icache=system.cp_cntrl0.L1Icache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=1
-
-[system.cp_cntrl0.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.cp_cntrl0.unblockFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[4]
-
-[system.cpu0]
-type=TimingSimpleCPU
-children=apic_clk_domain clk_domain dtb interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu0.clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu0.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu0.tracer
-workload=system.cpu0.workload
-dcache_port=system.cp_cntrl0.sequencer.slave[1]
-icache_port=system.cp_cntrl0.sequencer.slave[0]
-
-[system.cpu0.apic_clk_domain]
-type=DerivedClockDomain
-clk_divider=16
-clk_domain=system.cpu0.clk_domain
-eventq_index=0
-
-[system.cpu0.clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0.dtb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu0.dtb.walker
-
-[system.cpu0.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu0.clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-port=system.cp_cntrl0.sequencer.slave[3]
-
-[system.cpu0.interrupts]
-type=X86LocalApic
-clk_domain=system.cpu0.apic_clk_domain
-eventq_index=0
-int_latency=1000
-pio_addr=2305843009213693952
-pio_latency=100000
-system=system
-int_master=system.cp_cntrl0.sequencer.slave[4]
-int_slave=system.cp_cntrl0.sequencer.master[1]
-pio=system.cp_cntrl0.sequencer.master[0]
-
-[system.cpu0.isa]
-type=X86ISA
-eventq_index=0
-
-[system.cpu0.itb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu0.itb.walker
-
-[system.cpu0.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu0.clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-port=system.cp_cntrl0.sequencer.slave[2]
-
-[system.cpu0.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu0.workload]
-type=LiveProcess
-cmd=gpu-hello
-cwd=
-drivers=system.cpu2.cl_driver
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello
-gid=100
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu1]
-type=Shader
-children=CUs0 CUs1 clk_domain
-CUs=system.cpu1.CUs0 system.cpu1.CUs1
-clk_domain=system.cpu1.clk_domain
-cpu_pointer=system.cpu0
-eventq_index=0
-globalmem=65536
-impl_kern_boundary_sync=true
-n_wf=8
-separate_acquire_release=false
-timing=true
-translation=false
-
-[system.cpu1.CUs0]
-type=ComputeUnit
-children=ldsBus localDataStore vector_register_file0 vector_register_file1 vector_register_file2 vector_register_file3 wavefronts00 wavefronts01 wavefronts02 wavefronts03 wavefronts04 wavefronts05 wavefronts06 wavefronts07 wavefronts08 wavefronts09 wavefronts10 wavefronts11 wavefronts12 wavefronts13 wavefronts14 wavefronts15 wavefronts16 wavefronts17 wavefronts18 wavefronts19 wavefronts20 wavefronts21 wavefronts22 wavefronts23 wavefronts24 wavefronts25 wavefronts26 wavefronts27 wavefronts28 wavefronts29 wavefronts30 wavefronts31
-clk_domain=system.cpu1.clk_domain
-coalescer_to_vrf_bus_width=32
-countPages=false
-cu_id=0
-debugSegFault=false
-dpbypass_pipe_length=4
-eventq_index=0
-execPolicy=OLDEST-FIRST
-functionalTLB=true
-global_mem_queue_size=256
-issue_period=4
-localDataStore=system.cpu1.CUs0.localDataStore
-localMemBarrier=false
-local_mem_queue_size=256
-mem_req_latency=9
-mem_resp_latency=9
-n_wf=8
-num_SIMDs=4
-num_global_mem_pipes=1
-num_shared_mem_pipes=1
-perLaneTLB=false
-prefetch_depth=0
-prefetch_prev_type=PF_PHASE
-prefetch_stride=1
-spbypass_pipe_length=4
-system=system
-vector_register_file=system.cpu1.CUs0.vector_register_file0 system.cpu1.CUs0.vector_register_file1 system.cpu1.CUs0.vector_register_file2 system.cpu1.CUs0.vector_register_file3
-vrf_to_coalescer_bus_width=32
-wavefronts=system.cpu1.CUs0.wavefronts00 system.cpu1.CUs0.wavefronts01 system.cpu1.CUs0.wavefronts02 system.cpu1.CUs0.wavefronts03 system.cpu1.CUs0.wavefronts04 system.cpu1.CUs0.wavefronts05 system.cpu1.CUs0.wavefronts06 system.cpu1.CUs0.wavefronts07 system.cpu1.CUs0.wavefronts08 system.cpu1.CUs0.wavefronts09 system.cpu1.CUs0.wavefronts10 system.cpu1.CUs0.wavefronts11 system.cpu1.CUs0.wavefronts12 system.cpu1.CUs0.wavefronts13 system.cpu1.CUs0.wavefronts14 system.cpu1.CUs0.wavefronts15 system.cpu1.CUs0.wavefronts16 system.cpu1.CUs0.wavefronts17 system.cpu1.CUs0.wavefronts18 system.cpu1.CUs0.wavefronts19 system.cpu1.CUs0.wavefronts20 system.cpu1.CUs0.wavefronts21 system.cpu1.CUs0.wavefronts22 system.cpu1.CUs0.wavefronts23 system.cpu1.CUs0.wavefronts24 system.cpu1.CUs0.wavefronts25 system.cpu1.CUs0.wavefronts26 system.cpu1.CUs0.wavefronts27 system.cpu1.CUs0.wavefronts28 system.cpu1.CUs0.wavefronts29 system.cpu1.CUs0.wavefronts30 system.cpu1.CUs0.wavefronts31
-wfSize=64
-xactCasMode=false
-ldsPort=system.cpu1.CUs0.ldsBus.slave
-memory_port=system.tcp_cntrl0.coalescer.slave[0] system.tcp_cntrl0.coalescer.slave[1] system.tcp_cntrl0.coalescer.slave[2] system.tcp_cntrl0.coalescer.slave[3] system.tcp_cntrl0.coalescer.slave[4] system.tcp_cntrl0.coalescer.slave[5] system.tcp_cntrl0.coalescer.slave[6] system.tcp_cntrl0.coalescer.slave[7] system.tcp_cntrl0.coalescer.slave[8] system.tcp_cntrl0.coalescer.slave[9] system.tcp_cntrl0.coalescer.slave[10] system.tcp_cntrl0.coalescer.slave[11] system.tcp_cntrl0.coalescer.slave[12] system.tcp_cntrl0.coalescer.slave[13] system.tcp_cntrl0.coalescer.slave[14] system.tcp_cntrl0.coalescer.slave[15] system.tcp_cntrl0.coalescer.slave[16] system.tcp_cntrl0.coalescer.slave[17] system.tcp_cntrl0.coalescer.slave[18] system.tcp_cntrl0.coalescer.slave[19] system.tcp_cntrl0.coalescer.slave[20] system.tcp_cntrl0.coalescer.slave[21] system.tcp_cntrl0.coalescer.slave[22] system.tcp_cntrl0.coalescer.slave[23] system.tcp_cntrl0.coalescer.slave[24] system.tcp_cntrl0.coalescer.slave[25] system.tcp_cntrl0.coalescer.slave[26] system.tcp_cntrl0.coalescer.slave[27] system.tcp_cntrl0.coalescer.slave[28] system.tcp_cntrl0.coalescer.slave[29] system.tcp_cntrl0.coalescer.slave[30] system.tcp_cntrl0.coalescer.slave[31] system.tcp_cntrl0.coalescer.slave[32] system.tcp_cntrl0.coalescer.slave[33] system.tcp_cntrl0.coalescer.slave[34] system.tcp_cntrl0.coalescer.slave[35] system.tcp_cntrl0.coalescer.slave[36] system.tcp_cntrl0.coalescer.slave[37] system.tcp_cntrl0.coalescer.slave[38] system.tcp_cntrl0.coalescer.slave[39] system.tcp_cntrl0.coalescer.slave[40] system.tcp_cntrl0.coalescer.slave[41] system.tcp_cntrl0.coalescer.slave[42] system.tcp_cntrl0.coalescer.slave[43] system.tcp_cntrl0.coalescer.slave[44] system.tcp_cntrl0.coalescer.slave[45] system.tcp_cntrl0.coalescer.slave[46] system.tcp_cntrl0.coalescer.slave[47] system.tcp_cntrl0.coalescer.slave[48] system.tcp_cntrl0.coalescer.slave[49] system.tcp_cntrl0.coalescer.slave[50] system.tcp_cntrl0.coalescer.slave[51] system.tcp_cntrl0.coalescer.slave[52] system.tcp_cntrl0.coalescer.slave[53] system.tcp_cntrl0.coalescer.slave[54] system.tcp_cntrl0.coalescer.slave[55] system.tcp_cntrl0.coalescer.slave[56] system.tcp_cntrl0.coalescer.slave[57] system.tcp_cntrl0.coalescer.slave[58] system.tcp_cntrl0.coalescer.slave[59] system.tcp_cntrl0.coalescer.slave[60] system.tcp_cntrl0.coalescer.slave[61] system.tcp_cntrl0.coalescer.slave[62] system.tcp_cntrl0.coalescer.slave[63]
-sqc_port=system.sqc_cntrl0.sequencer.slave[0]
-sqc_tlb_port=system.sqc_coalescer.slave[0]
-translation_port=system.l1_coalescer0.slave[0]
-
-[system.cpu1.CUs0.ldsBus]
-type=Bridge
-clk_domain=system.cpu1.clk_domain
-delay=0
-eventq_index=0
-ranges=0:18446744073709551615
-req_size=16
-resp_size=16
-master=system.cpu1.CUs0.localDataStore.cuPort
-slave=system.cpu1.CUs0.ldsPort
-
-[system.cpu1.CUs0.localDataStore]
-type=LdsState
-bankConflictPenalty=1
-banks=32
-clk_domain=system.cpu1.clk_domain
-eventq_index=0
-range=0:65535
-size=65536
-cuPort=system.cpu1.CUs0.ldsBus.master
-
-[system.cpu1.CUs0.vector_register_file0]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=0
-
-[system.cpu1.CUs0.vector_register_file1]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=1
-
-[system.cpu1.CUs0.vector_register_file2]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=2
-
-[system.cpu1.CUs0.vector_register_file3]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=3
-
-[system.cpu1.CUs0.wavefronts00]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=0
-
-[system.cpu1.CUs0.wavefronts01]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=1
-
-[system.cpu1.CUs0.wavefronts02]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=2
-
-[system.cpu1.CUs0.wavefronts03]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=3
-
-[system.cpu1.CUs0.wavefronts04]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=4
-
-[system.cpu1.CUs0.wavefronts05]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=5
-
-[system.cpu1.CUs0.wavefronts06]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=6
-
-[system.cpu1.CUs0.wavefronts07]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=7
-
-[system.cpu1.CUs0.wavefronts08]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=0
-
-[system.cpu1.CUs0.wavefronts09]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=1
-
-[system.cpu1.CUs0.wavefronts10]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=2
-
-[system.cpu1.CUs0.wavefronts11]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=3
-
-[system.cpu1.CUs0.wavefronts12]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=4
-
-[system.cpu1.CUs0.wavefronts13]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=5
-
-[system.cpu1.CUs0.wavefronts14]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=6
-
-[system.cpu1.CUs0.wavefronts15]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=7
-
-[system.cpu1.CUs0.wavefronts16]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=0
-
-[system.cpu1.CUs0.wavefronts17]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=1
-
-[system.cpu1.CUs0.wavefronts18]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=2
-
-[system.cpu1.CUs0.wavefronts19]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=3
-
-[system.cpu1.CUs0.wavefronts20]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=4
-
-[system.cpu1.CUs0.wavefronts21]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=5
-
-[system.cpu1.CUs0.wavefronts22]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=6
-
-[system.cpu1.CUs0.wavefronts23]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=7
-
-[system.cpu1.CUs0.wavefronts24]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=0
-
-[system.cpu1.CUs0.wavefronts25]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=1
-
-[system.cpu1.CUs0.wavefronts26]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=2
-
-[system.cpu1.CUs0.wavefronts27]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=3
-
-[system.cpu1.CUs0.wavefronts28]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=4
-
-[system.cpu1.CUs0.wavefronts29]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=5
-
-[system.cpu1.CUs0.wavefronts30]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=6
-
-[system.cpu1.CUs0.wavefronts31]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=7
-
-[system.cpu1.CUs1]
-type=ComputeUnit
-children=ldsBus localDataStore vector_register_file0 vector_register_file1 vector_register_file2 vector_register_file3 wavefronts00 wavefronts01 wavefronts02 wavefronts03 wavefronts04 wavefronts05 wavefronts06 wavefronts07 wavefronts08 wavefronts09 wavefronts10 wavefronts11 wavefronts12 wavefronts13 wavefronts14 wavefronts15 wavefronts16 wavefronts17 wavefronts18 wavefronts19 wavefronts20 wavefronts21 wavefronts22 wavefronts23 wavefronts24 wavefronts25 wavefronts26 wavefronts27 wavefronts28 wavefronts29 wavefronts30 wavefronts31
-clk_domain=system.cpu1.clk_domain
-coalescer_to_vrf_bus_width=32
-countPages=false
-cu_id=1
-debugSegFault=false
-dpbypass_pipe_length=4
-eventq_index=0
-execPolicy=OLDEST-FIRST
-functionalTLB=true
-global_mem_queue_size=256
-issue_period=4
-localDataStore=system.cpu1.CUs1.localDataStore
-localMemBarrier=false
-local_mem_queue_size=256
-mem_req_latency=9
-mem_resp_latency=9
-n_wf=8
-num_SIMDs=4
-num_global_mem_pipes=1
-num_shared_mem_pipes=1
-perLaneTLB=false
-prefetch_depth=0
-prefetch_prev_type=PF_PHASE
-prefetch_stride=1
-spbypass_pipe_length=4
-system=system
-vector_register_file=system.cpu1.CUs1.vector_register_file0 system.cpu1.CUs1.vector_register_file1 system.cpu1.CUs1.vector_register_file2 system.cpu1.CUs1.vector_register_file3
-vrf_to_coalescer_bus_width=32
-wavefronts=system.cpu1.CUs1.wavefronts00 system.cpu1.CUs1.wavefronts01 system.cpu1.CUs1.wavefronts02 system.cpu1.CUs1.wavefronts03 system.cpu1.CUs1.wavefronts04 system.cpu1.CUs1.wavefronts05 system.cpu1.CUs1.wavefronts06 system.cpu1.CUs1.wavefronts07 system.cpu1.CUs1.wavefronts08 system.cpu1.CUs1.wavefronts09 system.cpu1.CUs1.wavefronts10 system.cpu1.CUs1.wavefronts11 system.cpu1.CUs1.wavefronts12 system.cpu1.CUs1.wavefronts13 system.cpu1.CUs1.wavefronts14 system.cpu1.CUs1.wavefronts15 system.cpu1.CUs1.wavefronts16 system.cpu1.CUs1.wavefronts17 system.cpu1.CUs1.wavefronts18 system.cpu1.CUs1.wavefronts19 system.cpu1.CUs1.wavefronts20 system.cpu1.CUs1.wavefronts21 system.cpu1.CUs1.wavefronts22 system.cpu1.CUs1.wavefronts23 system.cpu1.CUs1.wavefronts24 system.cpu1.CUs1.wavefronts25 system.cpu1.CUs1.wavefronts26 system.cpu1.CUs1.wavefronts27 system.cpu1.CUs1.wavefronts28 system.cpu1.CUs1.wavefronts29 system.cpu1.CUs1.wavefronts30 system.cpu1.CUs1.wavefronts31
-wfSize=64
-xactCasMode=false
-ldsPort=system.cpu1.CUs1.ldsBus.slave
-memory_port=system.tcp_cntrl1.coalescer.slave[0] system.tcp_cntrl1.coalescer.slave[1] system.tcp_cntrl1.coalescer.slave[2] system.tcp_cntrl1.coalescer.slave[3] system.tcp_cntrl1.coalescer.slave[4] system.tcp_cntrl1.coalescer.slave[5] system.tcp_cntrl1.coalescer.slave[6] system.tcp_cntrl1.coalescer.slave[7] system.tcp_cntrl1.coalescer.slave[8] system.tcp_cntrl1.coalescer.slave[9] system.tcp_cntrl1.coalescer.slave[10] system.tcp_cntrl1.coalescer.slave[11] system.tcp_cntrl1.coalescer.slave[12] system.tcp_cntrl1.coalescer.slave[13] system.tcp_cntrl1.coalescer.slave[14] system.tcp_cntrl1.coalescer.slave[15] system.tcp_cntrl1.coalescer.slave[16] system.tcp_cntrl1.coalescer.slave[17] system.tcp_cntrl1.coalescer.slave[18] system.tcp_cntrl1.coalescer.slave[19] system.tcp_cntrl1.coalescer.slave[20] system.tcp_cntrl1.coalescer.slave[21] system.tcp_cntrl1.coalescer.slave[22] system.tcp_cntrl1.coalescer.slave[23] system.tcp_cntrl1.coalescer.slave[24] system.tcp_cntrl1.coalescer.slave[25] system.tcp_cntrl1.coalescer.slave[26] system.tcp_cntrl1.coalescer.slave[27] system.tcp_cntrl1.coalescer.slave[28] system.tcp_cntrl1.coalescer.slave[29] system.tcp_cntrl1.coalescer.slave[30] system.tcp_cntrl1.coalescer.slave[31] system.tcp_cntrl1.coalescer.slave[32] system.tcp_cntrl1.coalescer.slave[33] system.tcp_cntrl1.coalescer.slave[34] system.tcp_cntrl1.coalescer.slave[35] system.tcp_cntrl1.coalescer.slave[36] system.tcp_cntrl1.coalescer.slave[37] system.tcp_cntrl1.coalescer.slave[38] system.tcp_cntrl1.coalescer.slave[39] system.tcp_cntrl1.coalescer.slave[40] system.tcp_cntrl1.coalescer.slave[41] system.tcp_cntrl1.coalescer.slave[42] system.tcp_cntrl1.coalescer.slave[43] system.tcp_cntrl1.coalescer.slave[44] system.tcp_cntrl1.coalescer.slave[45] system.tcp_cntrl1.coalescer.slave[46] system.tcp_cntrl1.coalescer.slave[47] system.tcp_cntrl1.coalescer.slave[48] system.tcp_cntrl1.coalescer.slave[49] system.tcp_cntrl1.coalescer.slave[50] system.tcp_cntrl1.coalescer.slave[51] system.tcp_cntrl1.coalescer.slave[52] system.tcp_cntrl1.coalescer.slave[53] system.tcp_cntrl1.coalescer.slave[54] system.tcp_cntrl1.coalescer.slave[55] system.tcp_cntrl1.coalescer.slave[56] system.tcp_cntrl1.coalescer.slave[57] system.tcp_cntrl1.coalescer.slave[58] system.tcp_cntrl1.coalescer.slave[59] system.tcp_cntrl1.coalescer.slave[60] system.tcp_cntrl1.coalescer.slave[61] system.tcp_cntrl1.coalescer.slave[62] system.tcp_cntrl1.coalescer.slave[63]
-sqc_port=system.sqc_cntrl0.sequencer.slave[1]
-sqc_tlb_port=system.sqc_coalescer.slave[1]
-translation_port=system.l1_coalescer1.slave[0]
-
-[system.cpu1.CUs1.ldsBus]
-type=Bridge
-clk_domain=system.cpu1.clk_domain
-delay=0
-eventq_index=0
-ranges=0:18446744073709551615
-req_size=16
-resp_size=16
-master=system.cpu1.CUs1.localDataStore.cuPort
-slave=system.cpu1.CUs1.ldsPort
-
-[system.cpu1.CUs1.localDataStore]
-type=LdsState
-bankConflictPenalty=1
-banks=32
-clk_domain=system.cpu1.clk_domain
-eventq_index=0
-range=0:65535
-size=65536
-cuPort=system.cpu1.CUs1.ldsBus.master
-
-[system.cpu1.CUs1.vector_register_file0]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=0
-
-[system.cpu1.CUs1.vector_register_file1]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=1
-
-[system.cpu1.CUs1.vector_register_file2]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=2
-
-[system.cpu1.CUs1.vector_register_file3]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=3
-
-[system.cpu1.CUs1.wavefronts00]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=0
-
-[system.cpu1.CUs1.wavefronts01]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=1
-
-[system.cpu1.CUs1.wavefronts02]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=2
-
-[system.cpu1.CUs1.wavefronts03]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=3
-
-[system.cpu1.CUs1.wavefronts04]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=4
-
-[system.cpu1.CUs1.wavefronts05]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=5
-
-[system.cpu1.CUs1.wavefronts06]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=6
-
-[system.cpu1.CUs1.wavefronts07]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=7
-
-[system.cpu1.CUs1.wavefronts08]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=0
-
-[system.cpu1.CUs1.wavefronts09]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=1
-
-[system.cpu1.CUs1.wavefronts10]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=2
-
-[system.cpu1.CUs1.wavefronts11]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=3
-
-[system.cpu1.CUs1.wavefronts12]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=4
-
-[system.cpu1.CUs1.wavefronts13]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=5
-
-[system.cpu1.CUs1.wavefronts14]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=6
-
-[system.cpu1.CUs1.wavefronts15]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=7
-
-[system.cpu1.CUs1.wavefronts16]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=0
-
-[system.cpu1.CUs1.wavefronts17]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=1
-
-[system.cpu1.CUs1.wavefronts18]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=2
-
-[system.cpu1.CUs1.wavefronts19]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=3
-
-[system.cpu1.CUs1.wavefronts20]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=4
-
-[system.cpu1.CUs1.wavefronts21]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=5
-
-[system.cpu1.CUs1.wavefronts22]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=6
-
-[system.cpu1.CUs1.wavefronts23]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=7
-
-[system.cpu1.CUs1.wavefronts24]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=0
-
-[system.cpu1.CUs1.wavefronts25]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=1
-
-[system.cpu1.CUs1.wavefronts26]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=2
-
-[system.cpu1.CUs1.wavefronts27]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=3
-
-[system.cpu1.CUs1.wavefronts28]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=4
-
-[system.cpu1.CUs1.wavefronts29]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=5
-
-[system.cpu1.CUs1.wavefronts30]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=6
-
-[system.cpu1.CUs1.wavefronts31]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=7
-
-[system.cpu1.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.cpu1.clk_domain.voltage_domain
-
-[system.cpu1.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.cpu2]
-type=GpuDispatcher
-children=cl_driver
-cl_driver=system.cpu2.cl_driver
-clk_domain=system.clk_domain
-cpu=system.cpu0
-eventq_index=0
-pio_addr=8589934592
-pio_latency=1000
-shader_pointer=system.cpu1
-system=system
-dma=system.piobus.slave[1]
-pio=system.piobus.master[0]
-translation_port=system.dispatcher_coalescer.slave[0]
-
-[system.cpu2.cl_driver]
-type=ClDriver
-codefile=/dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm
-eventq_index=0
-filename=hsa
-
-[system.dir_cntrl0]
-type=Directory_Controller
-children=L3CacheMemory L3triggerQueue ProbeFilterMemory directory probeToCore requestFromCores responseFromCores responseFromMemory responseToCore triggerQueue unblockFromCores
-CAB_TCC=false
-L3CacheMemory=system.dir_cntrl0.L3CacheMemory
-L3triggerQueue=system.dir_cntrl0.L3triggerQueue
-ProbeFilterMemory=system.dir_cntrl0.ProbeFilterMemory
-TCC_select_num_bits=0
-buffer_size=0
-clk_domain=system.clk_domain
-cluster_id=0
-directory=system.dir_cntrl0.directory
-eventq_index=0
-inclusiveDir=true
-l3_hit_latency=15
-noTCCdir=true
-number_of_TBEs=2560
-probeToCore=system.dir_cntrl0.probeToCore
-recycle_latency=10
-requestFromCores=system.dir_cntrl0.requestFromCores
-responseFromCores=system.dir_cntrl0.responseFromCores
-responseFromMemory=system.dir_cntrl0.responseFromMemory
-responseToCore=system.dir_cntrl0.responseToCore
-response_latency=30
-ruby_system=system.ruby
-system=system
-to_memory_controller_latency=1
-transitions_per_cycle=32
-triggerQueue=system.dir_cntrl0.triggerQueue
-unblockFromCores=system.dir_cntrl0.unblockFromCores
-useL3OnWT=false
-version=0
-memory=system.mem_ctrls.port
-
-[system.dir_cntrl0.L3CacheMemory]
-type=RubyCache
-children=replacement_policy
-assoc=16
-block_size=0
-dataAccessLatency=20
-dataArrayBanks=16.0
-eventq_index=0
-is_icache=false
-replacement_policy=system.dir_cntrl0.L3CacheMemory.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=16777216
-start_index_bit=6
-tagAccessLatency=15
-tagArrayBanks=16.0
-
-[system.dir_cntrl0.L3CacheMemory.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=16
-block_size=64
-eventq_index=0
-size=16777216
-
-[system.dir_cntrl0.L3triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.dir_cntrl0.ProbeFilterMemory]
-type=RubyCache
-children=replacement_policy
-assoc=8
-block_size=64
-dataAccessLatency=1
-dataArrayBanks=256
-eventq_index=0
-is_icache=false
-replacement_policy=system.dir_cntrl0.ProbeFilterMemory.replacement_policy
-resourceStalls=true
-ruby_system=system.ruby
-size=1048576
-start_index_bit=6
-tagAccessLatency=8
-tagArrayBanks=8
-
-[system.dir_cntrl0.ProbeFilterMemory.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=8
-block_size=64
-eventq_index=0
-size=1048576
-
-[system.dir_cntrl0.directory]
-type=RubyDirectoryMemory
-eventq_index=0
-numa_high_bit=5
-size=536870912
-version=0
-
-[system.dir_cntrl0.probeToCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[0]
-
-[system.dir_cntrl0.requestFromCores]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[0]
-
-[system.dir_cntrl0.responseFromCores]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[1]
-
-[system.dir_cntrl0.responseFromMemory]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.dir_cntrl0.responseToCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[1]
-
-[system.dir_cntrl0.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.dir_cntrl0.unblockFromCores]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[2]
-
-[system.dispatcher_coalescer]
-type=TLBCoalescer
-children=clk_domain
-clk_domain=system.dispatcher_coalescer.clk_domain
-coalescingWindow=1
-disableCoalescing=false
-eventq_index=0
-probesPerCycle=2
-master=system.dispatcher_tlb.slave[0]
-slave=system.cpu2.translation_port
-
-[system.dispatcher_coalescer.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.dispatcher_coalescer.clk_domain.voltage_domain
-
-[system.dispatcher_coalescer.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.dispatcher_tlb]
-type=X86GPUTLB
-children=clk_domain
-accessDistance=false
-allocationPolicy=true
-assoc=32
-clk_domain=system.dispatcher_tlb.clk_domain
-eventq_index=0
-hitLatency=1
-maxOutstandingReqs=64
-missLatency1=5
-missLatency2=750
-size=32
-master=system.l2_coalescer.slave[1]
-slave=system.dispatcher_coalescer.master[0]
-
-[system.dispatcher_tlb.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.dispatcher_tlb.clk_domain.voltage_domain
-
-[system.dispatcher_tlb.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.l1_coalescer0]
-type=TLBCoalescer
-children=clk_domain
-clk_domain=system.l1_coalescer0.clk_domain
-coalescingWindow=1
-disableCoalescing=false
-eventq_index=0
-probesPerCycle=2
-master=system.l1_tlb0.slave[0]
-slave=system.cpu1.CUs0.translation_port[0]
-
-[system.l1_coalescer0.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l1_coalescer0.clk_domain.voltage_domain
-
-[system.l1_coalescer0.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l1_coalescer1]
-type=TLBCoalescer
-children=clk_domain
-clk_domain=system.l1_coalescer1.clk_domain
-coalescingWindow=1
-disableCoalescing=false
-eventq_index=0
-probesPerCycle=2
-master=system.l1_tlb1.slave[0]
-slave=system.cpu1.CUs1.translation_port[0]
-
-[system.l1_coalescer1.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l1_coalescer1.clk_domain.voltage_domain
-
-[system.l1_coalescer1.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l1_tlb0]
-type=X86GPUTLB
-children=clk_domain
-accessDistance=false
-allocationPolicy=true
-assoc=32
-clk_domain=system.l1_tlb0.clk_domain
-eventq_index=0
-hitLatency=1
-maxOutstandingReqs=64
-missLatency1=5
-missLatency2=750
-size=32
-master=system.l2_coalescer.slave[2]
-slave=system.l1_coalescer0.master[0]
-
-[system.l1_tlb0.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l1_tlb0.clk_domain.voltage_domain
-
-[system.l1_tlb0.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l1_tlb1]
-type=X86GPUTLB
-children=clk_domain
-accessDistance=false
-allocationPolicy=true
-assoc=32
-clk_domain=system.l1_tlb1.clk_domain
-eventq_index=0
-hitLatency=1
-maxOutstandingReqs=64
-missLatency1=5
-missLatency2=750
-size=32
-master=system.l2_coalescer.slave[3]
-slave=system.l1_coalescer1.master[0]
-
-[system.l1_tlb1.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l1_tlb1.clk_domain.voltage_domain
-
-[system.l1_tlb1.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l2_coalescer]
-type=TLBCoalescer
-children=clk_domain
-clk_domain=system.l2_coalescer.clk_domain
-coalescingWindow=1
-disableCoalescing=false
-eventq_index=0
-probesPerCycle=2
-master=system.l2_tlb.slave[0]
-slave=system.sqc_tlb.master[0] system.dispatcher_tlb.master[0] system.l1_tlb0.master[0] system.l1_tlb1.master[0]
-
-[system.l2_coalescer.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l2_coalescer.clk_domain.voltage_domain
-
-[system.l2_coalescer.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l2_tlb]
-type=X86GPUTLB
-children=clk_domain
-accessDistance=false
-allocationPolicy=true
-assoc=32
-clk_domain=system.l2_tlb.clk_domain
-eventq_index=0
-hitLatency=69
-maxOutstandingReqs=64
-missLatency1=5
-missLatency2=750
-size=4096
-master=system.l3_coalescer.slave[0]
-slave=system.l2_coalescer.master[0]
-
-[system.l2_tlb.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l2_tlb.clk_domain.voltage_domain
-
-[system.l2_tlb.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l3_coalescer]
-type=TLBCoalescer
-children=clk_domain
-clk_domain=system.l3_coalescer.clk_domain
-coalescingWindow=1
-disableCoalescing=false
-eventq_index=0
-probesPerCycle=2
-master=system.l3_tlb.slave[0]
-slave=system.l2_tlb.master[0]
-
-[system.l3_coalescer.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l3_coalescer.clk_domain.voltage_domain
-
-[system.l3_coalescer.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l3_tlb]
-type=X86GPUTLB
-children=clk_domain
-accessDistance=false
-allocationPolicy=true
-assoc=32
-clk_domain=system.l3_tlb.clk_domain
-eventq_index=0
-hitLatency=150
-maxOutstandingReqs=64
-missLatency1=5
-missLatency2=750
-size=8192
-slave=system.l3_coalescer.master[0]
-
-[system.l3_tlb.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l3_tlb.clk_domain.voltage_domain
-
-[system.l3_tlb.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.mem_ctrls]
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-IDD02=0.000000
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-IDD2P02=0.000000
-IDD2P1=0.000000
-IDD2P12=0.000000
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-IDD3N2=0.000000
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-IDD3P02=0.000000
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-IDD3P12=0.000000
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-IDD5=0.220000
-IDD52=0.000000
-IDD6=0.000000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
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-device_bus_width=8
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-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
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-mem_sched_policy=frfcfs
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-null=false
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-static_frontend_latency=10000
-tBURST=5000
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-tCK=1250
-tCL=13750
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-tRCD=13750
-tREFI=7800000
-tRFC=260000
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-tXS=0
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-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.dir_cntrl0.memory
-
-[system.piobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
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-frontend_latency=0
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-use_default_range=false
-width=32
-master=system.cpu2.pio
-slave=system.cp_cntrl0.sequencer.mem_master_port system.cpu2.dma
-
-[system.ruby]
-type=RubySystem
-children=clk_domain network phys_mem
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-clk_domain=system.ruby.clk_domain
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-hot_lines=false
-memory_size_bits=48
-num_of_sequencers=5
-number_of_virtual_networks=10
-phys_mem=system.ruby.phys_mem
-randomization=false
-
-[system.ruby.clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.ruby.network]
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-adaptive_routing=false
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-control_msg_size=8
-endpoint_bandwidth=1000
-eventq_index=0
-ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4 system.ruby.network.ext_links5
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
-netifs=
-number_of_virtual_networks=10
-routers=system.ruby.network.ext_links0.int_node system.ruby.network.ext_links1.int_node system.ruby.network.ext_links2.int_node
-ruby_system=system.ruby
-topology=Crossbar
-master=system.dir_cntrl0.requestFromCores.slave system.dir_cntrl0.responseFromCores.slave system.dir_cntrl0.unblockFromCores.slave system.cp_cntrl0.probeToCore.slave system.cp_cntrl0.responseToCore.slave system.tcp_cntrl0.probeToTCP.slave system.tcp_cntrl0.responseToTCP.slave system.tcp_cntrl1.probeToTCP.slave system.tcp_cntrl1.responseToTCP.slave system.sqc_cntrl0.probeToSQC.slave system.sqc_cntrl0.responseToSQC.slave system.tcc_cntrl0.requestFromTCP.slave system.tcc_cntrl0.probeFromNB.slave system.tcc_cntrl0.responseFromNB.slave
-slave=system.dir_cntrl0.probeToCore.master system.dir_cntrl0.responseToCore.master system.cp_cntrl0.requestFromCore.master system.cp_cntrl0.responseFromCore.master system.cp_cntrl0.unblockFromCore.master system.tcp_cntrl0.requestFromTCP.master system.tcp_cntrl0.responseFromTCP.master system.tcp_cntrl0.unblockFromCore.master system.tcp_cntrl1.requestFromTCP.master system.tcp_cntrl1.responseFromTCP.master system.tcp_cntrl1.unblockFromCore.master system.sqc_cntrl0.requestFromSQC.master system.tcc_cntrl0.responseToCore.master system.tcc_cntrl0.requestToNB.master system.tcc_cntrl0.responseToNB.master system.tcc_cntrl0.unblockToNB.master
-
-[system.ruby.network.ext_links0]
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-latency=1
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-weight=1
-
-[system.ruby.network.ext_links0.int_node]
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-router_id=0
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-
-[system.ruby.network.ext_links0.int_node.port_buffers00]
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-[system.ruby.network.ext_links0.int_node.port_buffers01]
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-[system.ruby.network.ext_links0.int_node.port_buffers02]
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-[system.ruby.network.ext_links0.int_node.port_buffers03]
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-[system.ruby.network.ext_links0.int_node.port_buffers04]
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-[system.ruby.network.ext_links0.int_node.port_buffers05]
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-[system.ruby.network.ext_links0.int_node.port_buffers06]
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-[system.ruby.network.ext_links0.int_node.port_buffers07]
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-[system.ruby.network.ext_links0.int_node.port_buffers08]
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-[system.ruby.network.ext_links0.int_node.port_buffers09]
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-[system.ruby.network.ext_links0.int_node.port_buffers10]
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-[system.ruby.network.ext_links0.int_node.port_buffers11]
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-[system.ruby.network.ext_links0.int_node.port_buffers14]
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-eventq_index=0
-ext_node=system.sqc_cntrl0
-int_node=system.ruby.network.ext_links2.int_node
-latency=1
-link_id=4
-weight=1
-
-[system.ruby.network.ext_links5]
-type=SimpleExtLink
-bandwidth_factor=32
-eventq_index=0
-ext_node=system.tcc_cntrl0
-int_node=system.ruby.network.ext_links2.int_node
-latency=1
-link_id=5
-weight=1
-
-[system.ruby.network.int_link_buffers00]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers01]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers02]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers03]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers04]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers05]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers06]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers07]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers08]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers09]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers10]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers11]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers12]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers13]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers14]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers15]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers16]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers17]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers18]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers19]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers20]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers21]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers22]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers23]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers24]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers25]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers26]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers27]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers28]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers29]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers30]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers31]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers32]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers33]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers34]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers35]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers36]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers37]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers38]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers39]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_links0]
-type=SimpleIntLink
-bandwidth_factor=32
-eventq_index=0
-latency=1
-link_id=0
-node_a=system.ruby.network.ext_links0.int_node
-node_b=system.ruby.network.ext_links1.int_node
-weight=1
-
-[system.ruby.network.int_links1]
-type=SimpleIntLink
-bandwidth_factor=32
-eventq_index=0
-latency=1
-link_id=1
-node_a=system.ruby.network.ext_links0.int_node
-node_b=system.ruby.network.ext_links2.int_node
-weight=1
-
-[system.ruby.phys_mem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.ruby.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=false
-latency=30000
-latency_var=0
-null=false
-range=0:536870911
-
-[system.sqc_cntrl0]
-type=SQC_Controller
-children=L1cache mandatoryQueue probeToSQC requestFromSQC responseToSQC sequencer
-L1cache=system.sqc_cntrl0.L1cache
-TCC_select_num_bits=0
-buffer_size=0
-clk_domain=system.clk_domain
-cluster_id=0
-eventq_index=0
-issue_latency=80
-l2_hit_latency=18
-mandatoryQueue=system.sqc_cntrl0.mandatoryQueue
-number_of_TBEs=256
-probeToSQC=system.sqc_cntrl0.probeToSQC
-recycle_latency=10
-requestFromSQC=system.sqc_cntrl0.requestFromSQC
-responseToSQC=system.sqc_cntrl0.responseToSQC
-ruby_system=system.ruby
-sequencer=system.sqc_cntrl0.sequencer
-system=system
-transitions_per_cycle=32
-version=0
-
-[system.sqc_cntrl0.L1cache]
-type=RubyCache
-children=replacement_policy
-assoc=8
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=8
-eventq_index=0
-is_icache=false
-replacement_policy=system.sqc_cntrl0.L1cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=32768
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=8
-
-[system.sqc_cntrl0.L1cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=8
-block_size=64
-eventq_index=0
-size=32768
-
-[system.sqc_cntrl0.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.sqc_cntrl0.probeToSQC]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[9]
-
-[system.sqc_cntrl0.requestFromSQC]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[11]
-
-[system.sqc_cntrl0.responseToSQC]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[10]
-
-[system.sqc_cntrl0.sequencer]
-type=RubySequencer
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.sqc_cntrl0.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-eventq_index=0
-icache=system.sqc_cntrl0.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=false
-max_outstanding_requests=16
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=false
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=6
-slave=system.cpu1.CUs0.sqc_port system.cpu1.CUs1.sqc_port
-
-[system.sqc_coalescer]
-type=TLBCoalescer
-children=clk_domain
-clk_domain=system.sqc_coalescer.clk_domain
-coalescingWindow=1
-disableCoalescing=false
-eventq_index=0
-probesPerCycle=2
-master=system.sqc_tlb.slave[0]
-slave=system.cpu1.CUs0.sqc_tlb_port system.cpu1.CUs1.sqc_tlb_port
-
-[system.sqc_coalescer.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.sqc_coalescer.clk_domain.voltage_domain
-
-[system.sqc_coalescer.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.sqc_tlb]
-type=X86GPUTLB
-children=clk_domain
-accessDistance=false
-allocationPolicy=true
-assoc=32
-clk_domain=system.sqc_tlb.clk_domain
-eventq_index=0
-hitLatency=1
-maxOutstandingReqs=64
-missLatency1=5
-missLatency2=750
-size=32
-master=system.l2_coalescer.slave[0]
-slave=system.sqc_coalescer.master[0]
-
-[system.sqc_tlb.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.sqc_tlb.clk_domain.voltage_domain
-
-[system.sqc_tlb.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.sys_port_proxy]
-type=RubyPortProxy
-clk_domain=system.clk_domain
-eventq_index=0
-is_cpu_sequencer=true
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=0
-slave=system.system_port
-
-[system.tcc_cntrl0]
-type=TCC_Controller
-children=L2cache probeFromNB requestFromTCP requestToNB responseFromNB responseToCore responseToNB triggerQueue unblockToNB
-L2cache=system.tcc_cntrl0.L2cache
-WB=false
-buffer_size=0
-clk_domain=system.clk_domain
-cluster_id=0
-eventq_index=0
-l2_request_latency=120
-l2_response_latency=16
-number_of_TBEs=5120
-probeFromNB=system.tcc_cntrl0.probeFromNB
-recycle_latency=10
-requestFromTCP=system.tcc_cntrl0.requestFromTCP
-requestToNB=system.tcc_cntrl0.requestToNB
-responseFromNB=system.tcc_cntrl0.responseFromNB
-responseToCore=system.tcc_cntrl0.responseToCore
-responseToNB=system.tcc_cntrl0.responseToNB
-ruby_system=system.ruby
-system=system
-transitions_per_cycle=32
-triggerQueue=system.tcc_cntrl0.triggerQueue
-unblockToNB=system.tcc_cntrl0.unblockToNB
-version=0
-
-[system.tcc_cntrl0.L2cache]
-type=RubyCache
-children=replacement_policy
-assoc=16
-block_size=0
-dataAccessLatency=8
-dataArrayBanks=256
-eventq_index=0
-is_icache=false
-replacement_policy=system.tcc_cntrl0.L2cache.replacement_policy
-resourceStalls=true
-ruby_system=system.ruby
-size=2097152
-start_index_bit=6
-tagAccessLatency=2
-tagArrayBanks=256
-
-[system.tcc_cntrl0.L2cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=16
-block_size=64
-eventq_index=0
-size=2097152
-
-[system.tcc_cntrl0.probeFromNB]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[12]
-
-[system.tcc_cntrl0.requestFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[11]
-
-[system.tcc_cntrl0.requestToNB]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[13]
-
-[system.tcc_cntrl0.responseFromNB]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[13]
-
-[system.tcc_cntrl0.responseToCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[12]
-
-[system.tcc_cntrl0.responseToNB]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[14]
-
-[system.tcc_cntrl0.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.tcc_cntrl0.unblockToNB]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[15]
-
-[system.tcp_cntrl0]
-type=TCP_Controller
-children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore
-L1cache=system.tcp_cntrl0.L1cache
-TCC_select_num_bits=0
-WB=false
-buffer_size=0
-clk_domain=system.clk_domain
-cluster_id=0
-coalescer=system.tcp_cntrl0.coalescer
-disableL1=false
-eventq_index=0
-issue_latency=1
-l2_hit_latency=18
-mandatoryQueue=system.tcp_cntrl0.mandatoryQueue
-number_of_TBEs=2560
-probeToTCP=system.tcp_cntrl0.probeToTCP
-recycle_latency=10
-requestFromTCP=system.tcp_cntrl0.requestFromTCP
-responseFromTCP=system.tcp_cntrl0.responseFromTCP
-responseToTCP=system.tcp_cntrl0.responseToTCP
-ruby_system=system.ruby
-sequencer=system.tcp_cntrl0.sequencer
-system=system
-transitions_per_cycle=32
-unblockFromCore=system.tcp_cntrl0.unblockFromCore
-use_seq_not_coal=false
-version=0
-
-[system.tcp_cntrl0.L1cache]
-type=RubyCache
-children=replacement_policy
-assoc=16
-block_size=0
-dataAccessLatency=4
-dataArrayBanks=16
-eventq_index=0
-is_icache=false
-replacement_policy=system.tcp_cntrl0.L1cache.replacement_policy
-resourceStalls=true
-ruby_system=system.ruby
-size=16384
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=16
-
-[system.tcp_cntrl0.L1cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=16
-block_size=64
-eventq_index=0
-size=16384
-
-[system.tcp_cntrl0.coalescer]
-type=VIPERCoalescer
-assume_rfo=false
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.tcp_cntrl0.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-eventq_index=0
-icache=system.tcp_cntrl0.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=false
-max_inv_per_cycle=32
-max_outstanding_requests=2560
-max_wb_per_cycle=32
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=false
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=2
-slave=system.cpu1.CUs0.memory_port[0] system.cpu1.CUs0.memory_port[1] system.cpu1.CUs0.memory_port[2] system.cpu1.CUs0.memory_port[3] system.cpu1.CUs0.memory_port[4] system.cpu1.CUs0.memory_port[5] system.cpu1.CUs0.memory_port[6] system.cpu1.CUs0.memory_port[7] system.cpu1.CUs0.memory_port[8] system.cpu1.CUs0.memory_port[9] system.cpu1.CUs0.memory_port[10] system.cpu1.CUs0.memory_port[11] system.cpu1.CUs0.memory_port[12] system.cpu1.CUs0.memory_port[13] system.cpu1.CUs0.memory_port[14] system.cpu1.CUs0.memory_port[15] system.cpu1.CUs0.memory_port[16] system.cpu1.CUs0.memory_port[17] system.cpu1.CUs0.memory_port[18] system.cpu1.CUs0.memory_port[19] system.cpu1.CUs0.memory_port[20] system.cpu1.CUs0.memory_port[21] system.cpu1.CUs0.memory_port[22] system.cpu1.CUs0.memory_port[23] system.cpu1.CUs0.memory_port[24] system.cpu1.CUs0.memory_port[25] system.cpu1.CUs0.memory_port[26] system.cpu1.CUs0.memory_port[27] system.cpu1.CUs0.memory_port[28] system.cpu1.CUs0.memory_port[29] system.cpu1.CUs0.memory_port[30] system.cpu1.CUs0.memory_port[31] system.cpu1.CUs0.memory_port[32] system.cpu1.CUs0.memory_port[33] system.cpu1.CUs0.memory_port[34] system.cpu1.CUs0.memory_port[35] system.cpu1.CUs0.memory_port[36] system.cpu1.CUs0.memory_port[37] system.cpu1.CUs0.memory_port[38] system.cpu1.CUs0.memory_port[39] system.cpu1.CUs0.memory_port[40] system.cpu1.CUs0.memory_port[41] system.cpu1.CUs0.memory_port[42] system.cpu1.CUs0.memory_port[43] system.cpu1.CUs0.memory_port[44] system.cpu1.CUs0.memory_port[45] system.cpu1.CUs0.memory_port[46] system.cpu1.CUs0.memory_port[47] system.cpu1.CUs0.memory_port[48] system.cpu1.CUs0.memory_port[49] system.cpu1.CUs0.memory_port[50] system.cpu1.CUs0.memory_port[51] system.cpu1.CUs0.memory_port[52] system.cpu1.CUs0.memory_port[53] system.cpu1.CUs0.memory_port[54] system.cpu1.CUs0.memory_port[55] system.cpu1.CUs0.memory_port[56] system.cpu1.CUs0.memory_port[57] system.cpu1.CUs0.memory_port[58] system.cpu1.CUs0.memory_port[59] system.cpu1.CUs0.memory_port[60] system.cpu1.CUs0.memory_port[61] system.cpu1.CUs0.memory_port[62] system.cpu1.CUs0.memory_port[63]
-
-[system.tcp_cntrl0.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.tcp_cntrl0.probeToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[5]
-
-[system.tcp_cntrl0.requestFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[5]
-
-[system.tcp_cntrl0.responseFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[6]
-
-[system.tcp_cntrl0.responseToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[6]
-
-[system.tcp_cntrl0.sequencer]
-type=RubySequencer
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.tcp_cntrl0.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-eventq_index=0
-icache=system.tcp_cntrl0.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=3
-
-[system.tcp_cntrl0.unblockFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[7]
-
-[system.tcp_cntrl1]
-type=TCP_Controller
-children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore
-L1cache=system.tcp_cntrl1.L1cache
-TCC_select_num_bits=0
-WB=false
-buffer_size=0
-clk_domain=system.clk_domain
-cluster_id=0
-coalescer=system.tcp_cntrl1.coalescer
-disableL1=false
-eventq_index=0
-issue_latency=1
-l2_hit_latency=18
-mandatoryQueue=system.tcp_cntrl1.mandatoryQueue
-number_of_TBEs=2560
-probeToTCP=system.tcp_cntrl1.probeToTCP
-recycle_latency=10
-requestFromTCP=system.tcp_cntrl1.requestFromTCP
-responseFromTCP=system.tcp_cntrl1.responseFromTCP
-responseToTCP=system.tcp_cntrl1.responseToTCP
-ruby_system=system.ruby
-sequencer=system.tcp_cntrl1.sequencer
-system=system
-transitions_per_cycle=32
-unblockFromCore=system.tcp_cntrl1.unblockFromCore
-use_seq_not_coal=false
-version=1
-
-[system.tcp_cntrl1.L1cache]
-type=RubyCache
-children=replacement_policy
-assoc=16
-block_size=0
-dataAccessLatency=4
-dataArrayBanks=16
-eventq_index=0
-is_icache=false
-replacement_policy=system.tcp_cntrl1.L1cache.replacement_policy
-resourceStalls=true
-ruby_system=system.ruby
-size=16384
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=16
-
-[system.tcp_cntrl1.L1cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=16
-block_size=64
-eventq_index=0
-size=16384
-
-[system.tcp_cntrl1.coalescer]
-type=VIPERCoalescer
-assume_rfo=false
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.tcp_cntrl1.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-eventq_index=0
-icache=system.tcp_cntrl1.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=false
-max_inv_per_cycle=32
-max_outstanding_requests=2560
-max_wb_per_cycle=32
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=false
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=4
-slave=system.cpu1.CUs1.memory_port[0] system.cpu1.CUs1.memory_port[1] system.cpu1.CUs1.memory_port[2] system.cpu1.CUs1.memory_port[3] system.cpu1.CUs1.memory_port[4] system.cpu1.CUs1.memory_port[5] system.cpu1.CUs1.memory_port[6] system.cpu1.CUs1.memory_port[7] system.cpu1.CUs1.memory_port[8] system.cpu1.CUs1.memory_port[9] system.cpu1.CUs1.memory_port[10] system.cpu1.CUs1.memory_port[11] system.cpu1.CUs1.memory_port[12] system.cpu1.CUs1.memory_port[13] system.cpu1.CUs1.memory_port[14] system.cpu1.CUs1.memory_port[15] system.cpu1.CUs1.memory_port[16] system.cpu1.CUs1.memory_port[17] system.cpu1.CUs1.memory_port[18] system.cpu1.CUs1.memory_port[19] system.cpu1.CUs1.memory_port[20] system.cpu1.CUs1.memory_port[21] system.cpu1.CUs1.memory_port[22] system.cpu1.CUs1.memory_port[23] system.cpu1.CUs1.memory_port[24] system.cpu1.CUs1.memory_port[25] system.cpu1.CUs1.memory_port[26] system.cpu1.CUs1.memory_port[27] system.cpu1.CUs1.memory_port[28] system.cpu1.CUs1.memory_port[29] system.cpu1.CUs1.memory_port[30] system.cpu1.CUs1.memory_port[31] system.cpu1.CUs1.memory_port[32] system.cpu1.CUs1.memory_port[33] system.cpu1.CUs1.memory_port[34] system.cpu1.CUs1.memory_port[35] system.cpu1.CUs1.memory_port[36] system.cpu1.CUs1.memory_port[37] system.cpu1.CUs1.memory_port[38] system.cpu1.CUs1.memory_port[39] system.cpu1.CUs1.memory_port[40] system.cpu1.CUs1.memory_port[41] system.cpu1.CUs1.memory_port[42] system.cpu1.CUs1.memory_port[43] system.cpu1.CUs1.memory_port[44] system.cpu1.CUs1.memory_port[45] system.cpu1.CUs1.memory_port[46] system.cpu1.CUs1.memory_port[47] system.cpu1.CUs1.memory_port[48] system.cpu1.CUs1.memory_port[49] system.cpu1.CUs1.memory_port[50] system.cpu1.CUs1.memory_port[51] system.cpu1.CUs1.memory_port[52] system.cpu1.CUs1.memory_port[53] system.cpu1.CUs1.memory_port[54] system.cpu1.CUs1.memory_port[55] system.cpu1.CUs1.memory_port[56] system.cpu1.CUs1.memory_port[57] system.cpu1.CUs1.memory_port[58] system.cpu1.CUs1.memory_port[59] system.cpu1.CUs1.memory_port[60] system.cpu1.CUs1.memory_port[61] system.cpu1.CUs1.memory_port[62] system.cpu1.CUs1.memory_port[63]
-
-[system.tcp_cntrl1.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.tcp_cntrl1.probeToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[7]
-
-[system.tcp_cntrl1.requestFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[8]
-
-[system.tcp_cntrl1.responseFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[9]
-
-[system.tcp_cntrl1.responseToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[8]
-
-[system.tcp_cntrl1.sequencer]
-type=RubySequencer
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.tcp_cntrl1.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-eventq_index=0
-icache=system.tcp_cntrl1.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=5
-
-[system.tcp_cntrl1.unblockFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[10]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: system.ruby.network adopting orphan SimObject param 'int_links'
-warn: system.ruby.network adopting orphan SimObject param 'ext_links'
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 19 2016 13:39:50
-gem5 started Jan 19 2016 13:40:22
-gem5 executing on zizzer, pid 50252
-command line: build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_VIPER_Baseline -re /z/atgutier/gem5/gem5-commit/tests/run.py build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_VIPER_Baseline
-
-Using GPU kernel code file(s) /dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm
-Global frequency set at 1000000000000 ticks per second
-Forcing maxCoalescedReqs to 32 (TLB assoc.)
-Forcing maxCoalescedReqs to 32 (TLB assoc.)
-Forcing maxCoalescedReqs to 32 (TLB assoc.)
-Forcing maxCoalescedReqs to 32 (TLB assoc.)
-Forcing maxCoalescedReqs to 32 (TLB assoc.)
-Forcing maxCoalescedReqs to 32 (TLB assoc.)
-info: Entering event queue @ 0. Starting simulation...
-keys = 0x7b2bc0, &keys = 0x798998, keys[0] = 23
-the gpu says:
-\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fe
-Exiting @ tick 548459500 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000548 # Number of seconds simulated
-sim_ticks 548459500 # Number of ticks simulated
-final_tick 548459500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 76623 # Simulator instruction rate (inst/s)
-host_op_rate 157567 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 627550839 # Simulator tick rate (ticks/s)
-host_mem_usage 1298164 # Number of bytes of host memory used
-host_seconds 0.87 # Real time elapsed on the host
-sim_insts 66963 # Number of instructions simulated
-sim_ops 137705 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.mem_ctrls.bytes_read::dir_cntrl0 99840 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 99840 # Number of bytes read from this memory
-system.mem_ctrls.num_reads::dir_cntrl0 1560 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 1560 # Number of read requests responded to by this memory
-system.mem_ctrls.bw_read::dir_cntrl0 182037142 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 182037142 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::dir_cntrl0 182037142 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 182037142 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 1560 # Number of read requests accepted
-system.mem_ctrls.writeReqs 0 # Number of write requests accepted
-system.mem_ctrls.readBursts 1560 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 99840 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 99840 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 122 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 192 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 93 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 44 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 61 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 79 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 52 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 42 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8 54 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9 56 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 182 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11 90 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12 223 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 125 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 51 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 94 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
-system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
-system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 548231000 # Total gap between requests
-system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 1560 # Read request sizes (log2)
-system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 1545 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 3 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2 2 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3 4 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4 5 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 467 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 212.008565 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 148.026325 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 209.604491 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 171 36.62% 36.62% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 154 32.98% 69.59% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 64 13.70% 83.30% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 31 6.64% 89.94% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 16 3.43% 93.36% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 12 2.57% 95.93% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 7 1.50% 97.43% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 3 0.64% 98.07% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 9 1.93% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 467 # Bytes accessed per row activation
-system.mem_ctrls.totQLat 15697750 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 44947750 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 7800000 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 10062.66 # Average queueing delay per DRAM burst
-system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 28812.66 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 182.04 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 182.04 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
-system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 1.42 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 1.42 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 1.01 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 1088 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 69.74 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 351430.13 # Average gap between requests
-system.mem_ctrls.pageHitRate 69.74 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 1323000 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 721875 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 5335200 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 35599200 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 300176820 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 63865500 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 407021595 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 746.421165 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 107390750 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 18200000 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 422764250 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls_1.actEnergy 2207520 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 1204500 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 6731400 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 35599200 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 328972365 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 38606250 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 413321235 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 757.973831 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 62414250 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 18200000 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 464697000 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.ruby.clk_domain.clock 500 # Clock period in ticks
-system.ruby.phys_mem.bytes_read::cpu0.inst 696760 # Number of bytes read from this memory
-system.ruby.phys_mem.bytes_read::cpu0.data 119832 # Number of bytes read from this memory
-system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 3280 # Number of bytes read from this memory
-system.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit 3280 # Number of bytes read from this memory
-system.ruby.phys_mem.bytes_read::total 823152 # Number of bytes read from this memory
-system.ruby.phys_mem.bytes_inst_read::cpu0.inst 696760 # Number of instructions bytes read from this memory
-system.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit 2000 # Number of instructions bytes read from this memory
-system.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit 2000 # Number of instructions bytes read from this memory
-system.ruby.phys_mem.bytes_inst_read::total 700760 # Number of instructions bytes read from this memory
-system.ruby.phys_mem.bytes_written::cpu0.data 72767 # Number of bytes written to this memory
-system.ruby.phys_mem.bytes_written::cpu1.CUs0.ComputeUnit 256 # Number of bytes written to this memory
-system.ruby.phys_mem.bytes_written::cpu1.CUs1.ComputeUnit 256 # Number of bytes written to this memory
-system.ruby.phys_mem.bytes_written::total 73279 # Number of bytes written to this memory
-system.ruby.phys_mem.num_reads::cpu0.inst 87095 # Number of read requests responded to by this memory
-system.ruby.phys_mem.num_reads::cpu0.data 16686 # Number of read requests responded to by this memory
-system.ruby.phys_mem.num_reads::cpu1.CUs0.ComputeUnit 555 # Number of read requests responded to by this memory
-system.ruby.phys_mem.num_reads::cpu1.CUs1.ComputeUnit 555 # Number of read requests responded to by this memory
-system.ruby.phys_mem.num_reads::total 104891 # Number of read requests responded to by this memory
-system.ruby.phys_mem.num_writes::cpu0.data 10422 # Number of write requests responded to by this memory
-system.ruby.phys_mem.num_writes::cpu1.CUs0.ComputeUnit 256 # Number of write requests responded to by this memory
-system.ruby.phys_mem.num_writes::cpu1.CUs1.ComputeUnit 256 # Number of write requests responded to by this memory
-system.ruby.phys_mem.num_writes::total 10934 # Number of write requests responded to by this memory
-system.ruby.phys_mem.bw_read::cpu0.inst 1270394623 # Total read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_read::cpu0.data 218488330 # Total read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit 5980387 # Total read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit 5980387 # Total read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_read::total 1500843727 # Total read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_inst_read::cpu0.inst 1270394623 # Instruction read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit 3646577 # Instruction read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit 3646577 # Instruction read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_inst_read::total 1277687778 # Instruction read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_write::cpu0.data 132675248 # Write bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 466762 # Write bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 466762 # Write bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_write::total 133608771 # Write bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_total::cpu0.inst 1270394623 # Total bandwidth to/from this memory (bytes/s)
-system.ruby.phys_mem.bw_total::cpu0.data 351163577 # Total bandwidth to/from this memory (bytes/s)
-system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 6447149 # Total bandwidth to/from this memory (bytes/s)
-system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 6447149 # Total bandwidth to/from this memory (bytes/s)
-system.ruby.phys_mem.bw_total::total 1634452498 # Total bandwidth to/from this memory (bytes/s)
-system.ruby.outstanding_req_hist::bucket_size 1
-system.ruby.outstanding_req_hist::max_bucket 9
-system.ruby.outstanding_req_hist::samples 114203
-system.ruby.outstanding_req_hist::mean 1.000035
-system.ruby.outstanding_req_hist::gmean 1.000024
-system.ruby.outstanding_req_hist::stdev 0.005918
-system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 114199 100.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist::total 114203
-system.ruby.latency_hist::bucket_size 64
-system.ruby.latency_hist::max_bucket 639
-system.ruby.latency_hist::samples 114203
-system.ruby.latency_hist::mean 3.766924
-system.ruby.latency_hist::gmean 1.075767
-system.ruby.latency_hist::stdev 23.927354
-system.ruby.latency_hist | 112668 98.66% 98.66% | 0 0.00% 98.66% | 0 0.00% 98.66% | 1489 1.30% 99.96% | 10 0.01% 99.97% | 13 0.01% 99.98% | 16 0.01% 99.99% | 7 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist::total 114203
-system.ruby.hit_latency_hist::bucket_size 64
-system.ruby.hit_latency_hist::max_bucket 639
-system.ruby.hit_latency_hist::samples 1535
-system.ruby.hit_latency_hist::mean 206.165472
-system.ruby.hit_latency_hist::gmean 204.491657
-system.ruby.hit_latency_hist::stdev 32.551053
-system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1489 97.00% 97.00% | 10 0.65% 97.65% | 13 0.85% 98.50% | 16 1.04% 99.54% | 7 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist::total 1535
-system.ruby.miss_latency_hist::bucket_size 2
-system.ruby.miss_latency_hist::max_bucket 19
-system.ruby.miss_latency_hist::samples 112668
-system.ruby.miss_latency_hist::mean 1.009426
-system.ruby.miss_latency_hist::gmean 1.001543
-system.ruby.miss_latency_hist::stdev 0.411800
-system.ruby.miss_latency_hist | 112609 99.95% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 59 0.05% 100.00%
-system.ruby.miss_latency_hist::total 112668
-system.ruby.L1Cache.incomplete_times 112609
-system.ruby.L2Cache.incomplete_times 59
-system.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits
-system.cp_cntrl0.L1D0cache.demand_misses 506 # Number of cache demand misses
-system.cp_cntrl0.L1D0cache.demand_accesses 506 # Number of cache demand accesses
-system.cp_cntrl0.L1D0cache.num_data_array_reads 16155 # number of data array reads
-system.cp_cntrl0.L1D0cache.num_data_array_writes 11985 # number of data array writes
-system.cp_cntrl0.L1D0cache.num_tag_array_reads 27132 # number of tag array reads
-system.cp_cntrl0.L1D0cache.num_tag_array_writes 1584 # number of tag array writes
-system.cp_cntrl0.L1D1cache.demand_hits 0 # Number of cache demand hits
-system.cp_cntrl0.L1D1cache.demand_misses 0 # Number of cache demand misses
-system.cp_cntrl0.L1D1cache.demand_accesses 0 # Number of cache demand accesses
-system.cp_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
-system.cp_cntrl0.L1Icache.demand_misses 1088 # Number of cache demand misses
-system.cp_cntrl0.L1Icache.demand_accesses 1088 # Number of cache demand accesses
-system.cp_cntrl0.L1Icache.num_data_array_reads 86007 # number of data array reads
-system.cp_cntrl0.L1Icache.num_data_array_writes 54 # number of data array writes
-system.cp_cntrl0.L1Icache.num_tag_array_reads 87684 # number of tag array reads
-system.cp_cntrl0.L1Icache.num_tag_array_writes 54 # number of tag array writes
-system.cp_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits
-system.cp_cntrl0.L2cache.demand_misses 1535 # Number of cache demand misses
-system.cp_cntrl0.L2cache.demand_accesses 1535 # Number of cache demand accesses
-system.cp_cntrl0.L2cache.num_data_array_reads 120 # number of data array reads
-system.cp_cntrl0.L2cache.num_data_array_writes 11982 # number of data array writes
-system.cp_cntrl0.L2cache.num_tag_array_reads 12046 # number of tag array reads
-system.cp_cntrl0.L2cache.num_tag_array_writes 1641 # number of tag array writes
-system.cpu0.clk_domain.clock 500 # Clock period in ticks
-system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu0.workload.numSyscalls 21 # Number of system calls
-system.cpu0.numCycles 1096919 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 66963 # Number of instructions committed
-system.cpu0.committedOps 137705 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 136380 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 1279 # Number of float alu accesses
-system.cpu0.num_func_calls 3196 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 12151 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 136380 # number of integer instructions
-system.cpu0.num_fp_insts 1279 # number of float instructions
-system.cpu0.num_int_register_reads 257490 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 110039 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 1981 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 981 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 78262 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 42183 # number of times the CC registers were written
-system.cpu0.num_mem_refs 27198 # number of memory refs
-system.cpu0.num_load_insts 16684 # Number of load instructions
-system.cpu0.num_store_insts 10514 # Number of store instructions
-system.cpu0.num_idle_cycles 7577.003986 # Number of idle cycles
-system.cpu0.num_busy_cycles 1089341.996014 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.993092 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.006908 # Percentage of idle cycles
-system.cpu0.Branches 16199 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 615 0.45% 0.45% # Class of executed instruction
-system.cpu0.op_class::IntAlu 108791 79.00% 79.45% # Class of executed instruction
-system.cpu0.op_class::IntMult 13 0.01% 79.46% # Class of executed instruction
-system.cpu0.op_class::IntDiv 138 0.10% 79.56% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 950 0.69% 80.25% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::MemRead 16684 12.12% 92.36% # Class of executed instruction
-system.cpu0.op_class::MemWrite 10514 7.64% 100.00% # Class of executed instruction
-system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 137705 # Class of executed instruction
-system.cpu1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.cpu1.clk_domain.clock 1000 # Clock period in ticks
-system.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 372 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::total 39 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts01.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts01.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts04.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
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-system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts05.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
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-system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts07.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
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-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 353 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 344 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 329 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 4357 # number of cycles the CU issues nothing
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 133 # number of cycles the CU issued at least one instruction
-system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 1547 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 483 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 439 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 403 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 436 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 26 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.spc::samples 4490 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::mean 0.031403 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::stdev 0.185563 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::0 4357 97.04% 97.04% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::1 126 2.81% 99.84% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::2 6 0.13% 99.98% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::3 1 0.02% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::total 4490 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 68 # number of CU transitions from active to idle
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 68 # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 59.558824 # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 213.072854 # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 48 70.59% 70.59% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 8 11.76% 82.35% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 1 1.47% 83.82% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 1 1.47% 85.29% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 2 2.94% 88.24% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.47% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 7 10.29% 100.00% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value 1300 # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 68 # duration of idle periods in cycles
-system.cpu1.CUs0.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF
-system.cpu1.CUs0.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF
-system.cpu1.CUs0.tlb_requests 769 # number of uncoalesced requests
-system.cpu1.CUs0.tlb_cycles -373675448000 # total number of cycles for all uncoalesced requests
-system.cpu1.CUs0.avg_translation_latency -485923859.557867 # Avg. translation latency for data translations
-system.cpu1.CUs0.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs0.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs0.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs0.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs0.lds_bank_access_cnt 54 # Total number of LDS bank accesses
-system.cpu1.CUs0.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::mean 8 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::stdev 6.196773 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::10-11 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::12-13 4 66.67% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.global_mem_instr_cnt 17 # dynamic global memory instructions count
-system.cpu1.CUs0.local_mem_instr_cnt 6 # dynamic local memory intruction count
-system.cpu1.CUs0.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity
-system.cpu1.CUs0.num_instr_executed 141 # number of instructions executed
-system.cpu1.CUs0.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::mean 94.900709 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::stdev 247.493154 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::0-1 1 0.71% 0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::4-5 53 37.59% 46.81% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::6-7 31 21.99% 68.79% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::8-9 3 2.13% 70.92% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::10 1 0.71% 71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::overflows 40 28.37% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::min_value 1 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::max_value 1303 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.num_vec_ops_executed 6769 # number of vec ops executed (e.g. VSZ/inst)
-system.cpu1.CUs0.num_total_cycles 4490 # number of cycles the CU ran for
-system.cpu1.CUs0.vpc 1.507572 # Vector Operations per cycle (this CU only)
-system.cpu1.CUs0.ipc 0.031403 # Instructions per cycle (this CU only)
-system.cpu1.CUs0.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::mean 48.007092 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::stdev 23.719942 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::9-12 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::13-16 36 25.53% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::mean 37.833333 # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::stdev 27.064737 # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::9-12 0 0.00% 5.56% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::13-16 8 44.44% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::mean 19.500000 # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::stdev 22.322634 # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::9-12 0 0.00% 16.67% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::13-16 4 66.67% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction
-system.cpu1.CUs0.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed
-system.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD
-system.cpu1.CUs0.num_CAS_ops 0 # number of compare and swap operations
-system.cpu1.CUs0.num_failed_CAS_ops 0 # number of compare and swap operations that failed
-system.cpu1.CUs0.num_completed_wfs 4 # number of completed wavefronts
-system.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 377 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::total 39 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts01.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts01.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts02.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts02.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts03.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts03.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts04.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts04.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts05.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts05.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts06.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts06.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts07.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts07.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 355 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 352 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 337 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 4359 # number of cycles the CU issues nothing
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 131 # number of cycles the CU issued at least one instruction
-system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 1552 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 447 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 464 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 464 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 426 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 33 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.spc::samples 4490 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::mean 0.031403 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::stdev 0.189130 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::0 4359 97.08% 97.08% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::1 123 2.74% 99.82% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::2 6 0.13% 99.96% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::3 2 0.04% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::total 4490 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 74 # number of CU transitions from active to idle
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 74 # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 55.324324 # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 207.911408 # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 56 75.68% 75.68% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 7 9.46% 85.14% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 85.14% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 2 2.70% 87.84% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 1 1.35% 89.19% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 1 1.35% 90.54% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 90.54% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 90.54% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 90.54% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 90.54% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 90.54% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 90.54% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 90.54% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 90.54% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 90.54% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 90.54% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 7 9.46% 100.00% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value 1304 # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 74 # duration of idle periods in cycles
-system.cpu1.CUs1.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF
-system.cpu1.CUs1.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF
-system.cpu1.CUs1.tlb_requests 769 # number of uncoalesced requests
-system.cpu1.CUs1.tlb_cycles -373672588000 # total number of cycles for all uncoalesced requests
-system.cpu1.CUs1.avg_translation_latency -485920140.442133 # Avg. translation latency for data translations
-system.cpu1.CUs1.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs1.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs1.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs1.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs1.lds_bank_access_cnt 53 # Total number of LDS bank accesses
-system.cpu1.CUs1.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::mean 7.833333 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::stdev 6.080022 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::10-11 1 16.67% 50.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::12-13 3 50.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.global_mem_instr_cnt 17 # dynamic global memory instructions count
-system.cpu1.CUs1.local_mem_instr_cnt 6 # dynamic local memory intruction count
-system.cpu1.CUs1.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity
-system.cpu1.CUs1.num_instr_executed 141 # number of instructions executed
-system.cpu1.CUs1.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::mean 95.106383 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::stdev 249.293307 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::0-1 1 0.71% 0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::2-3 12 8.51% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::4-5 53 37.59% 46.81% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::6-7 29 20.57% 67.38% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::8-9 5 3.55% 70.92% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::10 1 0.71% 71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::overflows 40 28.37% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::min_value 1 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::max_value 1307 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.num_vec_ops_executed 6762 # number of vec ops executed (e.g. VSZ/inst)
-system.cpu1.CUs1.num_total_cycles 4490 # number of cycles the CU ran for
-system.cpu1.CUs1.vpc 1.506013 # Vector Operations per cycle (this CU only)
-system.cpu1.CUs1.ipc 0.031403 # Instructions per cycle (this CU only)
-system.cpu1.CUs1.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::mean 47.957447 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::stdev 23.818022 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::9-12 9 6.38% 9.93% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::13-16 27 19.15% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::mean 37.722222 # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::stdev 27.174394 # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::9-12 2 11.11% 16.67% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::13-16 6 33.33% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::mean 19.333333 # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::stdev 22.384518 # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::9-12 1 16.67% 33.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::13-16 3 50.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction
-system.cpu1.CUs1.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed
-system.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD
-system.cpu1.CUs1.num_CAS_ops 0 # number of compare and swap operations
-system.cpu1.CUs1.num_failed_CAS_ops 0 # number of compare and swap operations that failed
-system.cpu1.CUs1.num_completed_wfs 4 # number of completed wavefronts
-system.cpu2.num_kernel_launched 1 # number of kernel launched
-system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits
-system.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses
-system.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses
-system.dir_cntrl0.L3CacheMemory.num_data_array_writes 1560 # number of data array writes
-system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1560 # number of tag array reads
-system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1578 # number of tag array writes
-system.dir_cntrl0.ProbeFilterMemory.demand_hits 0 # Number of cache demand hits
-system.dir_cntrl0.ProbeFilterMemory.demand_misses 0 # Number of cache demand misses
-system.dir_cntrl0.ProbeFilterMemory.demand_accesses 0 # Number of cache demand accesses
-system.dir_cntrl0.ProbeFilterMemory.num_tag_array_reads 1560 # number of tag array reads
-system.dir_cntrl0.ProbeFilterMemory.num_tag_array_writes 1560 # number of tag array writes
-system.dispatcher_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.dispatcher_coalescer.clk_domain.clock 1000 # Clock period in ticks
-system.dispatcher_coalescer.uncoalesced_accesses 0 # Number of uncoalesced TLB accesses
-system.dispatcher_coalescer.coalesced_accesses 0 # Number of coalesced TLB accesses
-system.dispatcher_coalescer.queuing_cycles 0 # Number of cycles spent in queue
-system.dispatcher_coalescer.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs
-system.dispatcher_coalescer.local_latency nan # Avg. latency over all incoming pkts
-system.dispatcher_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.dispatcher_tlb.clk_domain.clock 1000 # Clock period in ticks
-system.dispatcher_tlb.local_TLB_accesses 0 # Number of TLB accesses
-system.dispatcher_tlb.local_TLB_hits 0 # Number of TLB hits
-system.dispatcher_tlb.local_TLB_misses 0 # Number of TLB misses
-system.dispatcher_tlb.local_TLB_miss_rate nan # TLB miss rate
-system.dispatcher_tlb.global_TLB_accesses 0 # Number of TLB accesses
-system.dispatcher_tlb.global_TLB_hits 0 # Number of TLB hits
-system.dispatcher_tlb.global_TLB_misses 0 # Number of TLB misses
-system.dispatcher_tlb.global_TLB_miss_rate nan # TLB miss rate
-system.dispatcher_tlb.access_cycles 0 # Cycles spent accessing this TLB level
-system.dispatcher_tlb.page_table_cycles 0 # Cycles spent accessing the page table
-system.dispatcher_tlb.unique_pages 0 # Number of unique pages touched
-system.dispatcher_tlb.local_cycles 0 # Number of cycles spent in queue for all incoming reqs
-system.dispatcher_tlb.local_latency nan # Avg. latency over incoming coalesced reqs
-system.dispatcher_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
-system.l1_coalescer0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l1_coalescer0.clk_domain.clock 1000 # Clock period in ticks
-system.l1_coalescer0.uncoalesced_accesses 778 # Number of uncoalesced TLB accesses
-system.l1_coalescer0.coalesced_accesses 0 # Number of coalesced TLB accesses
-system.l1_coalescer0.queuing_cycles 0 # Number of cycles spent in queue
-system.l1_coalescer0.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs
-system.l1_coalescer0.local_latency 0 # Avg. latency over all incoming pkts
-system.l1_coalescer1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l1_coalescer1.clk_domain.clock 1000 # Clock period in ticks
-system.l1_coalescer1.uncoalesced_accesses 769 # Number of uncoalesced TLB accesses
-system.l1_coalescer1.coalesced_accesses 0 # Number of coalesced TLB accesses
-system.l1_coalescer1.queuing_cycles 0 # Number of cycles spent in queue
-system.l1_coalescer1.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs
-system.l1_coalescer1.local_latency 0 # Avg. latency over all incoming pkts
-system.l1_tlb0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l1_tlb0.clk_domain.clock 1000 # Clock period in ticks
-system.l1_tlb0.local_TLB_accesses 778 # Number of TLB accesses
-system.l1_tlb0.local_TLB_hits 774 # Number of TLB hits
-system.l1_tlb0.local_TLB_misses 4 # Number of TLB misses
-system.l1_tlb0.local_TLB_miss_rate 0.514139 # TLB miss rate
-system.l1_tlb0.global_TLB_accesses 778 # Number of TLB accesses
-system.l1_tlb0.global_TLB_hits 774 # Number of TLB hits
-system.l1_tlb0.global_TLB_misses 4 # Number of TLB misses
-system.l1_tlb0.global_TLB_miss_rate 0.514139 # TLB miss rate
-system.l1_tlb0.access_cycles 0 # Cycles spent accessing this TLB level
-system.l1_tlb0.page_table_cycles 0 # Cycles spent accessing the page table
-system.l1_tlb0.unique_pages 4 # Number of unique pages touched
-system.l1_tlb0.local_cycles 0 # Number of cycles spent in queue for all incoming reqs
-system.l1_tlb0.local_latency 0 # Avg. latency over incoming coalesced reqs
-system.l1_tlb0.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
-system.l1_tlb1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l1_tlb1.clk_domain.clock 1000 # Clock period in ticks
-system.l1_tlb1.local_TLB_accesses 769 # Number of TLB accesses
-system.l1_tlb1.local_TLB_hits 766 # Number of TLB hits
-system.l1_tlb1.local_TLB_misses 3 # Number of TLB misses
-system.l1_tlb1.local_TLB_miss_rate 0.390117 # TLB miss rate
-system.l1_tlb1.global_TLB_accesses 769 # Number of TLB accesses
-system.l1_tlb1.global_TLB_hits 766 # Number of TLB hits
-system.l1_tlb1.global_TLB_misses 3 # Number of TLB misses
-system.l1_tlb1.global_TLB_miss_rate 0.390117 # TLB miss rate
-system.l1_tlb1.access_cycles 0 # Cycles spent accessing this TLB level
-system.l1_tlb1.page_table_cycles 0 # Cycles spent accessing the page table
-system.l1_tlb1.unique_pages 3 # Number of unique pages touched
-system.l1_tlb1.local_cycles 0 # Number of cycles spent in queue for all incoming reqs
-system.l1_tlb1.local_latency 0 # Avg. latency over incoming coalesced reqs
-system.l1_tlb1.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
-system.l2_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l2_coalescer.clk_domain.clock 1000 # Clock period in ticks
-system.l2_coalescer.uncoalesced_accesses 8 # Number of uncoalesced TLB accesses
-system.l2_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses
-system.l2_coalescer.queuing_cycles 8000 # Number of cycles spent in queue
-system.l2_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs
-system.l2_coalescer.local_latency 125 # Avg. latency over all incoming pkts
-system.l2_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l2_tlb.clk_domain.clock 1000 # Clock period in ticks
-system.l2_tlb.local_TLB_accesses 8 # Number of TLB accesses
-system.l2_tlb.local_TLB_hits 3 # Number of TLB hits
-system.l2_tlb.local_TLB_misses 5 # Number of TLB misses
-system.l2_tlb.local_TLB_miss_rate 62.500000 # TLB miss rate
-system.l2_tlb.global_TLB_accesses 15 # Number of TLB accesses
-system.l2_tlb.global_TLB_hits 3 # Number of TLB hits
-system.l2_tlb.global_TLB_misses 12 # Number of TLB misses
-system.l2_tlb.global_TLB_miss_rate 80 # TLB miss rate
-system.l2_tlb.access_cycles 552008 # Cycles spent accessing this TLB level
-system.l2_tlb.page_table_cycles 0 # Cycles spent accessing the page table
-system.l2_tlb.unique_pages 5 # Number of unique pages touched
-system.l2_tlb.local_cycles 69001 # Number of cycles spent in queue for all incoming reqs
-system.l2_tlb.local_latency 8625.125000 # Avg. latency over incoming coalesced reqs
-system.l2_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
-system.l3_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l3_coalescer.clk_domain.clock 1000 # Clock period in ticks
-system.l3_coalescer.uncoalesced_accesses 5 # Number of uncoalesced TLB accesses
-system.l3_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses
-system.l3_coalescer.queuing_cycles 8000 # Number of cycles spent in queue
-system.l3_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs
-system.l3_coalescer.local_latency 200 # Avg. latency over all incoming pkts
-system.l3_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l3_tlb.clk_domain.clock 1000 # Clock period in ticks
-system.l3_tlb.local_TLB_accesses 5 # Number of TLB accesses
-system.l3_tlb.local_TLB_hits 0 # Number of TLB hits
-system.l3_tlb.local_TLB_misses 5 # Number of TLB misses
-system.l3_tlb.local_TLB_miss_rate 100 # TLB miss rate
-system.l3_tlb.global_TLB_accesses 12 # Number of TLB accesses
-system.l3_tlb.global_TLB_hits 0 # Number of TLB hits
-system.l3_tlb.global_TLB_misses 12 # Number of TLB misses
-system.l3_tlb.global_TLB_miss_rate 100 # TLB miss rate
-system.l3_tlb.access_cycles 1200000 # Cycles spent accessing this TLB level
-system.l3_tlb.page_table_cycles 6000000 # Cycles spent accessing the page table
-system.l3_tlb.unique_pages 5 # Number of unique pages touched
-system.l3_tlb.local_cycles 150000 # Number of cycles spent in queue for all incoming reqs
-system.l3_tlb.local_latency 30000 # Avg. latency over incoming coalesced reqs
-system.l3_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
-system.piobus.trans_dist::WriteReq 94 # Transaction distribution
-system.piobus.trans_dist::WriteResp 94 # Transaction distribution
-system.piobus.pkt_count_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 188 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::total 188 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_size_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 748 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.pkt_size::total 748 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.reqLayer0.occupancy 188000 # Layer occupancy (ticks)
-system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.piobus.respLayer0.occupancy 94000 # Layer occupancy (ticks)
-system.piobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.ruby.network.ext_links0.int_node.percent_links_utilized 0.130525
-system.ruby.network.ext_links0.int_node.msg_count.Control::0 4
-system.ruby.network.ext_links0.int_node.msg_count.Data::0 18
-system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1542
-system.ruby.network.ext_links0.int_node.msg_count.Response_Data::2 1546
-system.ruby.network.ext_links0.int_node.msg_count.Response_Control::2 2
-system.ruby.network.ext_links0.int_node.msg_count.Writeback_Control::2 16
-system.ruby.network.ext_links0.int_node.msg_count.Unblock_Control::4 1541
-system.ruby.network.ext_links0.int_node.msg_bytes.Control::0 32
-system.ruby.network.ext_links0.int_node.msg_bytes.Data::0 1296
-system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0 12336
-system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 111312
-system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 16
-system.ruby.network.ext_links0.int_node.msg_bytes.Writeback_Control::2 128
-system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12328
-system.ruby.network.ext_links1.int_node.percent_links_utilized 0.192653
-system.ruby.network.ext_links1.int_node.msg_count.Control::0 3
-system.ruby.network.ext_links1.int_node.msg_count.Request_Control::0 1535
-system.ruby.network.ext_links1.int_node.msg_count.Response_Data::2 1537
-system.ruby.network.ext_links1.int_node.msg_count.Response_Control::2 1
-system.ruby.network.ext_links1.int_node.msg_count.Unblock_Control::4 1534
-system.ruby.network.ext_links1.int_node.msg_bytes.Control::0 24
-system.ruby.network.ext_links1.int_node.msg_bytes.Request_Control::0 12280
-system.ruby.network.ext_links1.int_node.msg_bytes.Response_Data::2 110664
-system.ruby.network.ext_links1.int_node.msg_bytes.Response_Control::2 8
-system.ruby.network.ext_links1.int_node.msg_bytes.Unblock_Control::4 12272
-system.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits
-system.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses
-system.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses
-system.tcp_cntrl0.L1cache.num_data_array_reads 6 # number of data array reads
-system.tcp_cntrl0.L1cache.num_data_array_writes 11 # number of data array writes
-system.tcp_cntrl0.L1cache.num_tag_array_reads 1297 # number of tag array reads
-system.tcp_cntrl0.L1cache.num_tag_array_writes 11 # number of tag array writes
-system.tcp_cntrl0.L1cache.num_tag_array_stalls 1271 # number of stalls caused by tag array
-system.tcp_cntrl0.L1cache.num_data_array_stalls 2 # number of stalls caused by data array
-system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP
-system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers
-system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl0.coalescer.gpu_ld_misses 5 # loads that miss in the GPU
-system.tcp_cntrl0.coalescer.gpu_tcp_st_hits 0 # stores that hit in the TCP
-system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers
-system.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl0.coalescer.gpu_st_misses 9 # stores that miss in the GPU
-system.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP
-system.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers
-system.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl0.coalescer.cp_ld_misses 0 # loads that miss in the GPU
-system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP
-system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
-system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU
-system.ruby.network.ext_links2.int_node.percent_links_utilized 0.002557
-system.ruby.network.ext_links2.int_node.msg_count.Control::0 1
-system.ruby.network.ext_links2.int_node.msg_count.Data::0 18
-system.ruby.network.ext_links2.int_node.msg_count.Data::1 18
-system.ruby.network.ext_links2.int_node.msg_count.Request_Control::0 7
-system.ruby.network.ext_links2.int_node.msg_count.Request_Control::1 9
-system.ruby.network.ext_links2.int_node.msg_count.Response_Data::2 9
-system.ruby.network.ext_links2.int_node.msg_count.Response_Data::3 11
-system.ruby.network.ext_links2.int_node.msg_count.Response_Control::2 1
-system.ruby.network.ext_links2.int_node.msg_count.Writeback_Control::2 16
-system.ruby.network.ext_links2.int_node.msg_count.Writeback_Control::3 16
-system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::4 7
-system.ruby.network.ext_links2.int_node.msg_bytes.Control::0 8
-system.ruby.network.ext_links2.int_node.msg_bytes.Data::0 1296
-system.ruby.network.ext_links2.int_node.msg_bytes.Data::1 1296
-system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::0 56
-system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::1 72
-system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::2 648
-system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::3 792
-system.ruby.network.ext_links2.int_node.msg_bytes.Response_Control::2 8
-system.ruby.network.ext_links2.int_node.msg_bytes.Writeback_Control::2 128
-system.ruby.network.ext_links2.int_node.msg_bytes.Writeback_Control::3 128
-system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::4 56
-system.tcp_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits
-system.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses
-system.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses
-system.tcp_cntrl1.L1cache.num_data_array_reads 6 # number of data array reads
-system.tcp_cntrl1.L1cache.num_data_array_writes 11 # number of data array writes
-system.tcp_cntrl1.L1cache.num_tag_array_reads 1297 # number of tag array reads
-system.tcp_cntrl1.L1cache.num_tag_array_writes 11 # number of tag array writes
-system.tcp_cntrl1.L1cache.num_tag_array_stalls 1271 # number of stalls caused by tag array
-system.tcp_cntrl1.L1cache.num_data_array_stalls 2 # number of stalls caused by data array
-system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP
-system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers
-system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl1.coalescer.gpu_ld_misses 5 # loads that miss in the GPU
-system.tcp_cntrl1.coalescer.gpu_tcp_st_hits 0 # stores that hit in the TCP
-system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers
-system.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl1.coalescer.gpu_st_misses 9 # stores that miss in the GPU
-system.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP
-system.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers
-system.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl1.coalescer.cp_ld_misses 0 # loads that miss in the GPU
-system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP
-system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
-system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU
-system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits
-system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses
-system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses
-system.sqc_cntrl0.L1cache.num_data_array_reads 86 # number of data array reads
-system.sqc_cntrl0.L1cache.num_tag_array_reads 91 # number of tag array reads
-system.sqc_cntrl0.L1cache.num_tag_array_writes 10 # number of tag array writes
-system.sqc_cntrl0.sequencer.load_waiting_on_load 98 # Number of times a load aliased with a pending load
-system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits
-system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses
-system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses
-system.tcc_cntrl0.L2cache.num_data_array_writes 9 # number of data array writes
-system.tcc_cntrl0.L2cache.num_tag_array_reads 35 # number of tag array reads
-system.tcc_cntrl0.L2cache.num_tag_array_writes 11 # number of tag array writes
-system.ruby.network.msg_count.Control 8
-system.ruby.network.msg_count.Data 54
-system.ruby.network.msg_count.Request_Control 3093
-system.ruby.network.msg_count.Response_Data 3103
-system.ruby.network.msg_count.Response_Control 4
-system.ruby.network.msg_count.Writeback_Control 48
-system.ruby.network.msg_count.Unblock_Control 3082
-system.ruby.network.msg_byte.Control 64
-system.ruby.network.msg_byte.Data 3888
-system.ruby.network.msg_byte.Request_Control 24744
-system.ruby.network.msg_byte.Response_Data 223416
-system.ruby.network.msg_byte.Response_Control 32
-system.ruby.network.msg_byte.Writeback_Control 384
-system.ruby.network.msg_byte.Unblock_Control 24656
-system.sqc_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.sqc_coalescer.clk_domain.clock 1000 # Clock period in ticks
-system.sqc_coalescer.uncoalesced_accesses 86 # Number of uncoalesced TLB accesses
-system.sqc_coalescer.coalesced_accesses 66 # Number of coalesced TLB accesses
-system.sqc_coalescer.queuing_cycles 288000 # Number of cycles spent in queue
-system.sqc_coalescer.local_queuing_cycles 288000 # Number of cycles spent in queue for all incoming reqs
-system.sqc_coalescer.local_latency 3348.837209 # Avg. latency over all incoming pkts
-system.sqc_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.sqc_tlb.clk_domain.clock 1000 # Clock period in ticks
-system.sqc_tlb.local_TLB_accesses 66 # Number of TLB accesses
-system.sqc_tlb.local_TLB_hits 65 # Number of TLB hits
-system.sqc_tlb.local_TLB_misses 1 # Number of TLB misses
-system.sqc_tlb.local_TLB_miss_rate 1.515152 # TLB miss rate
-system.sqc_tlb.global_TLB_accesses 86 # Number of TLB accesses
-system.sqc_tlb.global_TLB_hits 78 # Number of TLB hits
-system.sqc_tlb.global_TLB_misses 8 # Number of TLB misses
-system.sqc_tlb.global_TLB_miss_rate 9.302326 # TLB miss rate
-system.sqc_tlb.access_cycles 86008 # Cycles spent accessing this TLB level
-system.sqc_tlb.page_table_cycles 0 # Cycles spent accessing the page table
-system.sqc_tlb.unique_pages 1 # Number of unique pages touched
-system.sqc_tlb.local_cycles 66001 # Number of cycles spent in queue for all incoming reqs
-system.sqc_tlb.local_latency 1000.015152 # Avg. latency over incoming coalesced reqs
-system.sqc_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
-system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.074413
-system.ruby.network.ext_links0.int_node.throttle0.msg_count.Data::0 18
-system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1542
-system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2 2
-system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2 2
-system.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4 1541
-system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Data::0 1296
-system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0 12336
-system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Data::2 144
-system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2 16
-system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Unblock_Control::4 12328
-system.ruby.network.ext_links0.int_node.throttle1.link_utilization 0.314928
-system.ruby.network.ext_links0.int_node.throttle1.msg_count.Control::0 3
-system.ruby.network.ext_links0.int_node.throttle1.msg_count.Response_Data::2 1535
-system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Control::0 24
-system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Response_Data::2 110520
-system.ruby.network.ext_links0.int_node.throttle2.link_utilization 0.002234
-system.ruby.network.ext_links0.int_node.throttle2.msg_count.Control::0 1
-system.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Data::2 9
-system.ruby.network.ext_links0.int_node.throttle2.msg_count.Writeback_Control::2 16
-system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Control::0 8
-system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Data::2 648
-system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Writeback_Control::2 128
-system.ruby.network.ext_links1.int_node.throttle0.link_utilization 0.314928
-system.ruby.network.ext_links1.int_node.throttle0.msg_count.Control::0 3
-system.ruby.network.ext_links1.int_node.throttle0.msg_count.Response_Data::2 1535
-system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Control::0 24
-system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Response_Data::2 110520
-system.ruby.network.ext_links1.int_node.throttle1.link_utilization 0.070379
-system.ruby.network.ext_links1.int_node.throttle1.msg_count.Request_Control::0 1535
-system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Data::2 2
-system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Control::2 1
-system.ruby.network.ext_links1.int_node.throttle1.msg_count.Unblock_Control::4 1534
-system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Request_Control::0 12280
-system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Data::2 144
-system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Control::2 8
-system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Unblock_Control::4 12272
-system.ruby.network.ext_links2.int_node.throttle0.link_utilization 0.000798
-system.ruby.network.ext_links2.int_node.throttle0.msg_count.Response_Data::3 3
-system.ruby.network.ext_links2.int_node.throttle0.msg_count.Writeback_Control::3 8
-system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Response_Data::3 216
-system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Writeback_Control::3 64
-system.ruby.network.ext_links2.int_node.throttle1.link_utilization 0.000798
-system.ruby.network.ext_links2.int_node.throttle1.msg_count.Response_Data::3 3
-system.ruby.network.ext_links2.int_node.throttle1.msg_count.Writeback_Control::3 8
-system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Response_Data::3 216
-system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Writeback_Control::3 64
-system.ruby.network.ext_links2.int_node.throttle2.link_utilization 0.006131
-system.ruby.network.ext_links2.int_node.throttle2.msg_count.Control::0 1
-system.ruby.network.ext_links2.int_node.throttle2.msg_count.Data::1 18
-system.ruby.network.ext_links2.int_node.throttle2.msg_count.Request_Control::1 9
-system.ruby.network.ext_links2.int_node.throttle2.msg_count.Response_Data::2 9
-system.ruby.network.ext_links2.int_node.throttle2.msg_count.Writeback_Control::2 16
-system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Control::0 8
-system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Data::1 1296
-system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Request_Control::1 72
-system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Response_Data::2 648
-system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Writeback_Control::2 128
-system.ruby.network.ext_links2.int_node.throttle3.link_utilization 0.001026
-system.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::3 5
-system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::3 360
-system.ruby.network.ext_links2.int_node.throttle4.link_utilization 0.004034
-system.ruby.network.ext_links2.int_node.throttle4.msg_count.Data::0 18
-system.ruby.network.ext_links2.int_node.throttle4.msg_count.Request_Control::0 7
-system.ruby.network.ext_links2.int_node.throttle4.msg_count.Response_Control::2 1
-system.ruby.network.ext_links2.int_node.throttle4.msg_count.Unblock_Control::4 7
-system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Data::0 1296
-system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Request_Control::0 56
-system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Response_Control::2 8
-system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Unblock_Control::4 56
-system.ruby.CorePair_Controller.C0_Load_L1miss 180 0.00% 0.00%
-system.ruby.CorePair_Controller.C0_Load_L1hit 16155 0.00% 0.00%
-system.ruby.CorePair_Controller.Ifetch0_L1hit 86007 0.00% 0.00%
-system.ruby.CorePair_Controller.Ifetch0_L1miss 1088 0.00% 0.00%
-system.ruby.CorePair_Controller.C0_Store_L1miss 325 0.00% 0.00%
-system.ruby.CorePair_Controller.C0_Store_L1hit 10448 0.00% 0.00%
-system.ruby.CorePair_Controller.NB_AckS 1034 0.00% 0.00%
-system.ruby.CorePair_Controller.NB_AckM 326 0.00% 0.00%
-system.ruby.CorePair_Controller.NB_AckE 175 0.00% 0.00%
-system.ruby.CorePair_Controller.L1I_Repl 589 0.00% 0.00%
-system.ruby.CorePair_Controller.L1D0_Repl 24 0.00% 0.00%
-system.ruby.CorePair_Controller.L2_to_L1D0 5 0.00% 0.00%
-system.ruby.CorePair_Controller.L2_to_L1I 54 0.00% 0.00%
-system.ruby.CorePair_Controller.PrbInvData 1 0.00% 0.00%
-system.ruby.CorePair_Controller.PrbShrData 2 0.00% 0.00%
-system.ruby.CorePair_Controller.I.C0_Load_L1miss 175 0.00% 0.00%
-system.ruby.CorePair_Controller.I.Ifetch0_L1miss 1034 0.00% 0.00%
-system.ruby.CorePair_Controller.I.C0_Store_L1miss 325 0.00% 0.00%
-system.ruby.CorePair_Controller.S.Ifetch0_L1hit 86007 0.00% 0.00%
-system.ruby.CorePair_Controller.S.Ifetch0_L1miss 54 0.00% 0.00%
-system.ruby.CorePair_Controller.S.L1I_Repl 589 0.00% 0.00%
-system.ruby.CorePair_Controller.E0.C0_Load_L1miss 2 0.00% 0.00%
-system.ruby.CorePair_Controller.E0.C0_Load_L1hit 3356 0.00% 0.00%
-system.ruby.CorePair_Controller.E0.C0_Store_L1hit 46 0.00% 0.00%
-system.ruby.CorePair_Controller.E0.L1D0_Repl 16 0.00% 0.00%
-system.ruby.CorePair_Controller.E0.PrbShrData 1 0.00% 0.00%
-system.ruby.CorePair_Controller.O.C0_Load_L1hit 3 0.00% 0.00%
-system.ruby.CorePair_Controller.O.C0_Store_L1hit 1 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.C0_Load_L1miss 3 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.C0_Load_L1hit 12796 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.C0_Store_L1hit 10401 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.L1D0_Repl 8 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.PrbInvData 1 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.PrbShrData 1 0.00% 0.00%
-system.ruby.CorePair_Controller.I_M0.NB_AckM 325 0.00% 0.00%
-system.ruby.CorePair_Controller.I_E0S.NB_AckE 175 0.00% 0.00%
-system.ruby.CorePair_Controller.Si_F0.L2_to_L1I 54 0.00% 0.00%
-system.ruby.CorePair_Controller.O_M0.NB_AckM 1 0.00% 0.00%
-system.ruby.CorePair_Controller.S0.NB_AckS 1034 0.00% 0.00%
-system.ruby.CorePair_Controller.E0_F.L2_to_L1D0 2 0.00% 0.00%
-system.ruby.CorePair_Controller.M0_F.L2_to_L1D0 3 0.00% 0.00%
-system.ruby.Directory_Controller.RdBlkS 1034 0.00% 0.00%
-system.ruby.Directory_Controller.RdBlkM 326 0.00% 0.00%
-system.ruby.Directory_Controller.RdBlk 182 0.00% 0.00%
-system.ruby.Directory_Controller.WriteThrough 16 0.00% 0.00%
-system.ruby.Directory_Controller.Atomic 3 0.00% 0.00%
-system.ruby.Directory_Controller.CPUPrbResp 4 0.00% 0.00%
-system.ruby.Directory_Controller.ProbeAcksComplete 1560 0.00% 0.00%
-system.ruby.Directory_Controller.MemData 1560 0.00% 0.00%
-system.ruby.Directory_Controller.CoreUnblock 1541 0.00% 0.00%
-system.ruby.Directory_Controller.UnblockWriteThrough 18 0.00% 0.00%
-system.ruby.Directory_Controller.U.RdBlkS 1034 0.00% 0.00%
-system.ruby.Directory_Controller.U.RdBlkM 326 0.00% 0.00%
-system.ruby.Directory_Controller.U.RdBlk 182 0.00% 0.00%
-system.ruby.Directory_Controller.U.WriteThrough 16 0.00% 0.00%
-system.ruby.Directory_Controller.U.Atomic 2 0.00% 0.00%
-system.ruby.Directory_Controller.BS_M.MemData 1034 0.00% 0.00%
-system.ruby.Directory_Controller.BM_M.MemData 343 0.00% 0.00%
-system.ruby.Directory_Controller.B_M.MemData 180 0.00% 0.00%
-system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 1034 0.00% 0.00%
-system.ruby.Directory_Controller.BM_PM.Atomic 1 0.00% 0.00%
-system.ruby.Directory_Controller.BM_PM.CPUPrbResp 1 0.00% 0.00%
-system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 343 0.00% 0.00%
-system.ruby.Directory_Controller.BM_PM.MemData 1 0.00% 0.00%
-system.ruby.Directory_Controller.B_PM.ProbeAcksComplete 180 0.00% 0.00%
-system.ruby.Directory_Controller.B_PM.MemData 2 0.00% 0.00%
-system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 1 0.00% 0.00%
-system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 1 0.00% 0.00%
-system.ruby.Directory_Controller.B_Pm.CPUPrbResp 2 0.00% 0.00%
-system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 2 0.00% 0.00%
-system.ruby.Directory_Controller.B.CoreUnblock 1541 0.00% 0.00%
-system.ruby.Directory_Controller.B.UnblockWriteThrough 18 0.00% 0.00%
-system.ruby.LD.latency_hist::bucket_size 64
-system.ruby.LD.latency_hist::max_bucket 639
-system.ruby.LD.latency_hist::samples 16335
-system.ruby.LD.latency_hist::mean 3.253444
-system.ruby.LD.latency_hist::gmean 1.059859
-system.ruby.LD.latency_hist::stdev 21.887471
-system.ruby.LD.latency_hist | 16160 98.93% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 170 1.04% 99.97% | 1 0.01% 99.98% | 1 0.01% 99.98% | 2 0.01% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.latency_hist::total 16335
-system.ruby.LD.hit_latency_hist::bucket_size 64
-system.ruby.LD.hit_latency_hist::max_bucket 639
-system.ruby.LD.hit_latency_hist::samples 175
-system.ruby.LD.hit_latency_hist::mean 210.828571
-system.ruby.LD.hit_latency_hist::gmean 209.031405
-system.ruby.LD.hit_latency_hist::stdev 34.022715
-system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 170 97.14% 97.14% | 1 0.57% 97.71% | 1 0.57% 98.29% | 2 1.14% 99.43% | 1 0.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.hit_latency_hist::total 175
-system.ruby.LD.miss_latency_hist::bucket_size 2
-system.ruby.LD.miss_latency_hist::max_bucket 19
-system.ruby.LD.miss_latency_hist::samples 16160
-system.ruby.LD.miss_latency_hist::mean 1.005569
-system.ruby.LD.miss_latency_hist::gmean 1.000911
-system.ruby.LD.miss_latency_hist::stdev 0.316580
-system.ruby.LD.miss_latency_hist | 16155 99.97% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 5 0.03% 100.00%
-system.ruby.LD.miss_latency_hist::total 16160
-system.ruby.ST.latency_hist::bucket_size 64
-system.ruby.ST.latency_hist::max_bucket 639
-system.ruby.ST.latency_hist::samples 10412
-system.ruby.ST.latency_hist::mean 7.384076
-system.ruby.ST.latency_hist::gmean 1.178989
-system.ruby.ST.latency_hist::stdev 36.341010
-system.ruby.ST.latency_hist | 10090 96.91% 96.91% | 0 0.00% 96.91% | 0 0.00% 96.91% | 309 2.97% 99.88% | 4 0.04% 99.91% | 2 0.02% 99.93% | 3 0.03% 99.96% | 4 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.latency_hist::total 10412
-system.ruby.ST.hit_latency_hist::bucket_size 64
-system.ruby.ST.hit_latency_hist::max_bucket 639
-system.ruby.ST.hit_latency_hist::samples 322
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-system.ruby.IFETCH.latency_hist | 86061 98.81% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1006 1.16% 99.97% | 5 0.01% 99.97% | 10 0.01% 99.99% | 11 0.01% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.IFETCH.miss_latency_hist | 86007 99.94% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 54 0.06% 100.00%
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-system.ruby.RMW_Read.latency_hist | 337 98.83% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 3 0.88% 99.71% | 1 0.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 75.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.Locked_RMW_Read.latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.Locked_RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.Locked_RMW_Write.miss_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.L1Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 112609 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.L2Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 59 100.00% 100.00%
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-system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 16155 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.LD.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 170 97.14% 97.14% | 1 0.57% 97.71% | 1 0.57% 98.29% | 2 1.14% 99.43% | 1 0.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.ST.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 309 95.96% 95.96% | 4 1.24% 97.20% | 2 0.62% 97.83% | 3 0.93% 98.76% | 4 1.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 86007 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 54 100.00% 100.00%
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-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1006 97.29% 97.29% | 5 0.48% 97.78% | 10 0.97% 98.74% | 11 1.06% 99.81% | 2 0.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 75.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.TCC_Controller.PrbInv 1 0.00% 0.00%
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-system.ruby.TCC_Controller.I.WBAck 16 0.00% 0.00%
-system.ruby.TCC_Controller.IV.RdBlk 2 0.00% 0.00%
-system.ruby.TCC_Controller.IV.Data 7 0.00% 0.00%
-system.ruby.TCC_Controller.A.Atomic 1 0.00% 0.00%
-system.ruby.TCC_Controller.A.AtomicDone 1 0.00% 0.00%
-system.ruby.TCC_Controller.A.Data 2 0.00% 0.00%
-system.ruby.TCP_Controller.Load | 5 50.00% 50.00% | 5 50.00% 100.00%
-system.ruby.TCP_Controller.Load::total 10
-system.ruby.TCP_Controller.StoreThrough | 8 50.00% 50.00% | 8 50.00% 100.00%
-system.ruby.TCP_Controller.StoreThrough::total 16
-system.ruby.TCP_Controller.Atomic | 1 50.00% 50.00% | 1 50.00% 100.00%
-system.ruby.TCP_Controller.Atomic::total 2
-system.ruby.TCP_Controller.Flush | 768 50.00% 50.00% | 768 50.00% 100.00%
-system.ruby.TCP_Controller.Flush::total 1536
-system.ruby.TCP_Controller.Evict | 512 50.00% 50.00% | 512 50.00% 100.00%
-system.ruby.TCP_Controller.Evict::total 1024
-system.ruby.TCP_Controller.TCC_Ack | 3 50.00% 50.00% | 3 50.00% 100.00%
-system.ruby.TCP_Controller.TCC_Ack::total 6
-system.ruby.TCP_Controller.TCC_AckWB | 8 50.00% 50.00% | 8 50.00% 100.00%
-system.ruby.TCP_Controller.TCC_AckWB::total 16
-system.ruby.TCP_Controller.I.Load | 2 50.00% 50.00% | 2 50.00% 100.00%
-system.ruby.TCP_Controller.I.Load::total 4
-system.ruby.TCP_Controller.I.StoreThrough | 8 50.00% 50.00% | 8 50.00% 100.00%
-system.ruby.TCP_Controller.I.StoreThrough::total 16
-system.ruby.TCP_Controller.I.Atomic | 1 50.00% 50.00% | 1 50.00% 100.00%
-system.ruby.TCP_Controller.I.Atomic::total 2
-system.ruby.TCP_Controller.I.Flush | 766 50.00% 50.00% | 766 50.00% 100.00%
-system.ruby.TCP_Controller.I.Flush::total 1532
-system.ruby.TCP_Controller.I.Evict | 510 50.00% 50.00% | 510 50.00% 100.00%
-system.ruby.TCP_Controller.I.Evict::total 1020
-system.ruby.TCP_Controller.I.TCC_Ack | 2 50.00% 50.00% | 2 50.00% 100.00%
-system.ruby.TCP_Controller.I.TCC_Ack::total 4
-system.ruby.TCP_Controller.I.TCC_AckWB | 8 50.00% 50.00% | 8 50.00% 100.00%
-system.ruby.TCP_Controller.I.TCC_AckWB::total 16
-system.ruby.TCP_Controller.V.Load | 3 50.00% 50.00% | 3 50.00% 100.00%
-system.ruby.TCP_Controller.V.Load::total 6
-system.ruby.TCP_Controller.V.Flush | 2 50.00% 50.00% | 2 50.00% 100.00%
-system.ruby.TCP_Controller.V.Flush::total 4
-system.ruby.TCP_Controller.V.Evict | 2 50.00% 50.00% | 2 50.00% 100.00%
-system.ruby.TCP_Controller.V.Evict::total 4
-system.ruby.TCP_Controller.A.TCC_Ack | 1 50.00% 50.00% | 1 50.00% 100.00%
-system.ruby.TCP_Controller.A.TCC_Ack::total 2
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cp_cntrl0 cpu0 cpu1 cpu2 dir_cntrl0 dispatcher_coalescer dispatcher_tlb dvfs_handler l1_coalescer0 l1_coalescer1 l1_tlb0 l1_tlb1 l2_coalescer l2_tlb l3_coalescer l3_tlb mem_ctrls piobus rb_cntrl0 reg_cntrl0 ruby sqc_cntrl0 sqc_coalescer sqc_tlb sys_port_proxy tcc_cntrl0 tcc_rb_cntrl0 tcp_cntrl0 tcp_cntrl1 voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:536870911
-memories=system.mem_ctrls system.ruby.phys_mem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.sys_port_proxy.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cp_cntrl0]
-type=CorePair_Controller
-children=L1D0cache L1D1cache L1Icache L2cache mandatoryQueue probeToCore requestFromCore responseFromCore responseToCore sequencer sequencer1 triggerQueue unblockFromCore
-L1D0cache=system.cp_cntrl0.L1D0cache
-L1D1cache=system.cp_cntrl0.L1D1cache
-L1Icache=system.cp_cntrl0.L1Icache
-L2cache=system.cp_cntrl0.L2cache
-buffer_size=0
-clk_domain=system.clk_domain
-cluster_id=0
-eventq_index=0
-issue_latency=1
-l2_hit_latency=18
-mandatoryQueue=system.cp_cntrl0.mandatoryQueue
-number_of_TBEs=256
-probeToCore=system.cp_cntrl0.probeToCore
-recycle_latency=10
-regionBufferNum=0
-requestFromCore=system.cp_cntrl0.requestFromCore
-responseFromCore=system.cp_cntrl0.responseFromCore
-responseToCore=system.cp_cntrl0.responseToCore
-ruby_system=system.ruby
-send_evictions=true
-sequencer=system.cp_cntrl0.sequencer
-sequencer1=system.cp_cntrl0.sequencer1
-system=system
-transitions_per_cycle=32
-triggerQueue=system.cp_cntrl0.triggerQueue
-unblockFromCore=system.cp_cntrl0.unblockFromCore
-version=0
-
-[system.cp_cntrl0.L1D0cache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=2
-eventq_index=0
-is_icache=false
-replacement_policy=system.cp_cntrl0.L1D0cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=65536
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=2
-
-[system.cp_cntrl0.L1D0cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=65536
-
-[system.cp_cntrl0.L1D1cache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=2
-eventq_index=0
-is_icache=false
-replacement_policy=system.cp_cntrl0.L1D1cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=65536
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=2
-
-[system.cp_cntrl0.L1D1cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=65536
-
-[system.cp_cntrl0.L1Icache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=2
-eventq_index=0
-is_icache=false
-replacement_policy=system.cp_cntrl0.L1Icache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=32768
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=2
-
-[system.cp_cntrl0.L1Icache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=32768
-
-[system.cp_cntrl0.L2cache]
-type=RubyCache
-children=replacement_policy
-assoc=8
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=16
-eventq_index=0
-is_icache=false
-replacement_policy=system.cp_cntrl0.L2cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=2097152
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=16
-
-[system.cp_cntrl0.L2cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=8
-block_size=64
-eventq_index=0
-size=2097152
-
-[system.cp_cntrl0.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.cp_cntrl0.probeToCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[0]
-
-[system.cp_cntrl0.requestFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[0]
-
-[system.cp_cntrl0.responseFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[1]
-
-[system.cp_cntrl0.responseToCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[1]
-
-[system.cp_cntrl0.sequencer]
-type=RubySequencer
-clk_domain=system.clk_domain
-coreid=0
-dcache=system.cp_cntrl0.L1D0cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-eventq_index=0
-icache=system.cp_cntrl0.L1Icache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=0
-master=system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave
-mem_master_port=system.piobus.slave[0]
-slave=system.cpu0.icache_port system.cpu0.dcache_port system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.interrupts.int_master
-
-[system.cp_cntrl0.sequencer1]
-type=RubySequencer
-clk_domain=system.clk_domain
-coreid=1
-dcache=system.cp_cntrl0.L1D1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-eventq_index=0
-icache=system.cp_cntrl0.L1Icache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=1
-
-[system.cp_cntrl0.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.cp_cntrl0.unblockFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[2]
-
-[system.cpu0]
-type=TimingSimpleCPU
-children=apic_clk_domain clk_domain dtb interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu0.clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu0.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu0.tracer
-workload=system.cpu0.workload
-dcache_port=system.cp_cntrl0.sequencer.slave[1]
-icache_port=system.cp_cntrl0.sequencer.slave[0]
-
-[system.cpu0.apic_clk_domain]
-type=DerivedClockDomain
-clk_divider=16
-clk_domain=system.cpu0.clk_domain
-eventq_index=0
-
-[system.cpu0.clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0.dtb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu0.dtb.walker
-
-[system.cpu0.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu0.clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-port=system.cp_cntrl0.sequencer.slave[3]
-
-[system.cpu0.interrupts]
-type=X86LocalApic
-clk_domain=system.cpu0.apic_clk_domain
-eventq_index=0
-int_latency=1000
-pio_addr=2305843009213693952
-pio_latency=100000
-system=system
-int_master=system.cp_cntrl0.sequencer.slave[4]
-int_slave=system.cp_cntrl0.sequencer.master[1]
-pio=system.cp_cntrl0.sequencer.master[0]
-
-[system.cpu0.isa]
-type=X86ISA
-eventq_index=0
-
-[system.cpu0.itb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu0.itb.walker
-
-[system.cpu0.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu0.clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-port=system.cp_cntrl0.sequencer.slave[2]
-
-[system.cpu0.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu0.workload]
-type=LiveProcess
-cmd=gpu-hello
-cwd=
-drivers=system.cpu2.cl_driver
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello
-gid=100
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu1]
-type=Shader
-children=CUs0 CUs1 clk_domain
-CUs=system.cpu1.CUs0 system.cpu1.CUs1
-clk_domain=system.cpu1.clk_domain
-cpu_pointer=system.cpu0
-eventq_index=0
-globalmem=65536
-impl_kern_boundary_sync=true
-n_wf=8
-separate_acquire_release=false
-timing=true
-translation=false
-
-[system.cpu1.CUs0]
-type=ComputeUnit
-children=ldsBus localDataStore vector_register_file0 vector_register_file1 vector_register_file2 vector_register_file3 wavefronts00 wavefronts01 wavefronts02 wavefronts03 wavefronts04 wavefronts05 wavefronts06 wavefronts07 wavefronts08 wavefronts09 wavefronts10 wavefronts11 wavefronts12 wavefronts13 wavefronts14 wavefronts15 wavefronts16 wavefronts17 wavefronts18 wavefronts19 wavefronts20 wavefronts21 wavefronts22 wavefronts23 wavefronts24 wavefronts25 wavefronts26 wavefronts27 wavefronts28 wavefronts29 wavefronts30 wavefronts31
-clk_domain=system.cpu1.clk_domain
-coalescer_to_vrf_bus_width=32
-countPages=false
-cu_id=0
-debugSegFault=false
-dpbypass_pipe_length=4
-eventq_index=0
-execPolicy=OLDEST-FIRST
-functionalTLB=true
-global_mem_queue_size=256
-issue_period=4
-localDataStore=system.cpu1.CUs0.localDataStore
-localMemBarrier=false
-local_mem_queue_size=256
-mem_req_latency=9
-mem_resp_latency=9
-n_wf=8
-num_SIMDs=4
-num_global_mem_pipes=1
-num_shared_mem_pipes=1
-perLaneTLB=false
-prefetch_depth=0
-prefetch_prev_type=PF_PHASE
-prefetch_stride=1
-spbypass_pipe_length=4
-system=system
-vector_register_file=system.cpu1.CUs0.vector_register_file0 system.cpu1.CUs0.vector_register_file1 system.cpu1.CUs0.vector_register_file2 system.cpu1.CUs0.vector_register_file3
-vrf_to_coalescer_bus_width=32
-wavefronts=system.cpu1.CUs0.wavefronts00 system.cpu1.CUs0.wavefronts01 system.cpu1.CUs0.wavefronts02 system.cpu1.CUs0.wavefronts03 system.cpu1.CUs0.wavefronts04 system.cpu1.CUs0.wavefronts05 system.cpu1.CUs0.wavefronts06 system.cpu1.CUs0.wavefronts07 system.cpu1.CUs0.wavefronts08 system.cpu1.CUs0.wavefronts09 system.cpu1.CUs0.wavefronts10 system.cpu1.CUs0.wavefronts11 system.cpu1.CUs0.wavefronts12 system.cpu1.CUs0.wavefronts13 system.cpu1.CUs0.wavefronts14 system.cpu1.CUs0.wavefronts15 system.cpu1.CUs0.wavefronts16 system.cpu1.CUs0.wavefronts17 system.cpu1.CUs0.wavefronts18 system.cpu1.CUs0.wavefronts19 system.cpu1.CUs0.wavefronts20 system.cpu1.CUs0.wavefronts21 system.cpu1.CUs0.wavefronts22 system.cpu1.CUs0.wavefronts23 system.cpu1.CUs0.wavefronts24 system.cpu1.CUs0.wavefronts25 system.cpu1.CUs0.wavefronts26 system.cpu1.CUs0.wavefronts27 system.cpu1.CUs0.wavefronts28 system.cpu1.CUs0.wavefronts29 system.cpu1.CUs0.wavefronts30 system.cpu1.CUs0.wavefronts31
-wfSize=64
-xactCasMode=false
-ldsPort=system.cpu1.CUs0.ldsBus.slave
-memory_port=system.tcp_cntrl0.coalescer.slave[0] system.tcp_cntrl0.coalescer.slave[1] system.tcp_cntrl0.coalescer.slave[2] system.tcp_cntrl0.coalescer.slave[3] system.tcp_cntrl0.coalescer.slave[4] system.tcp_cntrl0.coalescer.slave[5] system.tcp_cntrl0.coalescer.slave[6] system.tcp_cntrl0.coalescer.slave[7] system.tcp_cntrl0.coalescer.slave[8] system.tcp_cntrl0.coalescer.slave[9] system.tcp_cntrl0.coalescer.slave[10] system.tcp_cntrl0.coalescer.slave[11] system.tcp_cntrl0.coalescer.slave[12] system.tcp_cntrl0.coalescer.slave[13] system.tcp_cntrl0.coalescer.slave[14] system.tcp_cntrl0.coalescer.slave[15] system.tcp_cntrl0.coalescer.slave[16] system.tcp_cntrl0.coalescer.slave[17] system.tcp_cntrl0.coalescer.slave[18] system.tcp_cntrl0.coalescer.slave[19] system.tcp_cntrl0.coalescer.slave[20] system.tcp_cntrl0.coalescer.slave[21] system.tcp_cntrl0.coalescer.slave[22] system.tcp_cntrl0.coalescer.slave[23] system.tcp_cntrl0.coalescer.slave[24] system.tcp_cntrl0.coalescer.slave[25] system.tcp_cntrl0.coalescer.slave[26] system.tcp_cntrl0.coalescer.slave[27] system.tcp_cntrl0.coalescer.slave[28] system.tcp_cntrl0.coalescer.slave[29] system.tcp_cntrl0.coalescer.slave[30] system.tcp_cntrl0.coalescer.slave[31] system.tcp_cntrl0.coalescer.slave[32] system.tcp_cntrl0.coalescer.slave[33] system.tcp_cntrl0.coalescer.slave[34] system.tcp_cntrl0.coalescer.slave[35] system.tcp_cntrl0.coalescer.slave[36] system.tcp_cntrl0.coalescer.slave[37] system.tcp_cntrl0.coalescer.slave[38] system.tcp_cntrl0.coalescer.slave[39] system.tcp_cntrl0.coalescer.slave[40] system.tcp_cntrl0.coalescer.slave[41] system.tcp_cntrl0.coalescer.slave[42] system.tcp_cntrl0.coalescer.slave[43] system.tcp_cntrl0.coalescer.slave[44] system.tcp_cntrl0.coalescer.slave[45] system.tcp_cntrl0.coalescer.slave[46] system.tcp_cntrl0.coalescer.slave[47] system.tcp_cntrl0.coalescer.slave[48] system.tcp_cntrl0.coalescer.slave[49] system.tcp_cntrl0.coalescer.slave[50] system.tcp_cntrl0.coalescer.slave[51] system.tcp_cntrl0.coalescer.slave[52] system.tcp_cntrl0.coalescer.slave[53] system.tcp_cntrl0.coalescer.slave[54] system.tcp_cntrl0.coalescer.slave[55] system.tcp_cntrl0.coalescer.slave[56] system.tcp_cntrl0.coalescer.slave[57] system.tcp_cntrl0.coalescer.slave[58] system.tcp_cntrl0.coalescer.slave[59] system.tcp_cntrl0.coalescer.slave[60] system.tcp_cntrl0.coalescer.slave[61] system.tcp_cntrl0.coalescer.slave[62] system.tcp_cntrl0.coalescer.slave[63]
-sqc_port=system.sqc_cntrl0.sequencer.slave[0]
-sqc_tlb_port=system.sqc_coalescer.slave[0]
-translation_port=system.l1_coalescer0.slave[0]
-
-[system.cpu1.CUs0.ldsBus]
-type=Bridge
-clk_domain=system.cpu1.clk_domain
-delay=0
-eventq_index=0
-ranges=0:18446744073709551615
-req_size=16
-resp_size=16
-master=system.cpu1.CUs0.localDataStore.cuPort
-slave=system.cpu1.CUs0.ldsPort
-
-[system.cpu1.CUs0.localDataStore]
-type=LdsState
-bankConflictPenalty=1
-banks=32
-clk_domain=system.cpu1.clk_domain
-eventq_index=0
-range=0:65535
-size=65536
-cuPort=system.cpu1.CUs0.ldsBus.master
-
-[system.cpu1.CUs0.vector_register_file0]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=0
-
-[system.cpu1.CUs0.vector_register_file1]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=1
-
-[system.cpu1.CUs0.vector_register_file2]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=2
-
-[system.cpu1.CUs0.vector_register_file3]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=3
-
-[system.cpu1.CUs0.wavefronts00]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=0
-
-[system.cpu1.CUs0.wavefronts01]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=1
-
-[system.cpu1.CUs0.wavefronts02]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=2
-
-[system.cpu1.CUs0.wavefronts03]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=3
-
-[system.cpu1.CUs0.wavefronts04]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=4
-
-[system.cpu1.CUs0.wavefronts05]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=5
-
-[system.cpu1.CUs0.wavefronts06]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=6
-
-[system.cpu1.CUs0.wavefronts07]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=7
-
-[system.cpu1.CUs0.wavefronts08]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=0
-
-[system.cpu1.CUs0.wavefronts09]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=1
-
-[system.cpu1.CUs0.wavefronts10]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=2
-
-[system.cpu1.CUs0.wavefronts11]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=3
-
-[system.cpu1.CUs0.wavefronts12]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=4
-
-[system.cpu1.CUs0.wavefronts13]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=5
-
-[system.cpu1.CUs0.wavefronts14]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=6
-
-[system.cpu1.CUs0.wavefronts15]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=7
-
-[system.cpu1.CUs0.wavefronts16]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=0
-
-[system.cpu1.CUs0.wavefronts17]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=1
-
-[system.cpu1.CUs0.wavefronts18]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=2
-
-[system.cpu1.CUs0.wavefronts19]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=3
-
-[system.cpu1.CUs0.wavefronts20]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=4
-
-[system.cpu1.CUs0.wavefronts21]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=5
-
-[system.cpu1.CUs0.wavefronts22]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=6
-
-[system.cpu1.CUs0.wavefronts23]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=7
-
-[system.cpu1.CUs0.wavefronts24]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=0
-
-[system.cpu1.CUs0.wavefronts25]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=1
-
-[system.cpu1.CUs0.wavefronts26]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=2
-
-[system.cpu1.CUs0.wavefronts27]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=3
-
-[system.cpu1.CUs0.wavefronts28]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=4
-
-[system.cpu1.CUs0.wavefronts29]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=5
-
-[system.cpu1.CUs0.wavefronts30]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=6
-
-[system.cpu1.CUs0.wavefronts31]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=7
-
-[system.cpu1.CUs1]
-type=ComputeUnit
-children=ldsBus localDataStore vector_register_file0 vector_register_file1 vector_register_file2 vector_register_file3 wavefronts00 wavefronts01 wavefronts02 wavefronts03 wavefronts04 wavefronts05 wavefronts06 wavefronts07 wavefronts08 wavefronts09 wavefronts10 wavefronts11 wavefronts12 wavefronts13 wavefronts14 wavefronts15 wavefronts16 wavefronts17 wavefronts18 wavefronts19 wavefronts20 wavefronts21 wavefronts22 wavefronts23 wavefronts24 wavefronts25 wavefronts26 wavefronts27 wavefronts28 wavefronts29 wavefronts30 wavefronts31
-clk_domain=system.cpu1.clk_domain
-coalescer_to_vrf_bus_width=32
-countPages=false
-cu_id=1
-debugSegFault=false
-dpbypass_pipe_length=4
-eventq_index=0
-execPolicy=OLDEST-FIRST
-functionalTLB=true
-global_mem_queue_size=256
-issue_period=4
-localDataStore=system.cpu1.CUs1.localDataStore
-localMemBarrier=false
-local_mem_queue_size=256
-mem_req_latency=9
-mem_resp_latency=9
-n_wf=8
-num_SIMDs=4
-num_global_mem_pipes=1
-num_shared_mem_pipes=1
-perLaneTLB=false
-prefetch_depth=0
-prefetch_prev_type=PF_PHASE
-prefetch_stride=1
-spbypass_pipe_length=4
-system=system
-vector_register_file=system.cpu1.CUs1.vector_register_file0 system.cpu1.CUs1.vector_register_file1 system.cpu1.CUs1.vector_register_file2 system.cpu1.CUs1.vector_register_file3
-vrf_to_coalescer_bus_width=32
-wavefronts=system.cpu1.CUs1.wavefronts00 system.cpu1.CUs1.wavefronts01 system.cpu1.CUs1.wavefronts02 system.cpu1.CUs1.wavefronts03 system.cpu1.CUs1.wavefronts04 system.cpu1.CUs1.wavefronts05 system.cpu1.CUs1.wavefronts06 system.cpu1.CUs1.wavefronts07 system.cpu1.CUs1.wavefronts08 system.cpu1.CUs1.wavefronts09 system.cpu1.CUs1.wavefronts10 system.cpu1.CUs1.wavefronts11 system.cpu1.CUs1.wavefronts12 system.cpu1.CUs1.wavefronts13 system.cpu1.CUs1.wavefronts14 system.cpu1.CUs1.wavefronts15 system.cpu1.CUs1.wavefronts16 system.cpu1.CUs1.wavefronts17 system.cpu1.CUs1.wavefronts18 system.cpu1.CUs1.wavefronts19 system.cpu1.CUs1.wavefronts20 system.cpu1.CUs1.wavefronts21 system.cpu1.CUs1.wavefronts22 system.cpu1.CUs1.wavefronts23 system.cpu1.CUs1.wavefronts24 system.cpu1.CUs1.wavefronts25 system.cpu1.CUs1.wavefronts26 system.cpu1.CUs1.wavefronts27 system.cpu1.CUs1.wavefronts28 system.cpu1.CUs1.wavefronts29 system.cpu1.CUs1.wavefronts30 system.cpu1.CUs1.wavefronts31
-wfSize=64
-xactCasMode=false
-ldsPort=system.cpu1.CUs1.ldsBus.slave
-memory_port=system.tcp_cntrl1.coalescer.slave[0] system.tcp_cntrl1.coalescer.slave[1] system.tcp_cntrl1.coalescer.slave[2] system.tcp_cntrl1.coalescer.slave[3] system.tcp_cntrl1.coalescer.slave[4] system.tcp_cntrl1.coalescer.slave[5] system.tcp_cntrl1.coalescer.slave[6] system.tcp_cntrl1.coalescer.slave[7] system.tcp_cntrl1.coalescer.slave[8] system.tcp_cntrl1.coalescer.slave[9] system.tcp_cntrl1.coalescer.slave[10] system.tcp_cntrl1.coalescer.slave[11] system.tcp_cntrl1.coalescer.slave[12] system.tcp_cntrl1.coalescer.slave[13] system.tcp_cntrl1.coalescer.slave[14] system.tcp_cntrl1.coalescer.slave[15] system.tcp_cntrl1.coalescer.slave[16] system.tcp_cntrl1.coalescer.slave[17] system.tcp_cntrl1.coalescer.slave[18] system.tcp_cntrl1.coalescer.slave[19] system.tcp_cntrl1.coalescer.slave[20] system.tcp_cntrl1.coalescer.slave[21] system.tcp_cntrl1.coalescer.slave[22] system.tcp_cntrl1.coalescer.slave[23] system.tcp_cntrl1.coalescer.slave[24] system.tcp_cntrl1.coalescer.slave[25] system.tcp_cntrl1.coalescer.slave[26] system.tcp_cntrl1.coalescer.slave[27] system.tcp_cntrl1.coalescer.slave[28] system.tcp_cntrl1.coalescer.slave[29] system.tcp_cntrl1.coalescer.slave[30] system.tcp_cntrl1.coalescer.slave[31] system.tcp_cntrl1.coalescer.slave[32] system.tcp_cntrl1.coalescer.slave[33] system.tcp_cntrl1.coalescer.slave[34] system.tcp_cntrl1.coalescer.slave[35] system.tcp_cntrl1.coalescer.slave[36] system.tcp_cntrl1.coalescer.slave[37] system.tcp_cntrl1.coalescer.slave[38] system.tcp_cntrl1.coalescer.slave[39] system.tcp_cntrl1.coalescer.slave[40] system.tcp_cntrl1.coalescer.slave[41] system.tcp_cntrl1.coalescer.slave[42] system.tcp_cntrl1.coalescer.slave[43] system.tcp_cntrl1.coalescer.slave[44] system.tcp_cntrl1.coalescer.slave[45] system.tcp_cntrl1.coalescer.slave[46] system.tcp_cntrl1.coalescer.slave[47] system.tcp_cntrl1.coalescer.slave[48] system.tcp_cntrl1.coalescer.slave[49] system.tcp_cntrl1.coalescer.slave[50] system.tcp_cntrl1.coalescer.slave[51] system.tcp_cntrl1.coalescer.slave[52] system.tcp_cntrl1.coalescer.slave[53] system.tcp_cntrl1.coalescer.slave[54] system.tcp_cntrl1.coalescer.slave[55] system.tcp_cntrl1.coalescer.slave[56] system.tcp_cntrl1.coalescer.slave[57] system.tcp_cntrl1.coalescer.slave[58] system.tcp_cntrl1.coalescer.slave[59] system.tcp_cntrl1.coalescer.slave[60] system.tcp_cntrl1.coalescer.slave[61] system.tcp_cntrl1.coalescer.slave[62] system.tcp_cntrl1.coalescer.slave[63]
-sqc_port=system.sqc_cntrl0.sequencer.slave[1]
-sqc_tlb_port=system.sqc_coalescer.slave[1]
-translation_port=system.l1_coalescer1.slave[0]
-
-[system.cpu1.CUs1.ldsBus]
-type=Bridge
-clk_domain=system.cpu1.clk_domain
-delay=0
-eventq_index=0
-ranges=0:18446744073709551615
-req_size=16
-resp_size=16
-master=system.cpu1.CUs1.localDataStore.cuPort
-slave=system.cpu1.CUs1.ldsPort
-
-[system.cpu1.CUs1.localDataStore]
-type=LdsState
-bankConflictPenalty=1
-banks=32
-clk_domain=system.cpu1.clk_domain
-eventq_index=0
-range=0:65535
-size=65536
-cuPort=system.cpu1.CUs1.ldsBus.master
-
-[system.cpu1.CUs1.vector_register_file0]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=0
-
-[system.cpu1.CUs1.vector_register_file1]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=1
-
-[system.cpu1.CUs1.vector_register_file2]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=2
-
-[system.cpu1.CUs1.vector_register_file3]
-type=VectorRegisterFile
-eventq_index=0
-min_alloc=4
-num_regs_per_simd=2048
-simd_id=3
-
-[system.cpu1.CUs1.wavefronts00]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=0
-
-[system.cpu1.CUs1.wavefronts01]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=1
-
-[system.cpu1.CUs1.wavefronts02]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=2
-
-[system.cpu1.CUs1.wavefronts03]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=3
-
-[system.cpu1.CUs1.wavefronts04]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=4
-
-[system.cpu1.CUs1.wavefronts05]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=5
-
-[system.cpu1.CUs1.wavefronts06]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=6
-
-[system.cpu1.CUs1.wavefronts07]
-type=Wavefront
-eventq_index=0
-simdId=0
-wf_slot_id=7
-
-[system.cpu1.CUs1.wavefronts08]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=0
-
-[system.cpu1.CUs1.wavefronts09]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=1
-
-[system.cpu1.CUs1.wavefronts10]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=2
-
-[system.cpu1.CUs1.wavefronts11]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=3
-
-[system.cpu1.CUs1.wavefronts12]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=4
-
-[system.cpu1.CUs1.wavefronts13]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=5
-
-[system.cpu1.CUs1.wavefronts14]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=6
-
-[system.cpu1.CUs1.wavefronts15]
-type=Wavefront
-eventq_index=0
-simdId=1
-wf_slot_id=7
-
-[system.cpu1.CUs1.wavefronts16]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=0
-
-[system.cpu1.CUs1.wavefronts17]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=1
-
-[system.cpu1.CUs1.wavefronts18]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=2
-
-[system.cpu1.CUs1.wavefronts19]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=3
-
-[system.cpu1.CUs1.wavefronts20]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=4
-
-[system.cpu1.CUs1.wavefronts21]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=5
-
-[system.cpu1.CUs1.wavefronts22]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=6
-
-[system.cpu1.CUs1.wavefronts23]
-type=Wavefront
-eventq_index=0
-simdId=2
-wf_slot_id=7
-
-[system.cpu1.CUs1.wavefronts24]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=0
-
-[system.cpu1.CUs1.wavefronts25]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=1
-
-[system.cpu1.CUs1.wavefronts26]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=2
-
-[system.cpu1.CUs1.wavefronts27]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=3
-
-[system.cpu1.CUs1.wavefronts28]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=4
-
-[system.cpu1.CUs1.wavefronts29]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=5
-
-[system.cpu1.CUs1.wavefronts30]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=6
-
-[system.cpu1.CUs1.wavefronts31]
-type=Wavefront
-eventq_index=0
-simdId=3
-wf_slot_id=7
-
-[system.cpu1.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.cpu1.clk_domain.voltage_domain
-
-[system.cpu1.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.cpu2]
-type=GpuDispatcher
-children=cl_driver
-cl_driver=system.cpu2.cl_driver
-clk_domain=system.clk_domain
-cpu=system.cpu0
-eventq_index=0
-pio_addr=8589934592
-pio_latency=1000
-shader_pointer=system.cpu1
-system=system
-dma=system.piobus.slave[1]
-pio=system.piobus.master[0]
-translation_port=system.dispatcher_coalescer.slave[0]
-
-[system.cpu2.cl_driver]
-type=ClDriver
-codefile=/dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm
-eventq_index=0
-filename=hsa
-
-[system.dir_cntrl0]
-type=Directory_Controller
-children=L3CacheMemory L3triggerQueue directory probeToCore reqFromRegBuf reqFromRegDir reqToRegDir requestFromCores responseFromCores responseFromMemory responseToCore triggerQueue unblockFromCores unblockToRegDir
-L3CacheMemory=system.dir_cntrl0.L3CacheMemory
-L3triggerQueue=system.dir_cntrl0.L3triggerQueue
-buffer_size=0
-clk_domain=system.clk_domain
-cluster_id=0
-directory=system.dir_cntrl0.directory
-eventq_index=0
-l3_hit_latency=15
-number_of_TBEs=5120
-probeToCore=system.dir_cntrl0.probeToCore
-recycle_latency=10
-reqFromRegBuf=system.dir_cntrl0.reqFromRegBuf
-reqFromRegDir=system.dir_cntrl0.reqFromRegDir
-reqToRegDir=system.dir_cntrl0.reqToRegDir
-requestFromCores=system.dir_cntrl0.requestFromCores
-responseFromCores=system.dir_cntrl0.responseFromCores
-responseFromMemory=system.dir_cntrl0.responseFromMemory
-responseToCore=system.dir_cntrl0.responseToCore
-response_latency=25
-response_latency_regionDir=1
-ruby_system=system.ruby
-system=system
-to_memory_controller_latency=1
-transitions_per_cycle=32
-triggerQueue=system.dir_cntrl0.triggerQueue
-unblockFromCores=system.dir_cntrl0.unblockFromCores
-unblockToRegDir=system.dir_cntrl0.unblockToRegDir
-useL3OnWT=false
-version=0
-memory=system.mem_ctrls.port
-
-[system.dir_cntrl0.L3CacheMemory]
-type=RubyCache
-children=replacement_policy
-assoc=16
-block_size=0
-dataAccessLatency=20
-dataArrayBanks=16.0
-eventq_index=0
-is_icache=false
-replacement_policy=system.dir_cntrl0.L3CacheMemory.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=16777216
-start_index_bit=6
-tagAccessLatency=15
-tagArrayBanks=16.0
-
-[system.dir_cntrl0.L3CacheMemory.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=16
-block_size=64
-eventq_index=0
-size=16777216
-
-[system.dir_cntrl0.L3triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.dir_cntrl0.directory]
-type=RubyDirectoryMemory
-eventq_index=0
-numa_high_bit=5
-size=536870912
-version=0
-
-[system.dir_cntrl0.probeToCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[18]
-
-[system.dir_cntrl0.reqFromRegBuf]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[24]
-
-[system.dir_cntrl0.reqFromRegDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[25]
-
-[system.dir_cntrl0.reqToRegDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[20]
-
-[system.dir_cntrl0.requestFromCores]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[21]
-
-[system.dir_cntrl0.responseFromCores]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[22]
-
-[system.dir_cntrl0.responseFromMemory]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.dir_cntrl0.responseToCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[19]
-
-[system.dir_cntrl0.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.dir_cntrl0.unblockFromCores]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[23]
-
-[system.dir_cntrl0.unblockToRegDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[21]
-
-[system.dispatcher_coalescer]
-type=TLBCoalescer
-children=clk_domain
-clk_domain=system.dispatcher_coalescer.clk_domain
-coalescingWindow=1
-disableCoalescing=false
-eventq_index=0
-probesPerCycle=2
-master=system.dispatcher_tlb.slave[0]
-slave=system.cpu2.translation_port
-
-[system.dispatcher_coalescer.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.dispatcher_coalescer.clk_domain.voltage_domain
-
-[system.dispatcher_coalescer.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.dispatcher_tlb]
-type=X86GPUTLB
-children=clk_domain
-accessDistance=false
-allocationPolicy=true
-assoc=32
-clk_domain=system.dispatcher_tlb.clk_domain
-eventq_index=0
-hitLatency=1
-maxOutstandingReqs=64
-missLatency1=5
-missLatency2=750
-size=32
-master=system.l2_coalescer.slave[1]
-slave=system.dispatcher_coalescer.master[0]
-
-[system.dispatcher_tlb.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.dispatcher_tlb.clk_domain.voltage_domain
-
-[system.dispatcher_tlb.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.l1_coalescer0]
-type=TLBCoalescer
-children=clk_domain
-clk_domain=system.l1_coalescer0.clk_domain
-coalescingWindow=1
-disableCoalescing=false
-eventq_index=0
-probesPerCycle=2
-master=system.l1_tlb0.slave[0]
-slave=system.cpu1.CUs0.translation_port[0]
-
-[system.l1_coalescer0.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l1_coalescer0.clk_domain.voltage_domain
-
-[system.l1_coalescer0.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l1_coalescer1]
-type=TLBCoalescer
-children=clk_domain
-clk_domain=system.l1_coalescer1.clk_domain
-coalescingWindow=1
-disableCoalescing=false
-eventq_index=0
-probesPerCycle=2
-master=system.l1_tlb1.slave[0]
-slave=system.cpu1.CUs1.translation_port[0]
-
-[system.l1_coalescer1.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l1_coalescer1.clk_domain.voltage_domain
-
-[system.l1_coalescer1.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l1_tlb0]
-type=X86GPUTLB
-children=clk_domain
-accessDistance=false
-allocationPolicy=true
-assoc=32
-clk_domain=system.l1_tlb0.clk_domain
-eventq_index=0
-hitLatency=1
-maxOutstandingReqs=64
-missLatency1=5
-missLatency2=750
-size=32
-master=system.l2_coalescer.slave[2]
-slave=system.l1_coalescer0.master[0]
-
-[system.l1_tlb0.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l1_tlb0.clk_domain.voltage_domain
-
-[system.l1_tlb0.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l1_tlb1]
-type=X86GPUTLB
-children=clk_domain
-accessDistance=false
-allocationPolicy=true
-assoc=32
-clk_domain=system.l1_tlb1.clk_domain
-eventq_index=0
-hitLatency=1
-maxOutstandingReqs=64
-missLatency1=5
-missLatency2=750
-size=32
-master=system.l2_coalescer.slave[3]
-slave=system.l1_coalescer1.master[0]
-
-[system.l1_tlb1.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l1_tlb1.clk_domain.voltage_domain
-
-[system.l1_tlb1.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l2_coalescer]
-type=TLBCoalescer
-children=clk_domain
-clk_domain=system.l2_coalescer.clk_domain
-coalescingWindow=1
-disableCoalescing=false
-eventq_index=0
-probesPerCycle=2
-master=system.l2_tlb.slave[0]
-slave=system.sqc_tlb.master[0] system.dispatcher_tlb.master[0] system.l1_tlb0.master[0] system.l1_tlb1.master[0]
-
-[system.l2_coalescer.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l2_coalescer.clk_domain.voltage_domain
-
-[system.l2_coalescer.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l2_tlb]
-type=X86GPUTLB
-children=clk_domain
-accessDistance=false
-allocationPolicy=true
-assoc=32
-clk_domain=system.l2_tlb.clk_domain
-eventq_index=0
-hitLatency=69
-maxOutstandingReqs=64
-missLatency1=5
-missLatency2=750
-size=4096
-master=system.l3_coalescer.slave[0]
-slave=system.l2_coalescer.master[0]
-
-[system.l2_tlb.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l2_tlb.clk_domain.voltage_domain
-
-[system.l2_tlb.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l3_coalescer]
-type=TLBCoalescer
-children=clk_domain
-clk_domain=system.l3_coalescer.clk_domain
-coalescingWindow=1
-disableCoalescing=false
-eventq_index=0
-probesPerCycle=2
-master=system.l3_tlb.slave[0]
-slave=system.l2_tlb.master[0]
-
-[system.l3_coalescer.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l3_coalescer.clk_domain.voltage_domain
-
-[system.l3_coalescer.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.l3_tlb]
-type=X86GPUTLB
-children=clk_domain
-accessDistance=false
-allocationPolicy=true
-assoc=32
-clk_domain=system.l3_tlb.clk_domain
-eventq_index=0
-hitLatency=150
-maxOutstandingReqs=64
-missLatency1=5
-missLatency2=750
-size=8192
-slave=system.l3_coalescer.master[0]
-
-[system.l3_tlb.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.l3_tlb.clk_domain.voltage_domain
-
-[system.l3_tlb.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.mem_ctrls]
-type=DRAMCtrl
-IDD0=0.075000
-IDD02=0.000000
-IDD2N=0.050000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.000000
-IDD2P12=0.000000
-IDD3N=0.057000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.000000
-IDD3P12=0.000000
-IDD4R=0.187000
-IDD4R2=0.000000
-IDD4W=0.165000
-IDD4W2=0.000000
-IDD5=0.220000
-IDD52=0.000000
-IDD6=0.000000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-page_policy=open_adaptive
-range=0:536870911
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=0
-tXPDLL=0
-tXS=0
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.dir_cntrl0.memory
-
-[system.piobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-forward_latency=0
-frontend_latency=0
-response_latency=0
-use_default_range=false
-width=32
-master=system.cpu2.pio
-slave=system.cp_cntrl0.sequencer.mem_master_port system.cpu2.dma
-
-[system.rb_cntrl0]
-type=RegionBuffer_Controller
-children=cacheMemory notifyFromRegionDir probeFromRegionDir requestFromCore requestToNetwork responseFromCore responseToRegDir triggerQueue unblockFromDir
-TCC_select_num_bits=0
-blocksPerRegion=16
-buffer_size=0
-cacheMemory=system.rb_cntrl0.cacheMemory
-clk_domain=system.clk_domain
-cluster_id=0
-eventq_index=0
-isOnCPU=true
-nextEvictLatency=1
-noTCCdir=true
-notifyFromRegionDir=system.rb_cntrl0.notifyFromRegionDir
-number_of_TBEs=256
-probeFromRegionDir=system.rb_cntrl0.probeFromRegionDir
-recycle_latency=10
-requestFromCore=system.rb_cntrl0.requestFromCore
-requestToNetwork=system.rb_cntrl0.requestToNetwork
-responseFromCore=system.rb_cntrl0.responseFromCore
-responseToRegDir=system.rb_cntrl0.responseToRegDir
-ruby_system=system.ruby
-system=system
-toDirLatency=60
-toRegionDirLatency=120
-transitions_per_cycle=32
-triggerQueue=system.rb_cntrl0.triggerQueue
-unblockFromDir=system.rb_cntrl0.unblockFromDir
-version=0
-
-[system.rb_cntrl0.cacheMemory]
-type=RubyCache
-children=replacement_policy
-assoc=4
-block_size=1024
-dataAccessLatency=1
-dataArrayBanks=64
-eventq_index=0
-is_icache=false
-replacement_policy=system.rb_cntrl0.cacheMemory.replacement_policy
-resourceStalls=true
-ruby_system=system.ruby
-size=1048576
-start_index_bit=10
-tagAccessLatency=1
-tagArrayBanks=64
-
-[system.rb_cntrl0.cacheMemory.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=4
-block_size=64
-eventq_index=0
-size=1048576
-
-[system.rb_cntrl0.notifyFromRegionDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[4]
-
-[system.rb_cntrl0.probeFromRegionDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[5]
-
-[system.rb_cntrl0.requestFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[2]
-
-[system.rb_cntrl0.requestToNetwork]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[3]
-
-[system.rb_cntrl0.responseFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[3]
-
-[system.rb_cntrl0.responseToRegDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[4]
-
-[system.rb_cntrl0.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.rb_cntrl0.unblockFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[6]
-
-[system.reg_cntrl0]
-type=RegionDir_Controller
-children=cacheMemory notifyToRBuffer probeToRBuffer requestFromRegBuf requestToDir responseFromRBuffer triggerQueue
-TCC_select_num_bits=0
-always_migrate=false
-asym_migrate=false
-blocksPerRegion=16
-buffer_size=0
-cacheMemory=system.reg_cntrl0.cacheMemory
-clk_domain=system.clk_domain
-cluster_id=0
-cpuRegionBufferNum=0
-eventq_index=0
-gpuRegionBufferNum=1
-noTCCdir=true
-notifyToRBuffer=system.reg_cntrl0.notifyToRBuffer
-number_of_TBEs=32
-probeToRBuffer=system.reg_cntrl0.probeToRBuffer
-recycle_latency=10
-requestFromRegBuf=system.reg_cntrl0.requestFromRegBuf
-requestToDir=system.reg_cntrl0.requestToDir
-responseFromRBuffer=system.reg_cntrl0.responseFromRBuffer
-ruby_system=system.ruby
-sym_migrate=false
-system=system
-toDirLatency=1
-transitions_per_cycle=32
-triggerQueue=system.reg_cntrl0.triggerQueue
-version=0
-
-[system.reg_cntrl0.cacheMemory]
-type=RubyCache
-children=replacement_policy
-assoc=8
-block_size=1024
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.reg_cntrl0.cacheMemory.replacement_policy
-resourceStalls=true
-ruby_system=system.ruby
-size=2097152
-start_index_bit=10
-tagAccessLatency=4
-tagArrayBanks=8
-
-[system.reg_cntrl0.cacheMemory.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=8
-block_size=64
-eventq_index=0
-size=2097152
-
-[system.reg_cntrl0.notifyToRBuffer]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[23]
-
-[system.reg_cntrl0.probeToRBuffer]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[24]
-
-[system.reg_cntrl0.requestFromRegBuf]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[27]
-
-[system.reg_cntrl0.requestToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[22]
-
-[system.reg_cntrl0.responseFromRBuffer]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[26]
-
-[system.reg_cntrl0.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby]
-type=RubySystem
-children=clk_domain network phys_mem
-access_backing_store=true
-all_instructions=false
-block_size_bytes=64
-clk_domain=system.ruby.clk_domain
-eventq_index=0
-hot_lines=false
-memory_size_bits=48
-num_of_sequencers=5
-number_of_virtual_networks=10
-phys_mem=system.ruby.phys_mem
-randomization=false
-
-[system.ruby.clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.ruby.network]
-type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1
-adaptive_routing=false
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-control_msg_size=8
-endpoint_bandwidth=1000
-eventq_index=0
-ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4 system.ruby.network.ext_links5 system.ruby.network.ext_links6 system.ruby.network.ext_links7 system.ruby.network.ext_links8
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
-netifs=
-number_of_virtual_networks=10
-routers=system.ruby.network.ext_links0.int_node system.ruby.network.ext_links2.int_node system.ruby.network.ext_links4.int_node
-ruby_system=system.ruby
-topology=Crossbar
-master=system.cp_cntrl0.probeToCore.slave system.cp_cntrl0.responseToCore.slave system.rb_cntrl0.requestFromCore.slave system.rb_cntrl0.responseFromCore.slave system.rb_cntrl0.notifyFromRegionDir.slave system.rb_cntrl0.probeFromRegionDir.slave system.rb_cntrl0.unblockFromDir.slave system.tcp_cntrl0.probeToTCP.slave system.tcp_cntrl0.responseToTCP.slave system.tcp_cntrl1.probeToTCP.slave system.tcp_cntrl1.responseToTCP.slave system.sqc_cntrl0.probeToSQC.slave system.sqc_cntrl0.responseToSQC.slave system.tcc_cntrl0.requestFromTCP.slave system.tcc_cntrl0.probeFromNB.slave system.tcc_cntrl0.responseFromNB.slave system.tcc_rb_cntrl0.requestFromCore.slave system.tcc_rb_cntrl0.responseFromCore.slave system.tcc_rb_cntrl0.notifyFromRegionDir.slave system.tcc_rb_cntrl0.probeFromRegionDir.slave system.tcc_rb_cntrl0.unblockFromDir.slave system.dir_cntrl0.requestFromCores.slave system.dir_cntrl0.responseFromCores.slave system.dir_cntrl0.unblockFromCores.slave system.dir_cntrl0.reqFromRegBuf.slave system.dir_cntrl0.reqFromRegDir.slave system.reg_cntrl0.responseFromRBuffer.slave system.reg_cntrl0.requestFromRegBuf.slave
-slave=system.cp_cntrl0.requestFromCore.master system.cp_cntrl0.responseFromCore.master system.cp_cntrl0.unblockFromCore.master system.rb_cntrl0.requestToNetwork.master system.rb_cntrl0.responseToRegDir.master system.tcp_cntrl0.requestFromTCP.master system.tcp_cntrl0.responseFromTCP.master system.tcp_cntrl0.unblockFromCore.master system.tcp_cntrl1.requestFromTCP.master system.tcp_cntrl1.responseFromTCP.master system.tcp_cntrl1.unblockFromCore.master system.sqc_cntrl0.requestFromSQC.master system.tcc_cntrl0.responseToCore.master system.tcc_cntrl0.requestToNB.master system.tcc_cntrl0.responseToNB.master system.tcc_cntrl0.unblockToNB.master system.tcc_rb_cntrl0.requestToNetwork.master system.tcc_rb_cntrl0.responseToRegDir.master system.dir_cntrl0.probeToCore.master system.dir_cntrl0.responseToCore.master system.dir_cntrl0.reqToRegDir.master system.dir_cntrl0.unblockToRegDir.master system.reg_cntrl0.requestToDir.master system.reg_cntrl0.notifyToRBuffer.master system.reg_cntrl0.probeToRBuffer.master
-
-[system.ruby.network.ext_links0]
-type=SimpleExtLink
-children=int_node
-bandwidth_factor=32
-eventq_index=0
-ext_node=system.dir_cntrl0
-int_node=system.ruby.network.ext_links0.int_node
-latency=1
-link_id=0
-weight=1
-
-[system.ruby.network.ext_links0.int_node]
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-assoc=32
-clk_domain=system.sqc_tlb.clk_domain
-eventq_index=0
-hitLatency=1
-maxOutstandingReqs=64
-missLatency1=5
-missLatency2=750
-size=32
-master=system.l2_coalescer.slave[0]
-slave=system.sqc_coalescer.master[0]
-
-[system.sqc_tlb.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.sqc_tlb.clk_domain.voltage_domain
-
-[system.sqc_tlb.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.sys_port_proxy]
-type=RubyPortProxy
-clk_domain=system.clk_domain
-eventq_index=0
-is_cpu_sequencer=true
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=0
-slave=system.system_port
-
-[system.tcc_cntrl0]
-type=TCC_Controller
-children=L2cache probeFromNB requestFromTCP requestToNB responseFromNB responseToCore responseToNB triggerQueue unblockToNB
-L2cache=system.tcc_cntrl0.L2cache
-WB=false
-buffer_size=0
-clk_domain=system.clk_domain
-cluster_id=0
-eventq_index=0
-l2_request_latency=1
-l2_response_latency=16
-number_of_TBEs=5120
-probeFromNB=system.tcc_cntrl0.probeFromNB
-recycle_latency=10
-regionBufferNum=1
-requestFromTCP=system.tcc_cntrl0.requestFromTCP
-requestToNB=system.tcc_cntrl0.requestToNB
-responseFromNB=system.tcc_cntrl0.responseFromNB
-responseToCore=system.tcc_cntrl0.responseToCore
-responseToNB=system.tcc_cntrl0.responseToNB
-ruby_system=system.ruby
-system=system
-transitions_per_cycle=32
-triggerQueue=system.tcc_cntrl0.triggerQueue
-unblockToNB=system.tcc_cntrl0.unblockToNB
-version=0
-
-[system.tcc_cntrl0.L2cache]
-type=RubyCache
-children=replacement_policy
-assoc=16
-block_size=0
-dataAccessLatency=8
-dataArrayBanks=256
-eventq_index=0
-is_icache=false
-replacement_policy=system.tcc_cntrl0.L2cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=2097152
-start_index_bit=6
-tagAccessLatency=2
-tagArrayBanks=256
-
-[system.tcc_cntrl0.L2cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=16
-block_size=64
-eventq_index=0
-size=2097152
-
-[system.tcc_cntrl0.probeFromNB]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[14]
-
-[system.tcc_cntrl0.requestFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[13]
-
-[system.tcc_cntrl0.requestToNB]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[13]
-
-[system.tcc_cntrl0.responseFromNB]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[15]
-
-[system.tcc_cntrl0.responseToCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[12]
-
-[system.tcc_cntrl0.responseToNB]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[14]
-
-[system.tcc_cntrl0.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.tcc_cntrl0.unblockToNB]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[15]
-
-[system.tcc_rb_cntrl0]
-type=RegionBuffer_Controller
-children=cacheMemory notifyFromRegionDir probeFromRegionDir requestFromCore requestToNetwork responseFromCore responseToRegDir triggerQueue unblockFromDir
-TCC_select_num_bits=0
-blocksPerRegion=16
-buffer_size=0
-cacheMemory=system.tcc_rb_cntrl0.cacheMemory
-clk_domain=system.clk_domain
-cluster_id=0
-eventq_index=0
-isOnCPU=false
-nextEvictLatency=1
-noTCCdir=true
-notifyFromRegionDir=system.tcc_rb_cntrl0.notifyFromRegionDir
-number_of_TBEs=5120
-probeFromRegionDir=system.tcc_rb_cntrl0.probeFromRegionDir
-recycle_latency=10
-requestFromCore=system.tcc_rb_cntrl0.requestFromCore
-requestToNetwork=system.tcc_rb_cntrl0.requestToNetwork
-responseFromCore=system.tcc_rb_cntrl0.responseFromCore
-responseToRegDir=system.tcc_rb_cntrl0.responseToRegDir
-ruby_system=system.ruby
-system=system
-toDirLatency=60
-toRegionDirLatency=120
-transitions_per_cycle=32
-triggerQueue=system.tcc_rb_cntrl0.triggerQueue
-unblockFromDir=system.tcc_rb_cntrl0.unblockFromDir
-version=1
-
-[system.tcc_rb_cntrl0.cacheMemory]
-type=RubyCache
-children=replacement_policy
-assoc=4
-block_size=1024
-dataAccessLatency=1
-dataArrayBanks=64
-eventq_index=0
-is_icache=false
-replacement_policy=system.tcc_rb_cntrl0.cacheMemory.replacement_policy
-resourceStalls=true
-ruby_system=system.ruby
-size=1048576
-start_index_bit=10
-tagAccessLatency=1
-tagArrayBanks=64
-
-[system.tcc_rb_cntrl0.cacheMemory.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=4
-block_size=64
-eventq_index=0
-size=1048576
-
-[system.tcc_rb_cntrl0.notifyFromRegionDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[18]
-
-[system.tcc_rb_cntrl0.probeFromRegionDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[19]
-
-[system.tcc_rb_cntrl0.requestFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[16]
-
-[system.tcc_rb_cntrl0.requestToNetwork]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[16]
-
-[system.tcc_rb_cntrl0.responseFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[17]
-
-[system.tcc_rb_cntrl0.responseToRegDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[17]
-
-[system.tcc_rb_cntrl0.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.tcc_rb_cntrl0.unblockFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[20]
-
-[system.tcp_cntrl0]
-type=TCP_Controller
-children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore
-L1cache=system.tcp_cntrl0.L1cache
-TCC_select_num_bits=0
-WB=false
-buffer_size=0
-clk_domain=system.clk_domain
-cluster_id=0
-coalescer=system.tcp_cntrl0.coalescer
-disableL1=false
-eventq_index=0
-issue_latency=1
-l2_hit_latency=18
-mandatoryQueue=system.tcp_cntrl0.mandatoryQueue
-number_of_TBEs=2560
-probeToTCP=system.tcp_cntrl0.probeToTCP
-recycle_latency=10
-requestFromTCP=system.tcp_cntrl0.requestFromTCP
-responseFromTCP=system.tcp_cntrl0.responseFromTCP
-responseToTCP=system.tcp_cntrl0.responseToTCP
-ruby_system=system.ruby
-sequencer=system.tcp_cntrl0.sequencer
-system=system
-transitions_per_cycle=32
-unblockFromCore=system.tcp_cntrl0.unblockFromCore
-use_seq_not_coal=false
-version=0
-
-[system.tcp_cntrl0.L1cache]
-type=RubyCache
-children=replacement_policy
-assoc=16
-block_size=0
-dataAccessLatency=4
-dataArrayBanks=16
-eventq_index=0
-is_icache=false
-replacement_policy=system.tcp_cntrl0.L1cache.replacement_policy
-resourceStalls=true
-ruby_system=system.ruby
-size=16384
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=16
-
-[system.tcp_cntrl0.L1cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=16
-block_size=64
-eventq_index=0
-size=16384
-
-[system.tcp_cntrl0.coalescer]
-type=VIPERCoalescer
-assume_rfo=false
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.tcp_cntrl0.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-eventq_index=0
-icache=system.tcp_cntrl0.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=false
-max_inv_per_cycle=32
-max_outstanding_requests=2560
-max_wb_per_cycle=32
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=false
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=2
-slave=system.cpu1.CUs0.memory_port[0] system.cpu1.CUs0.memory_port[1] system.cpu1.CUs0.memory_port[2] system.cpu1.CUs0.memory_port[3] system.cpu1.CUs0.memory_port[4] system.cpu1.CUs0.memory_port[5] system.cpu1.CUs0.memory_port[6] system.cpu1.CUs0.memory_port[7] system.cpu1.CUs0.memory_port[8] system.cpu1.CUs0.memory_port[9] system.cpu1.CUs0.memory_port[10] system.cpu1.CUs0.memory_port[11] system.cpu1.CUs0.memory_port[12] system.cpu1.CUs0.memory_port[13] system.cpu1.CUs0.memory_port[14] system.cpu1.CUs0.memory_port[15] system.cpu1.CUs0.memory_port[16] system.cpu1.CUs0.memory_port[17] system.cpu1.CUs0.memory_port[18] system.cpu1.CUs0.memory_port[19] system.cpu1.CUs0.memory_port[20] system.cpu1.CUs0.memory_port[21] system.cpu1.CUs0.memory_port[22] system.cpu1.CUs0.memory_port[23] system.cpu1.CUs0.memory_port[24] system.cpu1.CUs0.memory_port[25] system.cpu1.CUs0.memory_port[26] system.cpu1.CUs0.memory_port[27] system.cpu1.CUs0.memory_port[28] system.cpu1.CUs0.memory_port[29] system.cpu1.CUs0.memory_port[30] system.cpu1.CUs0.memory_port[31] system.cpu1.CUs0.memory_port[32] system.cpu1.CUs0.memory_port[33] system.cpu1.CUs0.memory_port[34] system.cpu1.CUs0.memory_port[35] system.cpu1.CUs0.memory_port[36] system.cpu1.CUs0.memory_port[37] system.cpu1.CUs0.memory_port[38] system.cpu1.CUs0.memory_port[39] system.cpu1.CUs0.memory_port[40] system.cpu1.CUs0.memory_port[41] system.cpu1.CUs0.memory_port[42] system.cpu1.CUs0.memory_port[43] system.cpu1.CUs0.memory_port[44] system.cpu1.CUs0.memory_port[45] system.cpu1.CUs0.memory_port[46] system.cpu1.CUs0.memory_port[47] system.cpu1.CUs0.memory_port[48] system.cpu1.CUs0.memory_port[49] system.cpu1.CUs0.memory_port[50] system.cpu1.CUs0.memory_port[51] system.cpu1.CUs0.memory_port[52] system.cpu1.CUs0.memory_port[53] system.cpu1.CUs0.memory_port[54] system.cpu1.CUs0.memory_port[55] system.cpu1.CUs0.memory_port[56] system.cpu1.CUs0.memory_port[57] system.cpu1.CUs0.memory_port[58] system.cpu1.CUs0.memory_port[59] system.cpu1.CUs0.memory_port[60] system.cpu1.CUs0.memory_port[61] system.cpu1.CUs0.memory_port[62] system.cpu1.CUs0.memory_port[63]
-
-[system.tcp_cntrl0.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.tcp_cntrl0.probeToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[7]
-
-[system.tcp_cntrl0.requestFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[5]
-
-[system.tcp_cntrl0.responseFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[6]
-
-[system.tcp_cntrl0.responseToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[8]
-
-[system.tcp_cntrl0.sequencer]
-type=RubySequencer
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.tcp_cntrl0.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-eventq_index=0
-icache=system.tcp_cntrl0.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=3
-
-[system.tcp_cntrl0.unblockFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[7]
-
-[system.tcp_cntrl1]
-type=TCP_Controller
-children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore
-L1cache=system.tcp_cntrl1.L1cache
-TCC_select_num_bits=0
-WB=false
-buffer_size=0
-clk_domain=system.clk_domain
-cluster_id=0
-coalescer=system.tcp_cntrl1.coalescer
-disableL1=false
-eventq_index=0
-issue_latency=1
-l2_hit_latency=18
-mandatoryQueue=system.tcp_cntrl1.mandatoryQueue
-number_of_TBEs=2560
-probeToTCP=system.tcp_cntrl1.probeToTCP
-recycle_latency=10
-requestFromTCP=system.tcp_cntrl1.requestFromTCP
-responseFromTCP=system.tcp_cntrl1.responseFromTCP
-responseToTCP=system.tcp_cntrl1.responseToTCP
-ruby_system=system.ruby
-sequencer=system.tcp_cntrl1.sequencer
-system=system
-transitions_per_cycle=32
-unblockFromCore=system.tcp_cntrl1.unblockFromCore
-use_seq_not_coal=false
-version=1
-
-[system.tcp_cntrl1.L1cache]
-type=RubyCache
-children=replacement_policy
-assoc=16
-block_size=0
-dataAccessLatency=4
-dataArrayBanks=16
-eventq_index=0
-is_icache=false
-replacement_policy=system.tcp_cntrl1.L1cache.replacement_policy
-resourceStalls=true
-ruby_system=system.ruby
-size=16384
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=16
-
-[system.tcp_cntrl1.L1cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=16
-block_size=64
-eventq_index=0
-size=16384
-
-[system.tcp_cntrl1.coalescer]
-type=VIPERCoalescer
-assume_rfo=false
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.tcp_cntrl1.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-eventq_index=0
-icache=system.tcp_cntrl1.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=false
-max_inv_per_cycle=32
-max_outstanding_requests=2560
-max_wb_per_cycle=32
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=false
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=4
-slave=system.cpu1.CUs1.memory_port[0] system.cpu1.CUs1.memory_port[1] system.cpu1.CUs1.memory_port[2] system.cpu1.CUs1.memory_port[3] system.cpu1.CUs1.memory_port[4] system.cpu1.CUs1.memory_port[5] system.cpu1.CUs1.memory_port[6] system.cpu1.CUs1.memory_port[7] system.cpu1.CUs1.memory_port[8] system.cpu1.CUs1.memory_port[9] system.cpu1.CUs1.memory_port[10] system.cpu1.CUs1.memory_port[11] system.cpu1.CUs1.memory_port[12] system.cpu1.CUs1.memory_port[13] system.cpu1.CUs1.memory_port[14] system.cpu1.CUs1.memory_port[15] system.cpu1.CUs1.memory_port[16] system.cpu1.CUs1.memory_port[17] system.cpu1.CUs1.memory_port[18] system.cpu1.CUs1.memory_port[19] system.cpu1.CUs1.memory_port[20] system.cpu1.CUs1.memory_port[21] system.cpu1.CUs1.memory_port[22] system.cpu1.CUs1.memory_port[23] system.cpu1.CUs1.memory_port[24] system.cpu1.CUs1.memory_port[25] system.cpu1.CUs1.memory_port[26] system.cpu1.CUs1.memory_port[27] system.cpu1.CUs1.memory_port[28] system.cpu1.CUs1.memory_port[29] system.cpu1.CUs1.memory_port[30] system.cpu1.CUs1.memory_port[31] system.cpu1.CUs1.memory_port[32] system.cpu1.CUs1.memory_port[33] system.cpu1.CUs1.memory_port[34] system.cpu1.CUs1.memory_port[35] system.cpu1.CUs1.memory_port[36] system.cpu1.CUs1.memory_port[37] system.cpu1.CUs1.memory_port[38] system.cpu1.CUs1.memory_port[39] system.cpu1.CUs1.memory_port[40] system.cpu1.CUs1.memory_port[41] system.cpu1.CUs1.memory_port[42] system.cpu1.CUs1.memory_port[43] system.cpu1.CUs1.memory_port[44] system.cpu1.CUs1.memory_port[45] system.cpu1.CUs1.memory_port[46] system.cpu1.CUs1.memory_port[47] system.cpu1.CUs1.memory_port[48] system.cpu1.CUs1.memory_port[49] system.cpu1.CUs1.memory_port[50] system.cpu1.CUs1.memory_port[51] system.cpu1.CUs1.memory_port[52] system.cpu1.CUs1.memory_port[53] system.cpu1.CUs1.memory_port[54] system.cpu1.CUs1.memory_port[55] system.cpu1.CUs1.memory_port[56] system.cpu1.CUs1.memory_port[57] system.cpu1.CUs1.memory_port[58] system.cpu1.CUs1.memory_port[59] system.cpu1.CUs1.memory_port[60] system.cpu1.CUs1.memory_port[61] system.cpu1.CUs1.memory_port[62] system.cpu1.CUs1.memory_port[63]
-
-[system.tcp_cntrl1.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.tcp_cntrl1.probeToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[9]
-
-[system.tcp_cntrl1.requestFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[8]
-
-[system.tcp_cntrl1.responseFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[9]
-
-[system.tcp_cntrl1.responseToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[10]
-
-[system.tcp_cntrl1.sequencer]
-type=RubySequencer
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.tcp_cntrl1.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-eventq_index=0
-icache=system.tcp_cntrl1.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=5
-
-[system.tcp_cntrl1.unblockFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[10]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: system.ruby.network adopting orphan SimObject param 'int_links'
-warn: system.ruby.network adopting orphan SimObject param 'ext_links'
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 19 2016 13:45:43
-gem5 started Jan 19 2016 13:46:17
-gem5 executing on zizzer, pid 51290
-command line: build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_VIPER_Region -re /z/atgutier/gem5/gem5-commit/tests/run.py build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_VIPER_Region
-
-Using GPU kernel code file(s) /dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm
-Global frequency set at 1000000000000 ticks per second
-Forcing maxCoalescedReqs to 32 (TLB assoc.)
-Forcing maxCoalescedReqs to 32 (TLB assoc.)
-Forcing maxCoalescedReqs to 32 (TLB assoc.)
-Forcing maxCoalescedReqs to 32 (TLB assoc.)
-Forcing maxCoalescedReqs to 32 (TLB assoc.)
-Forcing maxCoalescedReqs to 32 (TLB assoc.)
-info: Entering event queue @ 0. Starting simulation...
-keys = 0x7b2bc0, &keys = 0x798998, keys[0] = 23
-the gpu says:
-\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fello\7fe
-Exiting @ tick 468854500 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000469 # Number of seconds simulated
-sim_ticks 468854500 # Number of ticks simulated
-final_tick 468854500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 67943 # Simulator instruction rate (inst/s)
-host_op_rate 139717 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 475693968 # Simulator tick rate (ticks/s)
-host_mem_usage 1301796 # Number of bytes of host memory used
-host_seconds 0.99 # Real time elapsed on the host
-sim_insts 66963 # Number of instructions simulated
-sim_ops 137705 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.mem_ctrls.bytes_read::dir_cntrl0 100032 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 100032 # Number of bytes read from this memory
-system.mem_ctrls.num_reads::dir_cntrl0 1563 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 1563 # Number of read requests responded to by this memory
-system.mem_ctrls.bw_read::dir_cntrl0 213354036 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 213354036 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::dir_cntrl0 213354036 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 213354036 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 1563 # Number of read requests accepted
-system.mem_ctrls.writeReqs 0 # Number of write requests accepted
-system.mem_ctrls.readBursts 1563 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 100032 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 100032 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 122 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 192 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 93 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 44 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 61 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 79 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 52 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 42 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8 54 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9 56 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 183 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11 90 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12 225 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 125 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 51 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 94 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
-system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
-system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 468627000 # Total gap between requests
-system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 1563 # Read request sizes (log2)
-system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 1548 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 4 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2 2 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3 2 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4 2 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6 2 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7 1 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 450 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 221.297778 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 151.217299 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 224.192300 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 165 36.67% 36.67% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 148 32.89% 69.56% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 55 12.22% 81.78% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 28 6.22% 88.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 19 4.22% 92.22% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 11 2.44% 94.67% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 8 1.78% 96.44% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 6 1.33% 97.78% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 10 2.22% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 450 # Bytes accessed per row activation
-system.mem_ctrls.totQLat 14130749 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 43436999 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 7815000 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 9040.79 # Average queueing delay per DRAM burst
-system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 27790.79 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 213.35 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 213.35 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
-system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 1.67 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 1.67 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 1.01 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 1109 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 70.95 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 299825.34 # Average gap between requests
-system.mem_ctrls.pageHitRate 70.95 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 1300320 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 709500 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 5335200 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 30513600 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 265391145 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 47661750 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 350911515 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 750.717244 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 79008000 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 15600000 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 374147000 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls_1.actEnergy 2101680 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 1146750 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 6801600 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 30513600 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 276170130 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 38206500 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 354940260 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 759.336079 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 61948750 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 15600000 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 389900000 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.ruby.clk_domain.clock 500 # Clock period in ticks
-system.ruby.phys_mem.bytes_read::cpu0.inst 696760 # Number of bytes read from this memory
-system.ruby.phys_mem.bytes_read::cpu0.data 119832 # Number of bytes read from this memory
-system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 3280 # Number of bytes read from this memory
-system.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit 3280 # Number of bytes read from this memory
-system.ruby.phys_mem.bytes_read::total 823152 # Number of bytes read from this memory
-system.ruby.phys_mem.bytes_inst_read::cpu0.inst 696760 # Number of instructions bytes read from this memory
-system.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit 2000 # Number of instructions bytes read from this memory
-system.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit 2000 # Number of instructions bytes read from this memory
-system.ruby.phys_mem.bytes_inst_read::total 700760 # Number of instructions bytes read from this memory
-system.ruby.phys_mem.bytes_written::cpu0.data 72767 # Number of bytes written to this memory
-system.ruby.phys_mem.bytes_written::cpu1.CUs0.ComputeUnit 256 # Number of bytes written to this memory
-system.ruby.phys_mem.bytes_written::cpu1.CUs1.ComputeUnit 256 # Number of bytes written to this memory
-system.ruby.phys_mem.bytes_written::total 73279 # Number of bytes written to this memory
-system.ruby.phys_mem.num_reads::cpu0.inst 87095 # Number of read requests responded to by this memory
-system.ruby.phys_mem.num_reads::cpu0.data 16686 # Number of read requests responded to by this memory
-system.ruby.phys_mem.num_reads::cpu1.CUs0.ComputeUnit 555 # Number of read requests responded to by this memory
-system.ruby.phys_mem.num_reads::cpu1.CUs1.ComputeUnit 555 # Number of read requests responded to by this memory
-system.ruby.phys_mem.num_reads::total 104891 # Number of read requests responded to by this memory
-system.ruby.phys_mem.num_writes::cpu0.data 10422 # Number of write requests responded to by this memory
-system.ruby.phys_mem.num_writes::cpu1.CUs0.ComputeUnit 256 # Number of write requests responded to by this memory
-system.ruby.phys_mem.num_writes::cpu1.CUs1.ComputeUnit 256 # Number of write requests responded to by this memory
-system.ruby.phys_mem.num_writes::total 10934 # Number of write requests responded to by this memory
-system.ruby.phys_mem.bw_read::cpu0.inst 1486090034 # Total read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_read::cpu0.data 255584622 # Total read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit 6995774 # Total read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit 6995774 # Total read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_read::total 1755666203 # Total read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_inst_read::cpu0.inst 1486090034 # Instruction read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit 4265716 # Instruction read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit 4265716 # Instruction read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_inst_read::total 1494621466 # Instruction read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_write::cpu0.data 155201667 # Write bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 546012 # Write bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 546012 # Write bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_write::total 156293690 # Write bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_total::cpu0.inst 1486090034 # Total bandwidth to/from this memory (bytes/s)
-system.ruby.phys_mem.bw_total::cpu0.data 410786289 # Total bandwidth to/from this memory (bytes/s)
-system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 7541785 # Total bandwidth to/from this memory (bytes/s)
-system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 7541785 # Total bandwidth to/from this memory (bytes/s)
-system.ruby.phys_mem.bw_total::total 1911959894 # Total bandwidth to/from this memory (bytes/s)
-system.ruby.outstanding_req_hist::bucket_size 1
-system.ruby.outstanding_req_hist::max_bucket 9
-system.ruby.outstanding_req_hist::samples 114203
-system.ruby.outstanding_req_hist::mean 1.000035
-system.ruby.outstanding_req_hist::gmean 1.000024
-system.ruby.outstanding_req_hist::stdev 0.005918
-system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 114199 100.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist::total 114203
-system.ruby.latency_hist::bucket_size 64
-system.ruby.latency_hist::max_bucket 639
-system.ruby.latency_hist::samples 114203
-system.ruby.latency_hist::mean 3.070988
-system.ruby.latency_hist::gmean 1.072272
-system.ruby.latency_hist::stdev 18.192328
-system.ruby.latency_hist | 112654 98.64% 98.64% | 11 0.01% 98.65% | 1238 1.08% 99.74% | 266 0.23% 99.97% | 14 0.01% 99.98% | 12 0.01% 99.99% | 7 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist::total 114203
-system.ruby.hit_latency_hist::bucket_size 64
-system.ruby.hit_latency_hist::max_bucket 639
-system.ruby.hit_latency_hist::samples 1549
-system.ruby.hit_latency_hist::mean 152.827631
-system.ruby.hit_latency_hist::gmean 149.009432
-system.ruby.hit_latency_hist::stdev 40.628532
-system.ruby.hit_latency_hist | 0 0.00% 0.00% | 11 0.71% 0.71% | 1238 79.92% 80.63% | 266 17.17% 97.81% | 14 0.90% 98.71% | 12 0.77% 99.48% | 7 0.45% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist::total 1549
-system.ruby.miss_latency_hist::bucket_size 2
-system.ruby.miss_latency_hist::max_bucket 19
-system.ruby.miss_latency_hist::samples 112654
-system.ruby.miss_latency_hist::mean 1.011824
-system.ruby.miss_latency_hist::gmean 1.001936
-system.ruby.miss_latency_hist::stdev 0.461184
-system.ruby.miss_latency_hist | 112580 99.93% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 74 0.07% 100.00%
-system.ruby.miss_latency_hist::total 112654
-system.ruby.L1Cache.incomplete_times 112580
-system.ruby.L2Cache.incomplete_times 74
-system.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits
-system.cp_cntrl0.L1D0cache.demand_misses 1556 # Number of cache demand misses
-system.cp_cntrl0.L1D0cache.demand_accesses 1556 # Number of cache demand accesses
-system.cp_cntrl0.L1D0cache.num_data_array_reads 16142 # number of data array reads
-system.cp_cntrl0.L1D0cache.num_data_array_writes 11998 # number of data array writes
-system.cp_cntrl0.L1D0cache.num_tag_array_reads 27136 # number of tag array reads
-system.cp_cntrl0.L1D0cache.num_tag_array_writes 1431 # number of tag array writes
-system.cp_cntrl0.L1D1cache.demand_hits 0 # Number of cache demand hits
-system.cp_cntrl0.L1D1cache.demand_misses 0 # Number of cache demand misses
-system.cp_cntrl0.L1D1cache.demand_accesses 0 # Number of cache demand accesses
-system.cp_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
-system.cp_cntrl0.L1Icache.demand_misses 1287 # Number of cache demand misses
-system.cp_cntrl0.L1Icache.demand_accesses 1287 # Number of cache demand accesses
-system.cp_cntrl0.L1Icache.num_data_array_reads 85994 # number of data array reads
-system.cp_cntrl0.L1Icache.num_data_array_writes 67 # number of data array writes
-system.cp_cntrl0.L1Icache.num_tag_array_reads 87697 # number of tag array reads
-system.cp_cntrl0.L1Icache.num_tag_array_writes 67 # number of tag array writes
-system.cp_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits
-system.cp_cntrl0.L2cache.demand_misses 1549 # Number of cache demand misses
-system.cp_cntrl0.L2cache.demand_accesses 1549 # Number of cache demand accesses
-system.cp_cntrl0.L2cache.num_data_array_reads 167 # number of data array reads
-system.cp_cntrl0.L2cache.num_data_array_writes 11993 # number of data array writes
-system.cp_cntrl0.L2cache.num_tag_array_reads 12092 # number of tag array reads
-system.cp_cntrl0.L2cache.num_tag_array_writes 1694 # number of tag array writes
-system.cpu0.clk_domain.clock 500 # Clock period in ticks
-system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu0.workload.numSyscalls 21 # Number of system calls
-system.cpu0.numCycles 937709 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 66963 # Number of instructions committed
-system.cpu0.committedOps 137705 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 136380 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 1279 # Number of float alu accesses
-system.cpu0.num_func_calls 3196 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 12151 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 136380 # number of integer instructions
-system.cpu0.num_fp_insts 1279 # number of float instructions
-system.cpu0.num_int_register_reads 257490 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 110039 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 1981 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 981 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 78262 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 42183 # number of times the CC registers were written
-system.cpu0.num_mem_refs 27198 # number of memory refs
-system.cpu0.num_load_insts 16684 # Number of load instructions
-system.cpu0.num_store_insts 10514 # Number of store instructions
-system.cpu0.num_idle_cycles 7323.003984 # Number of idle cycles
-system.cpu0.num_busy_cycles 930385.996016 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.992191 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.007809 # Percentage of idle cycles
-system.cpu0.Branches 16199 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 615 0.45% 0.45% # Class of executed instruction
-system.cpu0.op_class::IntAlu 108791 79.00% 79.45% # Class of executed instruction
-system.cpu0.op_class::IntMult 13 0.01% 79.46% # Class of executed instruction
-system.cpu0.op_class::IntDiv 138 0.10% 79.56% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 950 0.69% 80.25% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::MemRead 16684 12.12% 92.36% # Class of executed instruction
-system.cpu0.op_class::MemWrite 10514 7.64% 100.00% # Class of executed instruction
-system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 137705 # Class of executed instruction
-system.cpu1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.cpu1.clk_domain.clock 1000 # Clock period in ticks
-system.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 271 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::total 39 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts01.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts01.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts02.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts02.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts02.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts03.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts03.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts04.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts04.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts04.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts05.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
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-system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts06.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts06.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts07.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts07.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 252 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 243 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs0.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 228 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 4103 # number of cycles the CU issues nothing
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 133 # number of cycles the CU issued at least one instruction
-system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 1359 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 382 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 338 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 302 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 373 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 26 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.spc::samples 4236 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::mean 0.033286 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::stdev 0.190882 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::0 4103 96.86% 96.86% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::1 126 2.97% 99.83% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::2 6 0.14% 99.98% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::3 1 0.02% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::total 4236 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 68 # number of CU transitions from active to idle
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 68 # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 53.455882 # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 203.558231 # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 48 70.59% 70.59% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 8 11.76% 82.35% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 1 1.47% 83.82% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 1 1.47% 85.29% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 2 2.94% 88.24% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.47% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 89.71% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 7 10.29% 100.00% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value 1317 # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 68 # duration of idle periods in cycles
-system.cpu1.CUs0.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF
-system.cpu1.CUs0.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF
-system.cpu1.CUs0.tlb_requests 769 # number of uncoalesced requests
-system.cpu1.CUs0.tlb_cycles -318202403000 # total number of cycles for all uncoalesced requests
-system.cpu1.CUs0.avg_translation_latency -413787260.078023 # Avg. translation latency for data translations
-system.cpu1.CUs0.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs0.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs0.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs0.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs0.lds_bank_access_cnt 54 # Total number of LDS bank accesses
-system.cpu1.CUs0.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::mean 8 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::stdev 6.196773 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::10-11 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::12-13 4 66.67% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.global_mem_instr_cnt 17 # dynamic global memory instructions count
-system.cpu1.CUs0.local_mem_instr_cnt 6 # dynamic local memory intruction count
-system.cpu1.CUs0.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity
-system.cpu1.CUs0.num_instr_executed 141 # number of instructions executed
-system.cpu1.CUs0.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::mean 84.978723 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::stdev 240.114362 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::0-1 1 0.71% 0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::4-5 53 37.59% 46.81% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::6-7 31 21.99% 68.79% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::8-9 3 2.13% 70.92% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::10 1 0.71% 71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::overflows 40 28.37% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::min_value 1 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::max_value 1320 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.num_vec_ops_executed 6769 # number of vec ops executed (e.g. VSZ/inst)
-system.cpu1.CUs0.num_total_cycles 4236 # number of cycles the CU ran for
-system.cpu1.CUs0.vpc 1.597970 # Vector Operations per cycle (this CU only)
-system.cpu1.CUs0.ipc 0.033286 # Instructions per cycle (this CU only)
-system.cpu1.CUs0.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::mean 48.007092 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::stdev 23.719942 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::9-12 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::13-16 36 25.53% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::mean 37.833333 # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::stdev 27.064737 # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::9-12 0 0.00% 5.56% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::13-16 8 44.44% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::mean 19.500000 # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::stdev 22.322634 # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::9-12 0 0.00% 16.67% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::13-16 4 66.67% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction
-system.cpu1.CUs0.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed
-system.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD
-system.cpu1.CUs0.num_CAS_ops 0 # number of compare and swap operations
-system.cpu1.CUs0.num_failed_CAS_ops 0 # number of compare and swap operations that failed
-system.cpu1.CUs0.num_completed_wfs 4 # number of completed wavefronts
-system.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 276 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::total 39 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts01.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts01.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
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-system.cpu1.CUs1.wavefronts02.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
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-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts03.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
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-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts04.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts04.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
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-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
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-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts05.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts05.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
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-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts06.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts06.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
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-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts07.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts07.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
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-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 254 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 251 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
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-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
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-system.cpu1.CUs1.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 236 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 4105 # number of cycles the CU issues nothing
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 131 # number of cycles the CU issued at least one instruction
-system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 1525 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 346 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 363 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 363 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 363 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 33 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.spc::samples 4236 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::mean 0.033286 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::stdev 0.194558 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::0 4105 96.91% 96.91% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::1 123 2.90% 99.81% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::2 6 0.14% 99.95% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::3 2 0.05% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::total 4236 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 74 # number of CU transitions from active to idle
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 74 # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 51.891892 # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 210.095188 # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 56 75.68% 75.68% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 7 9.46% 85.14% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 85.14% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 2 2.70% 87.84% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 1 1.35% 89.19% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 1 1.35% 90.54% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 90.54% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 90.54% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 90.54% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 90.54% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 90.54% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 90.54% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 90.54% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 90.54% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 90.54% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 90.54% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 7 9.46% 100.00% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value 1321 # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 74 # duration of idle periods in cycles
-system.cpu1.CUs1.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF
-system.cpu1.CUs1.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF
-system.cpu1.CUs1.tlb_requests 769 # number of uncoalesced requests
-system.cpu1.CUs1.tlb_cycles -318199598000 # total number of cycles for all uncoalesced requests
-system.cpu1.CUs1.avg_translation_latency -413783612.483745 # Avg. translation latency for data translations
-system.cpu1.CUs1.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs1.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs1.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs1.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs1.lds_bank_access_cnt 53 # Total number of LDS bank accesses
-system.cpu1.CUs1.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::mean 7.833333 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::stdev 6.080022 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::10-11 1 16.67% 50.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::12-13 3 50.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.global_mem_instr_cnt 17 # dynamic global memory instructions count
-system.cpu1.CUs1.local_mem_instr_cnt 6 # dynamic local memory intruction count
-system.cpu1.CUs1.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity
-system.cpu1.CUs1.num_instr_executed 141 # number of instructions executed
-system.cpu1.CUs1.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::mean 86.326241 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::stdev 246.713874 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::0-1 1 0.71% 0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::2-3 12 8.51% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::4-5 53 37.59% 46.81% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::6-7 29 20.57% 67.38% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::8-9 5 3.55% 70.92% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::10 1 0.71% 71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::overflows 40 28.37% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::min_value 1 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::max_value 1324 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.num_vec_ops_executed 6762 # number of vec ops executed (e.g. VSZ/inst)
-system.cpu1.CUs1.num_total_cycles 4236 # number of cycles the CU ran for
-system.cpu1.CUs1.vpc 1.596317 # Vector Operations per cycle (this CU only)
-system.cpu1.CUs1.ipc 0.033286 # Instructions per cycle (this CU only)
-system.cpu1.CUs1.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::mean 47.957447 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::stdev 23.818022 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::9-12 9 6.38% 9.93% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::13-16 27 19.15% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::mean 37.722222 # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::stdev 27.174394 # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::9-12 2 11.11% 16.67% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::13-16 6 33.33% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::mean 19.333333 # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::stdev 22.384518 # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::9-12 1 16.67% 33.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::13-16 3 50.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction
-system.cpu1.CUs1.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed
-system.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD
-system.cpu1.CUs1.num_CAS_ops 0 # number of compare and swap operations
-system.cpu1.CUs1.num_failed_CAS_ops 0 # number of compare and swap operations that failed
-system.cpu1.CUs1.num_completed_wfs 4 # number of completed wavefronts
-system.cpu2.num_kernel_launched 1 # number of kernel launched
-system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits
-system.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses
-system.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses
-system.dir_cntrl0.L3CacheMemory.num_data_array_writes 1600 # number of data array writes
-system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1602 # number of tag array reads
-system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1572 # number of tag array writes
-system.dispatcher_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.dispatcher_coalescer.clk_domain.clock 1000 # Clock period in ticks
-system.dispatcher_coalescer.uncoalesced_accesses 0 # Number of uncoalesced TLB accesses
-system.dispatcher_coalescer.coalesced_accesses 0 # Number of coalesced TLB accesses
-system.dispatcher_coalescer.queuing_cycles 0 # Number of cycles spent in queue
-system.dispatcher_coalescer.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs
-system.dispatcher_coalescer.local_latency nan # Avg. latency over all incoming pkts
-system.dispatcher_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.dispatcher_tlb.clk_domain.clock 1000 # Clock period in ticks
-system.dispatcher_tlb.local_TLB_accesses 0 # Number of TLB accesses
-system.dispatcher_tlb.local_TLB_hits 0 # Number of TLB hits
-system.dispatcher_tlb.local_TLB_misses 0 # Number of TLB misses
-system.dispatcher_tlb.local_TLB_miss_rate nan # TLB miss rate
-system.dispatcher_tlb.global_TLB_accesses 0 # Number of TLB accesses
-system.dispatcher_tlb.global_TLB_hits 0 # Number of TLB hits
-system.dispatcher_tlb.global_TLB_misses 0 # Number of TLB misses
-system.dispatcher_tlb.global_TLB_miss_rate nan # TLB miss rate
-system.dispatcher_tlb.access_cycles 0 # Cycles spent accessing this TLB level
-system.dispatcher_tlb.page_table_cycles 0 # Cycles spent accessing the page table
-system.dispatcher_tlb.unique_pages 0 # Number of unique pages touched
-system.dispatcher_tlb.local_cycles 0 # Number of cycles spent in queue for all incoming reqs
-system.dispatcher_tlb.local_latency nan # Avg. latency over incoming coalesced reqs
-system.dispatcher_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
-system.l1_coalescer0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l1_coalescer0.clk_domain.clock 1000 # Clock period in ticks
-system.l1_coalescer0.uncoalesced_accesses 778 # Number of uncoalesced TLB accesses
-system.l1_coalescer0.coalesced_accesses 0 # Number of coalesced TLB accesses
-system.l1_coalescer0.queuing_cycles 0 # Number of cycles spent in queue
-system.l1_coalescer0.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs
-system.l1_coalescer0.local_latency 0 # Avg. latency over all incoming pkts
-system.l1_coalescer1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l1_coalescer1.clk_domain.clock 1000 # Clock period in ticks
-system.l1_coalescer1.uncoalesced_accesses 769 # Number of uncoalesced TLB accesses
-system.l1_coalescer1.coalesced_accesses 0 # Number of coalesced TLB accesses
-system.l1_coalescer1.queuing_cycles 0 # Number of cycles spent in queue
-system.l1_coalescer1.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs
-system.l1_coalescer1.local_latency 0 # Avg. latency over all incoming pkts
-system.l1_tlb0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l1_tlb0.clk_domain.clock 1000 # Clock period in ticks
-system.l1_tlb0.local_TLB_accesses 778 # Number of TLB accesses
-system.l1_tlb0.local_TLB_hits 774 # Number of TLB hits
-system.l1_tlb0.local_TLB_misses 4 # Number of TLB misses
-system.l1_tlb0.local_TLB_miss_rate 0.514139 # TLB miss rate
-system.l1_tlb0.global_TLB_accesses 778 # Number of TLB accesses
-system.l1_tlb0.global_TLB_hits 774 # Number of TLB hits
-system.l1_tlb0.global_TLB_misses 4 # Number of TLB misses
-system.l1_tlb0.global_TLB_miss_rate 0.514139 # TLB miss rate
-system.l1_tlb0.access_cycles 0 # Cycles spent accessing this TLB level
-system.l1_tlb0.page_table_cycles 0 # Cycles spent accessing the page table
-system.l1_tlb0.unique_pages 4 # Number of unique pages touched
-system.l1_tlb0.local_cycles 0 # Number of cycles spent in queue for all incoming reqs
-system.l1_tlb0.local_latency 0 # Avg. latency over incoming coalesced reqs
-system.l1_tlb0.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
-system.l1_tlb1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l1_tlb1.clk_domain.clock 1000 # Clock period in ticks
-system.l1_tlb1.local_TLB_accesses 769 # Number of TLB accesses
-system.l1_tlb1.local_TLB_hits 766 # Number of TLB hits
-system.l1_tlb1.local_TLB_misses 3 # Number of TLB misses
-system.l1_tlb1.local_TLB_miss_rate 0.390117 # TLB miss rate
-system.l1_tlb1.global_TLB_accesses 769 # Number of TLB accesses
-system.l1_tlb1.global_TLB_hits 766 # Number of TLB hits
-system.l1_tlb1.global_TLB_misses 3 # Number of TLB misses
-system.l1_tlb1.global_TLB_miss_rate 0.390117 # TLB miss rate
-system.l1_tlb1.access_cycles 0 # Cycles spent accessing this TLB level
-system.l1_tlb1.page_table_cycles 0 # Cycles spent accessing the page table
-system.l1_tlb1.unique_pages 3 # Number of unique pages touched
-system.l1_tlb1.local_cycles 0 # Number of cycles spent in queue for all incoming reqs
-system.l1_tlb1.local_latency 0 # Avg. latency over incoming coalesced reqs
-system.l1_tlb1.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
-system.l2_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l2_coalescer.clk_domain.clock 1000 # Clock period in ticks
-system.l2_coalescer.uncoalesced_accesses 8 # Number of uncoalesced TLB accesses
-system.l2_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses
-system.l2_coalescer.queuing_cycles 8000 # Number of cycles spent in queue
-system.l2_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs
-system.l2_coalescer.local_latency 125 # Avg. latency over all incoming pkts
-system.l2_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l2_tlb.clk_domain.clock 1000 # Clock period in ticks
-system.l2_tlb.local_TLB_accesses 8 # Number of TLB accesses
-system.l2_tlb.local_TLB_hits 3 # Number of TLB hits
-system.l2_tlb.local_TLB_misses 5 # Number of TLB misses
-system.l2_tlb.local_TLB_miss_rate 62.500000 # TLB miss rate
-system.l2_tlb.global_TLB_accesses 15 # Number of TLB accesses
-system.l2_tlb.global_TLB_hits 3 # Number of TLB hits
-system.l2_tlb.global_TLB_misses 12 # Number of TLB misses
-system.l2_tlb.global_TLB_miss_rate 80 # TLB miss rate
-system.l2_tlb.access_cycles 552008 # Cycles spent accessing this TLB level
-system.l2_tlb.page_table_cycles 0 # Cycles spent accessing the page table
-system.l2_tlb.unique_pages 5 # Number of unique pages touched
-system.l2_tlb.local_cycles 69001 # Number of cycles spent in queue for all incoming reqs
-system.l2_tlb.local_latency 8625.125000 # Avg. latency over incoming coalesced reqs
-system.l2_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
-system.l3_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l3_coalescer.clk_domain.clock 1000 # Clock period in ticks
-system.l3_coalescer.uncoalesced_accesses 5 # Number of uncoalesced TLB accesses
-system.l3_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses
-system.l3_coalescer.queuing_cycles 8000 # Number of cycles spent in queue
-system.l3_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs
-system.l3_coalescer.local_latency 200 # Avg. latency over all incoming pkts
-system.l3_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l3_tlb.clk_domain.clock 1000 # Clock period in ticks
-system.l3_tlb.local_TLB_accesses 5 # Number of TLB accesses
-system.l3_tlb.local_TLB_hits 0 # Number of TLB hits
-system.l3_tlb.local_TLB_misses 5 # Number of TLB misses
-system.l3_tlb.local_TLB_miss_rate 100 # TLB miss rate
-system.l3_tlb.global_TLB_accesses 12 # Number of TLB accesses
-system.l3_tlb.global_TLB_hits 0 # Number of TLB hits
-system.l3_tlb.global_TLB_misses 12 # Number of TLB misses
-system.l3_tlb.global_TLB_miss_rate 100 # TLB miss rate
-system.l3_tlb.access_cycles 1200000 # Cycles spent accessing this TLB level
-system.l3_tlb.page_table_cycles 6000000 # Cycles spent accessing the page table
-system.l3_tlb.unique_pages 5 # Number of unique pages touched
-system.l3_tlb.local_cycles 150000 # Number of cycles spent in queue for all incoming reqs
-system.l3_tlb.local_latency 30000 # Avg. latency over incoming coalesced reqs
-system.l3_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
-system.piobus.trans_dist::WriteReq 94 # Transaction distribution
-system.piobus.trans_dist::WriteResp 94 # Transaction distribution
-system.piobus.pkt_count_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 188 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::total 188 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_size_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 748 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.pkt_size::total 748 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.reqLayer0.occupancy 188000 # Layer occupancy (ticks)
-system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.piobus.respLayer0.occupancy 94000 # Layer occupancy (ticks)
-system.piobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.rb_cntrl0.cacheMemory.demand_hits 0 # Number of cache demand hits
-system.rb_cntrl0.cacheMemory.demand_misses 0 # Number of cache demand misses
-system.rb_cntrl0.cacheMemory.demand_accesses 0 # Number of cache demand accesses
-system.rb_cntrl0.cacheMemory.num_tag_array_reads 1553 # number of tag array reads
-system.rb_cntrl0.cacheMemory.num_tag_array_writes 3123 # number of tag array writes
-system.reg_cntrl0.cacheMemory.demand_hits 0 # Number of cache demand hits
-system.reg_cntrl0.cacheMemory.demand_misses 0 # Number of cache demand misses
-system.reg_cntrl0.cacheMemory.demand_accesses 0 # Number of cache demand accesses
-system.reg_cntrl0.cacheMemory.num_tag_array_reads 279 # number of tag array reads
-system.reg_cntrl0.cacheMemory.num_tag_array_writes 279 # number of tag array writes
-system.ruby.network.ext_links0.int_node.percent_links_utilized 0.122493
-system.ruby.network.ext_links0.int_node.msg_count.Data::0 16
-system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1558
-system.ruby.network.ext_links0.int_node.msg_count.Request_Control::5 279
-system.ruby.network.ext_links0.int_node.msg_count.Request_Control::7 279
-system.ruby.network.ext_links0.int_node.msg_count.Request_Control::8 8
-system.ruby.network.ext_links0.int_node.msg_count.Response_Data::2 1577
-system.ruby.network.ext_links0.int_node.msg_count.Response_Control::2 303
-system.ruby.network.ext_links0.int_node.msg_count.Response_Control::4 34
-system.ruby.network.ext_links0.int_node.msg_count.Writeback_Control::2 24
-system.ruby.network.ext_links0.int_node.msg_count.Unblock_Control::4 1556
-system.ruby.network.ext_links0.int_node.msg_bytes.Data::0 1152
-system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0 12464
-system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::5 2232
-system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::7 2232
-system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::8 64
-system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 113544
-system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 2424
-system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::4 272
-system.ruby.network.ext_links0.int_node.msg_bytes.Writeback_Control::2 192
-system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12448
-system.ruby.network.ext_links2.int_node.percent_links_utilized 0.185852
-system.ruby.network.ext_links2.int_node.msg_count.Control::0 23
-system.ruby.network.ext_links2.int_node.msg_count.Request_Control::0 3098
-system.ruby.network.ext_links2.int_node.msg_count.Request_Control::7 274
-system.ruby.network.ext_links2.int_node.msg_count.Request_Control::8 4
-system.ruby.network.ext_links2.int_node.msg_count.Response_Data::2 1568
-system.ruby.network.ext_links2.int_node.msg_count.Response_Control::2 281
-system.ruby.network.ext_links2.int_node.msg_count.Response_Control::4 23
-system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::4 3098
-system.ruby.network.ext_links2.int_node.msg_bytes.Control::0 184
-system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::0 24784
-system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::7 2192
-system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::8 32
-system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::2 112896
-system.ruby.network.ext_links2.int_node.msg_bytes.Response_Control::2 2248
-system.ruby.network.ext_links2.int_node.msg_bytes.Response_Control::4 184
-system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::4 24784
-system.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits
-system.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses
-system.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses
-system.tcp_cntrl0.L1cache.num_data_array_reads 6 # number of data array reads
-system.tcp_cntrl0.L1cache.num_data_array_writes 11 # number of data array writes
-system.tcp_cntrl0.L1cache.num_tag_array_reads 1297 # number of tag array reads
-system.tcp_cntrl0.L1cache.num_tag_array_writes 11 # number of tag array writes
-system.tcp_cntrl0.L1cache.num_tag_array_stalls 1271 # number of stalls caused by tag array
-system.tcp_cntrl0.L1cache.num_data_array_stalls 2 # number of stalls caused by data array
-system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP
-system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers
-system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl0.coalescer.gpu_ld_misses 5 # loads that miss in the GPU
-system.tcp_cntrl0.coalescer.gpu_tcp_st_hits 0 # stores that hit in the TCP
-system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers
-system.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl0.coalescer.gpu_st_misses 9 # stores that miss in the GPU
-system.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP
-system.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers
-system.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl0.coalescer.cp_ld_misses 0 # loads that miss in the GPU
-system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP
-system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
-system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU
-system.ruby.network.ext_links4.int_node.percent_links_utilized 0.003510
-system.ruby.network.ext_links4.int_node.msg_count.Control::0 11
-system.ruby.network.ext_links4.int_node.msg_count.Data::0 34
-system.ruby.network.ext_links4.int_node.msg_count.Data::1 18
-system.ruby.network.ext_links4.int_node.msg_count.Request_Control::0 16
-system.ruby.network.ext_links4.int_node.msg_count.Request_Control::1 9
-system.ruby.network.ext_links4.int_node.msg_count.Request_Control::7 5
-system.ruby.network.ext_links4.int_node.msg_count.Request_Control::8 4
-system.ruby.network.ext_links4.int_node.msg_count.Response_Data::2 9
-system.ruby.network.ext_links4.int_node.msg_count.Response_Data::3 11
-system.ruby.network.ext_links4.int_node.msg_count.Response_Control::2 22
-system.ruby.network.ext_links4.int_node.msg_count.Response_Control::4 11
-system.ruby.network.ext_links4.int_node.msg_count.Writeback_Control::2 16
-system.ruby.network.ext_links4.int_node.msg_count.Writeback_Control::3 16
-system.ruby.network.ext_links4.int_node.msg_count.Unblock_Control::4 32
-system.ruby.network.ext_links4.int_node.msg_bytes.Control::0 88
-system.ruby.network.ext_links4.int_node.msg_bytes.Data::0 2448
-system.ruby.network.ext_links4.int_node.msg_bytes.Data::1 1296
-system.ruby.network.ext_links4.int_node.msg_bytes.Request_Control::0 128
-system.ruby.network.ext_links4.int_node.msg_bytes.Request_Control::1 72
-system.ruby.network.ext_links4.int_node.msg_bytes.Request_Control::7 40
-system.ruby.network.ext_links4.int_node.msg_bytes.Request_Control::8 32
-system.ruby.network.ext_links4.int_node.msg_bytes.Response_Data::2 648
-system.ruby.network.ext_links4.int_node.msg_bytes.Response_Data::3 792
-system.ruby.network.ext_links4.int_node.msg_bytes.Response_Control::2 176
-system.ruby.network.ext_links4.int_node.msg_bytes.Response_Control::4 88
-system.ruby.network.ext_links4.int_node.msg_bytes.Writeback_Control::2 128
-system.ruby.network.ext_links4.int_node.msg_bytes.Writeback_Control::3 128
-system.ruby.network.ext_links4.int_node.msg_bytes.Unblock_Control::4 256
-system.tcp_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits
-system.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses
-system.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses
-system.tcp_cntrl1.L1cache.num_data_array_reads 6 # number of data array reads
-system.tcp_cntrl1.L1cache.num_data_array_writes 11 # number of data array writes
-system.tcp_cntrl1.L1cache.num_tag_array_reads 1297 # number of tag array reads
-system.tcp_cntrl1.L1cache.num_tag_array_writes 11 # number of tag array writes
-system.tcp_cntrl1.L1cache.num_tag_array_stalls 1271 # number of stalls caused by tag array
-system.tcp_cntrl1.L1cache.num_data_array_stalls 2 # number of stalls caused by data array
-system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP
-system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers
-system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl1.coalescer.gpu_ld_misses 5 # loads that miss in the GPU
-system.tcp_cntrl1.coalescer.gpu_tcp_st_hits 0 # stores that hit in the TCP
-system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers
-system.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl1.coalescer.gpu_st_misses 9 # stores that miss in the GPU
-system.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP
-system.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers
-system.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl1.coalescer.cp_ld_misses 0 # loads that miss in the GPU
-system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP
-system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
-system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU
-system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits
-system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses
-system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses
-system.sqc_cntrl0.L1cache.num_data_array_reads 86 # number of data array reads
-system.sqc_cntrl0.L1cache.num_tag_array_reads 91 # number of tag array reads
-system.sqc_cntrl0.L1cache.num_tag_array_writes 10 # number of tag array writes
-system.sqc_cntrl0.sequencer.load_waiting_on_load 98 # Number of times a load aliased with a pending load
-system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits
-system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses
-system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses
-system.tcc_cntrl0.L2cache.num_data_array_writes 9 # number of data array writes
-system.tcc_cntrl0.L2cache.num_tag_array_reads 45 # number of tag array reads
-system.tcc_cntrl0.L2cache.num_tag_array_writes 21 # number of tag array writes
-system.tcc_rb_cntrl0.cacheMemory.demand_hits 0 # Number of cache demand hits
-system.tcc_rb_cntrl0.cacheMemory.demand_misses 0 # Number of cache demand misses
-system.tcc_rb_cntrl0.cacheMemory.demand_accesses 0 # Number of cache demand accesses
-system.tcc_rb_cntrl0.cacheMemory.num_tag_array_reads 29 # number of tag array reads
-system.tcc_rb_cntrl0.cacheMemory.num_tag_array_writes 89 # number of tag array writes
-system.tcc_rb_cntrl0.cacheMemory.num_tag_array_stalls 20 # number of stalls caused by tag array
-system.ruby.network.msg_count.Control 34
-system.ruby.network.msg_count.Data 68
-system.ruby.network.msg_count.Request_Control 5534
-system.ruby.network.msg_count.Response_Data 3165
-system.ruby.network.msg_count.Response_Control 674
-system.ruby.network.msg_count.Writeback_Control 56
-system.ruby.network.msg_count.Unblock_Control 4686
-system.ruby.network.msg_byte.Control 272
-system.ruby.network.msg_byte.Data 4896
-system.ruby.network.msg_byte.Request_Control 44272
-system.ruby.network.msg_byte.Response_Data 227880
-system.ruby.network.msg_byte.Response_Control 5392
-system.ruby.network.msg_byte.Writeback_Control 448
-system.ruby.network.msg_byte.Unblock_Control 37488
-system.sqc_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.sqc_coalescer.clk_domain.clock 1000 # Clock period in ticks
-system.sqc_coalescer.uncoalesced_accesses 86 # Number of uncoalesced TLB accesses
-system.sqc_coalescer.coalesced_accesses 66 # Number of coalesced TLB accesses
-system.sqc_coalescer.queuing_cycles 288000 # Number of cycles spent in queue
-system.sqc_coalescer.local_queuing_cycles 288000 # Number of cycles spent in queue for all incoming reqs
-system.sqc_coalescer.local_latency 3348.837209 # Avg. latency over all incoming pkts
-system.sqc_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.sqc_tlb.clk_domain.clock 1000 # Clock period in ticks
-system.sqc_tlb.local_TLB_accesses 66 # Number of TLB accesses
-system.sqc_tlb.local_TLB_hits 65 # Number of TLB hits
-system.sqc_tlb.local_TLB_misses 1 # Number of TLB misses
-system.sqc_tlb.local_TLB_miss_rate 1.515152 # TLB miss rate
-system.sqc_tlb.global_TLB_accesses 86 # Number of TLB accesses
-system.sqc_tlb.global_TLB_hits 78 # Number of TLB hits
-system.sqc_tlb.global_TLB_misses 8 # Number of TLB misses
-system.sqc_tlb.global_TLB_miss_rate 9.302326 # TLB miss rate
-system.sqc_tlb.access_cycles 86008 # Cycles spent accessing this TLB level
-system.sqc_tlb.page_table_cycles 0 # Cycles spent accessing the page table
-system.sqc_tlb.unique_pages 1 # Number of unique pages touched
-system.sqc_tlb.local_cycles 66001 # Number of cycles spent in queue for all incoming reqs
-system.sqc_tlb.local_latency 1000.015152 # Avg. latency over incoming coalesced reqs
-system.sqc_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
-system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.091873
-system.ruby.network.ext_links0.int_node.throttle0.msg_count.Data::0 16
-system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1279
-system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::5 279
-system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2 19
-system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2 17
-system.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4 1556
-system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Data::0 1152
-system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0 10232
-system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::5 2232
-system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Data::2 1368
-system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2 136
-system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Unblock_Control::4 12448
-system.ruby.network.ext_links0.int_node.throttle1.link_utilization 0.015277
-system.ruby.network.ext_links0.int_node.throttle1.msg_count.Request_Control::0 279
-system.ruby.network.ext_links0.int_node.throttle1.msg_count.Response_Control::2 286
-system.ruby.network.ext_links0.int_node.throttle1.msg_count.Writeback_Control::2 8
-system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Request_Control::0 2232
-system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Response_Control::2 2288
-system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Writeback_Control::2 64
-system.ruby.network.ext_links0.int_node.throttle2.link_utilization 0.379702
-system.ruby.network.ext_links0.int_node.throttle2.msg_count.Request_Control::7 274
-system.ruby.network.ext_links0.int_node.throttle2.msg_count.Request_Control::8 4
-system.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Data::2 1549
-system.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Control::4 23
-system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Request_Control::7 2192
-system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Request_Control::8 32
-system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Data::2 111528
-system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Control::4 184
-system.ruby.network.ext_links0.int_node.throttle3.link_utilization 0.003119
-system.ruby.network.ext_links0.int_node.throttle3.msg_count.Request_Control::7 5
-system.ruby.network.ext_links0.int_node.throttle3.msg_count.Request_Control::8 4
-system.ruby.network.ext_links0.int_node.throttle3.msg_count.Response_Data::2 9
-system.ruby.network.ext_links0.int_node.throttle3.msg_count.Response_Control::4 11
-system.ruby.network.ext_links0.int_node.throttle3.msg_count.Writeback_Control::2 16
-system.ruby.network.ext_links0.int_node.throttle3.msg_bytes.Request_Control::7 40
-system.ruby.network.ext_links0.int_node.throttle3.msg_bytes.Request_Control::8 32
-system.ruby.network.ext_links0.int_node.throttle3.msg_bytes.Response_Data::2 648
-system.ruby.network.ext_links0.int_node.throttle3.msg_bytes.Response_Control::4 88
-system.ruby.network.ext_links0.int_node.throttle3.msg_bytes.Writeback_Control::2 128
-system.ruby.network.ext_links2.int_node.throttle0.link_utilization 0.372290
-system.ruby.network.ext_links2.int_node.throttle0.msg_count.Control::0 23
-system.ruby.network.ext_links2.int_node.throttle0.msg_count.Response_Data::2 1549
-system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Control::0 184
-system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Response_Data::2 111528
-system.ruby.network.ext_links2.int_node.throttle1.link_utilization 0.090620
-system.ruby.network.ext_links2.int_node.throttle1.msg_count.Request_Control::0 1549
-system.ruby.network.ext_links2.int_node.throttle1.msg_count.Request_Control::7 274
-system.ruby.network.ext_links2.int_node.throttle1.msg_count.Request_Control::8 4
-system.ruby.network.ext_links2.int_node.throttle1.msg_count.Response_Control::4 23
-system.ruby.network.ext_links2.int_node.throttle1.msg_count.Unblock_Control::4 1549
-system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Request_Control::0 12392
-system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Request_Control::7 2192
-system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Request_Control::8 32
-system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Response_Control::4 184
-system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Unblock_Control::4 12392
-system.ruby.network.ext_links2.int_node.throttle2.link_utilization 0.094646
-system.ruby.network.ext_links2.int_node.throttle2.msg_count.Request_Control::0 1549
-system.ruby.network.ext_links2.int_node.throttle2.msg_count.Response_Data::2 19
-system.ruby.network.ext_links2.int_node.throttle2.msg_count.Response_Control::2 281
-system.ruby.network.ext_links2.int_node.throttle2.msg_count.Unblock_Control::4 1549
-system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Request_Control::0 12392
-system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Response_Data::2 1368
-system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Response_Control::2 2248
-system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Unblock_Control::4 12392
-system.ruby.network.ext_links4.int_node.throttle0.link_utilization 0.000933
-system.ruby.network.ext_links4.int_node.throttle0.msg_count.Response_Data::3 3
-system.ruby.network.ext_links4.int_node.throttle0.msg_count.Writeback_Control::3 8
-system.ruby.network.ext_links4.int_node.throttle0.msg_bytes.Response_Data::3 216
-system.ruby.network.ext_links4.int_node.throttle0.msg_bytes.Writeback_Control::3 64
-system.ruby.network.ext_links4.int_node.throttle1.link_utilization 0.000933
-system.ruby.network.ext_links4.int_node.throttle1.msg_count.Response_Data::3 3
-system.ruby.network.ext_links4.int_node.throttle1.msg_count.Writeback_Control::3 8
-system.ruby.network.ext_links4.int_node.throttle1.msg_bytes.Response_Data::3 216
-system.ruby.network.ext_links4.int_node.throttle1.msg_bytes.Writeback_Control::3 64
-system.ruby.network.ext_links4.int_node.throttle2.link_utilization 0.007438
-system.ruby.network.ext_links4.int_node.throttle2.msg_count.Control::0 11
-system.ruby.network.ext_links4.int_node.throttle2.msg_count.Data::1 18
-system.ruby.network.ext_links4.int_node.throttle2.msg_count.Request_Control::1 9
-system.ruby.network.ext_links4.int_node.throttle2.msg_count.Response_Data::2 9
-system.ruby.network.ext_links4.int_node.throttle2.msg_count.Writeback_Control::2 16
-system.ruby.network.ext_links4.int_node.throttle2.msg_bytes.Control::0 88
-system.ruby.network.ext_links4.int_node.throttle2.msg_bytes.Data::1 1296
-system.ruby.network.ext_links4.int_node.throttle2.msg_bytes.Request_Control::1 72
-system.ruby.network.ext_links4.int_node.throttle2.msg_bytes.Response_Data::2 648
-system.ruby.network.ext_links4.int_node.throttle2.msg_bytes.Writeback_Control::2 128
-system.ruby.network.ext_links4.int_node.throttle3.link_utilization 0.001200
-system.ruby.network.ext_links4.int_node.throttle3.msg_count.Response_Data::3 5
-system.ruby.network.ext_links4.int_node.throttle3.msg_bytes.Response_Data::3 360
-system.ruby.network.ext_links4.int_node.throttle4.link_utilization 0.005705
-system.ruby.network.ext_links4.int_node.throttle4.msg_count.Data::0 18
-system.ruby.network.ext_links4.int_node.throttle4.msg_count.Request_Control::0 7
-system.ruby.network.ext_links4.int_node.throttle4.msg_count.Request_Control::7 5
-system.ruby.network.ext_links4.int_node.throttle4.msg_count.Request_Control::8 4
-system.ruby.network.ext_links4.int_node.throttle4.msg_count.Response_Control::4 11
-system.ruby.network.ext_links4.int_node.throttle4.msg_count.Unblock_Control::4 25
-system.ruby.network.ext_links4.int_node.throttle4.msg_bytes.Data::0 1296
-system.ruby.network.ext_links4.int_node.throttle4.msg_bytes.Request_Control::0 56
-system.ruby.network.ext_links4.int_node.throttle4.msg_bytes.Request_Control::7 40
-system.ruby.network.ext_links4.int_node.throttle4.msg_bytes.Request_Control::8 32
-system.ruby.network.ext_links4.int_node.throttle4.msg_bytes.Response_Control::4 88
-system.ruby.network.ext_links4.int_node.throttle4.msg_bytes.Unblock_Control::4 200
-system.ruby.network.ext_links4.int_node.throttle5.link_utilization 0.004852
-system.ruby.network.ext_links4.int_node.throttle5.msg_count.Data::0 16
-system.ruby.network.ext_links4.int_node.throttle5.msg_count.Request_Control::0 9
-system.ruby.network.ext_links4.int_node.throttle5.msg_count.Response_Control::2 22
-system.ruby.network.ext_links4.int_node.throttle5.msg_count.Unblock_Control::4 7
-system.ruby.network.ext_links4.int_node.throttle5.msg_bytes.Data::0 1152
-system.ruby.network.ext_links4.int_node.throttle5.msg_bytes.Request_Control::0 72
-system.ruby.network.ext_links4.int_node.throttle5.msg_bytes.Response_Control::2 176
-system.ruby.network.ext_links4.int_node.throttle5.msg_bytes.Unblock_Control::4 56
-system.ruby.CorePair_Controller.C0_Load_L1miss 193 0.00% 0.00%
-system.ruby.CorePair_Controller.C0_Load_L1hit 16142 0.00% 0.00%
-system.ruby.CorePair_Controller.Ifetch0_L1hit 85994 0.00% 0.00%
-system.ruby.CorePair_Controller.Ifetch0_L1miss 1101 0.00% 0.00%
-system.ruby.CorePair_Controller.C0_Store_L1miss 327 0.00% 0.00%
-system.ruby.CorePair_Controller.C0_Store_L1hit 10446 0.00% 0.00%
-system.ruby.CorePair_Controller.NB_AckS 1047 0.00% 0.00%
-system.ruby.CorePair_Controller.NB_AckM 329 0.00% 0.00%
-system.ruby.CorePair_Controller.NB_AckE 173 0.00% 0.00%
-system.ruby.CorePair_Controller.L1I_Repl 602 0.00% 0.00%
-system.ruby.CorePair_Controller.L1D0_Repl 28 0.00% 0.00%
-system.ruby.CorePair_Controller.L2_to_L1D0 7 0.00% 0.00%
-system.ruby.CorePair_Controller.L2_to_L1I 67 0.00% 0.00%
-system.ruby.CorePair_Controller.PrbInvData 15 0.00% 0.00%
-system.ruby.CorePair_Controller.PrbInvDataDemand 2 0.00% 0.00%
-system.ruby.CorePair_Controller.PrbShrData 4 0.00% 0.00%
-system.ruby.CorePair_Controller.PrbShrDataDemand 2 0.00% 0.00%
-system.ruby.CorePair_Controller.I.C0_Load_L1miss 186 0.00% 0.00%
-system.ruby.CorePair_Controller.I.Ifetch0_L1miss 1034 0.00% 0.00%
-system.ruby.CorePair_Controller.I.C0_Store_L1miss 325 0.00% 0.00%
-system.ruby.CorePair_Controller.I.PrbInvDataDemand 1 0.00% 0.00%
-system.ruby.CorePair_Controller.S.C0_Load_L1hit 643 0.00% 0.00%
-system.ruby.CorePair_Controller.S.Ifetch0_L1hit 85994 0.00% 0.00%
-system.ruby.CorePair_Controller.S.Ifetch0_L1miss 67 0.00% 0.00%
-system.ruby.CorePair_Controller.S.C0_Store_L1hit 4 0.00% 0.00%
-system.ruby.CorePair_Controller.S.L1I_Repl 602 0.00% 0.00%
-system.ruby.CorePair_Controller.E0.C0_Load_L1miss 2 0.00% 0.00%
-system.ruby.CorePair_Controller.E0.C0_Load_L1hit 2728 0.00% 0.00%
-system.ruby.CorePair_Controller.E0.C0_Store_L1hit 50 0.00% 0.00%
-system.ruby.CorePair_Controller.E0.L1D0_Repl 16 0.00% 0.00%
-system.ruby.CorePair_Controller.E0.PrbInvData 1 0.00% 0.00%
-system.ruby.CorePair_Controller.E0.PrbShrData 1 0.00% 0.00%
-system.ruby.CorePair_Controller.E0.PrbShrDataDemand 1 0.00% 0.00%
-system.ruby.CorePair_Controller.O.PrbInvData 4 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.C0_Load_L1miss 5 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.C0_Load_L1hit 12771 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.C0_Store_L1miss 2 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.C0_Store_L1hit 10392 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.L1D0_Repl 12 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.PrbInvData 10 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.PrbInvDataDemand 1 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.PrbShrData 3 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.PrbShrDataDemand 1 0.00% 0.00%
-system.ruby.CorePair_Controller.I_M0.NB_AckM 325 0.00% 0.00%
-system.ruby.CorePair_Controller.I_E0S.NB_AckS 13 0.00% 0.00%
-system.ruby.CorePair_Controller.I_E0S.NB_AckE 173 0.00% 0.00%
-system.ruby.CorePair_Controller.Si_F0.L2_to_L1I 67 0.00% 0.00%
-system.ruby.CorePair_Controller.S_M0.NB_AckM 4 0.00% 0.00%
-system.ruby.CorePair_Controller.S0.NB_AckS 1034 0.00% 0.00%
-system.ruby.CorePair_Controller.E0_F.L2_to_L1D0 2 0.00% 0.00%
-system.ruby.CorePair_Controller.M0_F.L2_to_L1D0 5 0.00% 0.00%
-system.ruby.Directory_Controller.RdBlkS 190 0.00% 0.00%
-system.ruby.Directory_Controller.RdBlkM 31 0.00% 0.00%
-system.ruby.Directory_Controller.RdBlk 56 0.00% 0.00%
-system.ruby.Directory_Controller.WriteThrough 1 0.00% 0.00%
-system.ruby.Directory_Controller.Atomic 1 0.00% 0.00%
-system.ruby.Directory_Controller.RdBlkSP 844 0.00% 0.00%
-system.ruby.Directory_Controller.RdBlkMP 298 0.00% 0.00%
-system.ruby.Directory_Controller.RdBlkP 137 0.00% 0.00%
-system.ruby.Directory_Controller.WriteThroughP 15 0.00% 0.00%
-system.ruby.Directory_Controller.AtomicP 1 0.00% 0.00%
-system.ruby.Directory_Controller.CPUPrbResp 28 0.00% 0.00%
-system.ruby.Directory_Controller.LastCPUPrbResp 8 0.00% 0.00%
-system.ruby.Directory_Controller.ProbeAcksComplete 271 0.00% 0.00%
-system.ruby.Directory_Controller.L3Hit 11 0.00% 0.00%
-system.ruby.Directory_Controller.MemData 1563 0.00% 0.00%
-system.ruby.Directory_Controller.CoreUnblock 1556 0.00% 0.00%
-system.ruby.Directory_Controller.UnblockWriteThrough 18 0.00% 0.00%
-system.ruby.Directory_Controller.U.RdBlkS 190 0.00% 0.00%
-system.ruby.Directory_Controller.U.RdBlkM 31 0.00% 0.00%
-system.ruby.Directory_Controller.U.RdBlk 56 0.00% 0.00%
-system.ruby.Directory_Controller.U.WriteThrough 1 0.00% 0.00%
-system.ruby.Directory_Controller.U.Atomic 1 0.00% 0.00%
-system.ruby.Directory_Controller.U.RdBlkSP 844 0.00% 0.00%
-system.ruby.Directory_Controller.U.RdBlkMP 298 0.00% 0.00%
-system.ruby.Directory_Controller.U.RdBlkP 137 0.00% 0.00%
-system.ruby.Directory_Controller.U.WriteThroughP 15 0.00% 0.00%
-system.ruby.Directory_Controller.U.AtomicP 1 0.00% 0.00%
-system.ruby.Directory_Controller.U.CPUPrbResp 28 0.00% 0.00%
-system.ruby.Directory_Controller.BS_M.MemData 1034 0.00% 0.00%
-system.ruby.Directory_Controller.BM_M.MemData 347 0.00% 0.00%
-system.ruby.Directory_Controller.B_M.L3Hit 11 0.00% 0.00%
-system.ruby.Directory_Controller.B_M.MemData 180 0.00% 0.00%
-system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 190 0.00% 0.00%
-system.ruby.Directory_Controller.BM_PM.LastCPUPrbResp 4 0.00% 0.00%
-system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 29 0.00% 0.00%
-system.ruby.Directory_Controller.B_PM.LastCPUPrbResp 2 0.00% 0.00%
-system.ruby.Directory_Controller.B_PM.ProbeAcksComplete 52 0.00% 0.00%
-system.ruby.Directory_Controller.B_PM.MemData 2 0.00% 0.00%
-system.ruby.Directory_Controller.B_Pm.LastCPUPrbResp 2 0.00% 0.00%
-system.ruby.Directory_Controller.B.CoreUnblock 1556 0.00% 0.00%
-system.ruby.Directory_Controller.B.UnblockWriteThrough 18 0.00% 0.00%
-system.ruby.RegionBuffer_Controller.CPURead | 1220 99.43% 99.43% | 7 0.57% 100.00%
-system.ruby.RegionBuffer_Controller.CPURead::total 1227
-system.ruby.RegionBuffer_Controller.CPUWrite | 331 89.95% 89.95% | 37 10.05% 100.00%
-system.ruby.RegionBuffer_Controller.CPUWrite::total 368
-system.ruby.RegionBuffer_Controller.PrivateNotify | 272 98.91% 98.91% | 3 1.09% 100.00%
-system.ruby.RegionBuffer_Controller.PrivateNotify::total 275
-system.ruby.RegionBuffer_Controller.SharedNotify | 2 50.00% 50.00% | 2 50.00% 100.00%
-system.ruby.RegionBuffer_Controller.SharedNotify::total 4
-system.ruby.RegionBuffer_Controller.InvRegion | 2 50.00% 50.00% | 2 50.00% 100.00%
-system.ruby.RegionBuffer_Controller.InvRegion::total 4
-system.ruby.RegionBuffer_Controller.DowngradeRegion | 2 50.00% 50.00% | 2 50.00% 100.00%
-system.ruby.RegionBuffer_Controller.DowngradeRegion::total 4
-system.ruby.RegionBuffer_Controller.InvAck | 23 67.65% 67.65% | 11 32.35% 100.00%
-system.ruby.RegionBuffer_Controller.InvAck::total 34
-system.ruby.RegionBuffer_Controller.DoneAck | 1572 96.26% 96.26% | 61 3.74% 100.00%
-system.ruby.RegionBuffer_Controller.DoneAck::total 1633
-system.ruby.RegionBuffer_Controller.AllOutstanding | 6 54.55% 54.55% | 5 45.45% 100.00%
-system.ruby.RegionBuffer_Controller.AllOutstanding::total 11
-system.ruby.RegionBuffer_Controller.Evict | 64 66.67% 66.67% | 32 33.33% 100.00%
-system.ruby.RegionBuffer_Controller.Evict::total 96
-system.ruby.RegionBuffer_Controller.LastAck_PrbResp | 4 50.00% 50.00% | 4 50.00% 100.00%
-system.ruby.RegionBuffer_Controller.LastAck_PrbResp::total 8
-system.ruby.RegionBuffer_Controller.StallAccess | 0 0.00% 0.00% | 16 100.00% 100.00%
-system.ruby.RegionBuffer_Controller.StallAccess::total 16
-system.ruby.RegionBuffer_Controller.NP.CPURead | 243 98.78% 98.78% | 3 1.22% 100.00%
-system.ruby.RegionBuffer_Controller.NP.CPURead::total 246
-system.ruby.RegionBuffer_Controller.NP.CPUWrite | 29 96.67% 96.67% | 1 3.33% 100.00%
-system.ruby.RegionBuffer_Controller.NP.CPUWrite::total 30
-system.ruby.RegionBuffer_Controller.P.CPURead | 965 99.59% 99.59% | 4 0.41% 100.00%
-system.ruby.RegionBuffer_Controller.P.CPURead::total 969
-system.ruby.RegionBuffer_Controller.P.CPUWrite | 298 94.90% 94.90% | 16 5.10% 100.00%
-system.ruby.RegionBuffer_Controller.P.CPUWrite::total 314
-system.ruby.RegionBuffer_Controller.P.InvRegion | 1 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.RegionBuffer_Controller.P.InvRegion::total 1
-system.ruby.RegionBuffer_Controller.P.DowngradeRegion | 2 50.00% 50.00% | 2 50.00% 100.00%
-system.ruby.RegionBuffer_Controller.P.DowngradeRegion::total 4
-system.ruby.RegionBuffer_Controller.P.DoneAck | 1535 98.52% 98.52% | 23 1.48% 100.00%
-system.ruby.RegionBuffer_Controller.P.DoneAck::total 1558
-system.ruby.RegionBuffer_Controller.P.StallAccess | 0 0.00% 0.00% | 15 100.00% 100.00%
-system.ruby.RegionBuffer_Controller.P.StallAccess::total 15
-system.ruby.RegionBuffer_Controller.S.CPURead | 12 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.RegionBuffer_Controller.S.CPURead::total 12
-system.ruby.RegionBuffer_Controller.S.CPUWrite | 2 66.67% 66.67% | 1 33.33% 100.00%
-system.ruby.RegionBuffer_Controller.S.CPUWrite::total 3
-system.ruby.RegionBuffer_Controller.S.InvRegion | 1 33.33% 33.33% | 2 66.67% 100.00%
-system.ruby.RegionBuffer_Controller.S.InvRegion::total 3
-system.ruby.RegionBuffer_Controller.S.DoneAck | 14 87.50% 87.50% | 2 12.50% 100.00%
-system.ruby.RegionBuffer_Controller.S.DoneAck::total 16
-system.ruby.RegionBuffer_Controller.NP_PS.PrivateNotify | 270 99.26% 99.26% | 2 0.74% 100.00%
-system.ruby.RegionBuffer_Controller.NP_PS.PrivateNotify::total 272
-system.ruby.RegionBuffer_Controller.NP_PS.SharedNotify | 2 50.00% 50.00% | 2 50.00% 100.00%
-system.ruby.RegionBuffer_Controller.NP_PS.SharedNotify::total 4
-system.ruby.RegionBuffer_Controller.NP_PS.DoneAck | 8 25.81% 25.81% | 23 74.19% 100.00%
-system.ruby.RegionBuffer_Controller.NP_PS.DoneAck::total 31
-system.ruby.RegionBuffer_Controller.NP_PS.StallAccess | 0 0.00% 0.00% | 1 100.00% 100.00%
-system.ruby.RegionBuffer_Controller.NP_PS.StallAccess::total 1
-system.ruby.RegionBuffer_Controller.S_P.CPUWrite | 0 0.00% 0.00% | 18 100.00% 100.00%
-system.ruby.RegionBuffer_Controller.S_P.CPUWrite::total 18
-system.ruby.RegionBuffer_Controller.S_P.PrivateNotify | 2 66.67% 66.67% | 1 33.33% 100.00%
-system.ruby.RegionBuffer_Controller.S_P.PrivateNotify::total 3
-system.ruby.RegionBuffer_Controller.S_P.DoneAck | 15 53.57% 53.57% | 13 46.43% 100.00%
-system.ruby.RegionBuffer_Controller.S_P.DoneAck::total 28
-system.ruby.RegionBuffer_Controller.P_NP.InvAck | 17 60.71% 60.71% | 11 39.29% 100.00%
-system.ruby.RegionBuffer_Controller.P_NP.InvAck::total 28
-system.ruby.RegionBuffer_Controller.P_NP.Evict | 32 50.00% 50.00% | 32 50.00% 100.00%
-system.ruby.RegionBuffer_Controller.P_NP.Evict::total 64
-system.ruby.RegionBuffer_Controller.P_NP.LastAck_PrbResp | 2 50.00% 50.00% | 2 50.00% 100.00%
-system.ruby.RegionBuffer_Controller.P_NP.LastAck_PrbResp::total 4
-system.ruby.RegionBuffer_Controller.P_S.InvAck | 6 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.RegionBuffer_Controller.P_S.InvAck::total 6
-system.ruby.RegionBuffer_Controller.P_S.Evict | 32 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.RegionBuffer_Controller.P_S.Evict::total 32
-system.ruby.RegionBuffer_Controller.P_S.LastAck_PrbResp | 2 50.00% 50.00% | 2 50.00% 100.00%
-system.ruby.RegionBuffer_Controller.P_S.LastAck_PrbResp::total 4
-system.ruby.RegionBuffer_Controller.P_NP_O.AllOutstanding | 2 50.00% 50.00% | 2 50.00% 100.00%
-system.ruby.RegionBuffer_Controller.P_NP_O.AllOutstanding::total 4
-system.ruby.RegionBuffer_Controller.P_S_O.AllOutstanding | 2 50.00% 50.00% | 2 50.00% 100.00%
-system.ruby.RegionBuffer_Controller.P_S_O.AllOutstanding::total 4
-system.ruby.RegionBuffer_Controller.S_O.AllOutstanding | 2 66.67% 66.67% | 1 33.33% 100.00%
-system.ruby.RegionBuffer_Controller.S_O.AllOutstanding::total 3
-system.ruby.RegionBuffer_Controller.SS_P.CPUWrite | 2 66.67% 66.67% | 1 33.33% 100.00%
-system.ruby.RegionBuffer_Controller.SS_P.CPUWrite::total 3
-system.ruby.RegionDir_Controller.SendInv 1 0.00% 0.00%
-system.ruby.RegionDir_Controller.SendUpgrade 3 0.00% 0.00%
-system.ruby.RegionDir_Controller.SendDowngrade 4 0.00% 0.00%
-system.ruby.RegionDir_Controller.PrivateRequest 271 0.00% 0.00%
-system.ruby.RegionDir_Controller.InvAckCore 4 0.00% 0.00%
-system.ruby.RegionDir_Controller.InvAckCoreNoShare 4 0.00% 0.00%
-system.ruby.RegionDir_Controller.CPUPrivateAck 278 0.00% 0.00%
-system.ruby.RegionDir_Controller.LastAck 8 0.00% 0.00%
-system.ruby.RegionDir_Controller.DirReadyAck 8 0.00% 0.00%
-system.ruby.RegionDir_Controller.TriggerInv 4 0.00% 0.00%
-system.ruby.RegionDir_Controller.TriggerDowngrade 4 0.00% 0.00%
-system.ruby.RegionDir_Controller.NP.PrivateRequest 271 0.00% 0.00%
-system.ruby.RegionDir_Controller.P.SendInv 1 0.00% 0.00%
-system.ruby.RegionDir_Controller.P.SendDowngrade 4 0.00% 0.00%
-system.ruby.RegionDir_Controller.S.SendUpgrade 3 0.00% 0.00%
-system.ruby.RegionDir_Controller.NP_P.CPUPrivateAck 270 0.00% 0.00%
-system.ruby.RegionDir_Controller.P_P.CPUPrivateAck 1 0.00% 0.00%
-system.ruby.RegionDir_Controller.P_S.CPUPrivateAck 4 0.00% 0.00%
-system.ruby.RegionDir_Controller.S_P.CPUPrivateAck 3 0.00% 0.00%
-system.ruby.RegionDir_Controller.P_AS.InvAckCore 4 0.00% 0.00%
-system.ruby.RegionDir_Controller.P_AS.LastAck 4 0.00% 0.00%
-system.ruby.RegionDir_Controller.S_AP.InvAckCoreNoShare 3 0.00% 0.00%
-system.ruby.RegionDir_Controller.S_AP.LastAck 3 0.00% 0.00%
-system.ruby.RegionDir_Controller.P_AP.InvAckCoreNoShare 1 0.00% 0.00%
-system.ruby.RegionDir_Controller.P_AP.LastAck 1 0.00% 0.00%
-system.ruby.RegionDir_Controller.P_AP_W.DirReadyAck 1 0.00% 0.00%
-system.ruby.RegionDir_Controller.P_AP_W.TriggerInv 1 0.00% 0.00%
-system.ruby.RegionDir_Controller.P_AS_W.DirReadyAck 4 0.00% 0.00%
-system.ruby.RegionDir_Controller.P_AS_W.TriggerDowngrade 4 0.00% 0.00%
-system.ruby.RegionDir_Controller.S_AP_W.DirReadyAck 3 0.00% 0.00%
-system.ruby.RegionDir_Controller.S_AP_W.TriggerInv 3 0.00% 0.00%
-system.ruby.LD.latency_hist::bucket_size 64
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-system.ruby.LD.latency_hist::samples 16335
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-system.ruby.LD.latency_hist::gmean 1.060634
-system.ruby.LD.latency_hist::stdev 17.742972
-system.ruby.LD.latency_hist | 16149 98.86% 98.86% | 11 0.07% 98.93% | 119 0.73% 99.66% | 52 0.32% 99.98% | 2 0.01% 99.99% | 1 0.01% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.latency_hist::total 16335
-system.ruby.LD.hit_latency_hist::bucket_size 64
-system.ruby.LD.hit_latency_hist::max_bucket 639
-system.ruby.LD.hit_latency_hist::samples 186
-system.ruby.LD.hit_latency_hist::mean 162.333333
-system.ruby.LD.hit_latency_hist::gmean 157.431876
-system.ruby.LD.hit_latency_hist::stdev 43.755298
-system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 11 5.91% 5.91% | 119 63.98% 69.89% | 52 27.96% 97.85% | 2 1.08% 98.92% | 1 0.54% 99.46% | 1 0.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.hit_latency_hist::total 186
-system.ruby.LD.miss_latency_hist::bucket_size 2
-system.ruby.LD.miss_latency_hist::max_bucket 19
-system.ruby.LD.miss_latency_hist::samples 16149
-system.ruby.LD.miss_latency_hist::mean 1.007802
-system.ruby.LD.miss_latency_hist::gmean 1.001277
-system.ruby.LD.miss_latency_hist::stdev 0.374686
-system.ruby.LD.miss_latency_hist | 16142 99.96% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 7 0.04% 100.00%
-system.ruby.LD.miss_latency_hist::total 16149
-system.ruby.ST.latency_hist::bucket_size 64
-system.ruby.ST.latency_hist::max_bucket 639
-system.ruby.ST.latency_hist::samples 10412
-system.ruby.ST.latency_hist::mean 5.551287
-system.ruby.ST.latency_hist::gmean 1.167783
-system.ruby.ST.latency_hist::stdev 26.172531
-system.ruby.ST.latency_hist | 10087 96.88% 96.88% | 0 0.00% 96.88% | 289 2.78% 99.65% | 29 0.28% 99.93% | 4 0.04% 99.97% | 2 0.02% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.latency_hist::total 10412
-system.ruby.ST.hit_latency_hist::bucket_size 64
-system.ruby.ST.hit_latency_hist::max_bucket 639
-system.ruby.ST.hit_latency_hist::samples 325
-system.ruby.ST.hit_latency_hist::mean 146.809231
-system.ruby.ST.hit_latency_hist::gmean 143.903653
-system.ruby.ST.hit_latency_hist::stdev 36.751508
-system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 289 88.92% 88.92% | 29 8.92% 97.85% | 4 1.23% 99.08% | 2 0.62% 99.69% | 0 0.00% 99.69% | 1 0.31% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.hit_latency_hist::total 325
-system.ruby.ST.miss_latency_hist::bucket_size 1
-system.ruby.ST.miss_latency_hist::max_bucket 9
-system.ruby.ST.miss_latency_hist::samples 10087
-system.ruby.ST.miss_latency_hist::mean 1
-system.ruby.ST.miss_latency_hist::gmean 1
-system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 10087 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.miss_latency_hist::total 10087
-system.ruby.IFETCH.latency_hist::bucket_size 64
-system.ruby.IFETCH.latency_hist::max_bucket 639
-system.ruby.IFETCH.latency_hist::samples 87095
-system.ruby.IFETCH.latency_hist::mean 2.818945
-system.ruby.IFETCH.latency_hist::gmean 1.063630
-system.ruby.IFETCH.latency_hist::stdev 17.067789
-system.ruby.IFETCH.latency_hist | 86061 98.81% 98.81% | 0 0.00% 98.81% | 826 0.95% 99.76% | 185 0.21% 99.97% | 8 0.01% 99.98% | 9 0.01% 99.99% | 6 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.latency_hist::total 87095
-system.ruby.IFETCH.hit_latency_hist::bucket_size 64
-system.ruby.IFETCH.hit_latency_hist::max_bucket 639
-system.ruby.IFETCH.hit_latency_hist::samples 1034
-system.ruby.IFETCH.hit_latency_hist::mean 153.045455
-system.ruby.IFETCH.hit_latency_hist::gmean 149.192268
-system.ruby.IFETCH.hit_latency_hist::stdev 40.969954
-system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 826 79.88% 79.88% | 185 17.89% 97.78% | 8 0.77% 98.55% | 9 0.87% 99.42% | 6 0.58% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.hit_latency_hist::total 1034
-system.ruby.IFETCH.miss_latency_hist::bucket_size 2
-system.ruby.IFETCH.miss_latency_hist::max_bucket 19
-system.ruby.IFETCH.miss_latency_hist::samples 86061
-system.ruby.IFETCH.miss_latency_hist::mean 1.014013
-system.ruby.IFETCH.miss_latency_hist::gmean 1.002295
-system.ruby.IFETCH.miss_latency_hist::stdev 0.502042
-system.ruby.IFETCH.miss_latency_hist | 85994 99.92% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 67 0.08% 100.00%
-system.ruby.IFETCH.miss_latency_hist::total 86061
-system.ruby.RMW_Read.latency_hist::bucket_size 32
-system.ruby.RMW_Read.latency_hist::max_bucket 319
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-system.ruby.RMW_Read.latency_hist::gmean 1.059947
-system.ruby.RMW_Read.latency_hist::stdev 15.416875
-system.ruby.RMW_Read.latency_hist | 337 98.83% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 3 0.88% 99.71% | 1 0.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.RMW_Read.latency_hist::total 341
-system.ruby.RMW_Read.hit_latency_hist::bucket_size 32
-system.ruby.RMW_Read.hit_latency_hist::max_bucket 319
-system.ruby.RMW_Read.hit_latency_hist::samples 4
-system.ruby.RMW_Read.hit_latency_hist::mean 143.500000
-system.ruby.RMW_Read.hit_latency_hist::gmean 143.041358
-system.ruby.RMW_Read.hit_latency_hist::stdev 13.403980
-system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 75.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.RMW_Read.hit_latency_hist::total 4
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-system.ruby.RMW_Read.miss_latency_hist::max_bucket 9
-system.ruby.RMW_Read.miss_latency_hist::samples 337
-system.ruby.RMW_Read.miss_latency_hist::mean 1
-system.ruby.RMW_Read.miss_latency_hist::gmean 1
-system.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.RMW_Read.miss_latency_hist::total 337
-system.ruby.Locked_RMW_Read.latency_hist::bucket_size 1
-system.ruby.Locked_RMW_Read.latency_hist::max_bucket 9
-system.ruby.Locked_RMW_Read.latency_hist::samples 10
-system.ruby.Locked_RMW_Read.latency_hist::mean 1
-system.ruby.Locked_RMW_Read.latency_hist::gmean 1
-system.ruby.Locked_RMW_Read.latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Locked_RMW_Read.latency_hist::total 10
-system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 1
-system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 9
-system.ruby.Locked_RMW_Read.miss_latency_hist::samples 10
-system.ruby.Locked_RMW_Read.miss_latency_hist::mean 1
-system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 1
-system.ruby.Locked_RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Locked_RMW_Read.miss_latency_hist::total 10
-system.ruby.Locked_RMW_Write.latency_hist::bucket_size 1
-system.ruby.Locked_RMW_Write.latency_hist::max_bucket 9
-system.ruby.Locked_RMW_Write.latency_hist::samples 10
-system.ruby.Locked_RMW_Write.latency_hist::mean 1
-system.ruby.Locked_RMW_Write.latency_hist::gmean 1
-system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Locked_RMW_Write.latency_hist::total 10
-system.ruby.Locked_RMW_Write.miss_latency_hist::bucket_size 1
-system.ruby.Locked_RMW_Write.miss_latency_hist::max_bucket 9
-system.ruby.Locked_RMW_Write.miss_latency_hist::samples 10
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-system.ruby.Locked_RMW_Write.miss_latency_hist::gmean 1
-system.ruby.Locked_RMW_Write.miss_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Locked_RMW_Write.miss_latency_hist::total 10
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-system.ruby.L1Cache.miss_mach_latency_hist::gmean 1
-system.ruby.L1Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 112580 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache.miss_mach_latency_hist::total 112580
-system.ruby.L2Cache.miss_mach_latency_hist::bucket_size 2
-system.ruby.L2Cache.miss_mach_latency_hist::max_bucket 19
-system.ruby.L2Cache.miss_mach_latency_hist::samples 74
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-system.ruby.L2Cache.miss_mach_latency_hist::gmean 19.000000
-system.ruby.L2Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 74 100.00% 100.00%
-system.ruby.L2Cache.miss_mach_latency_hist::total 74
-system.ruby.L3Cache.hit_mach_latency_hist::bucket_size 16
-system.ruby.L3Cache.hit_mach_latency_hist::max_bucket 159
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-system.ruby.L3Cache.hit_mach_latency_hist::gmean 107.000000
-system.ruby.L3Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L3Cache.hit_mach_latency_hist::total 11
-system.ruby.Directory.hit_mach_latency_hist::bucket_size 64
-system.ruby.Directory.hit_mach_latency_hist::max_bucket 639
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-system.ruby.Directory.hit_mach_latency_hist::mean 153.155397
-system.ruby.Directory.hit_mach_latency_hist::gmean 149.362802
-system.ruby.Directory.hit_mach_latency_hist::stdev 40.587599
-system.ruby.Directory.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 1238 80.49% 80.49% | 266 17.30% 97.79% | 14 0.91% 98.70% | 12 0.78% 99.48% | 7 0.46% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory.hit_mach_latency_hist::total 1538
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 1
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 9
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 16142
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 1
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 16142 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 16142
-system.ruby.LD.L2Cache.miss_type_mach_latency_hist::bucket_size 2
-system.ruby.LD.L2Cache.miss_type_mach_latency_hist::max_bucket 19
-system.ruby.LD.L2Cache.miss_type_mach_latency_hist::samples 7
-system.ruby.LD.L2Cache.miss_type_mach_latency_hist::mean 19
-system.ruby.LD.L2Cache.miss_type_mach_latency_hist::gmean 19.000000
-system.ruby.LD.L2Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 100.00% 100.00%
-system.ruby.LD.L2Cache.miss_type_mach_latency_hist::total 7
-system.ruby.LD.L3Cache.hit_type_mach_latency_hist::bucket_size 16
-system.ruby.LD.L3Cache.hit_type_mach_latency_hist::max_bucket 159
-system.ruby.LD.L3Cache.hit_type_mach_latency_hist::samples 11
-system.ruby.LD.L3Cache.hit_type_mach_latency_hist::mean 107
-system.ruby.LD.L3Cache.hit_type_mach_latency_hist::gmean 107.000000
-system.ruby.LD.L3Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.L3Cache.hit_type_mach_latency_hist::total 11
-system.ruby.LD.Directory.hit_type_mach_latency_hist::bucket_size 64
-system.ruby.LD.Directory.hit_type_mach_latency_hist::max_bucket 639
-system.ruby.LD.Directory.hit_type_mach_latency_hist::samples 175
-system.ruby.LD.Directory.hit_type_mach_latency_hist::mean 165.811429
-system.ruby.LD.Directory.hit_type_mach_latency_hist::gmean 161.300002
-system.ruby.LD.Directory.hit_type_mach_latency_hist::stdev 42.776536
-system.ruby.LD.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 119 68.00% 68.00% | 52 29.71% 97.71% | 2 1.14% 98.86% | 1 0.57% 99.43% | 1 0.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.Directory.hit_type_mach_latency_hist::total 175
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 1
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 9
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 10087
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 1
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 10087 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 10087
-system.ruby.ST.Directory.hit_type_mach_latency_hist::bucket_size 64
-system.ruby.ST.Directory.hit_type_mach_latency_hist::max_bucket 639
-system.ruby.ST.Directory.hit_type_mach_latency_hist::samples 325
-system.ruby.ST.Directory.hit_type_mach_latency_hist::mean 146.809231
-system.ruby.ST.Directory.hit_type_mach_latency_hist::gmean 143.903653
-system.ruby.ST.Directory.hit_type_mach_latency_hist::stdev 36.751508
-system.ruby.ST.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 289 88.92% 88.92% | 29 8.92% 97.85% | 4 1.23% 99.08% | 2 0.62% 99.69% | 0 0.00% 99.69% | 1 0.31% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.Directory.hit_type_mach_latency_hist::total 325
-system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::bucket_size 1
-system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::max_bucket 9
-system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::samples 85994
-system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::mean 1
-system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::gmean 1
-system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 85994 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::total 85994
-system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::bucket_size 2
-system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::max_bucket 19
-system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::samples 67
-system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::mean 19
-system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::gmean 19.000000
-system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 67 100.00% 100.00%
-system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::total 67
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::bucket_size 64
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::max_bucket 639
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::samples 1034
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::mean 153.045455
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::gmean 149.192268
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::stdev 40.969954
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 826 79.88% 79.88% | 185 17.89% 97.78% | 8 0.77% 98.55% | 9 0.87% 99.42% | 6 0.58% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::total 1034
-system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::bucket_size 1
-system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::max_bucket 9
-system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::samples 337
-system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::mean 1
-system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::gmean 1
-system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::total 337
-system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::bucket_size 32
-system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::max_bucket 319
-system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::samples 4
-system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::mean 143.500000
-system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::gmean 143.041358
-system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::stdev 13.403980
-system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 75.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::total 4
-system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::bucket_size 1
-system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::max_bucket 9
-system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::samples 10
-system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::mean 1
-system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::gmean 1
-system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::total 10
-system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::bucket_size 1
-system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::max_bucket 9
-system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::samples 10
-system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::mean 1
-system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::gmean 1
-system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::total 10
-system.ruby.SQC_Controller.Fetch 86 0.00% 0.00%
-system.ruby.SQC_Controller.Data 5 0.00% 0.00%
-system.ruby.SQC_Controller.I.Fetch 5 0.00% 0.00%
-system.ruby.SQC_Controller.I.Data 5 0.00% 0.00%
-system.ruby.SQC_Controller.V.Fetch 81 0.00% 0.00%
-system.ruby.TCC_Controller.RdBlk 9 0.00% 0.00%
-system.ruby.TCC_Controller.WrVicBlk 16 0.00% 0.00%
-system.ruby.TCC_Controller.Atomic 2 0.00% 0.00%
-system.ruby.TCC_Controller.AtomicDone 1 0.00% 0.00%
-system.ruby.TCC_Controller.Data 9 0.00% 0.00%
-system.ruby.TCC_Controller.PrbInv 11 0.00% 0.00%
-system.ruby.TCC_Controller.WBAck 16 0.00% 0.00%
-system.ruby.TCC_Controller.V.PrbInv 1 0.00% 0.00%
-system.ruby.TCC_Controller.I.RdBlk 7 0.00% 0.00%
-system.ruby.TCC_Controller.I.WrVicBlk 16 0.00% 0.00%
-system.ruby.TCC_Controller.I.Atomic 1 0.00% 0.00%
-system.ruby.TCC_Controller.I.PrbInv 10 0.00% 0.00%
-system.ruby.TCC_Controller.I.WBAck 16 0.00% 0.00%
-system.ruby.TCC_Controller.IV.RdBlk 2 0.00% 0.00%
-system.ruby.TCC_Controller.IV.Data 7 0.00% 0.00%
-system.ruby.TCC_Controller.A.Atomic 1 0.00% 0.00%
-system.ruby.TCC_Controller.A.AtomicDone 1 0.00% 0.00%
-system.ruby.TCC_Controller.A.Data 2 0.00% 0.00%
-system.ruby.TCP_Controller.Load | 5 50.00% 50.00% | 5 50.00% 100.00%
-system.ruby.TCP_Controller.Load::total 10
-system.ruby.TCP_Controller.StoreThrough | 8 50.00% 50.00% | 8 50.00% 100.00%
-system.ruby.TCP_Controller.StoreThrough::total 16
-system.ruby.TCP_Controller.Atomic | 1 50.00% 50.00% | 1 50.00% 100.00%
-system.ruby.TCP_Controller.Atomic::total 2
-system.ruby.TCP_Controller.Flush | 768 50.00% 50.00% | 768 50.00% 100.00%
-system.ruby.TCP_Controller.Flush::total 1536
-system.ruby.TCP_Controller.Evict | 512 50.00% 50.00% | 512 50.00% 100.00%
-system.ruby.TCP_Controller.Evict::total 1024
-system.ruby.TCP_Controller.TCC_Ack | 3 50.00% 50.00% | 3 50.00% 100.00%
-system.ruby.TCP_Controller.TCC_Ack::total 6
-system.ruby.TCP_Controller.TCC_AckWB | 8 50.00% 50.00% | 8 50.00% 100.00%
-system.ruby.TCP_Controller.TCC_AckWB::total 16
-system.ruby.TCP_Controller.I.Load | 2 50.00% 50.00% | 2 50.00% 100.00%
-system.ruby.TCP_Controller.I.Load::total 4
-system.ruby.TCP_Controller.I.StoreThrough | 8 50.00% 50.00% | 8 50.00% 100.00%
-system.ruby.TCP_Controller.I.StoreThrough::total 16
-system.ruby.TCP_Controller.I.Atomic | 1 50.00% 50.00% | 1 50.00% 100.00%
-system.ruby.TCP_Controller.I.Atomic::total 2
-system.ruby.TCP_Controller.I.Flush | 766 50.00% 50.00% | 766 50.00% 100.00%
-system.ruby.TCP_Controller.I.Flush::total 1532
-system.ruby.TCP_Controller.I.Evict | 510 50.00% 50.00% | 510 50.00% 100.00%
-system.ruby.TCP_Controller.I.Evict::total 1020
-system.ruby.TCP_Controller.I.TCC_Ack | 2 50.00% 50.00% | 2 50.00% 100.00%
-system.ruby.TCP_Controller.I.TCC_Ack::total 4
-system.ruby.TCP_Controller.I.TCC_AckWB | 8 50.00% 50.00% | 8 50.00% 100.00%
-system.ruby.TCP_Controller.I.TCC_AckWB::total 16
-system.ruby.TCP_Controller.V.Load | 3 50.00% 50.00% | 3 50.00% 100.00%
-system.ruby.TCP_Controller.V.Load::total 6
-system.ruby.TCP_Controller.V.Flush | 2 50.00% 50.00% | 2 50.00% 100.00%
-system.ruby.TCP_Controller.V.Flush::total 4
-system.ruby.TCP_Controller.V.Evict | 2 50.00% 50.00% | 2 50.00% 100.00%
-system.ruby.TCP_Controller.V.Evict::total 4
-system.ruby.TCP_Controller.A.TCC_Ack | 1 50.00% 50.00% | 1 50.00% 100.00%
-system.ruby.TCP_Controller.A.TCC_Ack::total 2
-
----------- End Simulation Statistics ----------
+++ /dev/null
-#
-# Copyright (c) 2015 Advanced Micro Devices, Inc.
-# All rights reserved.
-#
-# For use for simulation and test purposes only
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#
-# 1. Redistributions of source code must retain the above copyright notice,
-# this list of conditions and the following disclaimer.
-#
-# 2. Redistributions in binary form must reproduce the above copyright notice,
-# this list of conditions and the following disclaimer in the documentation
-# and/or other materials provided with the distribution.
-#
-# 3. Neither the name of the copyright holder nor the names of its contributors
-# may be used to endorse or promote products derived from this software
-# without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-# POSSIBILITY OF SUCH DAMAGE.
-#
-# Author: Brad Beckmann
-#
-
-from __future__ import print_function
-
-executable = binpath('gpu-hello')
-kernel_path = os.path.dirname(executable)
-kernel_files = glob.glob(os.path.join(kernel_path, '*.asm'))
-if kernel_files:
- print("Using GPU kernel code file(s)", ",".join(kernel_files))
-else:
- fatal("Can't locate kernel code (.asm) in " + kernel_path)
-
-driver = ClDriver(filename="hsa", codefile=kernel_files)
-root.system.cpu[2].cl_driver = driver
-root.system.cpu[0].workload = Process(cmd = 'gpu-hello',
- executable = binpath('gpu-hello'),
- drivers = [driver])
-
+++ /dev/null
-# Copyright (c) 2006-2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-m5.util.addToPath('../configs/common')
-from cpu2000 import eon_cook
-
-workload = eon_cook(isa, opsys, 'mdred')
-root.system.cpu[0].workload = workload.makeProcess()
+++ /dev/null
-# Copyright (c) 2006-2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-MemTest.max_loads=1e5
-MemTest.progress_interval=1e4
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=atomic
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.slave[2]
-icache_port=system.membus.slave[1]
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.membus.slave[4]
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.membus.slave[3]
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=Process
-cmd=vortex lendian.raw
-cwd=build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/vortex
-gid=100
-input=cin
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:134217727:0:0:0:0
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
+++ /dev/null
-Redirecting stdout to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Apr 3 2017 17:55:48
-gem5 started Apr 3 2017 17:56:13
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54215
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/50.vortex/arm/linux/simple-atomic
-
-Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 48960022500 because exiting with last active thread context
+++ /dev/null
- CREATE Db Header and Db Primal ...
- NEW DB [ 3] Created.
-
-VORTEX INPUT PARAMETERS::
- MESSAGE FileName: smred.msg
- OUTPUT FileName: smred.out
- DISK CACHE FileName: NULL
- PART DB FileName: parts.db
- DRAW DB FileName: draw.db
- PERSON DB FileName: emp.db
- PERSONS Data FileName: ./input/persons.250
- PARTS Count : 100
- OUTER Loops : 1
- INNER Loops : 1
- LOOKUP Parts : 25
- DELETE Parts : 10
- STUFF Parts : 10
- DEPTH Traverse: 5
- % DECREASE Parts : 0
- % INCREASE LookUps : 0
- % INCREASE Deletes : 0
- % INCREASE Stuffs : 0
- FREEZE_PACKETS : 1
- ALLOC_CHUNKS : 10000
- EXTEND_CHUNKS : 5000
- DELETE Draw objects : True
- DELETE Part objects : False
- QUE_BUG : 1000
- VOID_BOUNDARY : 67108864
- VOID_RESERVE : 1048576
-
- COMMIT_DBS : False
-
-
-
- BMT TEST :: files...
- EdbName := PartLib
- EdbFileName := parts.db
- DrwName := DrawLib
- DrwFileName := draw.db
- EmpName := PersonLib
- EmpFileName := emp.db
-
- Swap to DiskCache := False
- Freeze the cache := True
-
-
- BMT TEST :: parms...
- DeBug modulo := 1000
- Create Parts count:= 100
- Outer Loops := 1
- Inner Loops := 1
- Look Ups := 25
- Delete Parts := 10
- Stuff Parts := 10
- Traverse Limit := 5
- Delete Draws := True
- Delete Parts := False
- Delete ALL Parts := after every <mod 0>Outer Loop
-
- INITIALIZE LIBRARY ::
-
- INITIALIZE SCHEMA ::
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 4] Created.
- PartLibCreate:: Db[ 4]; VpartsDir= 1
-
- Part Count= 1
-
- Initialize the Class maps
- LIST HEADS loaded ... DbListHead_Class = 207
- DbListNode_Class = 206
-
-...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
-
-
-...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
-
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 5] Created.
- DrawLibCreate:: Db[ 5]; VpartsDir= 1
-
- Initialize the Class maps of this schema.
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 6] Created.
-
- ***NOTE*** Persons Library Extended!
-
- Create <131072> Persons.
- ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
-
- LAST Person Read::
- ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
-
- BUILD <Query0> for <Part2> class::
-
- if (link[1].length >= 5) ::
-
- Build Query2 for <Address> class::
-
- if (State == CA || State == T*)
-
- Build Query1 for <Person> class::
-
- if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
-
- BUILD <Query3> for <DrawObj> class::
-
- if (Id >= 3000
- && (Id >= 3000 && Id <= 3001)
- && Id >= 3002)
-
- BUILD <Query4> for <NamedDrawObj> class::
-
- if (Nam == Pre*
- || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
- || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
- && Id <= 7)
- SEED := 1008; Swap = False; RgnEntries = 135
-
- OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
-
- Create 100 New Parts
- Create Part 1. Token[ 4: 2].
-
- < 100> Parts Created. CurrentId= 100
-
- Connect each instantiated Part TO 3 unique Parts
- Connect Part 1. Token[ 4: 2]
- Connect Part 25. Token[ 4: 26] FromList= 26.
- Connect Part 12. Token[ 4: 13] FromList= 13.
- Connect Part 59. Token[ 4: 60] FromList= 60.
-
- SET <DrawObjs> entries::
- 1. [ 5: 5] := <1 >; @[: 6]
- Iteration count = 100
-
- SET <NamedDrawObjs> entries::
- 1. [ 5: 39] := <14 >;
- Iteration count = 12
-
- SET <LibRectangles> entries::
- 1. [ 5: 23] := <8 >; @[: 24]
- Iteration count = 12
-
- LIST <DbRectangles> entries::
- 1. [ 5: 23]
- Iteration count = 12
-
- SET <PersonNames > entries::
- Iteration count = 250
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 100
- < 100> Part images' Committed.
- < 0> are Named.
- < 50> Point images' Committed.
- < 81> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. TestObj Committed.
- < 0> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
- < 0> CartesianPoint images' Committed.
-
- BEGIN Inner Loop Sequence::.
-
- INNER LOOP [ 1: 1] :
-
- LOOK UP 25 Random Parts and Export each Part.
-
- LookUp for 26 parts; Asserts = 8
- <Part2 > Asserts = 2; NULL Asserts = 3.
- <DrawObj > Asserts = 0; NULL Asserts = 5.
- <NamedObj > Asserts = 0; NULL Asserts = 0.
- <Person > Asserts = 0; NULL Asserts = 5.
- <TestObj > Asserts = 60; NULL Asserts = 0.
-
- DELETE 10 Random Parts.
-
- PartDelete :: Token[ 4: 91].
- PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
- DisConnect link [ 0]:= 50; PartToken[ 51: 51].
- DisConnect link [ 1]:= 17; PartToken[ 18: 18].
- DisConnect link [ 2]:= 72; PartToken[ 73: 73].
- DeleteFromList:: Vchunk[ 4: 91]. (* 1)
- DisConnect FromList[ 0]:= 56; Token[ 57: 57].
- Vlists[ 89] := 100;
-
- Delete for 11 parts;
-
- Traverse Count= 0
-
- TRAVERSE PartId[ 6] and all Connections to 5 Levels
- SEED In Traverse Part [ 4: 65] @ Level = 4.
-
- Traverse Count= 357
- Traverse Asserts = 5. True Tests = 1
- < 5> DrawObj objects DELETED.
- < 2> are Named.
- < 2> Point objects DELETED.
-
- CREATE 10 Additional Parts
-
- Create 10 New Parts
- Create Part 101. Token[ 4: 102].
-
- < 10> Parts Created. CurrentId= 110
-
- Connect each instantiated Part TO 3 unique Parts
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 110
- < 81> Part images' Committed.
- < 0> are Named.
- < 38> Point images' Committed.
- < 31> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Committed.
- < 15> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
- < 16> CartesianPoint images' Committed.
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Deleted.
- < 15> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
- < 16> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
-
- END INNER LOOP [ 1: 1].
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- < 0> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- < 0> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
- STATUS= -201
-V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.048960
-sim_ticks 48960022500
-final_tick 48960022500
-sim_freq 1000000000000
-host_inst_rate 739512
-host_op_rate 945733
-host_tick_rate 510575162
-host_mem_usage 279300
-host_seconds 95.89
-sim_insts 70913204
-sim_ops 90688159
-system.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.physmem.pwrStateResidencyTicks::UNDEFINED 48960022500
-system.physmem.bytes_read::cpu.inst 312580364
-system.physmem.bytes_read::cpu.data 106573345
-system.physmem.bytes_read::total 419153709
-system.physmem.bytes_inst_read::cpu.inst 312580364
-system.physmem.bytes_inst_read::total 312580364
-system.physmem.bytes_written::cpu.data 78660211
-system.physmem.bytes_written::total 78660211
-system.physmem.num_reads::cpu.inst 78145091
-system.physmem.num_reads::cpu.data 22919730
-system.physmem.num_reads::total 101064821
-system.physmem.num_writes::cpu.data 19865820
-system.physmem.num_writes::total 19865820
-system.physmem.bw_read::cpu.inst 6384399925
-system.physmem.bw_read::cpu.data 2176742157
-system.physmem.bw_read::total 8561142083
-system.physmem.bw_inst_read::cpu.inst 6384399925
-system.physmem.bw_inst_read::total 6384399925
-system.physmem.bw_write::cpu.data 1606621218
-system.physmem.bw_write::total 1606621218
-system.physmem.bw_total::cpu.inst 6384399925
-system.physmem.bw_total::cpu.data 3783363376
-system.physmem.bw_total::total 10167763301
-system.pwrStateResidencyTicks::UNDEFINED 48960022500
-system.cpu_clk_domain.clock 500
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
-system.cpu.dstage2_mmu.stage2_tlb.hits 0
-system.cpu.dstage2_mmu.stage2_tlb.misses 0
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500
-system.cpu.dtb.walker.walks 0
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0
-system.cpu.dtb.walker.walkRequestOrigin::total 0
-system.cpu.dtb.inst_hits 0
-system.cpu.dtb.inst_misses 0
-system.cpu.dtb.read_hits 0
-system.cpu.dtb.read_misses 0
-system.cpu.dtb.write_hits 0
-system.cpu.dtb.write_misses 0
-system.cpu.dtb.flush_tlb 0
-system.cpu.dtb.flush_tlb_mva 0
-system.cpu.dtb.flush_tlb_mva_asid 0
-system.cpu.dtb.flush_tlb_asid 0
-system.cpu.dtb.flush_entries 0
-system.cpu.dtb.align_faults 0
-system.cpu.dtb.prefetch_faults 0
-system.cpu.dtb.domain_faults 0
-system.cpu.dtb.perms_faults 0
-system.cpu.dtb.read_accesses 0
-system.cpu.dtb.write_accesses 0
-system.cpu.dtb.inst_accesses 0
-system.cpu.dtb.hits 0
-system.cpu.dtb.misses 0
-system.cpu.dtb.accesses 0
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
-system.cpu.istage2_mmu.stage2_tlb.hits 0
-system.cpu.istage2_mmu.stage2_tlb.misses 0
-system.cpu.istage2_mmu.stage2_tlb.accesses 0
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500
-system.cpu.itb.walker.walks 0
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0
-system.cpu.itb.walker.walkRequestOrigin::total 0
-system.cpu.itb.inst_hits 0
-system.cpu.itb.inst_misses 0
-system.cpu.itb.read_hits 0
-system.cpu.itb.read_misses 0
-system.cpu.itb.write_hits 0
-system.cpu.itb.write_misses 0
-system.cpu.itb.flush_tlb 0
-system.cpu.itb.flush_tlb_mva 0
-system.cpu.itb.flush_tlb_mva_asid 0
-system.cpu.itb.flush_tlb_asid 0
-system.cpu.itb.flush_entries 0
-system.cpu.itb.align_faults 0
-system.cpu.itb.prefetch_faults 0
-system.cpu.itb.domain_faults 0
-system.cpu.itb.perms_faults 0
-system.cpu.itb.read_accesses 0
-system.cpu.itb.write_accesses 0
-system.cpu.itb.inst_accesses 0
-system.cpu.itb.hits 0
-system.cpu.itb.misses 0
-system.cpu.itb.accesses 0
-system.cpu.workload.numSyscalls 1946
-system.cpu.pwrStateResidencyTicks::ON 48960022500
-system.cpu.numCycles 97920046
-system.cpu.numWorkItemsStarted 0
-system.cpu.numWorkItemsCompleted 0
-system.cpu.committedInsts 70913204
-system.cpu.committedOps 90688159
-system.cpu.num_int_alu_accesses 81528528
-system.cpu.num_fp_alu_accesses 56
-system.cpu.num_func_calls 3311620
-system.cpu.num_conditional_control_insts 9253630
-system.cpu.num_int_insts 81528528
-system.cpu.num_fp_insts 56
-system.cpu.num_int_register_reads 141479271
-system.cpu.num_int_register_writes 53916335
-system.cpu.num_fp_register_reads 36
-system.cpu.num_fp_register_writes 20
-system.cpu.num_cc_register_reads 266608097
-system.cpu.num_cc_register_writes 36877111
-system.cpu.num_mem_refs 43422001
-system.cpu.num_load_insts 22866262
-system.cpu.num_store_insts 20555739
-system.cpu.num_idle_cycles 0
-system.cpu.num_busy_cycles 97920046
-system.cpu.not_idle_fraction 1
-system.cpu.idle_fraction 0
-system.cpu.Branches 13741468
-system.cpu.op_class::No_OpClass 0 0.00% 0.00%
-system.cpu.op_class::IntAlu 47187979 52.03% 52.03%
-system.cpu.op_class::IntMult 80119 0.09% 52.12%
-system.cpu.op_class::IntDiv 0 0.00% 52.12%
-system.cpu.op_class::FloatAdd 0 0.00% 52.12%
-system.cpu.op_class::FloatCmp 0 0.00% 52.12%
-system.cpu.op_class::FloatCvt 0 0.00% 52.12%
-system.cpu.op_class::FloatMult 0 0.00% 52.12%
-system.cpu.op_class::FloatMultAcc 0 0.00% 52.12%
-system.cpu.op_class::FloatDiv 0 0.00% 52.12%
-system.cpu.op_class::FloatMisc 0 0.00% 52.12%
-system.cpu.op_class::FloatSqrt 0 0.00% 52.12%
-system.cpu.op_class::SimdAdd 0 0.00% 52.12%
-system.cpu.op_class::SimdAddAcc 0 0.00% 52.12%
-system.cpu.op_class::SimdAlu 0 0.00% 52.12%
-system.cpu.op_class::SimdCmp 0 0.00% 52.12%
-system.cpu.op_class::SimdCvt 0 0.00% 52.12%
-system.cpu.op_class::SimdMisc 0 0.00% 52.12%
-system.cpu.op_class::SimdMult 0 0.00% 52.12%
-system.cpu.op_class::SimdMultAcc 0 0.00% 52.12%
-system.cpu.op_class::SimdShift 0 0.00% 52.12%
-system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12%
-system.cpu.op_class::SimdSqrt 0 0.00% 52.12%
-system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12%
-system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12%
-system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12%
-system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12%
-system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12%
-system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12%
-system.cpu.op_class::SimdFloatMult 0 0.00% 52.12%
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12%
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12%
-system.cpu.op_class::MemRead 22866242 25.21% 77.33%
-system.cpu.op_class::MemWrite 20555707 22.67% 100.00%
-system.cpu.op_class::FloatMemRead 20 0.00% 100.00%
-system.cpu.op_class::FloatMemWrite 32 0.00% 100.00%
-system.cpu.op_class::IprAccess 0 0.00% 100.00%
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
-system.cpu.op_class::total 90690106
-system.membus.snoop_filter.tot_requests 0
-system.membus.snoop_filter.hit_single_requests 0
-system.membus.snoop_filter.hit_multi_requests 0
-system.membus.snoop_filter.tot_snoops 0
-system.membus.snoop_filter.hit_single_snoops 0
-system.membus.snoop_filter.hit_multi_snoops 0
-system.membus.pwrStateResidencyTicks::UNDEFINED 48960022500
-system.membus.trans_dist::ReadReq 100925158
-system.membus.trans_dist::ReadResp 100941077
-system.membus.trans_dist::WriteReq 19849901
-system.membus.trans_dist::WriteResp 19849901
-system.membus.trans_dist::SoftPFReq 123744
-system.membus.trans_dist::SoftPFResp 123744
-system.membus.trans_dist::LoadLockedReq 15919
-system.membus.trans_dist::StoreCondReq 15919
-system.membus.trans_dist::StoreCondResp 15919
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290182
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100
-system.membus.pkt_count::total 241861282
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580364
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556
-system.membus.pkt_size::total 497813920
-system.membus.snoops 0
-system.membus.snoopTraffic 0
-system.membus.snoop_fanout::samples 120930641
-system.membus.snoop_fanout::mean 0
-system.membus.snoop_fanout::stdev 0
-system.membus.snoop_fanout::underflows 0 0.00% 0.00%
-system.membus.snoop_fanout::0 120930641 100.00% 100.00%
-system.membus.snoop_fanout::1 0 0.00% 100.00%
-system.membus.snoop_fanout::overflows 0 0.00% 100.00%
-system.membus.snoop_fanout::min_value 0
-system.membus.snoop_fanout::max_value 0
-system.membus.snoop_fanout::total 120930641
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tag_latency=2
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-tag_latency=2
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tag_latency=2
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=131072
-tag_latency=2
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=20
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tag_latency=20
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=20
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=2097152
-tag_latency=20
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=Process
-cmd=vortex lendian.raw
-cwd=build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/vortex
-gid=100
-input=cin
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:134217727:0:0:0:0
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
+++ /dev/null
-Redirecting stdout to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Apr 3 2017 17:55:48
-gem5 started Apr 3 2017 17:56:13
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54226
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/50.vortex/arm/linux/simple-timing
-
-Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 128204299500 because exiting with last active thread context
+++ /dev/null
- CREATE Db Header and Db Primal ...
- NEW DB [ 3] Created.
-
-VORTEX INPUT PARAMETERS::
- MESSAGE FileName: smred.msg
- OUTPUT FileName: smred.out
- DISK CACHE FileName: NULL
- PART DB FileName: parts.db
- DRAW DB FileName: draw.db
- PERSON DB FileName: emp.db
- PERSONS Data FileName: ./input/persons.250
- PARTS Count : 100
- OUTER Loops : 1
- INNER Loops : 1
- LOOKUP Parts : 25
- DELETE Parts : 10
- STUFF Parts : 10
- DEPTH Traverse: 5
- % DECREASE Parts : 0
- % INCREASE LookUps : 0
- % INCREASE Deletes : 0
- % INCREASE Stuffs : 0
- FREEZE_PACKETS : 1
- ALLOC_CHUNKS : 10000
- EXTEND_CHUNKS : 5000
- DELETE Draw objects : True
- DELETE Part objects : False
- QUE_BUG : 1000
- VOID_BOUNDARY : 67108864
- VOID_RESERVE : 1048576
-
- COMMIT_DBS : False
-
-
-
- BMT TEST :: files...
- EdbName := PartLib
- EdbFileName := parts.db
- DrwName := DrawLib
- DrwFileName := draw.db
- EmpName := PersonLib
- EmpFileName := emp.db
-
- Swap to DiskCache := False
- Freeze the cache := True
-
-
- BMT TEST :: parms...
- DeBug modulo := 1000
- Create Parts count:= 100
- Outer Loops := 1
- Inner Loops := 1
- Look Ups := 25
- Delete Parts := 10
- Stuff Parts := 10
- Traverse Limit := 5
- Delete Draws := True
- Delete Parts := False
- Delete ALL Parts := after every <mod 0>Outer Loop
-
- INITIALIZE LIBRARY ::
-
- INITIALIZE SCHEMA ::
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 4] Created.
- PartLibCreate:: Db[ 4]; VpartsDir= 1
-
- Part Count= 1
-
- Initialize the Class maps
- LIST HEADS loaded ... DbListHead_Class = 207
- DbListNode_Class = 206
-
-...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
-
-
-...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
-
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 5] Created.
- DrawLibCreate:: Db[ 5]; VpartsDir= 1
-
- Initialize the Class maps of this schema.
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 6] Created.
-
- ***NOTE*** Persons Library Extended!
-
- Create <131072> Persons.
- ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
-
- LAST Person Read::
- ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
-
- BUILD <Query0> for <Part2> class::
-
- if (link[1].length >= 5) ::
-
- Build Query2 for <Address> class::
-
- if (State == CA || State == T*)
-
- Build Query1 for <Person> class::
-
- if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
-
- BUILD <Query3> for <DrawObj> class::
-
- if (Id >= 3000
- && (Id >= 3000 && Id <= 3001)
- && Id >= 3002)
-
- BUILD <Query4> for <NamedDrawObj> class::
-
- if (Nam == Pre*
- || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
- || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
- && Id <= 7)
- SEED := 1008; Swap = False; RgnEntries = 135
-
- OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
-
- Create 100 New Parts
- Create Part 1. Token[ 4: 2].
-
- < 100> Parts Created. CurrentId= 100
-
- Connect each instantiated Part TO 3 unique Parts
- Connect Part 1. Token[ 4: 2]
- Connect Part 25. Token[ 4: 26] FromList= 26.
- Connect Part 12. Token[ 4: 13] FromList= 13.
- Connect Part 59. Token[ 4: 60] FromList= 60.
-
- SET <DrawObjs> entries::
- 1. [ 5: 5] := <1 >; @[: 6]
- Iteration count = 100
-
- SET <NamedDrawObjs> entries::
- 1. [ 5: 39] := <14 >;
- Iteration count = 12
-
- SET <LibRectangles> entries::
- 1. [ 5: 23] := <8 >; @[: 24]
- Iteration count = 12
-
- LIST <DbRectangles> entries::
- 1. [ 5: 23]
- Iteration count = 12
-
- SET <PersonNames > entries::
- Iteration count = 250
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 100
- < 100> Part images' Committed.
- < 0> are Named.
- < 50> Point images' Committed.
- < 81> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. TestObj Committed.
- < 0> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
- < 0> CartesianPoint images' Committed.
-
- BEGIN Inner Loop Sequence::.
-
- INNER LOOP [ 1: 1] :
-
- LOOK UP 25 Random Parts and Export each Part.
-
- LookUp for 26 parts; Asserts = 8
- <Part2 > Asserts = 2; NULL Asserts = 3.
- <DrawObj > Asserts = 0; NULL Asserts = 5.
- <NamedObj > Asserts = 0; NULL Asserts = 0.
- <Person > Asserts = 0; NULL Asserts = 5.
- <TestObj > Asserts = 60; NULL Asserts = 0.
-
- DELETE 10 Random Parts.
-
- PartDelete :: Token[ 4: 91].
- PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
- DisConnect link [ 0]:= 50; PartToken[ 51: 51].
- DisConnect link [ 1]:= 17; PartToken[ 18: 18].
- DisConnect link [ 2]:= 72; PartToken[ 73: 73].
- DeleteFromList:: Vchunk[ 4: 91]. (* 1)
- DisConnect FromList[ 0]:= 56; Token[ 57: 57].
- Vlists[ 89] := 100;
-
- Delete for 11 parts;
-
- Traverse Count= 0
-
- TRAVERSE PartId[ 6] and all Connections to 5 Levels
- SEED In Traverse Part [ 4: 65] @ Level = 4.
-
- Traverse Count= 357
- Traverse Asserts = 5. True Tests = 1
- < 5> DrawObj objects DELETED.
- < 2> are Named.
- < 2> Point objects DELETED.
-
- CREATE 10 Additional Parts
-
- Create 10 New Parts
- Create Part 101. Token[ 4: 102].
-
- < 10> Parts Created. CurrentId= 110
-
- Connect each instantiated Part TO 3 unique Parts
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 110
- < 81> Part images' Committed.
- < 0> are Named.
- < 38> Point images' Committed.
- < 31> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Committed.
- < 15> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
- < 16> CartesianPoint images' Committed.
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Deleted.
- < 15> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
- < 16> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
-
- END INNER LOOP [ 1: 1].
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- < 0> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- < 0> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
- STATUS= -201
-V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.128204
-sim_ticks 128204299500
-final_tick 128204299500
-sim_freq 1000000000000
-host_inst_rate 533817
-host_op_rate 681535
-host_tick_rate 972489774
-host_mem_usage 290320
-host_seconds 131.83
-sim_insts 70373651
-sim_ops 89847385
-system.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.physmem.pwrStateResidencyTicks::UNDEFINED 128204299500
-system.physmem.bytes_read::cpu.inst 233344
-system.physmem.bytes_read::cpu.data 7939200
-system.physmem.bytes_read::total 8172544
-system.physmem.bytes_inst_read::cpu.inst 233344
-system.physmem.bytes_inst_read::total 233344
-system.physmem.bytes_written::writebacks 5534528
-system.physmem.bytes_written::total 5534528
-system.physmem.num_reads::cpu.inst 3646
-system.physmem.num_reads::cpu.data 124050
-system.physmem.num_reads::total 127696
-system.physmem.num_writes::writebacks 86477
-system.physmem.num_writes::total 86477
-system.physmem.bw_read::cpu.inst 1820095
-system.physmem.bw_read::cpu.data 61926160
-system.physmem.bw_read::total 63746255
-system.physmem.bw_inst_read::cpu.inst 1820095
-system.physmem.bw_inst_read::total 1820095
-system.physmem.bw_write::writebacks 43169597
-system.physmem.bw_write::total 43169597
-system.physmem.bw_total::writebacks 43169597
-system.physmem.bw_total::cpu.inst 1820095
-system.physmem.bw_total::cpu.data 61926160
-system.physmem.bw_total::total 106915853
-system.pwrStateResidencyTicks::UNDEFINED 128204299500
-system.cpu_clk_domain.clock 500
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
-system.cpu.dstage2_mmu.stage2_tlb.hits 0
-system.cpu.dstage2_mmu.stage2_tlb.misses 0
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500
-system.cpu.dtb.walker.walks 0
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0
-system.cpu.dtb.walker.walkRequestOrigin::total 0
-system.cpu.dtb.inst_hits 0
-system.cpu.dtb.inst_misses 0
-system.cpu.dtb.read_hits 0
-system.cpu.dtb.read_misses 0
-system.cpu.dtb.write_hits 0
-system.cpu.dtb.write_misses 0
-system.cpu.dtb.flush_tlb 0
-system.cpu.dtb.flush_tlb_mva 0
-system.cpu.dtb.flush_tlb_mva_asid 0
-system.cpu.dtb.flush_tlb_asid 0
-system.cpu.dtb.flush_entries 0
-system.cpu.dtb.align_faults 0
-system.cpu.dtb.prefetch_faults 0
-system.cpu.dtb.domain_faults 0
-system.cpu.dtb.perms_faults 0
-system.cpu.dtb.read_accesses 0
-system.cpu.dtb.write_accesses 0
-system.cpu.dtb.inst_accesses 0
-system.cpu.dtb.hits 0
-system.cpu.dtb.misses 0
-system.cpu.dtb.accesses 0
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
-system.cpu.istage2_mmu.stage2_tlb.hits 0
-system.cpu.istage2_mmu.stage2_tlb.misses 0
-system.cpu.istage2_mmu.stage2_tlb.accesses 0
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500
-system.cpu.itb.walker.walks 0
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0
-system.cpu.itb.walker.walkRequestOrigin::total 0
-system.cpu.itb.inst_hits 0
-system.cpu.itb.inst_misses 0
-system.cpu.itb.read_hits 0
-system.cpu.itb.read_misses 0
-system.cpu.itb.write_hits 0
-system.cpu.itb.write_misses 0
-system.cpu.itb.flush_tlb 0
-system.cpu.itb.flush_tlb_mva 0
-system.cpu.itb.flush_tlb_mva_asid 0
-system.cpu.itb.flush_tlb_asid 0
-system.cpu.itb.flush_entries 0
-system.cpu.itb.align_faults 0
-system.cpu.itb.prefetch_faults 0
-system.cpu.itb.domain_faults 0
-system.cpu.itb.perms_faults 0
-system.cpu.itb.read_accesses 0
-system.cpu.itb.write_accesses 0
-system.cpu.itb.inst_accesses 0
-system.cpu.itb.hits 0
-system.cpu.itb.misses 0
-system.cpu.itb.accesses 0
-system.cpu.workload.numSyscalls 1946
-system.cpu.pwrStateResidencyTicks::ON 128204299500
-system.cpu.numCycles 256408599
-system.cpu.numWorkItemsStarted 0
-system.cpu.numWorkItemsCompleted 0
-system.cpu.committedInsts 70373651
-system.cpu.committedOps 89847385
-system.cpu.num_int_alu_accesses 81528528
-system.cpu.num_fp_alu_accesses 56
-system.cpu.num_func_calls 3311620
-system.cpu.num_conditional_control_insts 9253630
-system.cpu.num_int_insts 81528528
-system.cpu.num_fp_insts 56
-system.cpu.num_int_register_reads 141328435
-system.cpu.num_int_register_writes 53916335
-system.cpu.num_fp_register_reads 36
-system.cpu.num_fp_register_writes 20
-system.cpu.num_cc_register_reads 334802072
-system.cpu.num_cc_register_writes 36877111
-system.cpu.num_mem_refs 43422001
-system.cpu.num_load_insts 22866262
-system.cpu.num_store_insts 20555739
-system.cpu.num_idle_cycles 0
-system.cpu.num_busy_cycles 256408599
-system.cpu.not_idle_fraction 1
-system.cpu.idle_fraction 0
-system.cpu.Branches 13741468
-system.cpu.op_class::No_OpClass 0 0.00% 0.00%
-system.cpu.op_class::IntAlu 47187979 52.03% 52.03%
-system.cpu.op_class::IntMult 80119 0.09% 52.12%
-system.cpu.op_class::IntDiv 0 0.00% 52.12%
-system.cpu.op_class::FloatAdd 0 0.00% 52.12%
-system.cpu.op_class::FloatCmp 0 0.00% 52.12%
-system.cpu.op_class::FloatCvt 0 0.00% 52.12%
-system.cpu.op_class::FloatMult 0 0.00% 52.12%
-system.cpu.op_class::FloatMultAcc 0 0.00% 52.12%
-system.cpu.op_class::FloatDiv 0 0.00% 52.12%
-system.cpu.op_class::FloatMisc 0 0.00% 52.12%
-system.cpu.op_class::FloatSqrt 0 0.00% 52.12%
-system.cpu.op_class::SimdAdd 0 0.00% 52.12%
-system.cpu.op_class::SimdAddAcc 0 0.00% 52.12%
-system.cpu.op_class::SimdAlu 0 0.00% 52.12%
-system.cpu.op_class::SimdCmp 0 0.00% 52.12%
-system.cpu.op_class::SimdCvt 0 0.00% 52.12%
-system.cpu.op_class::SimdMisc 0 0.00% 52.12%
-system.cpu.op_class::SimdMult 0 0.00% 52.12%
-system.cpu.op_class::SimdMultAcc 0 0.00% 52.12%
-system.cpu.op_class::SimdShift 0 0.00% 52.12%
-system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12%
-system.cpu.op_class::SimdSqrt 0 0.00% 52.12%
-system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12%
-system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12%
-system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12%
-system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12%
-system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12%
-system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12%
-system.cpu.op_class::SimdFloatMult 0 0.00% 52.12%
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12%
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12%
-system.cpu.op_class::MemRead 22866242 25.21% 77.33%
-system.cpu.op_class::MemWrite 20555707 22.67% 100.00%
-system.cpu.op_class::FloatMemRead 20 0.00% 100.00%
-system.cpu.op_class::FloatMemWrite 32 0.00% 100.00%
-system.cpu.op_class::IprAccess 0 0.00% 100.00%
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
-system.cpu.op_class::total 90690106
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500
-system.cpu.dcache.tags.replacements 155902
-system.cpu.dcache.tags.tagsinuse 4075.864194
-system.cpu.dcache.tags.total_refs 42601590
-system.cpu.dcache.tags.sampled_refs 159998
-system.cpu.dcache.tags.avg_refs 266.263266
-system.cpu.dcache.tags.warmup_cycle 1116590500
-system.cpu.dcache.tags.occ_blocks::cpu.data 4075.864194
-system.cpu.dcache.tags.occ_percent::cpu.data 0.995084
-system.cpu.dcache.tags.occ_percent::total 0.995084
-system.cpu.dcache.tags.occ_task_id_blocks::1024 4096
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 45
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 774
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 3277
-system.cpu.dcache.tags.occ_task_id_percent::1024 1
-system.cpu.dcache.tags.tag_accesses 85731098
-system.cpu.dcache.tags.data_accesses 85731098
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 128204299500
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-system.cpu.dcache.ReadReq_hits::total 22743326
-system.cpu.dcache.WriteReq_hits::cpu.data 19742869
-system.cpu.dcache.WriteReq_hits::total 19742869
-system.cpu.dcache.SoftPFReq_hits::cpu.data 83557
-system.cpu.dcache.SoftPFReq_hits::total 83557
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919
-system.cpu.dcache.LoadLockedReq_hits::total 15919
-system.cpu.dcache.StoreCondReq_hits::cpu.data 15919
-system.cpu.dcache.StoreCondReq_hits::total 15919
-system.cpu.dcache.demand_hits::cpu.data 42486195
-system.cpu.dcache.demand_hits::total 42486195
-system.cpu.dcache.overall_hits::cpu.data 42569752
-system.cpu.dcache.overall_hits::total 42569752
-system.cpu.dcache.ReadReq_misses::cpu.data 36741
-system.cpu.dcache.ReadReq_misses::total 36741
-system.cpu.dcache.WriteReq_misses::cpu.data 107032
-system.cpu.dcache.WriteReq_misses::total 107032
-system.cpu.dcache.SoftPFReq_misses::cpu.data 40187
-system.cpu.dcache.SoftPFReq_misses::total 40187
-system.cpu.dcache.demand_misses::cpu.data 143773
-system.cpu.dcache.demand_misses::total 143773
-system.cpu.dcache.overall_misses::cpu.data 183960
-system.cpu.dcache.overall_misses::total 183960
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 594992500
-system.cpu.dcache.ReadReq_miss_latency::total 594992500
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 6509368500
-system.cpu.dcache.WriteReq_miss_latency::total 6509368500
-system.cpu.dcache.demand_miss_latency::cpu.data 7104361000
-system.cpu.dcache.demand_miss_latency::total 7104361000
-system.cpu.dcache.overall_miss_latency::cpu.data 7104361000
-system.cpu.dcache.overall_miss_latency::total 7104361000
-system.cpu.dcache.ReadReq_accesses::cpu.data 22780067
-system.cpu.dcache.ReadReq_accesses::total 22780067
-system.cpu.dcache.WriteReq_accesses::cpu.data 19849901
-system.cpu.dcache.WriteReq_accesses::total 19849901
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744
-system.cpu.dcache.SoftPFReq_accesses::total 123744
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919
-system.cpu.dcache.LoadLockedReq_accesses::total 15919
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919
-system.cpu.dcache.StoreCondReq_accesses::total 15919
-system.cpu.dcache.demand_accesses::cpu.data 42629968
-system.cpu.dcache.demand_accesses::total 42629968
-system.cpu.dcache.overall_accesses::cpu.data 42753712
-system.cpu.dcache.overall_accesses::total 42753712
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001613
-system.cpu.dcache.ReadReq_miss_rate::total 0.001613
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392
-system.cpu.dcache.WriteReq_miss_rate::total 0.005392
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324759
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.324759
-system.cpu.dcache.demand_miss_rate::cpu.data 0.003373
-system.cpu.dcache.demand_miss_rate::total 0.003373
-system.cpu.dcache.overall_miss_rate::cpu.data 0.004303
-system.cpu.dcache.overall_miss_rate::total 0.004303
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-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2291072
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18427136
-system.cpu.toL2Bus.pkt_size::total 20718208
-system.cpu.toL2Bus.snoops 96062
-system.cpu.toL2Bus.snoopTraffic 5534528
-system.cpu.toL2Bus.snoop_fanout::samples 274968
-system.cpu.toL2Bus.snoop_fanout::mean 0.025367
-system.cpu.toL2Bus.snoop_fanout::stdev 0.157929
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
-system.cpu.toL2Bus.snoop_fanout::0 268023 97.47% 97.47%
-system.cpu.toL2Bus.snoop_fanout::1 6915 2.51% 99.99%
-system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00%
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
-system.cpu.toL2Bus.snoop_fanout::min_value 0
-system.cpu.toL2Bus.snoop_fanout::max_value 2
-system.cpu.toL2Bus.snoop_fanout::total 274968
-system.cpu.toL2Bus.reqLayer0.occupancy 320665000
-system.cpu.toL2Bus.reqLayer0.utilization 0.3
-system.cpu.toL2Bus.respLayer0.occupancy 28362000
-system.cpu.toL2Bus.respLayer0.utilization 0.0
-system.cpu.toL2Bus.respLayer1.occupancy 239997000
-system.cpu.toL2Bus.respLayer1.utilization 0.2
-system.membus.snoop_filter.tot_requests 220672
-system.membus.snoop_filter.hit_single_requests 93041
-system.membus.snoop_filter.hit_multi_requests 0
-system.membus.snoop_filter.tot_snoops 0
-system.membus.snoop_filter.hit_single_snoops 0
-system.membus.snoop_filter.hit_multi_snoops 0
-system.membus.pwrStateResidencyTicks::UNDEFINED 128204299500
-system.membus.trans_dist::ReadResp 25376
-system.membus.trans_dist::WritebackDirty 86477
-system.membus.trans_dist::CleanEvict 6466
-system.membus.trans_dist::ReadExReq 102320
-system.membus.trans_dist::ReadExResp 102320
-system.membus.trans_dist::ReadSharedReq 25376
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 348335
-system.membus.pkt_count::total 348335
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13707072
-system.membus.pkt_size::total 13707072
-system.membus.snoops 0
-system.membus.snoopTraffic 0
-system.membus.snoop_fanout::samples 127704
-system.membus.snoop_fanout::mean 0
-system.membus.snoop_fanout::stdev 0
-system.membus.snoop_fanout::underflows 0 0.00% 0.00%
-system.membus.snoop_fanout::0 127704 100.00% 100.00%
-system.membus.snoop_fanout::1 0 0.00% 100.00%
-system.membus.snoop_fanout::overflows 0 0.00% 100.00%
-system.membus.snoop_fanout::min_value 0
-system.membus.snoop_fanout::max_value 0
-system.membus.snoop_fanout::total 127704
-system.membus.reqLayer0.occupancy 569386372
-system.membus.reqLayer0.utilization 0.4
-system.membus.respLayer1.occupancy 638480000
-system.membus.respLayer1.utilization 0.5
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=atomic
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dtb interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.slave[2]
-icache_port=system.membus.slave[1]
-
-[system.cpu.dtb]
-type=SparcTLB
-eventq_index=0
-size=64
-
-[system.cpu.interrupts]
-type=SparcInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=SparcISA
-eventq_index=0
-
-[system.cpu.itb]
-type=SparcTLB
-eventq_index=0
-size=64
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=Process
-cmd=vortex bendian.raw
-cwd=build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/sparc/linux/vortex
-gid=100
-input=cin
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:134217727:0:0:0:0
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Entering event queue @ 0. Starting simulation...
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-info: Increasing stack size by one page.
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
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-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
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-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
+++ /dev/null
-Redirecting stdout to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Apr 3 2017 18:41:19
-gem5 started Apr 3 2017 18:43:58
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 66518
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/50.vortex/sparc/linux/simple-atomic
-
-Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 68148677000 because exiting with last active thread context
+++ /dev/null
-
- SYSTEM TYPE...
- __ZTC__ := False
- __UNIX__ := True
- __RISC__ := True
- SPEC_CPU2000_LP64 := False
- __MAC__ := False
- __BCC__ := False
- __BORLANDC__ := False
- __GUI__ := False
- __WTC__ := False
- __HP__ := False
-
- CODE OPTIONS...
- __MACROIZE_HM__ := True
- __MACROIZE_MEM__ := True
- ENV01 := True
- USE_HPP_STYPE_HDRS := False
- USE_H_STYPE_HDRS := False
-
- CODE INCLUSION PARAMETERS...
- INCLUDE_ALL_CODE := False
- INCLUDE_DELETE_CODE := True
- __SWAP_GRP_POS__ := True
- __INCLUDE_MTRX__ := False
- __BAD_CODE__ := False
- API_INCLUDE := False
- BE_CAREFUL := False
- OLDWAY := False
- NOTUSED := False
-
- SYSTEM PARAMETERS...
- EXT_ENUM := 999999999L
- CHUNK_CONSTANT := 55555555
- CORE_CONSTANT := 55555555
- CORE_LIMIT := 20971520
- CorePage_Size := 384000
- ALIGN_BYTES := True
- CORE_BLOCK_ALIGN := 8
- FAR_MEM := False
-
- MEMORY MANAGEMENT PARAMETERS...
- SYSTEM_ALLOC := True
- SYSTEM_FREESTORE := True
- __NO_DISKCACHE__ := False
- __FREEZE_VCHUNKS__ := True
- __FREEZE_GRP_PACKETS__ := True
- __MINIMIZE_TREE_CACHE__:= True
-
- SYSTEM STD PARAMETERS...
- __STDOUT__ := False
- NULL := 0
- LPTR := False
- False_Status := 1
- True_Status := 0
- LARGE := True
- TWOBYTE_BOOL := False
- __NOSTR__ := False
-
- MEMORY VALIDATION PARAMETERS...
- CORE_CRC_CHECK := False
- VALIDATE_MEM_CHUNKS := False
-
- SYSTEM DEBUG OPTIONS...
- DEBUG := False
- MCSTAT := False
- TRACKBACK := False
- FLUSH_FILES := False
- DEBUG_CORE0 := False
- DEBUG_RISC := False
- __TREE_BUG__ := False
- __TRACK_FILE_READS__ := False
- PAGE_SPACE := False
- LEAVE_NO_TRACE := True
- NULL_TRACE_STRS := False
-
- TIME PARAMETERS...
- CLOCK_IS_LONG := False
- __DISPLAY_TIME__ := False
- __TREE_TIME__ := False
- __DISPLAY_ERRORS__ := False
-
- API MACROS...
- __BMT01__ := True
- OPTIMIZE := True
-
- END OF DEFINES.
-
-
-
- ... IMPLODE MEMORY ...
-
- SWAP to DiskCache := False
-
- FREEZE_GRP_PACKETS:= True
-
- QueBug := 1000
-
- sizeof(boolean) = 4
- sizeof(sizetype) = 4
- sizeof(chunkstruc) = 32
-
- sizeof(shorttype ) = 2
- sizeof(idtype ) = 2
- sizeof(sizetype ) = 4
- sizeof(indextype ) = 4
- sizeof(numtype ) = 4
- sizeof(handletype) = 4
- sizeof(tokentype ) = 8
-
- sizeof(short ) = 2
- sizeof(int ) = 4
-
- sizeof(lt64 ) = 4
- sizeof(farlongtype) = 4
- sizeof(long ) = 4
- sizeof(longaddr ) = 4
-
- sizeof(float ) = 4
- sizeof(double ) = 8
-
- sizeof(addrtype ) = 4
- sizeof(char * ) = 4
- ALLOC CORE_1 :: 8
- BHOOLE NATH
-
- OPEN File ./input/bendian.rnv
- *Status = 0
- DB HDR restored from FileVbn[ 0]
- DB BlkDirOffset : @ 2030c0
- DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
- DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
- DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
- DB Handle Chunk's StackPtr = 20797
-
- DB[ 1] LOADED; Handles= 20797
- KERNEL in CORE[ 1] Restored @ 1b4750
-
- OPEN File ./input/bendian.wnv
- *Status = 0
- DB HDR restored from FileVbn[ 0]
- DB BlkDirOffset : @ 21c40
- DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
- DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
- DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
- DB Handle Chunk's StackPtr = 17
-
- DB[ 2] LOADED; Handles= 17
- VORTEx_Status == -8 || fffffff8
-
- BE HERE NOW !!!
-
-
-
- ... VORTEx ON LINE ...
-
-
- ... END OF SESSION ...
+++ /dev/null
- CREATE Db Header and Db Primal ...
- NEW DB [ 3] Created.
-
-VORTEX INPUT PARAMETERS::
- MESSAGE FileName: smred.msg
- OUTPUT FileName: smred.out
- DISK CACHE FileName: NULL
- PART DB FileName: parts.db
- DRAW DB FileName: draw.db
- PERSON DB FileName: emp.db
- PERSONS Data FileName: ./input/persons.250
- PARTS Count : 100
- OUTER Loops : 1
- INNER Loops : 1
- LOOKUP Parts : 25
- DELETE Parts : 10
- STUFF Parts : 10
- DEPTH Traverse: 5
- % DECREASE Parts : 0
- % INCREASE LookUps : 0
- % INCREASE Deletes : 0
- % INCREASE Stuffs : 0
- FREEZE_PACKETS : 1
- ALLOC_CHUNKS : 10000
- EXTEND_CHUNKS : 5000
- DELETE Draw objects : True
- DELETE Part objects : False
- QUE_BUG : 1000
- VOID_BOUNDARY : 67108864
- VOID_RESERVE : 1048576
-
- COMMIT_DBS : False
-
-
-
- BMT TEST :: files...
- EdbName := PartLib
- EdbFileName := parts.db
- DrwName := DrawLib
- DrwFileName := draw.db
- EmpName := PersonLib
- EmpFileName := emp.db
-
- Swap to DiskCache := False
- Freeze the cache := True
-
-
- BMT TEST :: parms...
- DeBug modulo := 1000
- Create Parts count:= 100
- Outer Loops := 1
- Inner Loops := 1
- Look Ups := 25
- Delete Parts := 10
- Stuff Parts := 10
- Traverse Limit := 5
- Delete Draws := True
- Delete Parts := False
- Delete ALL Parts := after every <mod 0>Outer Loop
-
- INITIALIZE LIBRARY ::
-
- INITIALIZE SCHEMA ::
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 4] Created.
- PartLibCreate:: Db[ 4]; VpartsDir= 1
-
- Part Count= 1
-
- Initialize the Class maps
- LIST HEADS loaded ... DbListHead_Class = 207
- DbListNode_Class = 206
-
-...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
-
-
-...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
-
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 5] Created.
- DrawLibCreate:: Db[ 5]; VpartsDir= 1
-
- Initialize the Class maps of this schema.
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 6] Created.
-
- ***NOTE*** Persons Library Extended!
-
- Create <131072> Persons.
- ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
-
- LAST Person Read::
- ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
-
- BUILD <Query0> for <Part2> class::
-
- if (link[1].length >= 5) ::
-
- Build Query2 for <Address> class::
-
- if (State == CA || State == T*)
-
- Build Query1 for <Person> class::
-
- if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
-
- BUILD <Query3> for <DrawObj> class::
-
- if (Id >= 3000
- && (Id >= 3000 && Id <= 3001)
- && Id >= 3002)
-
- BUILD <Query4> for <NamedDrawObj> class::
-
- if (Nam == Pre*
- || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
- || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
- && Id <= 7)
- SEED := 1008; Swap = False; RgnEntries = 135
-
- OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
-
- Create 100 New Parts
- Create Part 1. Token[ 4: 2].
-
- < 100> Parts Created. CurrentId= 100
-
- Connect each instantiated Part TO 3 unique Parts
- Connect Part 1. Token[ 4: 2]
- Connect Part 25. Token[ 4: 26] FromList= 26.
- Connect Part 12. Token[ 4: 13] FromList= 13.
- Connect Part 59. Token[ 4: 60] FromList= 60.
-
- SET <DrawObjs> entries::
- 1. [ 5: 5] := <1 >; @[: 6]
- Iteration count = 100
-
- SET <NamedDrawObjs> entries::
- 1. [ 5: 39] := <14 >;
- Iteration count = 12
-
- SET <LibRectangles> entries::
- 1. [ 5: 23] := <8 >; @[: 24]
- Iteration count = 12
-
- LIST <DbRectangles> entries::
- 1. [ 5: 23]
- Iteration count = 12
-
- SET <PersonNames > entries::
- Iteration count = 250
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 100
- < 100> Part images' Committed.
- < 0> are Named.
- < 50> Point images' Committed.
- < 81> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. TestObj Committed.
- < 0> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
- < 0> CartesianPoint images' Committed.
-
- BEGIN Inner Loop Sequence::.
-
- INNER LOOP [ 1: 1] :
-
- LOOK UP 25 Random Parts and Export each Part.
-
- LookUp for 26 parts; Asserts = 8
- <Part2 > Asserts = 2; NULL Asserts = 3.
- <DrawObj > Asserts = 0; NULL Asserts = 5.
- <NamedObj > Asserts = 0; NULL Asserts = 0.
- <Person > Asserts = 0; NULL Asserts = 5.
- <TestObj > Asserts = 60; NULL Asserts = 0.
-
- DELETE 10 Random Parts.
-
- PartDelete :: Token[ 4: 91].
- PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
- DisConnect link [ 0]:= 50; PartToken[ 51: 51].
- DisConnect link [ 1]:= 17; PartToken[ 18: 18].
- DisConnect link [ 2]:= 72; PartToken[ 73: 73].
- DeleteFromList:: Vchunk[ 4: 91]. (* 1)
- DisConnect FromList[ 0]:= 56; Token[ 57: 57].
- Vlists[ 89] := 100;
-
- Delete for 11 parts;
-
- Traverse Count= 0
-
- TRAVERSE PartId[ 6] and all Connections to 5 Levels
- SEED In Traverse Part [ 4: 65] @ Level = 4.
-
- Traverse Count= 357
- Traverse Asserts = 5. True Tests = 1
- < 5> DrawObj objects DELETED.
- < 2> are Named.
- < 2> Point objects DELETED.
-
- CREATE 10 Additional Parts
-
- Create 10 New Parts
- Create Part 101. Token[ 4: 102].
-
- < 10> Parts Created. CurrentId= 110
-
- Connect each instantiated Part TO 3 unique Parts
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 110
- < 81> Part images' Committed.
- < 0> are Named.
- < 38> Point images' Committed.
- < 31> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Committed.
- < 15> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
- < 16> CartesianPoint images' Committed.
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Deleted.
- < 15> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
- < 16> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
-
- END INNER LOOP [ 1: 1].
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- < 0> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- < 0> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
- STATUS= -201
-V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.068149
-sim_ticks 68148677000
-final_tick 68148677000
-sim_freq 1000000000000
-host_inst_rate 1228497
-host_op_rate 1244404
-host_tick_rate 622924579
-host_mem_usage 262248
-host_seconds 109.40
-sim_insts 134398959
-sim_ops 136139187
-system.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.physmem.pwrStateResidencyTicks::UNDEFINED 68148677000
-system.physmem.bytes_read::cpu.inst 538214320
-system.physmem.bytes_read::cpu.data 147559360
-system.physmem.bytes_read::total 685773680
-system.physmem.bytes_inst_read::cpu.inst 538214320
-system.physmem.bytes_inst_read::total 538214320
-system.physmem.bytes_written::cpu.data 89882950
-system.physmem.bytes_written::total 89882950
-system.physmem.num_reads::cpu.inst 134553580
-system.physmem.num_reads::cpu.data 37231300
-system.physmem.num_reads::total 171784880
-system.physmem.num_writes::cpu.data 20864304
-system.physmem.num_writes::total 20864304
-system.physmem.num_other::cpu.data 15916
-system.physmem.num_other::total 15916
-system.physmem.bw_read::cpu.inst 7897648842
-system.physmem.bw_read::cpu.data 2165256414
-system.physmem.bw_read::total 10062905256
-system.physmem.bw_inst_read::cpu.inst 7897648842
-system.physmem.bw_inst_read::total 7897648842
-system.physmem.bw_write::cpu.data 1318924357
-system.physmem.bw_write::total 1318924357
-system.physmem.bw_total::cpu.inst 7897648842
-system.physmem.bw_total::cpu.data 3484180771
-system.physmem.bw_total::total 11381829614
-system.pwrStateResidencyTicks::UNDEFINED 68148677000
-system.cpu_clk_domain.clock 500
-system.cpu.workload.numSyscalls 1946
-system.cpu.pwrStateResidencyTicks::ON 68148677000
-system.cpu.numCycles 136297355
-system.cpu.numWorkItemsStarted 0
-system.cpu.numWorkItemsCompleted 0
-system.cpu.committedInsts 134398959
-system.cpu.committedOps 136139187
-system.cpu.num_int_alu_accesses 115187757
-system.cpu.num_fp_alu_accesses 2326976
-system.cpu.num_func_calls 1709332
-system.cpu.num_conditional_control_insts 8898968
-system.cpu.num_int_insts 115187757
-system.cpu.num_fp_insts 2326976
-system.cpu.num_int_register_reads 263032419
-system.cpu.num_int_register_writes 113147731
-system.cpu.num_fp_register_reads 4725606
-system.cpu.num_fp_register_writes 1150968
-system.cpu.num_mem_refs 58160261
-system.cpu.num_load_insts 37275864
-system.cpu.num_store_insts 20884397
-system.cpu.num_idle_cycles 0
-system.cpu.num_busy_cycles 136297355
-system.cpu.not_idle_fraction 1
-system.cpu.idle_fraction 0
-system.cpu.Branches 12719094
-system.cpu.op_class::No_OpClass 11445042 8.40% 8.40%
-system.cpu.op_class::IntAlu 66342067 48.68% 57.07%
-system.cpu.op_class::IntMult 0 0.00% 57.07%
-system.cpu.op_class::IntDiv 0 0.00% 57.07%
-system.cpu.op_class::FloatAdd 325584 0.24% 57.31%
-system.cpu.op_class::FloatCmp 0 0.00% 57.31%
-system.cpu.op_class::FloatCvt 0 0.00% 57.31%
-system.cpu.op_class::FloatMult 0 0.00% 57.31%
-system.cpu.op_class::FloatMultAcc 0 0.00% 57.31%
-system.cpu.op_class::FloatDiv 0 0.00% 57.31%
-system.cpu.op_class::FloatMisc 0 0.00% 57.31%
-system.cpu.op_class::FloatSqrt 0 0.00% 57.31%
-system.cpu.op_class::SimdAdd 0 0.00% 57.31%
-system.cpu.op_class::SimdAddAcc 0 0.00% 57.31%
-system.cpu.op_class::SimdAlu 0 0.00% 57.31%
-system.cpu.op_class::SimdCmp 0 0.00% 57.31%
-system.cpu.op_class::SimdCvt 0 0.00% 57.31%
-system.cpu.op_class::SimdMisc 0 0.00% 57.31%
-system.cpu.op_class::SimdMult 0 0.00% 57.31%
-system.cpu.op_class::SimdMultAcc 0 0.00% 57.31%
-system.cpu.op_class::SimdShift 0 0.00% 57.31%
-system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31%
-system.cpu.op_class::SimdSqrt 0 0.00% 57.31%
-system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31%
-system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31%
-system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31%
-system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31%
-system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31%
-system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31%
-system.cpu.op_class::SimdFloatMult 0 0.00% 57.31%
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31%
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31%
-system.cpu.op_class::MemRead 37046611 27.18% 84.49%
-system.cpu.op_class::MemWrite 19133112 14.04% 98.53%
-system.cpu.op_class::FloatMemRead 250107 0.18% 98.72%
-system.cpu.op_class::FloatMemWrite 1751285 1.28% 100.00%
-system.cpu.op_class::IprAccess 0 0.00% 100.00%
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
-system.cpu.op_class::total 136293808
-system.membus.snoop_filter.tot_requests 0
-system.membus.snoop_filter.hit_single_requests 0
-system.membus.snoop_filter.hit_multi_requests 0
-system.membus.snoop_filter.tot_snoops 0
-system.membus.snoop_filter.hit_single_snoops 0
-system.membus.snoop_filter.hit_multi_snoops 0
-system.membus.pwrStateResidencyTicks::UNDEFINED 68148677000
-system.membus.trans_dist::ReadReq 171784880
-system.membus.trans_dist::ReadResp 171784880
-system.membus.trans_dist::WriteReq 20864304
-system.membus.trans_dist::WriteResp 20864304
-system.membus.trans_dist::SwapReq 15916
-system.membus.trans_dist::SwapResp 15916
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 269107160
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 116223040
-system.membus.pkt_count::total 385330200
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214320
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 237569638
-system.membus.pkt_size::total 775783958
-system.membus.snoops 0
-system.membus.snoopTraffic 0
-system.membus.snoop_fanout::samples 192665100
-system.membus.snoop_fanout::mean 0
-system.membus.snoop_fanout::stdev 0
-system.membus.snoop_fanout::underflows 0 0.00% 0.00%
-system.membus.snoop_fanout::0 192665100 100.00% 100.00%
-system.membus.snoop_fanout::1 0 0.00% 100.00%
-system.membus.snoop_fanout::overflows 0 0.00% 100.00%
-system.membus.snoop_fanout::min_value 0
-system.membus.snoop_fanout::max_value 0
-system.membus.snoop_fanout::total 192665100
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-syscallRetryLatency=10000
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tag_latency=2
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-tag_latency=2
-
-[system.cpu.dtb]
-type=SparcTLB
-eventq_index=0
-size=64
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=2
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tag_latency=2
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=2
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=131072
-tag_latency=2
-
-[system.cpu.interrupts]
-type=SparcInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=SparcISA
-eventq_index=0
-
-[system.cpu.itb]
-type=SparcTLB
-eventq_index=0
-size=64
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-data_latency=20
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tag_latency=20
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-data_latency=20
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=2097152
-tag_latency=20
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=Process
-cmd=vortex bendian.raw
-cwd=build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/sparc/linux/vortex
-gid=100
-input=cin
-kvmInSE=false
-maxStackSize=67108864
-output=cout
-pgid=100
-pid=100
-ppid=0
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:134217727:0:0:0:0
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-info: Entering event queue @ 0. Starting simulation...
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-info: Increasing stack size by one page.
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall time(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
-warn: ignoring syscall times(...)
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+++ /dev/null
-Redirecting stdout to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Apr 3 2017 18:41:19
-gem5 started Apr 3 2017 18:41:55
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 65144
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/50.vortex/sparc/linux/simple-timing
-
-Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 203260902500 because exiting with last active thread context
+++ /dev/null
-
- SYSTEM TYPE...
- __ZTC__ := False
- __UNIX__ := True
- __RISC__ := True
- SPEC_CPU2000_LP64 := False
- __MAC__ := False
- __BCC__ := False
- __BORLANDC__ := False
- __GUI__ := False
- __WTC__ := False
- __HP__ := False
-
- CODE OPTIONS...
- __MACROIZE_HM__ := True
- __MACROIZE_MEM__ := True
- ENV01 := True
- USE_HPP_STYPE_HDRS := False
- USE_H_STYPE_HDRS := False
-
- CODE INCLUSION PARAMETERS...
- INCLUDE_ALL_CODE := False
- INCLUDE_DELETE_CODE := True
- __SWAP_GRP_POS__ := True
- __INCLUDE_MTRX__ := False
- __BAD_CODE__ := False
- API_INCLUDE := False
- BE_CAREFUL := False
- OLDWAY := False
- NOTUSED := False
-
- SYSTEM PARAMETERS...
- EXT_ENUM := 999999999L
- CHUNK_CONSTANT := 55555555
- CORE_CONSTANT := 55555555
- CORE_LIMIT := 20971520
- CorePage_Size := 384000
- ALIGN_BYTES := True
- CORE_BLOCK_ALIGN := 8
- FAR_MEM := False
-
- MEMORY MANAGEMENT PARAMETERS...
- SYSTEM_ALLOC := True
- SYSTEM_FREESTORE := True
- __NO_DISKCACHE__ := False
- __FREEZE_VCHUNKS__ := True
- __FREEZE_GRP_PACKETS__ := True
- __MINIMIZE_TREE_CACHE__:= True
-
- SYSTEM STD PARAMETERS...
- __STDOUT__ := False
- NULL := 0
- LPTR := False
- False_Status := 1
- True_Status := 0
- LARGE := True
- TWOBYTE_BOOL := False
- __NOSTR__ := False
-
- MEMORY VALIDATION PARAMETERS...
- CORE_CRC_CHECK := False
- VALIDATE_MEM_CHUNKS := False
-
- SYSTEM DEBUG OPTIONS...
- DEBUG := False
- MCSTAT := False
- TRACKBACK := False
- FLUSH_FILES := False
- DEBUG_CORE0 := False
- DEBUG_RISC := False
- __TREE_BUG__ := False
- __TRACK_FILE_READS__ := False
- PAGE_SPACE := False
- LEAVE_NO_TRACE := True
- NULL_TRACE_STRS := False
-
- TIME PARAMETERS...
- CLOCK_IS_LONG := False
- __DISPLAY_TIME__ := False
- __TREE_TIME__ := False
- __DISPLAY_ERRORS__ := False
-
- API MACROS...
- __BMT01__ := True
- OPTIMIZE := True
-
- END OF DEFINES.
-
-
-
- ... IMPLODE MEMORY ...
-
- SWAP to DiskCache := False
-
- FREEZE_GRP_PACKETS:= True
-
- QueBug := 1000
-
- sizeof(boolean) = 4
- sizeof(sizetype) = 4
- sizeof(chunkstruc) = 32
-
- sizeof(shorttype ) = 2
- sizeof(idtype ) = 2
- sizeof(sizetype ) = 4
- sizeof(indextype ) = 4
- sizeof(numtype ) = 4
- sizeof(handletype) = 4
- sizeof(tokentype ) = 8
-
- sizeof(short ) = 2
- sizeof(int ) = 4
-
- sizeof(lt64 ) = 4
- sizeof(farlongtype) = 4
- sizeof(long ) = 4
- sizeof(longaddr ) = 4
-
- sizeof(float ) = 4
- sizeof(double ) = 8
-
- sizeof(addrtype ) = 4
- sizeof(char * ) = 4
- ALLOC CORE_1 :: 8
- BHOOLE NATH
-
- OPEN File ./input/bendian.rnv
- *Status = 0
- DB HDR restored from FileVbn[ 0]
- DB BlkDirOffset : @ 2030c0
- DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
- DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
- DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
- DB Handle Chunk's StackPtr = 20797
-
- DB[ 1] LOADED; Handles= 20797
- KERNEL in CORE[ 1] Restored @ 1b4750
-
- OPEN File ./input/bendian.wnv
- *Status = 0
- DB HDR restored from FileVbn[ 0]
- DB BlkDirOffset : @ 21c40
- DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
- DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
- DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
- DB Handle Chunk's StackPtr = 17
-
- DB[ 2] LOADED; Handles= 17
- VORTEx_Status == -8 || fffffff8
-
- BE HERE NOW !!!
-
-
-
- ... VORTEx ON LINE ...
-
-
- ... END OF SESSION ...
+++ /dev/null
- CREATE Db Header and Db Primal ...
- NEW DB [ 3] Created.
-
-VORTEX INPUT PARAMETERS::
- MESSAGE FileName: smred.msg
- OUTPUT FileName: smred.out
- DISK CACHE FileName: NULL
- PART DB FileName: parts.db
- DRAW DB FileName: draw.db
- PERSON DB FileName: emp.db
- PERSONS Data FileName: ./input/persons.250
- PARTS Count : 100
- OUTER Loops : 1
- INNER Loops : 1
- LOOKUP Parts : 25
- DELETE Parts : 10
- STUFF Parts : 10
- DEPTH Traverse: 5
- % DECREASE Parts : 0
- % INCREASE LookUps : 0
- % INCREASE Deletes : 0
- % INCREASE Stuffs : 0
- FREEZE_PACKETS : 1
- ALLOC_CHUNKS : 10000
- EXTEND_CHUNKS : 5000
- DELETE Draw objects : True
- DELETE Part objects : False
- QUE_BUG : 1000
- VOID_BOUNDARY : 67108864
- VOID_RESERVE : 1048576
-
- COMMIT_DBS : False
-
-
-
- BMT TEST :: files...
- EdbName := PartLib
- EdbFileName := parts.db
- DrwName := DrawLib
- DrwFileName := draw.db
- EmpName := PersonLib
- EmpFileName := emp.db
-
- Swap to DiskCache := False
- Freeze the cache := True
-
-
- BMT TEST :: parms...
- DeBug modulo := 1000
- Create Parts count:= 100
- Outer Loops := 1
- Inner Loops := 1
- Look Ups := 25
- Delete Parts := 10
- Stuff Parts := 10
- Traverse Limit := 5
- Delete Draws := True
- Delete Parts := False
- Delete ALL Parts := after every <mod 0>Outer Loop
-
- INITIALIZE LIBRARY ::
-
- INITIALIZE SCHEMA ::
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 4] Created.
- PartLibCreate:: Db[ 4]; VpartsDir= 1
-
- Part Count= 1
-
- Initialize the Class maps
- LIST HEADS loaded ... DbListHead_Class = 207
- DbListNode_Class = 206
-
-...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
-
-
-...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
-
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 5] Created.
- DrawLibCreate:: Db[ 5]; VpartsDir= 1
-
- Initialize the Class maps of this schema.
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 6] Created.
-
- ***NOTE*** Persons Library Extended!
-
- Create <131072> Persons.
- ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
-
- LAST Person Read::
- ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
-
- BUILD <Query0> for <Part2> class::
-
- if (link[1].length >= 5) ::
-
- Build Query2 for <Address> class::
-
- if (State == CA || State == T*)
-
- Build Query1 for <Person> class::
-
- if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
-
- BUILD <Query3> for <DrawObj> class::
-
- if (Id >= 3000
- && (Id >= 3000 && Id <= 3001)
- && Id >= 3002)
-
- BUILD <Query4> for <NamedDrawObj> class::
-
- if (Nam == Pre*
- || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
- || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
- && Id <= 7)
- SEED := 1008; Swap = False; RgnEntries = 135
-
- OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
-
- Create 100 New Parts
- Create Part 1. Token[ 4: 2].
-
- < 100> Parts Created. CurrentId= 100
-
- Connect each instantiated Part TO 3 unique Parts
- Connect Part 1. Token[ 4: 2]
- Connect Part 25. Token[ 4: 26] FromList= 26.
- Connect Part 12. Token[ 4: 13] FromList= 13.
- Connect Part 59. Token[ 4: 60] FromList= 60.
-
- SET <DrawObjs> entries::
- 1. [ 5: 5] := <1 >; @[: 6]
- Iteration count = 100
-
- SET <NamedDrawObjs> entries::
- 1. [ 5: 39] := <14 >;
- Iteration count = 12
-
- SET <LibRectangles> entries::
- 1. [ 5: 23] := <8 >; @[: 24]
- Iteration count = 12
-
- LIST <DbRectangles> entries::
- 1. [ 5: 23]
- Iteration count = 12
-
- SET <PersonNames > entries::
- Iteration count = 250
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 100
- < 100> Part images' Committed.
- < 0> are Named.
- < 50> Point images' Committed.
- < 81> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. TestObj Committed.
- < 0> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
- < 0> CartesianPoint images' Committed.
-
- BEGIN Inner Loop Sequence::.
-
- INNER LOOP [ 1: 1] :
-
- LOOK UP 25 Random Parts and Export each Part.
-
- LookUp for 26 parts; Asserts = 8
- <Part2 > Asserts = 2; NULL Asserts = 3.
- <DrawObj > Asserts = 0; NULL Asserts = 5.
- <NamedObj > Asserts = 0; NULL Asserts = 0.
- <Person > Asserts = 0; NULL Asserts = 5.
- <TestObj > Asserts = 60; NULL Asserts = 0.
-
- DELETE 10 Random Parts.
-
- PartDelete :: Token[ 4: 91].
- PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
- DisConnect link [ 0]:= 50; PartToken[ 51: 51].
- DisConnect link [ 1]:= 17; PartToken[ 18: 18].
- DisConnect link [ 2]:= 72; PartToken[ 73: 73].
- DeleteFromList:: Vchunk[ 4: 91]. (* 1)
- DisConnect FromList[ 0]:= 56; Token[ 57: 57].
- Vlists[ 89] := 100;
-
- Delete for 11 parts;
-
- Traverse Count= 0
-
- TRAVERSE PartId[ 6] and all Connections to 5 Levels
- SEED In Traverse Part [ 4: 65] @ Level = 4.
-
- Traverse Count= 357
- Traverse Asserts = 5. True Tests = 1
- < 5> DrawObj objects DELETED.
- < 2> are Named.
- < 2> Point objects DELETED.
-
- CREATE 10 Additional Parts
-
- Create 10 New Parts
- Create Part 101. Token[ 4: 102].
-
- < 10> Parts Created. CurrentId= 110
-
- Connect each instantiated Part TO 3 unique Parts
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 110
- < 81> Part images' Committed.
- < 0> are Named.
- < 38> Point images' Committed.
- < 31> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Committed.
- < 15> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
- < 16> CartesianPoint images' Committed.
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Deleted.
- < 15> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
- < 16> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
-
- END INNER LOOP [ 1: 1].
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- < 0> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- < 0> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
- STATUS= -201
-V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.203261
-sim_ticks 203260902500
-final_tick 203260902500
-sim_freq 1000000000000
-host_inst_rate 815865
-host_op_rate 826429
-host_tick_rate 1233889280
-host_mem_usage 273008
-host_seconds 164.73
-sim_insts 134398959
-sim_ops 136139187
-system.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.physmem.pwrStateResidencyTicks::UNDEFINED 203260902500
-system.physmem.bytes_read::cpu.inst 526720
-system.physmem.bytes_read::cpu.data 7845184
-system.physmem.bytes_read::total 8371904
-system.physmem.bytes_inst_read::cpu.inst 526720
-system.physmem.bytes_inst_read::total 526720
-system.physmem.bytes_written::writebacks 5476224
-system.physmem.bytes_written::total 5476224
-system.physmem.num_reads::cpu.inst 8230
-system.physmem.num_reads::cpu.data 122581
-system.physmem.num_reads::total 130811
-system.physmem.num_writes::writebacks 85566
-system.physmem.num_writes::total 85566
-system.physmem.bw_read::cpu.inst 2591349
-system.physmem.bw_read::cpu.data 38596621
-system.physmem.bw_read::total 41187970
-system.physmem.bw_inst_read::cpu.inst 2591349
-system.physmem.bw_inst_read::total 2591349
-system.physmem.bw_write::writebacks 26941846
-system.physmem.bw_write::total 26941846
-system.physmem.bw_total::writebacks 26941846
-system.physmem.bw_total::cpu.inst 2591349
-system.physmem.bw_total::cpu.data 38596621
-system.physmem.bw_total::total 68129817
-system.pwrStateResidencyTicks::UNDEFINED 203260902500
-system.cpu_clk_domain.clock 500
-system.cpu.workload.numSyscalls 1946
-system.cpu.pwrStateResidencyTicks::ON 203260902500
-system.cpu.numCycles 406521805
-system.cpu.numWorkItemsStarted 0
-system.cpu.numWorkItemsCompleted 0
-system.cpu.committedInsts 134398959
-system.cpu.committedOps 136139187
-system.cpu.num_int_alu_accesses 115187757
-system.cpu.num_fp_alu_accesses 2326976
-system.cpu.num_func_calls 1709332
-system.cpu.num_conditional_control_insts 8898968
-system.cpu.num_int_insts 115187757
-system.cpu.num_fp_insts 2326976
-system.cpu.num_int_register_reads 263032419
-system.cpu.num_int_register_writes 113147730
-system.cpu.num_fp_register_reads 4725606
-system.cpu.num_fp_register_writes 1150968
-system.cpu.num_mem_refs 58160261
-system.cpu.num_load_insts 37275864
-system.cpu.num_store_insts 20884397
-system.cpu.num_idle_cycles 0
-system.cpu.num_busy_cycles 406521805
-system.cpu.not_idle_fraction 1
-system.cpu.idle_fraction 0
-system.cpu.Branches 12719094
-system.cpu.op_class::No_OpClass 11445042 8.40% 8.40%
-system.cpu.op_class::IntAlu 66342067 48.68% 57.07%
-system.cpu.op_class::IntMult 0 0.00% 57.07%
-system.cpu.op_class::IntDiv 0 0.00% 57.07%
-system.cpu.op_class::FloatAdd 325584 0.24% 57.31%
-system.cpu.op_class::FloatCmp 0 0.00% 57.31%
-system.cpu.op_class::FloatCvt 0 0.00% 57.31%
-system.cpu.op_class::FloatMult 0 0.00% 57.31%
-system.cpu.op_class::FloatMultAcc 0 0.00% 57.31%
-system.cpu.op_class::FloatDiv 0 0.00% 57.31%
-system.cpu.op_class::FloatMisc 0 0.00% 57.31%
-system.cpu.op_class::FloatSqrt 0 0.00% 57.31%
-system.cpu.op_class::SimdAdd 0 0.00% 57.31%
-system.cpu.op_class::SimdAddAcc 0 0.00% 57.31%
-system.cpu.op_class::SimdAlu 0 0.00% 57.31%
-system.cpu.op_class::SimdCmp 0 0.00% 57.31%
-system.cpu.op_class::SimdCvt 0 0.00% 57.31%
-system.cpu.op_class::SimdMisc 0 0.00% 57.31%
-system.cpu.op_class::SimdMult 0 0.00% 57.31%
-system.cpu.op_class::SimdMultAcc 0 0.00% 57.31%
-system.cpu.op_class::SimdShift 0 0.00% 57.31%
-system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31%
-system.cpu.op_class::SimdSqrt 0 0.00% 57.31%
-system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31%
-system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31%
-system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31%
-system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31%
-system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31%
-system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31%
-system.cpu.op_class::SimdFloatMult 0 0.00% 57.31%
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31%
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31%
-system.cpu.op_class::MemRead 37046611 27.18% 84.49%
-system.cpu.op_class::MemWrite 19133112 14.04% 98.53%
-system.cpu.op_class::FloatMemRead 250107 0.18% 98.72%
-system.cpu.op_class::FloatMemWrite 1751285 1.28% 100.00%
-system.cpu.op_class::IprAccess 0 0.00% 100.00%
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
-system.cpu.op_class::total 136293808
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 203260902500
-system.cpu.dcache.tags.replacements 146583
-system.cpu.dcache.tags.tagsinuse 4087.215868
-system.cpu.dcache.tags.total_refs 57960841
-system.cpu.dcache.tags.sampled_refs 150679
-system.cpu.dcache.tags.avg_refs 384.664359
-system.cpu.dcache.tags.warmup_cycle 829975500
-system.cpu.dcache.tags.occ_blocks::cpu.data 4087.215868
-system.cpu.dcache.tags.occ_percent::cpu.data 0.997855
-system.cpu.dcache.tags.occ_percent::total 0.997855
-system.cpu.dcache.tags.occ_task_id_blocks::1024 4096
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 36
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 462
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 3598
-system.cpu.dcache.tags.occ_task_id_percent::1024 1
-system.cpu.dcache.tags.tag_accesses 116373719
-system.cpu.dcache.tags.data_accesses 116373719
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 203260902500
-system.cpu.dcache.ReadReq_hits::cpu.data 37185800
-system.cpu.dcache.ReadReq_hits::total 37185800
-system.cpu.dcache.WriteReq_hits::cpu.data 20759140
-system.cpu.dcache.WriteReq_hits::total 20759140
-system.cpu.dcache.SwapReq_hits::cpu.data 15901
-system.cpu.dcache.SwapReq_hits::total 15901
-system.cpu.dcache.demand_hits::cpu.data 57944940
-system.cpu.dcache.demand_hits::total 57944940
-system.cpu.dcache.overall_hits::cpu.data 57944940
-system.cpu.dcache.overall_hits::total 57944940
-system.cpu.dcache.ReadReq_misses::cpu.data 45500
-system.cpu.dcache.ReadReq_misses::total 45500
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-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50540.522479
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50540.522479
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50504.348848
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50504.348848
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50540.522479
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50506.342745
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50508.493170
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50540.522479
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50506.342745
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50508.493170
-system.cpu.toL2Bus.snoop_filter.tot_requests 669262
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 331559
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66
-system.cpu.toL2Bus.snoop_filter.tot_snoops 3837
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3837
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 203260902500
-system.cpu.toL2Bus.trans_dist::ReadResp 232524
-system.cpu.toL2Bus.trans_dist::WritebackDirty 209181
-system.cpu.toL2Bus.trans_dist::WritebackClean 184976
-system.cpu.toL2Bus.trans_dist::CleanEvict 37328
-system.cpu.toL2Bus.trans_dist::ReadExReq 105179
-system.cpu.toL2Bus.trans_dist::ReadExResp 105179
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 45500
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559024
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447941
-system.cpu.toL2Bus.pkt_count::total 1006965
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23808000
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17554816
-system.cpu.toL2Bus.pkt_size::total 41362816
-system.cpu.toL2Bus.snoops 99926
-system.cpu.toL2Bus.snoopTraffic 5476224
-system.cpu.toL2Bus.snoop_fanout::samples 437629
-system.cpu.toL2Bus.snoop_fanout::mean 0.008919
-system.cpu.toL2Bus.snoop_fanout::stdev 0.094016
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
-system.cpu.toL2Bus.snoop_fanout::0 433726 99.11% 99.11%
-system.cpu.toL2Bus.snoop_fanout::1 3903 0.89% 100.00%
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
-system.cpu.toL2Bus.snoop_fanout::min_value 0
-system.cpu.toL2Bus.snoop_fanout::max_value 1
-system.cpu.toL2Bus.snoop_fanout::total 437629
-system.cpu.toL2Bus.reqLayer0.occupancy 643222000
-system.cpu.toL2Bus.reqLayer0.utilization 0.3
-system.cpu.toL2Bus.respLayer0.occupancy 280536000
-system.cpu.toL2Bus.respLayer0.utilization 0.1
-system.cpu.toL2Bus.respLayer1.occupancy 226018500
-system.cpu.toL2Bus.respLayer1.utilization 0.1
-system.membus.snoop_filter.tot_requests 226995
-system.membus.snoop_filter.hit_single_requests 96184
-system.membus.snoop_filter.hit_multi_requests 0
-system.membus.snoop_filter.tot_snoops 0
-system.membus.snoop_filter.hit_single_snoops 0
-system.membus.snoop_filter.hit_multi_snoops 0
-system.membus.pwrStateResidencyTicks::UNDEFINED 203260902500
-system.membus.trans_dist::ReadResp 29500
-system.membus.trans_dist::WritebackDirty 85566
-system.membus.trans_dist::CleanEvict 10618
-system.membus.trans_dist::ReadExReq 101311
-system.membus.trans_dist::ReadExResp 101311
-system.membus.trans_dist::ReadSharedReq 29500
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 357806
-system.membus.pkt_count::total 357806
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13848128
-system.membus.pkt_size::total 13848128
-system.membus.snoops 0
-system.membus.snoopTraffic 0
-system.membus.snoop_fanout::samples 130811
-system.membus.snoop_fanout::mean 0
-system.membus.snoop_fanout::stdev 0
-system.membus.snoop_fanout::underflows 0 0.00% 0.00%
-system.membus.snoop_fanout::0 130811 100.00% 100.00%
-system.membus.snoop_fanout::1 0 0.00% 100.00%
-system.membus.snoop_fanout::overflows 0 0.00% 100.00%
-system.membus.snoop_fanout::min_value 0
-system.membus.snoop_fanout::max_value 0
-system.membus.snoop_fanout::total 130811
-system.membus.reqLayer0.occupancy 570211500
-system.membus.reqLayer0.utilization 0.3
-system.membus.respLayer1.occupancy 654055000
-system.membus.respLayer1.utilization 0.3
-
----------- End Simulation Statistics ----------
+++ /dev/null
-# Copyright (c) 2006-2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-m5.util.addToPath('../configs/common')
-from cpu2000 import vortex
-
-workload = vortex(isa, opsys, 'smred')
-root.system.cpu[0].workload = workload.makeProcess()
+++ /dev/null
-# Copyright (c) 2012 ARM Limited
-# All rights reserved.
-#
-# The license below extends only to copyright in the software and shall
-# not be construed as granting a license to any other intellectual
-# property including but not limited to intellectual property relating
-# to a hardware implementation of the functionality of the software
-# licensed hereunder. You may use the software subject to the license
-# terms below provided that you ensure that this notice is replicated
-# unmodified and in its entirety in all distributions of the software,
-# modified or unmodified, in source code or in binary form.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-maxtick = 10000000000
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
-
-[system]
-type=System
-children=clk_domain cp_cntrl0 cpu dir_cntrl0 dvfs_handler mem_ctrls ruby sqc_cntrl0 sqc_cntrl1 sys_port_proxy tcc_cntrl0 tccdir_cntrl0 tcp_cntrl0 tcp_cntrl1 tcp_cntrl2 tcp_cntrl3 tcp_cntrl4 tcp_cntrl5 tcp_cntrl6 tcp_cntrl7 voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:268435455:0:0:0:0
-memories=system.mem_ctrls
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.sys_port_proxy.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cp_cntrl0]
-type=CorePair_Controller
-children=L1D0cache L1D1cache L1Icache L2cache mandatoryQueue probeToCore requestFromCore responseFromCore responseToCore sequencer sequencer1 triggerQueue unblockFromCore
-L1D0cache=system.cp_cntrl0.L1D0cache
-L1D1cache=system.cp_cntrl0.L1D1cache
-L1Icache=system.cp_cntrl0.L1Icache
-L2cache=system.cp_cntrl0.L2cache
-buffer_size=0
-clk_domain=system.clk_domain
-cluster_id=0
-default_p_state=UNDEFINED
-eventq_index=0
-issue_latency=15
-l2_hit_latency=18
-mandatoryQueue=system.cp_cntrl0.mandatoryQueue
-number_of_TBEs=256
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-probeToCore=system.cp_cntrl0.probeToCore
-recycle_latency=10
-requestFromCore=system.cp_cntrl0.requestFromCore
-responseFromCore=system.cp_cntrl0.responseFromCore
-responseToCore=system.cp_cntrl0.responseToCore
-ruby_system=system.ruby
-send_evictions=true
-sequencer=system.cp_cntrl0.sequencer
-sequencer1=system.cp_cntrl0.sequencer1
-system=system
-transitions_per_cycle=32
-triggerQueue=system.cp_cntrl0.triggerQueue
-unblockFromCore=system.cp_cntrl0.unblockFromCore
-version=0
-
-[system.cp_cntrl0.L1D0cache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.cp_cntrl0.L1D0cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.cp_cntrl0.L1D0cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.cp_cntrl0.L1D1cache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.cp_cntrl0.L1D1cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.cp_cntrl0.L1D1cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.cp_cntrl0.L1Icache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.cp_cntrl0.L1Icache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.cp_cntrl0.L1Icache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.cp_cntrl0.L2cache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.cp_cntrl0.L2cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=512
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.cp_cntrl0.L2cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=512
-
-[system.cp_cntrl0.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.cp_cntrl0.probeToCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[3]
-
-[system.cp_cntrl0.requestFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[2]
-
-[system.cp_cntrl0.responseFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[3]
-
-[system.cp_cntrl0.responseToCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[4]
-
-[system.cp_cntrl0.sequencer]
-type=RubySequencer
-clk_domain=system.clk_domain
-coreid=0
-dcache=system.cp_cntrl0.L1D0cache
-dcache_hit_latency=2
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.cp_cntrl0.L1Icache
-icache_hit_latency=2
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=true
-version=0
-slave=system.cpu.cpuInstDataPort[0]
-
-[system.cp_cntrl0.sequencer1]
-type=RubySequencer
-clk_domain=system.clk_domain
-coreid=1
-dcache=system.cp_cntrl0.L1D1cache
-dcache_hit_latency=2
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.cp_cntrl0.L1Icache
-icache_hit_latency=2
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=true
-version=1
-slave=system.cpu.cpuInstDataPort[1]
-
-[system.cp_cntrl0.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.cp_cntrl0.unblockFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[4]
-
-[system.cpu]
-type=RubyTester
-check_flush=false
-checks_to_complete=100
-clk_domain=system.clk_domain
-deadlock_threshold=50000
-default_p_state=UNDEFINED
-eventq_index=0
-num_cpus=12
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-system=system
-wakeup_frequency=10
-cpuDataPort=system.tcp_cntrl0.coalescer.slave[0] system.tcp_cntrl1.coalescer.slave[0] system.tcp_cntrl2.coalescer.slave[0] system.tcp_cntrl3.coalescer.slave[0] system.tcp_cntrl4.coalescer.slave[0] system.tcp_cntrl5.coalescer.slave[0] system.tcp_cntrl6.coalescer.slave[0] system.tcp_cntrl7.coalescer.slave[0]
-cpuInstDataPort=system.cp_cntrl0.sequencer.slave[0] system.cp_cntrl0.sequencer1.slave[0]
-cpuInstPort=system.sqc_cntrl0.sequencer.slave[0] system.sqc_cntrl1.sequencer.slave[0]
-
-[system.dir_cntrl0]
-type=Directory_Controller
-children=L3CacheMemory L3triggerQueue directory probeToCore requestFromCores responseFromCores responseFromMemory responseToCore triggerQueue unblockFromCores
-CPUonly=false
-L3CacheMemory=system.dir_cntrl0.L3CacheMemory
-L3triggerQueue=system.dir_cntrl0.L3triggerQueue
-TCC_select_num_bits=0
-buffer_size=0
-clk_domain=system.clk_domain
-cluster_id=0
-default_p_state=UNDEFINED
-directory=system.dir_cntrl0.directory
-eventq_index=0
-l3_hit_latency=15
-noTCCdir=false
-number_of_TBEs=20480
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-probeToCore=system.dir_cntrl0.probeToCore
-recycle_latency=10
-requestFromCores=system.dir_cntrl0.requestFromCores
-responseFromCores=system.dir_cntrl0.responseFromCores
-responseFromMemory=system.dir_cntrl0.responseFromMemory
-responseToCore=system.dir_cntrl0.responseToCore
-response_latency=30
-ruby_system=system.ruby
-system=system
-to_memory_controller_latency=1
-transitions_per_cycle=32
-triggerQueue=system.dir_cntrl0.triggerQueue
-unblockFromCores=system.dir_cntrl0.unblockFromCores
-useL3OnWT=false
-version=0
-memory=system.mem_ctrls.port
-
-[system.dir_cntrl0.L3CacheMemory]
-type=RubyCache
-children=replacement_policy
-assoc=8
-block_size=0
-dataAccessLatency=20
-dataArrayBanks=256.0
-eventq_index=0
-is_icache=false
-replacement_policy=system.dir_cntrl0.L3CacheMemory.replacement_policy
-resourceStalls=true
-ruby_system=system.ruby
-size=1024
-start_index_bit=6
-tagAccessLatency=15
-tagArrayBanks=256.0
-
-[system.dir_cntrl0.L3CacheMemory.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=8
-block_size=64
-eventq_index=0
-size=1024
-
-[system.dir_cntrl0.L3triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.dir_cntrl0.directory]
-type=RubyDirectoryMemory
-eventq_index=0
-numa_high_bit=5
-size=536870912
-version=0
-
-[system.dir_cntrl0.probeToCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[0]
-
-[system.dir_cntrl0.requestFromCores]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[0]
-
-[system.dir_cntrl0.responseFromCores]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[1]
-
-[system.dir_cntrl0.responseFromMemory]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.dir_cntrl0.responseToCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[1]
-
-[system.dir_cntrl0.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.dir_cntrl0.unblockFromCores]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[2]
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000
-
-[system.mem_ctrls]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-page_policy=open_adaptive
-power_model=Null
-range=0:268435455:5:19:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10
-static_frontend_latency=10
-tBURST=5
-tCCD_L=0
-tCK=1
-tCL=14
-tCS=3
-tRAS=35
-tRCD=14
-tREFI=7800
-tRFC=260
-tRP=14
-tRRD=6
-tRRD_L=0
-tRTP=8
-tRTW=3
-tWR=15
-tWTR=8
-tXAW=30
-tXP=6
-tXPDLL=0
-tXS=270
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.dir_cntrl0.memory
-
-[system.ruby]
-type=RubySystem
-children=clk_domain network
-access_backing_store=false
-all_instructions=false
-block_size_bytes=64
-clk_domain=system.ruby.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hot_lines=false
-memory_size_bits=48
-num_of_sequencers=12
-number_of_virtual_networks=10
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-phys_mem=Null
-power_model=Null
-randomization=true
-
-[system.ruby.clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.ruby.network]
-type=SimpleNetwork
-children=ext_links00 ext_links01 ext_links02 ext_links03 ext_links04 ext_links05 ext_links06 ext_links07 ext_links08 ext_links09 ext_links10 ext_links11 ext_links12 ext_links13 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_link_buffers48 int_link_buffers49 int_link_buffers50 int_link_buffers51 int_link_buffers52 int_link_buffers53 int_link_buffers54 int_link_buffers55 int_link_buffers56 int_link_buffers57 int_link_buffers58 int_link_buffers59 int_link_buffers60 int_link_buffers61 int_link_buffers62 int_link_buffers63 int_link_buffers64 int_link_buffers65 int_link_buffers66 int_link_buffers67 int_link_buffers68 int_link_buffers69 int_link_buffers70 int_link_buffers71 int_link_buffers72 int_link_buffers73 int_link_buffers74 int_link_buffers75 int_link_buffers76 int_link_buffers77 int_link_buffers78 int_link_buffers79 int_links0 int_links1 int_links2 int_links3
-adaptive_routing=false
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-control_msg_size=8
-default_p_state=UNDEFINED
-endpoint_bandwidth=1000
-eventq_index=0
-ext_links=system.ruby.network.ext_links00 system.ruby.network.ext_links01 system.ruby.network.ext_links02 system.ruby.network.ext_links03 system.ruby.network.ext_links04 system.ruby.network.ext_links05 system.ruby.network.ext_links06 system.ruby.network.ext_links07 system.ruby.network.ext_links08 system.ruby.network.ext_links09 system.ruby.network.ext_links10 system.ruby.network.ext_links11 system.ruby.network.ext_links12 system.ruby.network.ext_links13
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 system.ruby.network.int_link_buffers48 system.ruby.network.int_link_buffers49 system.ruby.network.int_link_buffers50 system.ruby.network.int_link_buffers51 system.ruby.network.int_link_buffers52 system.ruby.network.int_link_buffers53 system.ruby.network.int_link_buffers54 system.ruby.network.int_link_buffers55 system.ruby.network.int_link_buffers56 system.ruby.network.int_link_buffers57 system.ruby.network.int_link_buffers58 system.ruby.network.int_link_buffers59 system.ruby.network.int_link_buffers60 system.ruby.network.int_link_buffers61 system.ruby.network.int_link_buffers62 system.ruby.network.int_link_buffers63 system.ruby.network.int_link_buffers64 system.ruby.network.int_link_buffers65 system.ruby.network.int_link_buffers66 system.ruby.network.int_link_buffers67 system.ruby.network.int_link_buffers68 system.ruby.network.int_link_buffers69 system.ruby.network.int_link_buffers70 system.ruby.network.int_link_buffers71 system.ruby.network.int_link_buffers72 system.ruby.network.int_link_buffers73 system.ruby.network.int_link_buffers74 system.ruby.network.int_link_buffers75 system.ruby.network.int_link_buffers76 system.ruby.network.int_link_buffers77 system.ruby.network.int_link_buffers78 system.ruby.network.int_link_buffers79
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3
-netifs=
-number_of_virtual_networks=10
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-routers=system.ruby.network.ext_links00.int_node system.ruby.network.ext_links01.int_node system.ruby.network.ext_links02.int_node
-ruby_system=system.ruby
-topology=Crossbar
-master=system.dir_cntrl0.requestFromCores.slave system.dir_cntrl0.responseFromCores.slave system.dir_cntrl0.unblockFromCores.slave system.cp_cntrl0.probeToCore.slave system.cp_cntrl0.responseToCore.slave system.tcp_cntrl0.probeToTCP.slave system.tcp_cntrl0.responseToTCP.slave system.tcp_cntrl1.probeToTCP.slave system.tcp_cntrl1.responseToTCP.slave system.tcp_cntrl2.probeToTCP.slave system.tcp_cntrl2.responseToTCP.slave system.tcp_cntrl3.probeToTCP.slave system.tcp_cntrl3.responseToTCP.slave system.tcp_cntrl4.probeToTCP.slave system.tcp_cntrl4.responseToTCP.slave system.tcp_cntrl5.probeToTCP.slave system.tcp_cntrl5.responseToTCP.slave system.tcp_cntrl6.probeToTCP.slave system.tcp_cntrl6.responseToTCP.slave system.tcp_cntrl7.probeToTCP.slave system.tcp_cntrl7.responseToTCP.slave system.sqc_cntrl0.probeToSQC.slave system.sqc_cntrl0.responseToSQC.slave system.sqc_cntrl1.probeToSQC.slave system.sqc_cntrl1.responseToSQC.slave system.tcc_cntrl0.responseToTCC.slave system.tccdir_cntrl0.requestFromTCP.slave system.tccdir_cntrl0.responseFromTCP.slave system.tccdir_cntrl0.unblockFromTCP.slave system.tccdir_cntrl0.probeFromNB.slave system.tccdir_cntrl0.responseFromNB.slave
-slave=system.dir_cntrl0.probeToCore.master system.dir_cntrl0.responseToCore.master system.cp_cntrl0.requestFromCore.master system.cp_cntrl0.responseFromCore.master system.cp_cntrl0.unblockFromCore.master system.tcp_cntrl0.requestFromTCP.master system.tcp_cntrl0.responseFromTCP.master system.tcp_cntrl0.unblockFromCore.master system.tcp_cntrl1.requestFromTCP.master system.tcp_cntrl1.responseFromTCP.master system.tcp_cntrl1.unblockFromCore.master system.tcp_cntrl2.requestFromTCP.master system.tcp_cntrl2.responseFromTCP.master system.tcp_cntrl2.unblockFromCore.master system.tcp_cntrl3.requestFromTCP.master system.tcp_cntrl3.responseFromTCP.master system.tcp_cntrl3.unblockFromCore.master system.tcp_cntrl4.requestFromTCP.master system.tcp_cntrl4.responseFromTCP.master system.tcp_cntrl4.unblockFromCore.master system.tcp_cntrl5.requestFromTCP.master system.tcp_cntrl5.responseFromTCP.master system.tcp_cntrl5.unblockFromCore.master system.tcp_cntrl6.requestFromTCP.master system.tcp_cntrl6.responseFromTCP.master system.tcp_cntrl6.unblockFromCore.master system.tcp_cntrl7.requestFromTCP.master system.tcp_cntrl7.responseFromTCP.master system.tcp_cntrl7.unblockFromCore.master system.sqc_cntrl0.requestFromSQC.master system.sqc_cntrl0.responseFromSQC.master system.sqc_cntrl0.unblockFromCore.master system.sqc_cntrl1.requestFromSQC.master system.sqc_cntrl1.responseFromSQC.master system.sqc_cntrl1.unblockFromCore.master system.tcc_cntrl0.responseFromTCC.master system.tccdir_cntrl0.probeToCore.master system.tccdir_cntrl0.responseToCore.master system.tccdir_cntrl0.requestToNB.master system.tccdir_cntrl0.responseToNB.master system.tccdir_cntrl0.unblockToNB.master
-
-[system.ruby.network.ext_links00]
-type=SimpleExtLink
-children=int_node
-bandwidth_factor=512
-eventq_index=0
-ext_node=system.dir_cntrl0
-int_node=system.ruby.network.ext_links00.int_node
-latency=1
-link_id=0
-weight=1
-
-[system.ruby.network.ext_links00.int_node]
-type=Switch
-children=port_buffers000 port_buffers001 port_buffers002 port_buffers003 port_buffers004 port_buffers005 port_buffers006 port_buffers007 port_buffers008 port_buffers009 port_buffers010 port_buffers011 port_buffers012 port_buffers013 port_buffers014 port_buffers015 port_buffers016 port_buffers017 port_buffers018 port_buffers019 port_buffers020 port_buffers021 port_buffers022 port_buffers023 port_buffers024 port_buffers025 port_buffers026 port_buffers027 port_buffers028 port_buffers029 port_buffers030 port_buffers031 port_buffers032 port_buffers033 port_buffers034 port_buffers035 port_buffers036 port_buffers037 port_buffers038 port_buffers039 port_buffers040 port_buffers041 port_buffers042 port_buffers043 port_buffers044 port_buffers045 port_buffers046 port_buffers047 port_buffers048 port_buffers049 port_buffers050 port_buffers051 port_buffers052 port_buffers053 port_buffers054 port_buffers055 port_buffers056 port_buffers057 port_buffers058 port_buffers059 port_buffers060 port_buffers061 port_buffers062 port_buffers063 port_buffers064 port_buffers065 port_buffers066 port_buffers067 port_buffers068 port_buffers069 port_buffers070 port_buffers071 port_buffers072 port_buffers073 port_buffers074 port_buffers075 port_buffers076 port_buffers077 port_buffers078 port_buffers079 port_buffers080 port_buffers081 port_buffers082 port_buffers083 port_buffers084 port_buffers085 port_buffers086 port_buffers087 port_buffers088 port_buffers089 port_buffers090 port_buffers091 port_buffers092 port_buffers093 port_buffers094 port_buffers095 port_buffers096 port_buffers097 port_buffers098 port_buffers099 port_buffers100 port_buffers101 port_buffers102 port_buffers103 port_buffers104 port_buffers105 port_buffers106 port_buffers107 port_buffers108 port_buffers109 port_buffers110 port_buffers111 port_buffers112 port_buffers113 port_buffers114 port_buffers115 port_buffers116 port_buffers117 port_buffers118 port_buffers119 port_buffers120 port_buffers121 port_buffers122 port_buffers123 port_buffers124 port_buffers125 port_buffers126 port_buffers127 port_buffers128 port_buffers129 port_buffers130 port_buffers131 port_buffers132 port_buffers133 port_buffers134 port_buffers135 port_buffers136 port_buffers137 port_buffers138 port_buffers139 port_buffers140 port_buffers141 port_buffers142 port_buffers143 port_buffers144 port_buffers145 port_buffers146 port_buffers147 port_buffers148 port_buffers149 port_buffers150 port_buffers151 port_buffers152 port_buffers153 port_buffers154 port_buffers155 port_buffers156 port_buffers157 port_buffers158 port_buffers159
-clk_domain=system.ruby.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-port_buffers=system.ruby.network.ext_links00.int_node.port_buffers000 system.ruby.network.ext_links00.int_node.port_buffers001 system.ruby.network.ext_links00.int_node.port_buffers002 system.ruby.network.ext_links00.int_node.port_buffers003 system.ruby.network.ext_links00.int_node.port_buffers004 system.ruby.network.ext_links00.int_node.port_buffers005 system.ruby.network.ext_links00.int_node.port_buffers006 system.ruby.network.ext_links00.int_node.port_buffers007 system.ruby.network.ext_links00.int_node.port_buffers008 system.ruby.network.ext_links00.int_node.port_buffers009 system.ruby.network.ext_links00.int_node.port_buffers010 system.ruby.network.ext_links00.int_node.port_buffers011 system.ruby.network.ext_links00.int_node.port_buffers012 system.ruby.network.ext_links00.int_node.port_buffers013 system.ruby.network.ext_links00.int_node.port_buffers014 system.ruby.network.ext_links00.int_node.port_buffers015 system.ruby.network.ext_links00.int_node.port_buffers016 system.ruby.network.ext_links00.int_node.port_buffers017 system.ruby.network.ext_links00.int_node.port_buffers018 system.ruby.network.ext_links00.int_node.port_buffers019 system.ruby.network.ext_links00.int_node.port_buffers020 system.ruby.network.ext_links00.int_node.port_buffers021 system.ruby.network.ext_links00.int_node.port_buffers022 system.ruby.network.ext_links00.int_node.port_buffers023 system.ruby.network.ext_links00.int_node.port_buffers024 system.ruby.network.ext_links00.int_node.port_buffers025 system.ruby.network.ext_links00.int_node.port_buffers026 system.ruby.network.ext_links00.int_node.port_buffers027 system.ruby.network.ext_links00.int_node.port_buffers028 system.ruby.network.ext_links00.int_node.port_buffers029 system.ruby.network.ext_links00.int_node.port_buffers030 system.ruby.network.ext_links00.int_node.port_buffers031 system.ruby.network.ext_links00.int_node.port_buffers032 system.ruby.network.ext_links00.int_node.port_buffers033 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-
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-
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-[system.sqc_cntrl1.L1cache.replacement_policy]
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-[system.tcc_cntrl0.L2cache]
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-[system.tcc_cntrl0.L2cache.replacement_policy]
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-transitions_per_cycle=32
-triggerQueue=system.tccdir_cntrl0.triggerQueue
-unblockFromTCP=system.tccdir_cntrl0.unblockFromTCP
-unblockToNB=system.tccdir_cntrl0.unblockToNB
-version=0
-w_TCCUnblockToTCCDir=system.tcc_cntrl0.w_TCCUnblockToTCCDir
-w_probeToTCC=system.tcc_cntrl0.w_probeToTCC
-w_reqToTCC=system.tcc_cntrl0.w_reqToTCC
-w_reqToTCCDir=system.tcc_cntrl0.w_reqToTCCDir
-w_respToTCC=system.tcc_cntrl0.w_respToTCC
-w_respToTCCDir=system.tcc_cntrl0.w_respToTCCDir
-
-[system.tccdir_cntrl0.directory]
-type=RubyCache
-children=replacement_policy
-assoc=16
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.tccdir_cntrl0.directory.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=786432
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.tccdir_cntrl0.directory.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=16
-block_size=64
-eventq_index=0
-size=786432
-
-[system.tccdir_cntrl0.probeFromNB]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[29]
-
-[system.tccdir_cntrl0.probeToCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[36]
-
-[system.tccdir_cntrl0.requestFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[26]
-
-[system.tccdir_cntrl0.requestToNB]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[38]
-
-[system.tccdir_cntrl0.responseFromNB]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[30]
-
-[system.tccdir_cntrl0.responseFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[27]
-
-[system.tccdir_cntrl0.responseToCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[37]
-
-[system.tccdir_cntrl0.responseToNB]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[39]
-
-[system.tccdir_cntrl0.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.tccdir_cntrl0.unblockFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[28]
-
-[system.tccdir_cntrl0.unblockToNB]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[40]
-
-[system.tcp_cntrl0]
-type=TCP_Controller
-children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore
-L1cache=system.tcp_cntrl0.L1cache
-TCC_select_num_bits=0
-buffer_size=0
-clk_domain=system.clk_domain
-cluster_id=0
-coalescer=system.tcp_cntrl0.coalescer
-default_p_state=UNDEFINED
-eventq_index=0
-issue_latency=40
-l2_hit_latency=18
-mandatoryQueue=system.tcp_cntrl0.mandatoryQueue
-number_of_TBEs=2560
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-probeToTCP=system.tcp_cntrl0.probeToTCP
-recycle_latency=10
-requestFromTCP=system.tcp_cntrl0.requestFromTCP
-responseFromTCP=system.tcp_cntrl0.responseFromTCP
-responseToTCP=system.tcp_cntrl0.responseToTCP
-ruby_system=system.ruby
-sequencer=system.tcp_cntrl0.sequencer
-system=system
-transitions_per_cycle=32
-unblockFromCore=system.tcp_cntrl0.unblockFromCore
-use_seq_not_coal=false
-version=0
-
-[system.tcp_cntrl0.L1cache]
-type=RubyCache
-children=replacement_policy
-assoc=8
-block_size=0
-dataAccessLatency=4
-dataArrayBanks=16
-eventq_index=0
-is_icache=false
-replacement_policy=system.tcp_cntrl0.L1cache.replacement_policy
-resourceStalls=true
-ruby_system=system.ruby
-size=16384
-start_index_bit=6
-tagAccessLatency=4
-tagArrayBanks=4
-
-[system.tcp_cntrl0.L1cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=8
-block_size=64
-eventq_index=0
-size=16384
-
-[system.tcp_cntrl0.coalescer]
-type=RubyGPUCoalescer
-assume_rfo=true
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.tcp_cntrl0.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.tcp_cntrl0.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=false
-max_outstanding_requests=2560
-no_retry_on_stall=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=false
-system=system
-using_ruby_tester=true
-version=2
-slave=system.cpu.cpuDataPort[0]
-
-[system.tcp_cntrl0.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.tcp_cntrl0.probeToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[5]
-
-[system.tcp_cntrl0.requestFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[5]
-
-[system.tcp_cntrl0.responseFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[6]
-
-[system.tcp_cntrl0.responseToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[6]
-
-[system.tcp_cntrl0.sequencer]
-type=RubySequencer
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.tcp_cntrl0.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.tcp_cntrl0.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=3
-
-[system.tcp_cntrl0.unblockFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[7]
-
-[system.tcp_cntrl1]
-type=TCP_Controller
-children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore
-L1cache=system.tcp_cntrl1.L1cache
-TCC_select_num_bits=0
-buffer_size=0
-clk_domain=system.clk_domain
-cluster_id=0
-coalescer=system.tcp_cntrl1.coalescer
-default_p_state=UNDEFINED
-eventq_index=0
-issue_latency=40
-l2_hit_latency=18
-mandatoryQueue=system.tcp_cntrl1.mandatoryQueue
-number_of_TBEs=2560
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-probeToTCP=system.tcp_cntrl1.probeToTCP
-recycle_latency=10
-requestFromTCP=system.tcp_cntrl1.requestFromTCP
-responseFromTCP=system.tcp_cntrl1.responseFromTCP
-responseToTCP=system.tcp_cntrl1.responseToTCP
-ruby_system=system.ruby
-sequencer=system.tcp_cntrl1.sequencer
-system=system
-transitions_per_cycle=32
-unblockFromCore=system.tcp_cntrl1.unblockFromCore
-use_seq_not_coal=false
-version=1
-
-[system.tcp_cntrl1.L1cache]
-type=RubyCache
-children=replacement_policy
-assoc=8
-block_size=0
-dataAccessLatency=4
-dataArrayBanks=16
-eventq_index=0
-is_icache=false
-replacement_policy=system.tcp_cntrl1.L1cache.replacement_policy
-resourceStalls=true
-ruby_system=system.ruby
-size=16384
-start_index_bit=6
-tagAccessLatency=4
-tagArrayBanks=4
-
-[system.tcp_cntrl1.L1cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=8
-block_size=64
-eventq_index=0
-size=16384
-
-[system.tcp_cntrl1.coalescer]
-type=RubyGPUCoalescer
-assume_rfo=true
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.tcp_cntrl1.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.tcp_cntrl1.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=false
-max_outstanding_requests=2560
-no_retry_on_stall=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=false
-system=system
-using_ruby_tester=true
-version=4
-slave=system.cpu.cpuDataPort[1]
-
-[system.tcp_cntrl1.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.tcp_cntrl1.probeToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[7]
-
-[system.tcp_cntrl1.requestFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[8]
-
-[system.tcp_cntrl1.responseFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[9]
-
-[system.tcp_cntrl1.responseToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[8]
-
-[system.tcp_cntrl1.sequencer]
-type=RubySequencer
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.tcp_cntrl1.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.tcp_cntrl1.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=5
-
-[system.tcp_cntrl1.unblockFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[10]
-
-[system.tcp_cntrl2]
-type=TCP_Controller
-children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore
-L1cache=system.tcp_cntrl2.L1cache
-TCC_select_num_bits=0
-buffer_size=0
-clk_domain=system.clk_domain
-cluster_id=0
-coalescer=system.tcp_cntrl2.coalescer
-default_p_state=UNDEFINED
-eventq_index=0
-issue_latency=40
-l2_hit_latency=18
-mandatoryQueue=system.tcp_cntrl2.mandatoryQueue
-number_of_TBEs=2560
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-probeToTCP=system.tcp_cntrl2.probeToTCP
-recycle_latency=10
-requestFromTCP=system.tcp_cntrl2.requestFromTCP
-responseFromTCP=system.tcp_cntrl2.responseFromTCP
-responseToTCP=system.tcp_cntrl2.responseToTCP
-ruby_system=system.ruby
-sequencer=system.tcp_cntrl2.sequencer
-system=system
-transitions_per_cycle=32
-unblockFromCore=system.tcp_cntrl2.unblockFromCore
-use_seq_not_coal=false
-version=2
-
-[system.tcp_cntrl2.L1cache]
-type=RubyCache
-children=replacement_policy
-assoc=8
-block_size=0
-dataAccessLatency=4
-dataArrayBanks=16
-eventq_index=0
-is_icache=false
-replacement_policy=system.tcp_cntrl2.L1cache.replacement_policy
-resourceStalls=true
-ruby_system=system.ruby
-size=16384
-start_index_bit=6
-tagAccessLatency=4
-tagArrayBanks=4
-
-[system.tcp_cntrl2.L1cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=8
-block_size=64
-eventq_index=0
-size=16384
-
-[system.tcp_cntrl2.coalescer]
-type=RubyGPUCoalescer
-assume_rfo=true
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.tcp_cntrl2.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.tcp_cntrl2.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=false
-max_outstanding_requests=2560
-no_retry_on_stall=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=false
-system=system
-using_ruby_tester=true
-version=6
-slave=system.cpu.cpuDataPort[2]
-
-[system.tcp_cntrl2.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.tcp_cntrl2.probeToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[9]
-
-[system.tcp_cntrl2.requestFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[11]
-
-[system.tcp_cntrl2.responseFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[12]
-
-[system.tcp_cntrl2.responseToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[10]
-
-[system.tcp_cntrl2.sequencer]
-type=RubySequencer
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.tcp_cntrl2.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.tcp_cntrl2.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=7
-
-[system.tcp_cntrl2.unblockFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[13]
-
-[system.tcp_cntrl3]
-type=TCP_Controller
-children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore
-L1cache=system.tcp_cntrl3.L1cache
-TCC_select_num_bits=0
-buffer_size=0
-clk_domain=system.clk_domain
-cluster_id=0
-coalescer=system.tcp_cntrl3.coalescer
-default_p_state=UNDEFINED
-eventq_index=0
-issue_latency=40
-l2_hit_latency=18
-mandatoryQueue=system.tcp_cntrl3.mandatoryQueue
-number_of_TBEs=2560
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-probeToTCP=system.tcp_cntrl3.probeToTCP
-recycle_latency=10
-requestFromTCP=system.tcp_cntrl3.requestFromTCP
-responseFromTCP=system.tcp_cntrl3.responseFromTCP
-responseToTCP=system.tcp_cntrl3.responseToTCP
-ruby_system=system.ruby
-sequencer=system.tcp_cntrl3.sequencer
-system=system
-transitions_per_cycle=32
-unblockFromCore=system.tcp_cntrl3.unblockFromCore
-use_seq_not_coal=false
-version=3
-
-[system.tcp_cntrl3.L1cache]
-type=RubyCache
-children=replacement_policy
-assoc=8
-block_size=0
-dataAccessLatency=4
-dataArrayBanks=16
-eventq_index=0
-is_icache=false
-replacement_policy=system.tcp_cntrl3.L1cache.replacement_policy
-resourceStalls=true
-ruby_system=system.ruby
-size=16384
-start_index_bit=6
-tagAccessLatency=4
-tagArrayBanks=4
-
-[system.tcp_cntrl3.L1cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=8
-block_size=64
-eventq_index=0
-size=16384
-
-[system.tcp_cntrl3.coalescer]
-type=RubyGPUCoalescer
-assume_rfo=true
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.tcp_cntrl3.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.tcp_cntrl3.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=false
-max_outstanding_requests=2560
-no_retry_on_stall=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=false
-system=system
-using_ruby_tester=true
-version=8
-slave=system.cpu.cpuDataPort[3]
-
-[system.tcp_cntrl3.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.tcp_cntrl3.probeToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[11]
-
-[system.tcp_cntrl3.requestFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[14]
-
-[system.tcp_cntrl3.responseFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[15]
-
-[system.tcp_cntrl3.responseToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[12]
-
-[system.tcp_cntrl3.sequencer]
-type=RubySequencer
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.tcp_cntrl3.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.tcp_cntrl3.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=9
-
-[system.tcp_cntrl3.unblockFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[16]
-
-[system.tcp_cntrl4]
-type=TCP_Controller
-children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore
-L1cache=system.tcp_cntrl4.L1cache
-TCC_select_num_bits=0
-buffer_size=0
-clk_domain=system.clk_domain
-cluster_id=0
-coalescer=system.tcp_cntrl4.coalescer
-default_p_state=UNDEFINED
-eventq_index=0
-issue_latency=40
-l2_hit_latency=18
-mandatoryQueue=system.tcp_cntrl4.mandatoryQueue
-number_of_TBEs=2560
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-probeToTCP=system.tcp_cntrl4.probeToTCP
-recycle_latency=10
-requestFromTCP=system.tcp_cntrl4.requestFromTCP
-responseFromTCP=system.tcp_cntrl4.responseFromTCP
-responseToTCP=system.tcp_cntrl4.responseToTCP
-ruby_system=system.ruby
-sequencer=system.tcp_cntrl4.sequencer
-system=system
-transitions_per_cycle=32
-unblockFromCore=system.tcp_cntrl4.unblockFromCore
-use_seq_not_coal=false
-version=4
-
-[system.tcp_cntrl4.L1cache]
-type=RubyCache
-children=replacement_policy
-assoc=8
-block_size=0
-dataAccessLatency=4
-dataArrayBanks=16
-eventq_index=0
-is_icache=false
-replacement_policy=system.tcp_cntrl4.L1cache.replacement_policy
-resourceStalls=true
-ruby_system=system.ruby
-size=16384
-start_index_bit=6
-tagAccessLatency=4
-tagArrayBanks=4
-
-[system.tcp_cntrl4.L1cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=8
-block_size=64
-eventq_index=0
-size=16384
-
-[system.tcp_cntrl4.coalescer]
-type=RubyGPUCoalescer
-assume_rfo=true
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.tcp_cntrl4.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.tcp_cntrl4.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=false
-max_outstanding_requests=2560
-no_retry_on_stall=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=false
-system=system
-using_ruby_tester=true
-version=10
-slave=system.cpu.cpuDataPort[4]
-
-[system.tcp_cntrl4.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.tcp_cntrl4.probeToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[13]
-
-[system.tcp_cntrl4.requestFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[17]
-
-[system.tcp_cntrl4.responseFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[18]
-
-[system.tcp_cntrl4.responseToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[14]
-
-[system.tcp_cntrl4.sequencer]
-type=RubySequencer
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.tcp_cntrl4.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.tcp_cntrl4.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=11
-
-[system.tcp_cntrl4.unblockFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[19]
-
-[system.tcp_cntrl5]
-type=TCP_Controller
-children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore
-L1cache=system.tcp_cntrl5.L1cache
-TCC_select_num_bits=0
-buffer_size=0
-clk_domain=system.clk_domain
-cluster_id=0
-coalescer=system.tcp_cntrl5.coalescer
-default_p_state=UNDEFINED
-eventq_index=0
-issue_latency=40
-l2_hit_latency=18
-mandatoryQueue=system.tcp_cntrl5.mandatoryQueue
-number_of_TBEs=2560
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-probeToTCP=system.tcp_cntrl5.probeToTCP
-recycle_latency=10
-requestFromTCP=system.tcp_cntrl5.requestFromTCP
-responseFromTCP=system.tcp_cntrl5.responseFromTCP
-responseToTCP=system.tcp_cntrl5.responseToTCP
-ruby_system=system.ruby
-sequencer=system.tcp_cntrl5.sequencer
-system=system
-transitions_per_cycle=32
-unblockFromCore=system.tcp_cntrl5.unblockFromCore
-use_seq_not_coal=false
-version=5
-
-[system.tcp_cntrl5.L1cache]
-type=RubyCache
-children=replacement_policy
-assoc=8
-block_size=0
-dataAccessLatency=4
-dataArrayBanks=16
-eventq_index=0
-is_icache=false
-replacement_policy=system.tcp_cntrl5.L1cache.replacement_policy
-resourceStalls=true
-ruby_system=system.ruby
-size=16384
-start_index_bit=6
-tagAccessLatency=4
-tagArrayBanks=4
-
-[system.tcp_cntrl5.L1cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=8
-block_size=64
-eventq_index=0
-size=16384
-
-[system.tcp_cntrl5.coalescer]
-type=RubyGPUCoalescer
-assume_rfo=true
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.tcp_cntrl5.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.tcp_cntrl5.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=false
-max_outstanding_requests=2560
-no_retry_on_stall=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=false
-system=system
-using_ruby_tester=true
-version=12
-slave=system.cpu.cpuDataPort[5]
-
-[system.tcp_cntrl5.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.tcp_cntrl5.probeToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[15]
-
-[system.tcp_cntrl5.requestFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[20]
-
-[system.tcp_cntrl5.responseFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[21]
-
-[system.tcp_cntrl5.responseToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[16]
-
-[system.tcp_cntrl5.sequencer]
-type=RubySequencer
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.tcp_cntrl5.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.tcp_cntrl5.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=13
-
-[system.tcp_cntrl5.unblockFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[22]
-
-[system.tcp_cntrl6]
-type=TCP_Controller
-children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore
-L1cache=system.tcp_cntrl6.L1cache
-TCC_select_num_bits=0
-buffer_size=0
-clk_domain=system.clk_domain
-cluster_id=0
-coalescer=system.tcp_cntrl6.coalescer
-default_p_state=UNDEFINED
-eventq_index=0
-issue_latency=40
-l2_hit_latency=18
-mandatoryQueue=system.tcp_cntrl6.mandatoryQueue
-number_of_TBEs=2560
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-probeToTCP=system.tcp_cntrl6.probeToTCP
-recycle_latency=10
-requestFromTCP=system.tcp_cntrl6.requestFromTCP
-responseFromTCP=system.tcp_cntrl6.responseFromTCP
-responseToTCP=system.tcp_cntrl6.responseToTCP
-ruby_system=system.ruby
-sequencer=system.tcp_cntrl6.sequencer
-system=system
-transitions_per_cycle=32
-unblockFromCore=system.tcp_cntrl6.unblockFromCore
-use_seq_not_coal=false
-version=6
-
-[system.tcp_cntrl6.L1cache]
-type=RubyCache
-children=replacement_policy
-assoc=8
-block_size=0
-dataAccessLatency=4
-dataArrayBanks=16
-eventq_index=0
-is_icache=false
-replacement_policy=system.tcp_cntrl6.L1cache.replacement_policy
-resourceStalls=true
-ruby_system=system.ruby
-size=16384
-start_index_bit=6
-tagAccessLatency=4
-tagArrayBanks=4
-
-[system.tcp_cntrl6.L1cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=8
-block_size=64
-eventq_index=0
-size=16384
-
-[system.tcp_cntrl6.coalescer]
-type=RubyGPUCoalescer
-assume_rfo=true
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.tcp_cntrl6.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.tcp_cntrl6.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=false
-max_outstanding_requests=2560
-no_retry_on_stall=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=false
-system=system
-using_ruby_tester=true
-version=14
-slave=system.cpu.cpuDataPort[6]
-
-[system.tcp_cntrl6.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.tcp_cntrl6.probeToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[17]
-
-[system.tcp_cntrl6.requestFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[23]
-
-[system.tcp_cntrl6.responseFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[24]
-
-[system.tcp_cntrl6.responseToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[18]
-
-[system.tcp_cntrl6.sequencer]
-type=RubySequencer
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.tcp_cntrl6.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.tcp_cntrl6.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=15
-
-[system.tcp_cntrl6.unblockFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[25]
-
-[system.tcp_cntrl7]
-type=TCP_Controller
-children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore
-L1cache=system.tcp_cntrl7.L1cache
-TCC_select_num_bits=0
-buffer_size=0
-clk_domain=system.clk_domain
-cluster_id=0
-coalescer=system.tcp_cntrl7.coalescer
-default_p_state=UNDEFINED
-eventq_index=0
-issue_latency=40
-l2_hit_latency=18
-mandatoryQueue=system.tcp_cntrl7.mandatoryQueue
-number_of_TBEs=2560
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-probeToTCP=system.tcp_cntrl7.probeToTCP
-recycle_latency=10
-requestFromTCP=system.tcp_cntrl7.requestFromTCP
-responseFromTCP=system.tcp_cntrl7.responseFromTCP
-responseToTCP=system.tcp_cntrl7.responseToTCP
-ruby_system=system.ruby
-sequencer=system.tcp_cntrl7.sequencer
-system=system
-transitions_per_cycle=32
-unblockFromCore=system.tcp_cntrl7.unblockFromCore
-use_seq_not_coal=false
-version=7
-
-[system.tcp_cntrl7.L1cache]
-type=RubyCache
-children=replacement_policy
-assoc=8
-block_size=0
-dataAccessLatency=4
-dataArrayBanks=16
-eventq_index=0
-is_icache=false
-replacement_policy=system.tcp_cntrl7.L1cache.replacement_policy
-resourceStalls=true
-ruby_system=system.ruby
-size=16384
-start_index_bit=6
-tagAccessLatency=4
-tagArrayBanks=4
-
-[system.tcp_cntrl7.L1cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=8
-block_size=64
-eventq_index=0
-size=16384
-
-[system.tcp_cntrl7.coalescer]
-type=RubyGPUCoalescer
-assume_rfo=true
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.tcp_cntrl7.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.tcp_cntrl7.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=false
-max_outstanding_requests=2560
-no_retry_on_stall=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=false
-system=system
-using_ruby_tester=true
-version=16
-slave=system.cpu.cpuDataPort[7]
-
-[system.tcp_cntrl7.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.tcp_cntrl7.probeToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[19]
-
-[system.tcp_cntrl7.requestFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[26]
-
-[system.tcp_cntrl7.responseFromTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[27]
-
-[system.tcp_cntrl7.responseToTCP]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[20]
-
-[system.tcp_cntrl7.sequencer]
-type=RubySequencer
-clk_domain=system.clk_domain
-coreid=99
-dcache=system.tcp_cntrl7.L1cache
-dcache_hit_latency=1
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.tcp_cntrl7.L1cache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=17
-
-[system.tcp_cntrl7.unblockFromCore]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[28]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: system.ruby.network adopting orphan SimObject param 'int_links'
-warn: system.ruby.network adopting orphan SimObject param 'ext_links'
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
+++ /dev/null
-Redirecting stdout to build/HSAIL_X86/tests/opt/quick/se/60.gpu-randomtest/x86/linux/gpu-randomtest-ruby-GPU_RfO/simout
-Redirecting stderr to build/HSAIL_X86/tests/opt/quick/se/60.gpu-randomtest/x86/linux/gpu-randomtest-ruby-GPU_RfO/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 13 2016 21:24:38
-gem5 started Oct 13 2016 21:24:54
-gem5 executing on e108600-lin, pid 29891
-command line: /work/curdun01/gem5-external.hg/build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/60.gpu-randomtest/x86/linux/gpu-randomtest-ruby-GPU_RfO -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/60.gpu-randomtest/x86/linux/gpu-randomtest-ruby-GPU_RfO
-
-Global frequency set at 1000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 13821 because Ruby Tester completed
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000014 # Number of seconds simulated
-sim_ticks 13821 # Number of ticks simulated
-final_tick 13821 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 253620 # Simulator tick rate (ticks/s)
-host_mem_usage 491252 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.mem_ctrls.bytes_read::dir_cntrl0 16384 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 16384 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::dir_cntrl0 896 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 896 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::dir_cntrl0 256 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 256 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::dir_cntrl0 14 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 14 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::dir_cntrl0 1185442443 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 1185442443 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::dir_cntrl0 64828884 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 64828884 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::dir_cntrl0 1250271326 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 1250271326 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 256 # Number of read requests accepted
-system.mem_ctrls.writeReqs 14 # Number of write requests accepted
-system.mem_ctrls.readBursts 256 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 14 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 15488 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 896 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 16384 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 896 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 14 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 99 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 69 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 62 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 12 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
-system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
-system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 13710 # Total gap between requests
-system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 256 # Read request sizes (log2)
-system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 14 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 199 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 36 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2 6 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3 1 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 15 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 913.066667 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 883.543279 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 210.139908 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 3 20.00% 20.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 1 6.67% 26.67% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 11 73.33% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 15 # Bytes accessed per row activation
-system.mem_ctrls.totQLat 2184 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 6782 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 1210 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 9.02 # Average queueing delay per DRAM burst
-system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 28.02 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 1120.61 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 1185.44 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 64.83 # Average system write bandwidth in MiByte/s
-system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 8.75 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 8.75 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 1.20 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 3.35 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 223 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 92.15 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 0.00 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 50.78 # Average gap between requests
-system.mem_ctrls.pageHitRate 87.11 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 135660 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 57960 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 2764608 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 2757888 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 44928 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.actPowerDownEnergy 3490680 # Energy for active power-down per rank (pJ)
-system.mem_ctrls_0.prePowerDownEnergy 384 # Energy for precharge power-down per rank (pJ)
-system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
-system.mem_ctrls_0.totalEnergy 9866748 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 713.895377 # Core power per rank (mW)
-system.mem_ctrls_0.totalIdleTime 7568 # Total Idle time Per DRAM Rank
-system.mem_ctrls_0.memoryStateTime::IDLE 89 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 260 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 1 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 5816 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 7655 # Time in different power states
-system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 112176 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 2995200 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ)
-system.mem_ctrls_1.prePowerDownEnergy 2217600 # Energy for precharge power-down per rank (pJ)
-system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
-system.mem_ctrls_1.totalEnergy 5939616 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 429.752985 # Core power per rank (mW)
-system.mem_ctrls_1.totalIdleTime 0 # Total Idle time Per DRAM Rank
-system.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 260 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 5775 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.ruby.clk_domain.clock 1 # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.ruby.outstanding_req_hist_seqr::bucket_size 2
-system.ruby.outstanding_req_hist_seqr::max_bucket 19
-system.ruby.outstanding_req_hist_seqr::samples 63
-system.ruby.outstanding_req_hist_seqr::mean 12.873016
-system.ruby.outstanding_req_hist_seqr::gmean 11.658152
-system.ruby.outstanding_req_hist_seqr::stdev 4.202503
-system.ruby.outstanding_req_hist_seqr | 1 1.59% 1.59% | 2 3.17% 4.76% | 2 3.17% 7.94% | 5 7.94% 15.87% | 4 6.35% 22.22% | 3 4.76% 26.98% | 5 7.94% 34.92% | 16 25.40% 60.32% | 25 39.68% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist_seqr::total 63
-system.ruby.outstanding_req_hist_coalsr::bucket_size 2
-system.ruby.outstanding_req_hist_coalsr::max_bucket 19
-system.ruby.outstanding_req_hist_coalsr::samples 872
-system.ruby.outstanding_req_hist_coalsr::mean 2.547018
-system.ruby.outstanding_req_hist_coalsr::gmean 2.158955
-system.ruby.outstanding_req_hist_coalsr::stdev 1.537168
-system.ruby.outstanding_req_hist_coalsr | 236 27.06% 27.06% | 460 52.75% 79.82% | 126 14.45% 94.27% | 40 4.59% 98.85% | 9 1.03% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist_coalsr::total 872
-system.ruby.latency_hist_seqr::bucket_size 1024
-system.ruby.latency_hist_seqr::max_bucket 10239
-system.ruby.latency_hist_seqr::samples 48
-system.ruby.latency_hist_seqr::mean 3315.854167
-system.ruby.latency_hist_seqr::gmean 1841.298781
-system.ruby.latency_hist_seqr::stdev 1907.716848
-system.ruby.latency_hist_seqr | 11 22.92% 22.92% | 3 6.25% 29.17% | 3 6.25% 35.42% | 7 14.58% 50.00% | 20 41.67% 91.67% | 4 8.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist_seqr::total 48
-system.ruby.latency_hist_coalsr::bucket_size 128
-system.ruby.latency_hist_coalsr::max_bucket 1279
-system.ruby.latency_hist_coalsr::samples 858
-system.ruby.latency_hist_coalsr::mean 215.358974
-system.ruby.latency_hist_coalsr::gmean 107.894342
-system.ruby.latency_hist_coalsr::stdev 237.470134
-system.ruby.latency_hist_coalsr | 573 66.78% 66.78% | 36 4.20% 70.98% | 111 12.94% 83.92% | 37 4.31% 88.23% | 24 2.80% 91.03% | 19 2.21% 93.24% | 32 3.73% 96.97% | 23 2.68% 99.65% | 3 0.35% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist_coalsr::total 858
-system.ruby.hit_latency_hist_seqr::bucket_size 1024
-system.ruby.hit_latency_hist_seqr::max_bucket 10239
-system.ruby.hit_latency_hist_seqr::samples 42
-system.ruby.hit_latency_hist_seqr::mean 3644.142857
-system.ruby.hit_latency_hist_seqr::gmean 2737.850881
-system.ruby.hit_latency_hist_seqr::stdev 1757.652877
-system.ruby.hit_latency_hist_seqr | 7 16.67% 16.67% | 3 7.14% 23.81% | 1 2.38% 26.19% | 7 16.67% 42.86% | 20 47.62% 90.48% | 4 9.52% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist_seqr::total 42
-system.ruby.miss_latency_hist_seqr::bucket_size 512
-system.ruby.miss_latency_hist_seqr::max_bucket 5119
-system.ruby.miss_latency_hist_seqr::samples 6
-system.ruby.miss_latency_hist_seqr::mean 1017.833333
-system.ruby.miss_latency_hist_seqr::gmean 114.584426
-system.ruby.miss_latency_hist_seqr::stdev 1278.753677
-system.ruby.miss_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.miss_latency_hist_seqr::total 6
-system.ruby.miss_latency_hist_coalsr::bucket_size 128
-system.ruby.miss_latency_hist_coalsr::max_bucket 1279
-system.ruby.miss_latency_hist_coalsr::samples 858
-system.ruby.miss_latency_hist_coalsr::mean 215.358974
-system.ruby.miss_latency_hist_coalsr::gmean 107.894342
-system.ruby.miss_latency_hist_coalsr::stdev 237.470134
-system.ruby.miss_latency_hist_coalsr | 573 66.78% 66.78% | 36 4.20% 70.98% | 111 12.94% 83.92% | 37 4.31% 88.23% | 24 2.80% 91.03% | 19 2.21% 93.24% | 32 3.73% 96.97% | 23 2.68% 99.65% | 3 0.35% 100.00% | 0 0.00% 100.00%
-system.ruby.miss_latency_hist_coalsr::total 858
-system.ruby.L1Cache.incomplete_times_seqr 6
-system.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits
-system.cp_cntrl0.L1D0cache.demand_misses 45 # Number of cache demand misses
-system.cp_cntrl0.L1D0cache.demand_accesses 45 # Number of cache demand accesses
-system.cp_cntrl0.L1D0cache.num_data_array_writes 43 # number of data array writes
-system.cp_cntrl0.L1D0cache.num_tag_array_reads 155 # number of tag array reads
-system.cp_cntrl0.L1D0cache.num_tag_array_writes 41 # number of tag array writes
-system.cp_cntrl0.L1D1cache.demand_hits 0 # Number of cache demand hits
-system.cp_cntrl0.L1D1cache.demand_misses 45 # Number of cache demand misses
-system.cp_cntrl0.L1D1cache.demand_accesses 45 # Number of cache demand accesses
-system.cp_cntrl0.L1D1cache.num_data_array_writes 42 # number of data array writes
-system.cp_cntrl0.L1D1cache.num_tag_array_reads 74 # number of tag array reads
-system.cp_cntrl0.L1D1cache.num_tag_array_writes 42 # number of tag array writes
-system.cp_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
-system.cp_cntrl0.L1Icache.demand_misses 3 # Number of cache demand misses
-system.cp_cntrl0.L1Icache.demand_accesses 3 # Number of cache demand accesses
-system.cp_cntrl0.L1Icache.num_tag_array_reads 3 # number of tag array reads
-system.cp_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits
-system.cp_cntrl0.L2cache.demand_misses 93 # Number of cache demand misses
-system.cp_cntrl0.L2cache.demand_accesses 93 # Number of cache demand accesses
-system.cp_cntrl0.L2cache.num_data_array_reads 81 # number of data array reads
-system.cp_cntrl0.L2cache.num_data_array_writes 85 # number of data array writes
-system.cp_cntrl0.L2cache.num_tag_array_reads 372 # number of tag array reads
-system.cp_cntrl0.L2cache.num_tag_array_writes 362 # number of tag array writes
-system.cp_cntrl0.mandatoryQueue.avg_buf_msgs 25.716177 # Average number of messages in buffer
-system.cp_cntrl0.mandatoryQueue.avg_stall_time 2962.798293 # Average number of cycles messages are stalled in this MB
-system.cp_cntrl0.probeToCore.avg_buf_msgs 0.015627 # Average number of messages in buffer
-system.cp_cntrl0.probeToCore.avg_stall_time 33.503111 # Average number of cycles messages are stalled in this MB
-system.cp_cntrl0.requestFromCore.avg_buf_msgs 0.169512 # Average number of messages in buffer
-system.cp_cntrl0.requestFromCore.avg_stall_time 14.915352 # Average number of cycles messages are stalled in this MB
-system.cp_cntrl0.responseFromCore.avg_buf_msgs 0.311460 # Average number of messages in buffer
-system.cp_cntrl0.responseFromCore.avg_stall_time 14.764506 # Average number of cycles messages are stalled in this MB
-system.cp_cntrl0.responseToCore.avg_buf_msgs 0.011069 # Average number of messages in buffer
-system.cp_cntrl0.responseToCore.avg_stall_time 14.645999 # Average number of cycles messages are stalled in this MB
-system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.cp_cntrl0.sequencer.store_waiting_on_load 1 # Number of times a store aliased with a pending load
-system.cp_cntrl0.sequencer.store_waiting_on_store 4 # Number of times a store aliased with a pending store
-system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.cp_cntrl0.sequencer1.store_waiting_on_store 4 # Number of times a store aliased with a pending store
-system.cp_cntrl0.unblockFromCore.avg_buf_msgs 0.088699 # Average number of messages in buffer
-system.cp_cntrl0.unblockFromCore.avg_stall_time 14.634279 # Average number of cycles messages are stalled in this MB
-system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits
-system.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses
-system.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses
-system.dir_cntrl0.L3CacheMemory.num_data_array_writes 365 # number of data array writes
-system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 372 # number of tag array reads
-system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 369 # number of tag array writes
-system.dir_cntrl0.L3CacheMemory.num_tag_array_stalls 9126 # number of stalls caused by tag array
-system.dir_cntrl0.L3CacheMemory.num_data_array_stalls 4922 # number of stalls caused by data array
-system.dir_cntrl0.L3triggerQueue.avg_buf_msgs 0.048835 # Average number of messages in buffer
-system.dir_cntrl0.L3triggerQueue.avg_stall_time 12.961945 # Average number of cycles messages are stalled in this MB
-system.dir_cntrl0.probeToCore.avg_buf_msgs 0.653306 # Average number of messages in buffer
-system.dir_cntrl0.probeToCore.avg_stall_time 29.756909 # Average number of cycles messages are stalled in this MB
-system.dir_cntrl0.requestFromCores.avg_buf_msgs 4.168499 # Average number of messages in buffer
-system.dir_cntrl0.requestFromCores.avg_stall_time 219.183837 # Average number of cycles messages are stalled in this MB
-system.dir_cntrl0.requestFromCores.num_msg_stalls 6 # Number of times messages were stalled
-system.dir_cntrl0.responseFromCores.avg_buf_msgs 0.236001 # Average number of messages in buffer
-system.dir_cntrl0.responseFromCores.avg_stall_time 44.490812 # Average number of cycles messages are stalled in this MB
-system.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.033280 # Average number of messages in buffer
-system.dir_cntrl0.responseFromMemory.avg_stall_time 1.594198 # Average number of cycles messages are stalled in this MB
-system.dir_cntrl0.responseToCore.avg_buf_msgs 0.651932 # Average number of messages in buffer
-system.dir_cntrl0.responseToCore.avg_stall_time 21.888945 # Average number of cycles messages are stalled in this MB
-system.dir_cntrl0.triggerQueue.avg_buf_msgs 0.808711 # Average number of messages in buffer
-system.dir_cntrl0.triggerQueue.avg_stall_time 28.172406 # Average number of cycles messages are stalled in this MB
-system.dir_cntrl0.unblockFromCores.avg_buf_msgs 0.021343 # Average number of messages in buffer
-system.dir_cntrl0.unblockFromCores.avg_stall_time 89.749240 # Average number of cycles messages are stalled in this MB
-system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.ruby.network.ext_links00.int_node.port_buffers000.avg_buf_msgs 0.026914 # Average number of messages in buffer
-system.ruby.network.ext_links00.int_node.port_buffers000.avg_stall_time 83.794892 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links00.int_node.port_buffers002.avg_buf_msgs 0.026697 # Average number of messages in buffer
-system.ruby.network.ext_links00.int_node.port_buffers002.avg_stall_time 39.227029 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links00.int_node.port_buffers004.avg_buf_msgs 0.021343 # Average number of messages in buffer
-system.ruby.network.ext_links00.int_node.port_buffers004.avg_stall_time 88.782810 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links00.int_node.port_buffers005.avg_buf_msgs 0.015627 # Average number of messages in buffer
-system.ruby.network.ext_links00.int_node.port_buffers005.avg_stall_time 30.553683 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links00.int_node.port_buffers007.avg_buf_msgs 0.011069 # Average number of messages in buffer
-system.ruby.network.ext_links00.int_node.port_buffers007.avg_stall_time 11.722616 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links00.int_node.port_buffers015.avg_buf_msgs 0.006077 # Average number of messages in buffer
-system.ruby.network.ext_links00.int_node.port_buffers015.avg_stall_time 30.746563 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links00.int_node.port_buffers017.avg_buf_msgs 0.015627 # Average number of messages in buffer
-system.ruby.network.ext_links00.int_node.port_buffers017.avg_stall_time 30.419114 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links00.int_node.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.ruby.network.ext_links00.int_node.percent_links_utilized 0.199915
-system.ruby.network.ext_links00.int_node.msg_count.Control::0 300
-system.ruby.network.ext_links00.int_node.msg_count.Request_Control::0 372
-system.ruby.network.ext_links00.int_node.msg_count.Response_Data::2 383
-system.ruby.network.ext_links00.int_node.msg_count.Response_Control::2 217
-system.ruby.network.ext_links00.int_node.msg_count.Writeback_Data::2 67
-system.ruby.network.ext_links00.int_node.msg_count.Writeback_Control::2 71
-system.ruby.network.ext_links00.int_node.msg_count.Unblock_Control::4 295
-system.ruby.network.ext_links00.int_node.msg_bytes.Control::0 2400
-system.ruby.network.ext_links00.int_node.msg_bytes.Request_Control::0 2976
-system.ruby.network.ext_links00.int_node.msg_bytes.Response_Data::2 27576
-system.ruby.network.ext_links00.int_node.msg_bytes.Response_Control::2 1736
-system.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Data::2 4824
-system.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Control::2 568
-system.ruby.network.ext_links00.int_node.msg_bytes.Unblock_Control::4 2360
-system.ruby.network.ext_links01.int_node.port_buffers000.avg_buf_msgs 0.015627 # Average number of messages in buffer
-system.ruby.network.ext_links01.int_node.port_buffers000.avg_stall_time 32.520113 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links01.int_node.port_buffers002.avg_buf_msgs 0.011069 # Average number of messages in buffer
-system.ruby.network.ext_links01.int_node.port_buffers002.avg_stall_time 13.671683 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links01.int_node.port_buffers003.avg_buf_msgs 0.011214 # Average number of messages in buffer
-system.ruby.network.ext_links01.int_node.port_buffers003.avg_stall_time 15.908552 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links01.int_node.port_buffers005.avg_buf_msgs 0.020764 # Average number of messages in buffer
-system.ruby.network.ext_links01.int_node.port_buffers005.avg_stall_time 15.747649 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links01.int_node.port_buffers007.avg_buf_msgs 0.005860 # Average number of messages in buffer
-system.ruby.network.ext_links01.int_node.port_buffers007.avg_stall_time 15.608740 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links01.int_node.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.ruby.network.ext_links01.int_node.percent_links_utilized 0.123680
-system.ruby.network.ext_links01.int_node.msg_count.Control::0 216
-system.ruby.network.ext_links01.int_node.msg_count.Request_Control::0 155
-system.ruby.network.ext_links01.int_node.msg_count.Response_Data::2 95
-system.ruby.network.ext_links01.int_node.msg_count.Response_Control::2 207
-system.ruby.network.ext_links01.int_node.msg_count.Writeback_Data::2 67
-system.ruby.network.ext_links01.int_node.msg_count.Writeback_Control::2 71
-system.ruby.network.ext_links01.int_node.msg_count.Unblock_Control::4 81
-system.ruby.network.ext_links01.int_node.msg_bytes.Control::0 1728
-system.ruby.network.ext_links01.int_node.msg_bytes.Request_Control::0 1240
-system.ruby.network.ext_links01.int_node.msg_bytes.Response_Data::2 6840
-system.ruby.network.ext_links01.int_node.msg_bytes.Response_Control::2 1656
-system.ruby.network.ext_links01.int_node.msg_bytes.Writeback_Data::2 4824
-system.ruby.network.ext_links01.int_node.msg_bytes.Writeback_Control::2 568
-system.ruby.network.ext_links01.int_node.msg_bytes.Unblock_Control::4 648
-system.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits
-system.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses
-system.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses
-system.tcp_cntrl0.L1cache.num_data_array_reads 16 # number of data array reads
-system.tcp_cntrl0.L1cache.num_data_array_writes 112 # number of data array writes
-system.tcp_cntrl0.L1cache.num_tag_array_reads 309 # number of tag array reads
-system.tcp_cntrl0.L1cache.num_tag_array_writes 300 # number of tag array writes
-system.tcp_cntrl0.L1cache.num_tag_array_stalls 28 # number of stalls caused by tag array
-system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP
-system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 9 # TCP to TCP load transfers
-system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl0.coalescer.gpu_ld_misses 1 # loads that miss in the GPU
-system.tcp_cntrl0.coalescer.gpu_tcp_st_hits 9 # stores that hit in the TCP
-system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 74 # TCP to TCP store transfers
-system.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl0.coalescer.gpu_st_misses 19 # stores that miss in the GPU
-system.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP
-system.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers
-system.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl0.coalescer.cp_ld_misses 0 # loads that miss in the GPU
-system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP
-system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
-system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU
-system.tcp_cntrl0.mandatoryQueue.avg_buf_msgs 0.009767 # Average number of messages in buffer
-system.tcp_cntrl0.mandatoryQueue.avg_stall_time 1.140790 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl0.probeToTCP.avg_buf_msgs 0.007741 # Average number of messages in buffer
-system.tcp_cntrl0.probeToTCP.avg_stall_time 6.886268 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl0.requestFromTCP.avg_buf_msgs 0.308928 # Average number of messages in buffer
-system.tcp_cntrl0.requestFromTCP.avg_stall_time 39.646940 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl0.responseFromTCP.avg_buf_msgs 0.289249 # Average number of messages in buffer
-system.tcp_cntrl0.responseFromTCP.avg_stall_time 38.260744 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl0.responseToTCP.avg_buf_msgs 0.007597 # Average number of messages in buffer
-system.tcp_cntrl0.responseToTCP.avg_stall_time 2.919621 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.tcp_cntrl0.unblockFromCore.avg_buf_msgs 0.298076 # Average number of messages in buffer
-system.tcp_cntrl0.unblockFromCore.avg_stall_time 38.422804 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.ruby.network.ext_links02.int_node.port_buffers001.avg_buf_msgs 0.007235 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers001.avg_stall_time 5.756909 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers003.avg_buf_msgs 0.007452 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers003.avg_stall_time 1.927073 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers005.avg_buf_msgs 0.007018 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers005.avg_stall_time 5.309796 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers007.avg_buf_msgs 0.007018 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers007.avg_stall_time 1.940095 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers009.avg_buf_msgs 0.006656 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers009.avg_stall_time 5.861091 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers011.avg_buf_msgs 0.006945 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers011.avg_stall_time 1.961800 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers013.avg_buf_msgs 0.006222 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers013.avg_stall_time 5.483432 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers015.avg_buf_msgs 0.006367 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers015.avg_stall_time 1.879323 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers017.avg_buf_msgs 0.007524 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers017.avg_stall_time 5.492114 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers019.avg_buf_msgs 0.007452 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers019.avg_stall_time 1.931414 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers021.avg_buf_msgs 0.006367 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers021.avg_stall_time 5.539864 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers023.avg_buf_msgs 0.006656 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers023.avg_stall_time 1.957459 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers025.avg_buf_msgs 0.008031 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers025.avg_stall_time 5.544205 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers027.avg_buf_msgs 0.008320 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers027.avg_stall_time 1.947041 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers029.avg_buf_msgs 0.006439 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers029.avg_stall_time 5.457387 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers031.avg_buf_msgs 0.006728 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers031.avg_stall_time 1.901027 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers036.avg_buf_msgs 0.006077 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers036.avg_stall_time 32.725438 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers037.avg_buf_msgs 0.059543 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers037.avg_stall_time 41.896903 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers038.avg_buf_msgs 0.015627 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers038.avg_stall_time 32.376863 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers039.avg_buf_msgs 0.056794 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers039.avg_stall_time 40.742295 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers041.avg_buf_msgs 0.058602 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers041.avg_stall_time 41.125452 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers043.avg_buf_msgs 0.000796 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers043.avg_stall_time 2.867168 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers045.avg_buf_msgs 0.000868 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers045.avg_stall_time 1.317610 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers047.avg_buf_msgs 0.000796 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers047.avg_stall_time 3.139343 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers049.avg_buf_msgs 0.000868 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers049.avg_stall_time 1.151208 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers050.avg_buf_msgs 0.015700 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers050.avg_stall_time 119.555564 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers052.avg_buf_msgs 0.005933 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers052.avg_stall_time 118.925264 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.port_buffers054.avg_buf_msgs 0.015483 # Average number of messages in buffer
-system.ruby.network.ext_links02.int_node.port_buffers054.avg_stall_time 117.253220 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links02.int_node.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.ruby.network.ext_links02.int_node.percent_links_utilized 0.172944
-system.ruby.network.ext_links02.int_node.msg_count.Control::0 84
-system.ruby.network.ext_links02.int_node.msg_count.Control::1 789
-system.ruby.network.ext_links02.int_node.msg_count.Request_Control::0 217
-system.ruby.network.ext_links02.int_node.msg_count.Request_Control::1 823
-system.ruby.network.ext_links02.int_node.msg_count.Response_Data::2 288
-system.ruby.network.ext_links02.int_node.msg_count.Response_Data::3 1594
-system.ruby.network.ext_links02.int_node.msg_count.Response_Control::2 10
-system.ruby.network.ext_links02.int_node.msg_count.Response_Control::3 2
-system.ruby.network.ext_links02.int_node.msg_count.Unblock_Control::4 214
-system.ruby.network.ext_links02.int_node.msg_count.Unblock_Control::5 810
-system.ruby.network.ext_links02.int_node.msg_bytes.Control::0 672
-system.ruby.network.ext_links02.int_node.msg_bytes.Control::1 6312
-system.ruby.network.ext_links02.int_node.msg_bytes.Request_Control::0 1736
-system.ruby.network.ext_links02.int_node.msg_bytes.Request_Control::1 6584
-system.ruby.network.ext_links02.int_node.msg_bytes.Response_Data::2 20736
-system.ruby.network.ext_links02.int_node.msg_bytes.Response_Data::3 114768
-system.ruby.network.ext_links02.int_node.msg_bytes.Response_Control::2 80
-system.ruby.network.ext_links02.int_node.msg_bytes.Response_Control::3 16
-system.ruby.network.ext_links02.int_node.msg_bytes.Unblock_Control::4 1712
-system.ruby.network.ext_links02.int_node.msg_bytes.Unblock_Control::5 6480
-system.tcp_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits
-system.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses
-system.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses
-system.tcp_cntrl1.L1cache.num_data_array_reads 11 # number of data array reads
-system.tcp_cntrl1.L1cache.num_data_array_writes 108 # number of data array writes
-system.tcp_cntrl1.L1cache.num_tag_array_reads 298 # number of tag array reads
-system.tcp_cntrl1.L1cache.num_tag_array_writes 285 # number of tag array writes
-system.tcp_cntrl1.L1cache.num_tag_array_stalls 43 # number of stalls caused by tag array
-system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP
-system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 8 # TCP to TCP load transfers
-system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl1.coalescer.gpu_ld_misses 0 # loads that miss in the GPU
-system.tcp_cntrl1.coalescer.gpu_tcp_st_hits 11 # stores that hit in the TCP
-system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 69 # TCP to TCP store transfers
-system.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl1.coalescer.gpu_st_misses 20 # stores that miss in the GPU
-system.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP
-system.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers
-system.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl1.coalescer.cp_ld_misses 0 # loads that miss in the GPU
-system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP
-system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
-system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU
-system.tcp_cntrl1.mandatoryQueue.avg_buf_msgs 0.010491 # Average number of messages in buffer
-system.tcp_cntrl1.mandatoryQueue.avg_stall_time 1.432571 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl1.probeToTCP.avg_buf_msgs 0.007524 # Average number of messages in buffer
-system.tcp_cntrl1.probeToTCP.avg_stall_time 6.242584 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl1.requestFromTCP.avg_buf_msgs 0.289394 # Average number of messages in buffer
-system.tcp_cntrl1.requestFromTCP.avg_stall_time 39.762697 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl1.responseFromTCP.avg_buf_msgs 0.280712 # Average number of messages in buffer
-system.tcp_cntrl1.responseFromTCP.avg_stall_time 35.279988 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl1.responseToTCP.avg_buf_msgs 0.007235 # Average number of messages in buffer
-system.tcp_cntrl1.responseToTCP.avg_stall_time 2.914484 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.tcp_cntrl1.unblockFromCore.avg_buf_msgs 0.280712 # Average number of messages in buffer
-system.tcp_cntrl1.unblockFromCore.avg_stall_time 38.683259 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.tcp_cntrl2.L1cache.demand_hits 0 # Number of cache demand hits
-system.tcp_cntrl2.L1cache.demand_misses 0 # Number of cache demand misses
-system.tcp_cntrl2.L1cache.demand_accesses 0 # Number of cache demand accesses
-system.tcp_cntrl2.L1cache.num_data_array_reads 11 # number of data array reads
-system.tcp_cntrl2.L1cache.num_data_array_writes 106 # number of data array writes
-system.tcp_cntrl2.L1cache.num_tag_array_reads 286 # number of tag array reads
-system.tcp_cntrl2.L1cache.num_tag_array_writes 275 # number of tag array writes
-system.tcp_cntrl2.L1cache.num_tag_array_stalls 42 # number of stalls caused by tag array
-system.tcp_cntrl2.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.tcp_cntrl2.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP
-system.tcp_cntrl2.coalescer.gpu_tcp_ld_transfers 8 # TCP to TCP load transfers
-system.tcp_cntrl2.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl2.coalescer.gpu_ld_misses 1 # loads that miss in the GPU
-system.tcp_cntrl2.coalescer.gpu_tcp_st_hits 9 # stores that hit in the TCP
-system.tcp_cntrl2.coalescer.gpu_tcp_st_transfers 69 # TCP to TCP store transfers
-system.tcp_cntrl2.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl2.coalescer.gpu_st_misses 18 # stores that miss in the GPU
-system.tcp_cntrl2.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP
-system.tcp_cntrl2.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers
-system.tcp_cntrl2.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl2.coalescer.cp_ld_misses 0 # loads that miss in the GPU
-system.tcp_cntrl2.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP
-system.tcp_cntrl2.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
-system.tcp_cntrl2.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl2.coalescer.cp_st_misses 0 # stores that miss in the GPU
-system.tcp_cntrl2.mandatoryQueue.avg_buf_msgs 0.010418 # Average number of messages in buffer
-system.tcp_cntrl2.mandatoryQueue.avg_stall_time 1.277312 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl2.probeToTCP.avg_buf_msgs 0.006728 # Average number of messages in buffer
-system.tcp_cntrl2.probeToTCP.avg_stall_time 6.844596 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl2.requestFromTCP.avg_buf_msgs 0.280712 # Average number of messages in buffer
-system.tcp_cntrl2.requestFromTCP.avg_stall_time 39.878455 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl2.responseFromTCP.avg_buf_msgs 0.266242 # Average number of messages in buffer
-system.tcp_cntrl2.responseFromTCP.avg_stall_time 38.955289 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl2.responseToTCP.avg_buf_msgs 0.007307 # Average number of messages in buffer
-system.tcp_cntrl2.responseToTCP.avg_stall_time 2.965417 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.tcp_cntrl2.unblockFromCore.avg_buf_msgs 0.277818 # Average number of messages in buffer
-system.tcp_cntrl2.unblockFromCore.avg_stall_time 39.117349 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl2.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.tcp_cntrl3.L1cache.demand_hits 0 # Number of cache demand hits
-system.tcp_cntrl3.L1cache.demand_misses 0 # Number of cache demand misses
-system.tcp_cntrl3.L1cache.demand_accesses 0 # Number of cache demand accesses
-system.tcp_cntrl3.L1cache.num_data_array_reads 8 # number of data array reads
-system.tcp_cntrl3.L1cache.num_data_array_writes 95 # number of data array writes
-system.tcp_cntrl3.L1cache.num_tag_array_reads 260 # number of tag array reads
-system.tcp_cntrl3.L1cache.num_tag_array_writes 253 # number of tag array writes
-system.tcp_cntrl3.L1cache.num_tag_array_stalls 29 # number of stalls caused by tag array
-system.tcp_cntrl3.L1cache.num_data_array_stalls 3 # number of stalls caused by data array
-system.tcp_cntrl3.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.tcp_cntrl3.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP
-system.tcp_cntrl3.coalescer.gpu_tcp_ld_transfers 12 # TCP to TCP load transfers
-system.tcp_cntrl3.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl3.coalescer.gpu_ld_misses 0 # loads that miss in the GPU
-system.tcp_cntrl3.coalescer.gpu_tcp_st_hits 7 # stores that hit in the TCP
-system.tcp_cntrl3.coalescer.gpu_tcp_st_transfers 59 # TCP to TCP store transfers
-system.tcp_cntrl3.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl3.coalescer.gpu_st_misses 17 # stores that miss in the GPU
-system.tcp_cntrl3.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP
-system.tcp_cntrl3.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers
-system.tcp_cntrl3.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl3.coalescer.cp_ld_misses 0 # loads that miss in the GPU
-system.tcp_cntrl3.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP
-system.tcp_cntrl3.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
-system.tcp_cntrl3.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl3.coalescer.cp_st_misses 0 # stores that miss in the GPU
-system.tcp_cntrl3.mandatoryQueue.avg_buf_msgs 0.008465 # Average number of messages in buffer
-system.tcp_cntrl3.mandatoryQueue.avg_stall_time 1.170164 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl3.probeToTCP.avg_buf_msgs 0.006728 # Average number of messages in buffer
-system.tcp_cntrl3.probeToTCP.avg_stall_time 6.502170 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl3.requestFromTCP.avg_buf_msgs 0.261684 # Average number of messages in buffer
-system.tcp_cntrl3.requestFromTCP.avg_stall_time 39.039213 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl3.responseFromTCP.avg_buf_msgs 0.247504 # Average number of messages in buffer
-system.tcp_cntrl3.responseFromTCP.avg_stall_time 36.437563 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl3.responseToTCP.avg_buf_msgs 0.006801 # Average number of messages in buffer
-system.tcp_cntrl3.responseToTCP.avg_stall_time 2.855954 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.tcp_cntrl3.unblockFromCore.avg_buf_msgs 0.254666 # Average number of messages in buffer
-system.tcp_cntrl3.unblockFromCore.avg_stall_time 37.467805 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl3.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.tcp_cntrl4.L1cache.demand_hits 0 # Number of cache demand hits
-system.tcp_cntrl4.L1cache.demand_misses 0 # Number of cache demand misses
-system.tcp_cntrl4.L1cache.demand_accesses 0 # Number of cache demand accesses
-system.tcp_cntrl4.L1cache.num_data_array_reads 16 # number of data array reads
-system.tcp_cntrl4.L1cache.num_data_array_writes 117 # number of data array writes
-system.tcp_cntrl4.L1cache.num_tag_array_reads 309 # number of tag array reads
-system.tcp_cntrl4.L1cache.num_tag_array_writes 299 # number of tag array writes
-system.tcp_cntrl4.L1cache.num_tag_array_stalls 31 # number of stalls caused by tag array
-system.tcp_cntrl4.L1cache.num_data_array_stalls 4 # number of stalls caused by data array
-system.tcp_cntrl4.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.tcp_cntrl4.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP
-system.tcp_cntrl4.coalescer.gpu_tcp_ld_transfers 5 # TCP to TCP load transfers
-system.tcp_cntrl4.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl4.coalescer.gpu_ld_misses 0 # loads that miss in the GPU
-system.tcp_cntrl4.coalescer.gpu_tcp_st_hits 9 # stores that hit in the TCP
-system.tcp_cntrl4.coalescer.gpu_tcp_st_transfers 72 # TCP to TCP store transfers
-system.tcp_cntrl4.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl4.coalescer.gpu_st_misses 26 # stores that miss in the GPU
-system.tcp_cntrl4.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP
-system.tcp_cntrl4.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers
-system.tcp_cntrl4.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl4.coalescer.cp_ld_misses 0 # loads that miss in the GPU
-system.tcp_cntrl4.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP
-system.tcp_cntrl4.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
-system.tcp_cntrl4.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl4.coalescer.cp_st_misses 0 # stores that miss in the GPU
-system.tcp_cntrl4.mandatoryQueue.avg_buf_msgs 0.009478 # Average number of messages in buffer
-system.tcp_cntrl4.mandatoryQueue.avg_stall_time 1.107365 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl4.probeToTCP.avg_buf_msgs 0.008031 # Average number of messages in buffer
-system.tcp_cntrl4.probeToTCP.avg_stall_time 6.466141 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl4.requestFromTCP.avg_buf_msgs 0.298076 # Average number of messages in buffer
-system.tcp_cntrl4.requestFromTCP.avg_stall_time 39.733758 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl4.responseFromTCP.avg_buf_msgs 0.300969 # Average number of messages in buffer
-system.tcp_cntrl4.responseFromTCP.avg_stall_time 36.495442 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl4.responseToTCP.avg_buf_msgs 0.008175 # Average number of messages in buffer
-system.tcp_cntrl4.responseToTCP.avg_stall_time 2.934380 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.tcp_cntrl4.unblockFromCore.avg_buf_msgs 0.298076 # Average number of messages in buffer
-system.tcp_cntrl4.unblockFromCore.avg_stall_time 38.509622 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl4.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.tcp_cntrl5.L1cache.demand_hits 0 # Number of cache demand hits
-system.tcp_cntrl5.L1cache.demand_misses 0 # Number of cache demand misses
-system.tcp_cntrl5.L1cache.demand_accesses 0 # Number of cache demand accesses
-system.tcp_cntrl5.L1cache.num_data_array_reads 9 # number of data array reads
-system.tcp_cntrl5.L1cache.num_data_array_writes 101 # number of data array writes
-system.tcp_cntrl5.L1cache.num_tag_array_reads 276 # number of tag array reads
-system.tcp_cntrl5.L1cache.num_tag_array_writes 266 # number of tag array writes
-system.tcp_cntrl5.L1cache.num_tag_array_stalls 22 # number of stalls caused by tag array
-system.tcp_cntrl5.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.tcp_cntrl5.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP
-system.tcp_cntrl5.coalescer.gpu_tcp_ld_transfers 3 # TCP to TCP load transfers
-system.tcp_cntrl5.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl5.coalescer.gpu_ld_misses 0 # loads that miss in the GPU
-system.tcp_cntrl5.coalescer.gpu_tcp_st_hits 8 # stores that hit in the TCP
-system.tcp_cntrl5.coalescer.gpu_tcp_st_transfers 67 # TCP to TCP store transfers
-system.tcp_cntrl5.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl5.coalescer.gpu_st_misses 22 # stores that miss in the GPU
-system.tcp_cntrl5.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP
-system.tcp_cntrl5.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers
-system.tcp_cntrl5.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl5.coalescer.cp_ld_misses 0 # loads that miss in the GPU
-system.tcp_cntrl5.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP
-system.tcp_cntrl5.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
-system.tcp_cntrl5.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl5.coalescer.cp_st_misses 0 # stores that miss in the GPU
-system.tcp_cntrl5.mandatoryQueue.avg_buf_msgs 0.008465 # Average number of messages in buffer
-system.tcp_cntrl5.mandatoryQueue.avg_stall_time 1.079728 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl5.probeToTCP.avg_buf_msgs 0.006511 # Average number of messages in buffer
-system.tcp_cntrl5.probeToTCP.avg_stall_time 6.478585 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl5.requestFromTCP.avg_buf_msgs 0.269136 # Average number of messages in buffer
-system.tcp_cntrl5.requestFromTCP.avg_stall_time 39.849515 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl5.responseFromTCP.avg_buf_msgs 0.254015 # Average number of messages in buffer
-system.tcp_cntrl5.responseFromTCP.avg_stall_time 36.813775 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl5.responseToTCP.avg_buf_msgs 0.006945 # Average number of messages in buffer
-system.tcp_cntrl5.responseToTCP.avg_stall_time 2.959991 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.tcp_cntrl5.unblockFromCore.avg_buf_msgs 0.266242 # Average number of messages in buffer
-system.tcp_cntrl5.unblockFromCore.avg_stall_time 39.030531 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl5.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.tcp_cntrl6.L1cache.demand_hits 0 # Number of cache demand hits
-system.tcp_cntrl6.L1cache.demand_misses 0 # Number of cache demand misses
-system.tcp_cntrl6.L1cache.demand_accesses 0 # Number of cache demand accesses
-system.tcp_cntrl6.L1cache.num_data_array_reads 15 # number of data array reads
-system.tcp_cntrl6.L1cache.num_data_array_writes 120 # number of data array writes
-system.tcp_cntrl6.L1cache.num_tag_array_reads 336 # number of tag array reads
-system.tcp_cntrl6.L1cache.num_tag_array_writes 330 # number of tag array writes
-system.tcp_cntrl6.L1cache.num_tag_array_stalls 44 # number of stalls caused by tag array
-system.tcp_cntrl6.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.tcp_cntrl6.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP
-system.tcp_cntrl6.coalescer.gpu_tcp_ld_transfers 8 # TCP to TCP load transfers
-system.tcp_cntrl6.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl6.coalescer.gpu_ld_misses 1 # loads that miss in the GPU
-system.tcp_cntrl6.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP
-system.tcp_cntrl6.coalescer.gpu_tcp_st_transfers 86 # TCP to TCP store transfers
-system.tcp_cntrl6.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl6.coalescer.gpu_st_misses 20 # stores that miss in the GPU
-system.tcp_cntrl6.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP
-system.tcp_cntrl6.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers
-system.tcp_cntrl6.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl6.coalescer.cp_ld_misses 0 # loads that miss in the GPU
-system.tcp_cntrl6.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP
-system.tcp_cntrl6.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
-system.tcp_cntrl6.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl6.coalescer.cp_st_misses 0 # stores that miss in the GPU
-system.tcp_cntrl6.mandatoryQueue.avg_buf_msgs 0.010201 # Average number of messages in buffer
-system.tcp_cntrl6.mandatoryQueue.avg_stall_time 1.122414 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl6.probeToTCP.avg_buf_msgs 0.009405 # Average number of messages in buffer
-system.tcp_cntrl6.probeToTCP.avg_stall_time 6.666763 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl6.requestFromTCP.avg_buf_msgs 0.335697 # Average number of messages in buffer
-system.tcp_cntrl6.requestFromTCP.avg_stall_time 39.618000 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl6.responseFromTCP.avg_buf_msgs 0.321227 # Average number of messages in buffer
-system.tcp_cntrl6.responseFromTCP.avg_stall_time 36.842715 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl6.responseToTCP.avg_buf_msgs 0.008682 # Average number of messages in buffer
-system.tcp_cntrl6.responseToTCP.avg_stall_time 2.959051 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.tcp_cntrl6.unblockFromCore.avg_buf_msgs 0.331718 # Average number of messages in buffer
-system.tcp_cntrl6.unblockFromCore.avg_stall_time 38.822168 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl6.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.tcp_cntrl7.L1cache.demand_hits 0 # Number of cache demand hits
-system.tcp_cntrl7.L1cache.demand_misses 0 # Number of cache demand misses
-system.tcp_cntrl7.L1cache.demand_accesses 0 # Number of cache demand accesses
-system.tcp_cntrl7.L1cache.num_data_array_reads 13 # number of data array reads
-system.tcp_cntrl7.L1cache.num_data_array_writes 101 # number of data array writes
-system.tcp_cntrl7.L1cache.num_tag_array_reads 275 # number of tag array reads
-system.tcp_cntrl7.L1cache.num_tag_array_writes 266 # number of tag array writes
-system.tcp_cntrl7.L1cache.num_tag_array_stalls 11 # number of stalls caused by tag array
-system.tcp_cntrl7.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.tcp_cntrl7.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP
-system.tcp_cntrl7.coalescer.gpu_tcp_ld_transfers 9 # TCP to TCP load transfers
-system.tcp_cntrl7.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl7.coalescer.gpu_ld_misses 0 # loads that miss in the GPU
-system.tcp_cntrl7.coalescer.gpu_tcp_st_hits 7 # stores that hit in the TCP
-system.tcp_cntrl7.coalescer.gpu_tcp_st_transfers 66 # TCP to TCP store transfers
-system.tcp_cntrl7.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl7.coalescer.gpu_st_misses 18 # stores that miss in the GPU
-system.tcp_cntrl7.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP
-system.tcp_cntrl7.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers
-system.tcp_cntrl7.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl7.coalescer.cp_ld_misses 0 # loads that miss in the GPU
-system.tcp_cntrl7.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP
-system.tcp_cntrl7.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
-system.tcp_cntrl7.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl7.coalescer.cp_st_misses 0 # stores that miss in the GPU
-system.tcp_cntrl7.mandatoryQueue.avg_buf_msgs 0.008103 # Average number of messages in buffer
-system.tcp_cntrl7.mandatoryQueue.avg_stall_time 1.097743 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl7.probeToTCP.avg_buf_msgs 0.006511 # Average number of messages in buffer
-system.tcp_cntrl7.probeToTCP.avg_stall_time 6.394371 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl7.requestFromTCP.avg_buf_msgs 0.272030 # Average number of messages in buffer
-system.tcp_cntrl7.requestFromTCP.avg_stall_time 39.357546 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl7.responseFromTCP.avg_buf_msgs 0.254739 # Average number of messages in buffer
-system.tcp_cntrl7.responseFromTCP.avg_stall_time 36.263927 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl7.responseToTCP.avg_buf_msgs 0.006801 # Average number of messages in buffer
-system.tcp_cntrl7.responseToTCP.avg_stall_time 2.863696 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.tcp_cntrl7.unblockFromCore.avg_buf_msgs 0.269136 # Average number of messages in buffer
-system.tcp_cntrl7.unblockFromCore.avg_stall_time 37.901896 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl7.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits
-system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses
-system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses
-system.sqc_cntrl0.L1cache.num_data_array_reads 12 # number of data array reads
-system.sqc_cntrl0.L1cache.num_data_array_writes 12 # number of data array writes
-system.sqc_cntrl0.L1cache.num_tag_array_reads 23 # number of tag array reads
-system.sqc_cntrl0.L1cache.num_tag_array_writes 23 # number of tag array writes
-system.sqc_cntrl0.mandatoryQueue.avg_buf_msgs 0.000868 # Average number of messages in buffer
-system.sqc_cntrl0.mandatoryQueue.avg_stall_time 0.668499 # Average number of cycles messages are stalled in this MB
-system.sqc_cntrl0.probeToSQC.avg_buf_msgs 0.000796 # Average number of messages in buffer
-system.sqc_cntrl0.probeToSQC.avg_stall_time 3.344523 # Average number of cycles messages are stalled in this MB
-system.sqc_cntrl0.requestFromSQC.avg_buf_msgs 0.069454 # Average number of messages in buffer
-system.sqc_cntrl0.requestFromSQC.avg_stall_time 53.016930 # Average number of cycles messages are stalled in this MB
-system.sqc_cntrl0.responseFromSQC.avg_buf_msgs 0.063667 # Average number of messages in buffer
-system.sqc_cntrl0.responseFromSQC.avg_stall_time 37.760093 # Average number of cycles messages are stalled in this MB
-system.sqc_cntrl0.responseToSQC.avg_buf_msgs 0.000868 # Average number of messages in buffer
-system.sqc_cntrl0.responseToSQC.avg_stall_time 1.976197 # Average number of cycles messages are stalled in this MB
-system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.sqc_cntrl0.unblockFromCore.avg_buf_msgs 0.069454 # Average number of messages in buffer
-system.sqc_cntrl0.unblockFromCore.avg_stall_time 52.235566 # Average number of cycles messages are stalled in this MB
-system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.sqc_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits
-system.sqc_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses
-system.sqc_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses
-system.sqc_cntrl1.L1cache.num_data_array_reads 12 # number of data array reads
-system.sqc_cntrl1.L1cache.num_data_array_writes 12 # number of data array writes
-system.sqc_cntrl1.L1cache.num_tag_array_reads 23 # number of tag array reads
-system.sqc_cntrl1.L1cache.num_tag_array_writes 23 # number of tag array writes
-system.sqc_cntrl1.mandatoryQueue.avg_buf_msgs 0.000868 # Average number of messages in buffer
-system.sqc_cntrl1.mandatoryQueue.avg_stall_time 0.585299 # Average number of cycles messages are stalled in this MB
-system.sqc_cntrl1.probeToSQC.avg_buf_msgs 0.000796 # Average number of messages in buffer
-system.sqc_cntrl1.probeToSQC.avg_stall_time 3.662060 # Average number of cycles messages are stalled in this MB
-system.sqc_cntrl1.requestFromSQC.avg_buf_msgs 0.069454 # Average number of messages in buffer
-system.sqc_cntrl1.requestFromSQC.avg_stall_time 46.360874 # Average number of cycles messages are stalled in this MB
-system.sqc_cntrl1.responseFromSQC.avg_buf_msgs 0.063667 # Average number of messages in buffer
-system.sqc_cntrl1.responseFromSQC.avg_stall_time 41.389090 # Average number of cycles messages are stalled in this MB
-system.sqc_cntrl1.responseToSQC.avg_buf_msgs 0.000868 # Average number of messages in buffer
-system.sqc_cntrl1.responseToSQC.avg_stall_time 1.726595 # Average number of cycles messages are stalled in this MB
-system.sqc_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.sqc_cntrl1.unblockFromCore.avg_buf_msgs 0.069454 # Average number of messages in buffer
-system.sqc_cntrl1.unblockFromCore.avg_stall_time 45.579511 # Average number of cycles messages are stalled in this MB
-system.sqc_cntrl1.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits
-system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses
-system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses
-system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits
-system.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses
-system.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses
-system.tccdir_cntrl0.directory.num_tag_array_reads 896 # number of tag array reads
-system.tccdir_cntrl0.directory.num_tag_array_writes 882 # number of tag array writes
-system.tccdir_cntrl0.probeFromNB.avg_buf_msgs 0.035740 # Average number of messages in buffer
-system.tccdir_cntrl0.probeFromNB.avg_stall_time 35.754884 # Average number of cycles messages are stalled in this MB
-system.tccdir_cntrl0.probeToCore.avg_buf_msgs 0.265157 # Average number of messages in buffer
-system.tccdir_cntrl0.probeToCore.avg_stall_time 4.884604 # Average number of cycles messages are stalled in this MB
-system.tccdir_cntrl0.requestFromTCP.avg_buf_msgs 1.395239 # Average number of messages in buffer
-system.tccdir_cntrl0.requestFromTCP.avg_stall_time 55.396180 # Average number of cycles messages are stalled in this MB
-system.tccdir_cntrl0.requestToNB.avg_buf_msgs 1.900159 # Average number of messages in buffer
-system.tccdir_cntrl0.requestToNB.avg_stall_time 118.576183 # Average number of cycles messages are stalled in this MB
-system.tccdir_cntrl0.responseFromNB.avg_buf_msgs 0.015627 # Average number of messages in buffer
-system.tccdir_cntrl0.responseFromNB.avg_stall_time 33.355520 # Average number of cycles messages are stalled in this MB
-system.tccdir_cntrl0.responseFromTCP.avg_buf_msgs 0.056794 # Average number of messages in buffer
-system.tccdir_cntrl0.responseFromTCP.avg_stall_time 41.713066 # Average number of cycles messages are stalled in this MB
-system.tccdir_cntrl0.responseToCore.avg_buf_msgs 0.058602 # Average number of messages in buffer
-system.tccdir_cntrl0.responseToCore.avg_stall_time 0.980972 # Average number of cycles messages are stalled in this MB
-system.tccdir_cntrl0.responseToNB.avg_buf_msgs 0.718203 # Average number of messages in buffer
-system.tccdir_cntrl0.responseToNB.avg_stall_time 117.951092 # Average number of cycles messages are stalled in this MB
-system.tccdir_cntrl0.triggerQueue.avg_buf_msgs 0.052814 # Average number of messages in buffer
-system.tccdir_cntrl0.triggerQueue.avg_stall_time 0.973665 # Average number of cycles messages are stalled in this MB
-system.tccdir_cntrl0.unblockFromTCP.avg_buf_msgs 0.058602 # Average number of messages in buffer
-system.tccdir_cntrl0.unblockFromTCP.avg_stall_time 42.100275 # Average number of cycles messages are stalled in this MB
-system.tccdir_cntrl0.unblockToNB.avg_buf_msgs 1.864274 # Average number of messages in buffer
-system.tccdir_cntrl0.unblockToNB.avg_stall_time 116.292866 # Average number of cycles messages are stalled in this MB
-system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.ruby.network.int_link_buffers00.avg_buf_msgs 0.015627 # Average number of messages in buffer
-system.ruby.network.int_link_buffers00.avg_stall_time 31.536970 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers02.avg_buf_msgs 0.011069 # Average number of messages in buffer
-system.ruby.network.int_link_buffers02.avg_stall_time 12.697222 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers10.avg_buf_msgs 0.006077 # Average number of messages in buffer
-system.ruby.network.int_link_buffers10.avg_stall_time 31.736073 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers12.avg_buf_msgs 0.015627 # Average number of messages in buffer
-system.ruby.network.int_link_buffers12.avg_stall_time 31.398061 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers20.avg_buf_msgs 0.011214 # Average number of messages in buffer
-system.ruby.network.int_link_buffers20.avg_stall_time 16.901606 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers22.avg_buf_msgs 0.020764 # Average number of messages in buffer
-system.ruby.network.int_link_buffers22.avg_stall_time 16.730647 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers24.avg_buf_msgs 0.005860 # Average number of messages in buffer
-system.ruby.network.int_link_buffers24.avg_stall_time 16.583056 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers30.avg_buf_msgs 0.015700 # Average number of messages in buffer
-system.ruby.network.int_link_buffers30.avg_stall_time 120.534800 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers32.avg_buf_msgs 0.005933 # Average number of messages in buffer
-system.ruby.network.int_link_buffers32.avg_stall_time 119.899291 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers34.avg_buf_msgs 0.015483 # Average number of messages in buffer
-system.ruby.network.int_link_buffers34.avg_stall_time 118.213428 # Average number of cycles messages are stalled in this MB
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.ruby.network.msg_count.Control 1389
-system.ruby.network.msg_count.Request_Control 1567
-system.ruby.network.msg_count.Response_Data 2360
-system.ruby.network.msg_count.Response_Control 436
-system.ruby.network.msg_count.Writeback_Data 134
-system.ruby.network.msg_count.Writeback_Control 142
-system.ruby.network.msg_count.Unblock_Control 1400
-system.ruby.network.msg_byte.Control 11112
-system.ruby.network.msg_byte.Request_Control 12536
-system.ruby.network.msg_byte.Response_Data 169920
-system.ruby.network.msg_byte.Response_Control 3488
-system.ruby.network.msg_byte.Writeback_Data 9648
-system.ruby.network.msg_byte.Writeback_Control 1136
-system.ruby.network.msg_byte.Unblock_Control 11200
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states
-system.ruby.network.ext_links00.int_node.throttle0.link_utilization 0.254594
-system.ruby.network.ext_links00.int_node.throttle0.msg_count.Request_Control::0 372
-system.ruby.network.ext_links00.int_node.throttle0.msg_count.Response_Data::2 85
-system.ruby.network.ext_links00.int_node.throttle0.msg_count.Response_Control::2 217
-system.ruby.network.ext_links00.int_node.throttle0.msg_count.Writeback_Data::2 67
-system.ruby.network.ext_links00.int_node.throttle0.msg_count.Unblock_Control::4 295
-system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Request_Control::0 2976
-system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Response_Data::2 6120
-system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Response_Control::2 1736
-system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Writeback_Data::2 4824
-system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Unblock_Control::4 2360
-system.ruby.network.ext_links00.int_node.throttle1.link_utilization 0.115879
-system.ruby.network.ext_links00.int_node.throttle1.msg_count.Control::0 216
-system.ruby.network.ext_links00.int_node.throttle1.msg_count.Response_Data::2 82
-system.ruby.network.ext_links00.int_node.throttle1.msg_count.Writeback_Control::2 71
-system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Control::0 1728
-system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Response_Data::2 5904
-system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Writeback_Control::2 568
-system.ruby.network.ext_links00.int_node.throttle2.link_utilization 0.229271
-system.ruby.network.ext_links00.int_node.throttle2.msg_count.Control::0 84
-system.ruby.network.ext_links00.int_node.throttle2.msg_count.Response_Data::2 216
-system.ruby.network.ext_links00.int_node.throttle2.msg_bytes.Control::0 672
-system.ruby.network.ext_links00.int_node.throttle2.msg_bytes.Response_Data::2 15552
-system.ruby.network.ext_links01.int_node.throttle0.link_utilization 0.115879
-system.ruby.network.ext_links01.int_node.throttle0.msg_count.Control::0 216
-system.ruby.network.ext_links01.int_node.throttle0.msg_count.Response_Data::2 82
-system.ruby.network.ext_links01.int_node.throttle0.msg_count.Writeback_Control::2 71
-system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Control::0 1728
-system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Response_Data::2 5904
-system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Writeback_Control::2 568
-system.ruby.network.ext_links01.int_node.throttle1.link_utilization 0.131480
-system.ruby.network.ext_links01.int_node.throttle1.msg_count.Request_Control::0 155
-system.ruby.network.ext_links01.int_node.throttle1.msg_count.Response_Data::2 13
-system.ruby.network.ext_links01.int_node.throttle1.msg_count.Response_Control::2 207
-system.ruby.network.ext_links01.int_node.throttle1.msg_count.Writeback_Data::2 67
-system.ruby.network.ext_links01.int_node.throttle1.msg_count.Unblock_Control::4 81
-system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Request_Control::0 1240
-system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Response_Data::2 936
-system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Response_Control::2 1656
-system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Writeback_Data::2 4824
-system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Unblock_Control::4 648
-system.ruby.network.ext_links02.int_node.throttle0.link_utilization 0.116105
-system.ruby.network.ext_links02.int_node.throttle0.msg_count.Control::1 100
-system.ruby.network.ext_links02.int_node.throttle0.msg_count.Response_Data::3 103
-system.ruby.network.ext_links02.int_node.throttle0.msg_bytes.Control::1 800
-system.ruby.network.ext_links02.int_node.throttle0.msg_bytes.Response_Data::3 7416
-system.ruby.network.ext_links02.int_node.throttle1.link_utilization 0.109661
-system.ruby.network.ext_links02.int_node.throttle1.msg_count.Control::1 97
-system.ruby.network.ext_links02.int_node.throttle1.msg_count.Response_Data::3 97
-system.ruby.network.ext_links02.int_node.throttle1.msg_bytes.Control::1 776
-system.ruby.network.ext_links02.int_node.throttle1.msg_bytes.Response_Data::3 6984
-system.ruby.network.ext_links02.int_node.throttle2.link_utilization 0.108078
-system.ruby.network.ext_links02.int_node.throttle2.msg_count.Control::1 92
-system.ruby.network.ext_links02.int_node.throttle2.msg_count.Response_Data::3 96
-system.ruby.network.ext_links02.int_node.throttle2.msg_bytes.Control::1 736
-system.ruby.network.ext_links02.int_node.throttle2.msg_bytes.Response_Data::3 6912
-system.ruby.network.ext_links02.int_node.throttle3.link_utilization 0.099260
-system.ruby.network.ext_links02.int_node.throttle3.msg_count.Control::1 86
-system.ruby.network.ext_links02.int_node.throttle3.msg_count.Response_Data::3 88
-system.ruby.network.ext_links02.int_node.throttle3.msg_bytes.Control::1 688
-system.ruby.network.ext_links02.int_node.throttle3.msg_bytes.Response_Data::3 6336
-system.ruby.network.ext_links02.int_node.throttle4.link_utilization 0.116557
-system.ruby.network.ext_links02.int_node.throttle4.msg_count.Control::1 104
-system.ruby.network.ext_links02.int_node.throttle4.msg_count.Response_Data::3 103
-system.ruby.network.ext_links02.int_node.throttle4.msg_bytes.Control::1 832
-system.ruby.network.ext_links02.int_node.throttle4.msg_bytes.Response_Data::3 7416
-system.ruby.network.ext_links02.int_node.throttle5.link_utilization 0.103556
-system.ruby.network.ext_links02.int_node.throttle5.msg_count.Control::1 88
-system.ruby.network.ext_links02.int_node.throttle5.msg_count.Response_Data::3 92
-system.ruby.network.ext_links02.int_node.throttle5.msg_bytes.Control::1 704
-system.ruby.network.ext_links02.int_node.throttle5.msg_bytes.Response_Data::3 6624
-system.ruby.network.ext_links02.int_node.throttle6.link_utilization 0.129558
-system.ruby.network.ext_links02.int_node.throttle6.msg_count.Control::1 111
-system.ruby.network.ext_links02.int_node.throttle6.msg_count.Response_Data::3 115
-system.ruby.network.ext_links02.int_node.throttle6.msg_bytes.Control::1 888
-system.ruby.network.ext_links02.int_node.throttle6.msg_bytes.Response_Data::3 8280
-system.ruby.network.ext_links02.int_node.throttle7.link_utilization 0.104687
-system.ruby.network.ext_links02.int_node.throttle7.msg_count.Control::1 89
-system.ruby.network.ext_links02.int_node.throttle7.msg_count.Response_Data::3 93
-system.ruby.network.ext_links02.int_node.throttle7.msg_bytes.Control::1 712
-system.ruby.network.ext_links02.int_node.throttle7.msg_bytes.Response_Data::3 6696
-system.ruby.network.ext_links02.int_node.throttle8.link_utilization 0
-system.ruby.network.ext_links02.int_node.throttle9.link_utilization 1.210793
-system.ruby.network.ext_links02.int_node.throttle9.msg_count.Control::0 84
-system.ruby.network.ext_links02.int_node.throttle9.msg_count.Request_Control::1 823
-system.ruby.network.ext_links02.int_node.throttle9.msg_count.Response_Data::2 216
-system.ruby.network.ext_links02.int_node.throttle9.msg_count.Response_Data::3 783
-system.ruby.network.ext_links02.int_node.throttle9.msg_count.Response_Control::3 2
-system.ruby.network.ext_links02.int_node.throttle9.msg_count.Unblock_Control::5 810
-system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Control::0 672
-system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Request_Control::1 6584
-system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Response_Data::2 15552
-system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Response_Data::3 56376
-system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Response_Control::3 16
-system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Unblock_Control::5 6480
-system.ruby.network.ext_links02.int_node.throttle10.link_utilization 0.013453
-system.ruby.network.ext_links02.int_node.throttle10.msg_count.Control::1 11
-system.ruby.network.ext_links02.int_node.throttle10.msg_count.Response_Data::3 12
-system.ruby.network.ext_links02.int_node.throttle10.msg_bytes.Control::1 88
-system.ruby.network.ext_links02.int_node.throttle10.msg_bytes.Response_Data::3 864
-system.ruby.network.ext_links02.int_node.throttle11.link_utilization 0.013453
-system.ruby.network.ext_links02.int_node.throttle11.msg_count.Control::1 11
-system.ruby.network.ext_links02.int_node.throttle11.msg_count.Response_Data::3 12
-system.ruby.network.ext_links02.int_node.throttle11.msg_bytes.Control::1 88
-system.ruby.network.ext_links02.int_node.throttle11.msg_bytes.Response_Data::3 864
-system.ruby.network.ext_links02.int_node.throttle12.link_utilization 0.123114
-system.ruby.network.ext_links02.int_node.throttle12.msg_count.Request_Control::0 217
-system.ruby.network.ext_links02.int_node.throttle12.msg_count.Response_Data::2 72
-system.ruby.network.ext_links02.int_node.throttle12.msg_count.Response_Control::2 10
-system.ruby.network.ext_links02.int_node.throttle12.msg_count.Unblock_Control::4 214
-system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Request_Control::0 1736
-system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Response_Data::2 5184
-system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Response_Control::2 80
-system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Unblock_Control::4 1712
-system.ruby.CorePair_Controller.C0_Load_L1miss 1 0.00% 0.00%
-system.ruby.CorePair_Controller.C1_Load_L1miss 2 0.00% 0.00%
-system.ruby.CorePair_Controller.Ifetch0_L1miss 2 0.00% 0.00%
-system.ruby.CorePair_Controller.Ifetch1_L1miss 1 0.00% 0.00%
-system.ruby.CorePair_Controller.C0_Store_L1miss 45 0.00% 0.00%
-system.ruby.CorePair_Controller.C0_Store_L1hit 2 0.00% 0.00%
-system.ruby.CorePair_Controller.C1_Store_L1miss 72 0.00% 0.00%
-system.ruby.CorePair_Controller.NB_AckS 4 0.00% 0.00%
-system.ruby.CorePair_Controller.NB_AckM 78 0.00% 0.00%
-system.ruby.CorePair_Controller.NB_AckWB 71 0.00% 0.00%
-system.ruby.CorePair_Controller.L1D0_Repl 11 0.00% 0.00%
-system.ruby.CorePair_Controller.L2_Repl 35555 0.00% 0.00%
-system.ruby.CorePair_Controller.PrbInvData 212 0.00% 0.00%
-system.ruby.CorePair_Controller.PrbShrData 4 0.00% 0.00%
-system.ruby.CorePair_Controller.I.C0_Load_L1miss 1 0.00% 0.00%
-system.ruby.CorePair_Controller.I.C1_Load_L1miss 2 0.00% 0.00%
-system.ruby.CorePair_Controller.I.Ifetch0_L1miss 2 0.00% 0.00%
-system.ruby.CorePair_Controller.I.Ifetch1_L1miss 1 0.00% 0.00%
-system.ruby.CorePair_Controller.I.C0_Store_L1miss 41 0.00% 0.00%
-system.ruby.CorePair_Controller.I.C1_Store_L1miss 38 0.00% 0.00%
-system.ruby.CorePair_Controller.I.PrbInvData 198 0.00% 0.00%
-system.ruby.CorePair_Controller.I.PrbShrData 4 0.00% 0.00%
-system.ruby.CorePair_Controller.S.L2_Repl 3 0.00% 0.00%
-system.ruby.CorePair_Controller.S.PrbInvData 1 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.C0_Store_L1hit 2 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.L2_Repl 33 0.00% 0.00%
-system.ruby.CorePair_Controller.M0.PrbInvData 6 0.00% 0.00%
-system.ruby.CorePair_Controller.M1.C0_Store_L1miss 1 0.00% 0.00%
-system.ruby.CorePair_Controller.M1.L2_Repl 36 0.00% 0.00%
-system.ruby.CorePair_Controller.M1.PrbInvData 3 0.00% 0.00%
-system.ruby.CorePair_Controller.I_M0.C1_Store_L1miss 5 0.00% 0.00%
-system.ruby.CorePair_Controller.I_M0.NB_AckM 35 0.00% 0.00%
-system.ruby.CorePair_Controller.I_M0.L1D0_Repl 11 0.00% 0.00%
-system.ruby.CorePair_Controller.I_M0.L2_Repl 15350 0.00% 0.00%
-system.ruby.CorePair_Controller.I_M1.C0_Store_L1miss 3 0.00% 0.00%
-system.ruby.CorePair_Controller.I_M1.NB_AckM 35 0.00% 0.00%
-system.ruby.CorePair_Controller.I_M1.L2_Repl 14410 0.00% 0.00%
-system.ruby.CorePair_Controller.I_M0M1.NB_AckM 5 0.00% 0.00%
-system.ruby.CorePair_Controller.I_M0M1.L2_Repl 3283 0.00% 0.00%
-system.ruby.CorePair_Controller.I_M1M0.NB_AckM 3 0.00% 0.00%
-system.ruby.CorePair_Controller.I_M1M0.L2_Repl 1200 0.00% 0.00%
-system.ruby.CorePair_Controller.I_E0S.NB_AckS 1 0.00% 0.00%
-system.ruby.CorePair_Controller.I_E0S.L2_Repl 404 0.00% 0.00%
-system.ruby.CorePair_Controller.I_E1S.NB_AckS 1 0.00% 0.00%
-system.ruby.CorePair_Controller.I_E1S.L2_Repl 392 0.00% 0.00%
-system.ruby.CorePair_Controller.ES_I.NB_AckWB 2 0.00% 0.00%
-system.ruby.CorePair_Controller.MO_I.NB_AckWB 65 0.00% 0.00%
-system.ruby.CorePair_Controller.MO_I.PrbInvData 4 0.00% 0.00%
-system.ruby.CorePair_Controller.S0.C1_Store_L1miss 29 0.00% 0.00%
-system.ruby.CorePair_Controller.S0.NB_AckS 1 0.00% 0.00%
-system.ruby.CorePair_Controller.S0.L2_Repl 444 0.00% 0.00%
-system.ruby.CorePair_Controller.S1.NB_AckS 1 0.00% 0.00%
-system.ruby.CorePair_Controller.I_C.NB_AckWB 4 0.00% 0.00%
-system.ruby.Directory_Controller.RdBlkS 4 0.00% 0.00%
-system.ruby.Directory_Controller.RdBlkM 297 0.00% 0.00%
-system.ruby.Directory_Controller.RdBlk 6 0.00% 0.00%
-system.ruby.Directory_Controller.VicDirty 69 0.00% 0.00%
-system.ruby.Directory_Controller.VicClean 2 0.00% 0.00%
-system.ruby.Directory_Controller.CPUData 67 0.00% 0.00%
-system.ruby.Directory_Controller.StaleWB 4 0.00% 0.00%
-system.ruby.Directory_Controller.CPUPrbResp 298 0.00% 0.00%
-system.ruby.Directory_Controller.ProbeAcksComplete 298 0.00% 0.00%
-system.ruby.Directory_Controller.L3Hit 45 0.00% 0.00%
-system.ruby.Directory_Controller.MemData 256 0.00% 0.00%
-system.ruby.Directory_Controller.WBAck 14 0.00% 0.00%
-system.ruby.Directory_Controller.CoreUnblock 295 0.00% 0.00%
-system.ruby.Directory_Controller.U.RdBlkS 4 0.00% 0.00%
-system.ruby.Directory_Controller.U.RdBlkM 291 0.00% 0.00%
-system.ruby.Directory_Controller.U.RdBlk 6 0.00% 0.00%
-system.ruby.Directory_Controller.U.VicDirty 69 0.00% 0.00%
-system.ruby.Directory_Controller.U.VicClean 2 0.00% 0.00%
-system.ruby.Directory_Controller.U.WBAck 14 0.00% 0.00%
-system.ruby.Directory_Controller.BL.CPUData 67 0.00% 0.00%
-system.ruby.Directory_Controller.BL.StaleWB 4 0.00% 0.00%
-system.ruby.Directory_Controller.BM_M.MemData 9 0.00% 0.00%
-system.ruby.Directory_Controller.BS_PM.L3Hit 1 0.00% 0.00%
-system.ruby.Directory_Controller.BS_PM.MemData 3 0.00% 0.00%
-system.ruby.Directory_Controller.BM_PM.RdBlkM 1 0.00% 0.00%
-system.ruby.Directory_Controller.BM_PM.CPUPrbResp 13 0.00% 0.00%
-system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 9 0.00% 0.00%
-system.ruby.Directory_Controller.BM_PM.L3Hit 41 0.00% 0.00%
-system.ruby.Directory_Controller.BM_PM.MemData 241 0.00% 0.00%
-system.ruby.Directory_Controller.B_PM.L3Hit 3 0.00% 0.00%
-system.ruby.Directory_Controller.B_PM.MemData 3 0.00% 0.00%
-system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 3 0.00% 0.00%
-system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 3 0.00% 0.00%
-system.ruby.Directory_Controller.BM_Pm.RdBlkM 3 0.00% 0.00%
-system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 277 0.00% 0.00%
-system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 281 0.00% 0.00%
-system.ruby.Directory_Controller.B_Pm.CPUPrbResp 5 0.00% 0.00%
-system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 5 0.00% 0.00%
-system.ruby.Directory_Controller.B.RdBlkM 2 0.00% 0.00%
-system.ruby.Directory_Controller.B.CoreUnblock 295 0.00% 0.00%
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-system.ruby.LD.latency_hist_seqr::samples 1
-system.ruby.LD.latency_hist_seqr::mean 5256
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-system.ruby.LD.latency_hist_seqr::stdev nan
-system.ruby.LD.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.latency_hist_seqr::total 1
-system.ruby.LD.latency_hist_coalsr::bucket_size 64
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-system.ruby.LD.latency_hist_coalsr::samples 72
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-system.ruby.LD.latency_hist_coalsr::gmean 68.071118
-system.ruby.LD.latency_hist_coalsr::stdev 67.272969
-system.ruby.LD.latency_hist_coalsr | 7 9.72% 9.72% | 60 83.33% 93.06% | 1 1.39% 94.44% | 0 0.00% 94.44% | 3 4.17% 98.61% | 0 0.00% 98.61% | 0 0.00% 98.61% | 1 1.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.latency_hist_coalsr::total 72
-system.ruby.LD.hit_latency_hist_seqr::bucket_size 1024
-system.ruby.LD.hit_latency_hist_seqr::max_bucket 10239
-system.ruby.LD.hit_latency_hist_seqr::samples 1
-system.ruby.LD.hit_latency_hist_seqr::mean 5256
-system.ruby.LD.hit_latency_hist_seqr::gmean 5256.000000
-system.ruby.LD.hit_latency_hist_seqr::stdev nan
-system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.hit_latency_hist_seqr::total 1
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-system.ruby.LD.miss_latency_hist_coalsr::stdev 67.272969
-system.ruby.LD.miss_latency_hist_coalsr | 7 9.72% 9.72% | 60 83.33% 93.06% | 1 1.39% 94.44% | 0 0.00% 94.44% | 3 4.17% 98.61% | 0 0.00% 98.61% | 0 0.00% 98.61% | 1 1.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.miss_latency_hist_coalsr::total 72
-system.ruby.ST.latency_hist_seqr::bucket_size 1024
-system.ruby.ST.latency_hist_seqr::max_bucket 10239
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-system.ruby.ST.latency_hist_seqr::gmean 1760.149244
-system.ruby.ST.latency_hist_seqr::stdev 1907.255858
-system.ruby.ST.latency_hist_seqr | 11 23.91% 23.91% | 3 6.52% 30.43% | 3 6.52% 36.96% | 7 15.22% 52.17% | 20 43.48% 95.65% | 2 4.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.latency_hist_seqr::total 46
-system.ruby.ST.latency_hist_coalsr::bucket_size 128
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-system.ruby.ST.latency_hist_coalsr::stdev 244.652456
-system.ruby.ST.latency_hist_coalsr | 506 64.38% 64.38% | 35 4.45% 68.83% | 108 13.74% 82.57% | 36 4.58% 87.15% | 24 3.05% 90.20% | 19 2.42% 92.62% | 32 4.07% 96.69% | 23 2.93% 99.62% | 3 0.38% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.latency_hist_coalsr::total 786
-system.ruby.ST.hit_latency_hist_seqr::bucket_size 1024
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-system.ruby.ST.hit_latency_hist_seqr::samples 40
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-system.ruby.ST.hit_latency_hist_seqr::stdev 1765.919997
-system.ruby.ST.hit_latency_hist_seqr | 7 17.50% 17.50% | 3 7.50% 25.00% | 1 2.50% 27.50% | 7 17.50% 45.00% | 20 50.00% 95.00% | 2 5.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.hit_latency_hist_seqr::total 40
-system.ruby.ST.miss_latency_hist_seqr::bucket_size 512
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-system.ruby.ST.miss_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.ST.miss_latency_hist_coalsr::stdev 244.652456
-system.ruby.ST.miss_latency_hist_coalsr | 506 64.38% 64.38% | 35 4.45% 68.83% | 108 13.74% 82.57% | 36 4.58% 87.15% | 24 3.05% 90.20% | 19 2.42% 92.62% | 32 4.07% 96.69% | 23 2.93% 99.62% | 3 0.38% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.miss_latency_hist_coalsr::total 786
-system.ruby.IFETCH.latency_hist_seqr::bucket_size 1024
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-system.ruby.IFETCH.latency_hist_seqr::gmean 5129
-system.ruby.IFETCH.latency_hist_seqr::stdev nan
-system.ruby.IFETCH.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.latency_hist_seqr::total 1
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-system.ruby.IFETCH.hit_latency_hist_seqr::gmean 5129
-system.ruby.IFETCH.hit_latency_hist_seqr::stdev nan
-system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.L1Cache.miss_mach_latency_hist_seqr::stdev 1278.753677
-system.ruby.L1Cache.miss_mach_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.Directory.hit_mach_latency_hist_seqr::gmean 2737.850881
-system.ruby.Directory.hit_mach_latency_hist_seqr::stdev 1757.652877
-system.ruby.Directory.hit_mach_latency_hist_seqr | 7 16.67% 16.67% | 3 7.14% 23.81% | 1 2.38% 26.19% | 7 16.67% 42.86% | 20 47.62% 90.48% | 4 9.52% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory.hit_mach_latency_hist_seqr::total 42
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-system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 122.381501
-system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 128.958613
-system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr | 502 80.45% 80.45% | 36 5.77% 86.22% | 40 6.41% 92.63% | 24 3.85% 96.47% | 12 1.92% 98.40% | 6 0.96% 99.36% | 3 0.48% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::total 624
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-system.ruby.TCP.miss_mach_latency_hist_coalsr::mean 1.126761
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-system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 0.607796
-system.ruby.TCP.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 68 95.77% 95.77% | 0 0.00% 95.77% | 0 0.00% 95.77% | 3 4.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.TCCdir.miss_mach_latency_hist_coalsr::max_bucket 1279
-system.ruby.TCCdir.miss_mach_latency_hist_coalsr::samples 163
-system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 564.687117
-system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 498.870659
-system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 272.472640
-system.ruby.TCCdir.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 71 43.56% 43.56% | 13 7.98% 51.53% | 12 7.36% 58.90% | 13 7.98% 66.87% | 29 17.79% 84.66% | 22 13.50% 98.16% | 3 1.84% 100.00% | 0 0.00% 100.00%
-system.ruby.TCCdir.miss_mach_latency_hist_coalsr::total 163
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-system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::samples 1
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-system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::gmean 5256.000000
-system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::stdev nan
-system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 62
-system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 104.322581
-system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 100.218451
-system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 51.260433
-system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 60 96.77% 96.77% | 1 1.61% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 1 1.61% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 62
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-system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean 1.219014
-system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::stdev 1.133893
-system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 6 85.71% 85.71% | 0 0.00% 85.71% | 0 0.00% 85.71% | 1 14.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total 7
-system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32
-system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319
-system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::samples 3
-system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean 274.333333
-system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 273.844265
-system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 20.256686
-system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 1 33.33% 100.00%
-system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::total 3
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 512
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 5119
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::samples 6
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::mean 1017.833333
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::gmean 114.584426
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::stdev 1278.753677
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::total 6
-system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::bucket_size 1024
-system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::max_bucket 10239
-system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::samples 40
-system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::mean 3566.725000
-system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::gmean 2651.630943
-system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::stdev 1765.919997
-system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr | 7 17.50% 17.50% | 3 7.50% 25.00% | 1 2.50% 27.50% | 7 17.50% 45.00% | 20 50.00% 95.00% | 2 5.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::total 40
-system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 128
-system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 1279
-system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 562
-system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 153.355872
-system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 125.108856
-system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 133.952348
-system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 442 78.65% 78.65% | 35 6.23% 84.88% | 40 7.12% 91.99% | 23 4.09% 96.09% | 12 2.14% 98.22% | 6 1.07% 99.29% | 3 0.53% 99.82% | 1 0.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 562
-system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1
-system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9
-system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::samples 64
-system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean 1.093750
-system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean 1.044274
-system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::stdev 0.526104
-system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 62 96.88% 96.88% | 0 0.00% 96.88% | 0 0.00% 96.88% | 2 3.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::total 64
-system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 128
-system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 1279
-system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::samples 160
-system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 570.131250
-system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 504.512629
-system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 272.059675
-system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 68 42.50% 42.50% | 13 8.12% 50.62% | 12 7.50% 58.12% | 13 8.12% 66.25% | 29 18.12% 84.38% | 22 13.75% 98.12% | 3 1.88% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::total 160
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::bucket_size 1024
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::max_bucket 10239
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::samples 1
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean 5129
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean 5129
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::stdev nan
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::total 1
-system.ruby.SQC_Controller.Fetch | 12 50.00% 50.00% | 12 50.00% 100.00%
-system.ruby.SQC_Controller.Fetch::total 24
-system.ruby.SQC_Controller.TCC_AckS | 12 50.00% 50.00% | 12 50.00% 100.00%
-system.ruby.SQC_Controller.TCC_AckS::total 24
-system.ruby.SQC_Controller.PrbInvData | 11 50.00% 50.00% | 11 50.00% 100.00%
-system.ruby.SQC_Controller.PrbInvData::total 22
-system.ruby.SQC_Controller.I.Fetch | 12 50.00% 50.00% | 12 50.00% 100.00%
-system.ruby.SQC_Controller.I.Fetch::total 24
-system.ruby.SQC_Controller.S.PrbInvData | 11 50.00% 50.00% | 11 50.00% 100.00%
-system.ruby.SQC_Controller.S.PrbInvData::total 22
-system.ruby.SQC_Controller.I_S.TCC_AckS | 12 50.00% 50.00% | 12 50.00% 100.00%
-system.ruby.SQC_Controller.I_S.TCC_AckS::total 24
-system.ruby.TCCdir_Controller.RdBlk 115 0.00% 0.00%
-system.ruby.TCCdir_Controller.RdBlkM 2448 0.00% 0.00%
-system.ruby.TCCdir_Controller.RdBlkS 103 0.00% 0.00%
-system.ruby.TCCdir_Controller.CPUPrbResp 785 0.00% 0.00%
-system.ruby.TCCdir_Controller.ProbeAcksComplete 730 0.00% 0.00%
-system.ruby.TCCdir_Controller.CoreUnblock 807 0.00% 0.00%
-system.ruby.TCCdir_Controller.LastCoreUnblock 3 0.00% 0.00%
-system.ruby.TCCdir_Controller.NB_AckS 1 0.00% 0.00%
-system.ruby.TCCdir_Controller.NB_AckE 3 0.00% 0.00%
-system.ruby.TCCdir_Controller.NB_AckM 212 0.00% 0.00%
-system.ruby.TCCdir_Controller.PrbInvData 119 0.00% 0.00%
-system.ruby.TCCdir_Controller.PrbShrData 6 0.00% 0.00%
-system.ruby.TCCdir_Controller.I.RdBlk 3 0.00% 0.00%
-system.ruby.TCCdir_Controller.I.RdBlkM 154 0.00% 0.00%
-system.ruby.TCCdir_Controller.I.RdBlkS 1 0.00% 0.00%
-system.ruby.TCCdir_Controller.I.PrbInvData 9 0.00% 0.00%
-system.ruby.TCCdir_Controller.S.RdBlkM 1 0.00% 0.00%
-system.ruby.TCCdir_Controller.E.RdBlkM 1 0.00% 0.00%
-system.ruby.TCCdir_Controller.E.RdBlkS 1 0.00% 0.00%
-system.ruby.TCCdir_Controller.O.RdBlk 2 0.00% 0.00%
-system.ruby.TCCdir_Controller.O.RdBlkM 61 0.00% 0.00%
-system.ruby.TCCdir_Controller.O.RdBlkS 1 0.00% 0.00%
-system.ruby.TCCdir_Controller.O.PrbInvData 4 0.00% 0.00%
-system.ruby.TCCdir_Controller.O.PrbShrData 1 0.00% 0.00%
-system.ruby.TCCdir_Controller.M.RdBlk 61 0.00% 0.00%
-system.ruby.TCCdir_Controller.M.RdBlkM 512 0.00% 0.00%
-system.ruby.TCCdir_Controller.M.RdBlkS 20 0.00% 0.00%
-system.ruby.TCCdir_Controller.M.PrbInvData 62 0.00% 0.00%
-system.ruby.TCCdir_Controller.M.PrbShrData 4 0.00% 0.00%
-system.ruby.TCCdir_Controller.CP_I.RdBlkM 17 0.00% 0.00%
-system.ruby.TCCdir_Controller.CP_I.CPUPrbResp 70 0.00% 0.00%
-system.ruby.TCCdir_Controller.CP_I.ProbeAcksComplete 66 0.00% 0.00%
-system.ruby.TCCdir_Controller.CP_O.RdBlkM 4 0.00% 0.00%
-system.ruby.TCCdir_Controller.CP_O.CPUPrbResp 6 0.00% 0.00%
-system.ruby.TCCdir_Controller.CP_O.ProbeAcksComplete 5 0.00% 0.00%
-system.ruby.TCCdir_Controller.CP_OM.RdBlkM 14 0.00% 0.00%
-system.ruby.TCCdir_Controller.CP_OM.CPUPrbResp 1 0.00% 0.00%
-system.ruby.TCCdir_Controller.CP_OM.ProbeAcksComplete 1 0.00% 0.00%
-system.ruby.TCCdir_Controller.CP_IOM.RdBlkM 5 0.00% 0.00%
-system.ruby.TCCdir_Controller.CP_IOM.CPUPrbResp 2 0.00% 0.00%
-system.ruby.TCCdir_Controller.CP_IOM.ProbeAcksComplete 2 0.00% 0.00%
-system.ruby.TCCdir_Controller.I_M.RdBlk 26 0.00% 0.00%
-system.ruby.TCCdir_Controller.I_M.RdBlkM 960 0.00% 0.00%
-system.ruby.TCCdir_Controller.I_M.RdBlkS 3 0.00% 0.00%
-system.ruby.TCCdir_Controller.I_M.NB_AckM 154 0.00% 0.00%
-system.ruby.TCCdir_Controller.I_M.PrbInvData 1 0.00% 0.00%
-system.ruby.TCCdir_Controller.I_ES.NB_AckE 3 0.00% 0.00%
-system.ruby.TCCdir_Controller.I_S.NB_AckS 1 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBO_O.RdBlkM 5 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBO_O.RdBlkS 1 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBO_O.CPUPrbResp 3 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBO_O.ProbeAcksComplete 3 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBM_M.RdBlk 6 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBM_M.RdBlkM 94 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBM_M.RdBlkS 5 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBM_M.CPUPrbResp 510 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBM_M.ProbeAcksComplete 510 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBM_M.PrbInvData 15 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBM_O.RdBlkM 6 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBM_O.RdBlkS 5 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBM_O.CPUPrbResp 81 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBM_O.ProbeAcksComplete 81 0.00% 0.00%
-system.ruby.TCCdir_Controller.BB_M.RdBlk 13 0.00% 0.00%
-system.ruby.TCCdir_Controller.BB_M.RdBlkM 176 0.00% 0.00%
-system.ruby.TCCdir_Controller.BB_M.RdBlkS 5 0.00% 0.00%
-system.ruby.TCCdir_Controller.BB_M.CoreUnblock 509 0.00% 0.00%
-system.ruby.TCCdir_Controller.BB_M.PrbInvData 24 0.00% 0.00%
-system.ruby.TCCdir_Controller.BB_O.RdBlkM 26 0.00% 0.00%
-system.ruby.TCCdir_Controller.BB_O.RdBlkS 5 0.00% 0.00%
-system.ruby.TCCdir_Controller.BB_O.CoreUnblock 81 0.00% 0.00%
-system.ruby.TCCdir_Controller.BB_O.PrbInvData 2 0.00% 0.00%
-system.ruby.TCCdir_Controller.BB_OO.RdBlkM 14 0.00% 0.00%
-system.ruby.TCCdir_Controller.BB_OO.CoreUnblock 1 0.00% 0.00%
-system.ruby.TCCdir_Controller.BB_OO.LastCoreUnblock 3 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBS_M.CPUPrbResp 2 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBS_M.ProbeAcksComplete 2 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBO_M.RdBlkM 4 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBO_M.CPUPrbResp 110 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBO_M.ProbeAcksComplete 60 0.00% 0.00%
-system.ruby.TCCdir_Controller.S_M.NB_AckM 2 0.00% 0.00%
-system.ruby.TCCdir_Controller.O_M.RdBlkM 198 0.00% 0.00%
-system.ruby.TCCdir_Controller.O_M.RdBlkS 48 0.00% 0.00%
-system.ruby.TCCdir_Controller.O_M.NB_AckM 56 0.00% 0.00%
-system.ruby.TCCdir_Controller.O_M.PrbInvData 2 0.00% 0.00%
-system.ruby.TCCdir_Controller.O_M.PrbShrData 1 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBB_S.CoreUnblock 1 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBB_M.RdBlk 4 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBB_M.RdBlkM 196 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBB_M.RdBlkS 8 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBB_M.CoreUnblock 212 0.00% 0.00%
-system.ruby.TCCdir_Controller.BBB_E.CoreUnblock 3 0.00% 0.00%
-system.ruby.TCP_Controller.Load | 10 13.70% 13.70% | 10 13.70% 27.40% | 11 15.07% 42.47% | 12 16.44% 58.90% | 6 8.22% 67.12% | 3 4.11% 71.23% | 10 13.70% 84.93% | 11 15.07% 100.00%
-system.ruby.TCP_Controller.Load::total 73
-system.ruby.TCP_Controller.Store | 106 13.27% 13.27% | 102 12.77% 26.03% | 97 12.14% 38.17% | 86 10.76% 48.94% | 107 13.39% 62.33% | 98 12.27% 74.59% | 111 13.89% 88.49% | 92 11.51% 100.00%
-system.ruby.TCP_Controller.Store::total 799
-system.ruby.TCP_Controller.TCC_AckS | 9 14.52% 14.52% | 8 12.90% 27.42% | 8 12.90% 40.32% | 12 19.35% 59.68% | 5 8.06% 67.74% | 3 4.84% 72.58% | 8 12.90% 85.48% | 9 14.52% 100.00%
-system.ruby.TCP_Controller.TCC_AckS::total 62
-system.ruby.TCP_Controller.TCC_AckE | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00%
-system.ruby.TCP_Controller.TCC_AckE::total 3
-system.ruby.TCP_Controller.TCC_AckM | 93 12.88% 12.88% | 89 12.33% 25.21% | 87 12.05% 37.26% | 76 10.53% 47.78% | 98 13.57% 61.36% | 89 12.33% 73.68% | 106 14.68% 88.37% | 84 11.63% 100.00%
-system.ruby.TCP_Controller.TCC_AckM::total 722
-system.ruby.TCP_Controller.PrbInvData | 84 12.44% 12.44% | 87 12.89% 25.33% | 83 12.30% 37.63% | 78 11.56% 49.19% | 89 13.19% 62.37% | 79 11.70% 74.07% | 97 14.37% 88.44% | 78 11.56% 100.00%
-system.ruby.TCP_Controller.PrbInvData::total 675
-system.ruby.TCP_Controller.PrbShrData | 16 17.39% 17.39% | 10 10.87% 28.26% | 9 9.78% 38.04% | 8 8.70% 46.74% | 15 16.30% 63.04% | 9 9.78% 72.83% | 14 15.22% 88.04% | 11 11.96% 100.00%
-system.ruby.TCP_Controller.PrbShrData::total 92
-system.ruby.TCP_Controller.I.Load | 10 15.15% 15.15% | 9 13.64% 28.79% | 9 13.64% 42.42% | 12 18.18% 60.61% | 5 7.58% 68.18% | 3 4.55% 72.73% | 9 13.64% 86.36% | 9 13.64% 100.00%
-system.ruby.TCP_Controller.I.Load::total 66
-system.ruby.TCP_Controller.I.Store | 97 13.42% 13.42% | 91 12.59% 26.00% | 87 12.03% 38.04% | 79 10.93% 48.96% | 92 12.72% 61.69% | 89 12.31% 74.00% | 104 14.38% 88.38% | 84 11.62% 100.00%
-system.ruby.TCP_Controller.I.Store::total 723
-system.ruby.TCP_Controller.I.PrbInvData | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.TCP_Controller.I.PrbInvData::total 2
-system.ruby.TCP_Controller.S.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 2 66.67% 100.00% | 0 0.00% 100.00%
-system.ruby.TCP_Controller.S.Store::total 3
-system.ruby.TCP_Controller.S.PrbInvData | 6 14.29% 14.29% | 7 16.67% 30.95% | 7 16.67% 47.62% | 7 16.67% 64.29% | 2 4.76% 69.05% | 1 2.38% 71.43% | 5 11.90% 83.33% | 7 16.67% 100.00%
-system.ruby.TCP_Controller.S.PrbInvData::total 42
-system.ruby.TCP_Controller.S.PrbShrData | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.TCP_Controller.S.PrbShrData::total 1
-system.ruby.TCP_Controller.E.PrbInvData | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.TCP_Controller.E.PrbInvData::total 1
-system.ruby.TCP_Controller.E.PrbShrData | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.TCP_Controller.E.PrbShrData::total 1
-system.ruby.TCP_Controller.O.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 11.11% 11.11% | 0 0.00% 11.11% | 5 55.56% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 1 11.11% 100.00%
-system.ruby.TCP_Controller.O.Store::total 9
-system.ruby.TCP_Controller.O.PrbInvData | 9 16.07% 16.07% | 7 12.50% 28.57% | 8 14.29% 42.86% | 8 14.29% 57.14% | 7 12.50% 69.64% | 3 5.36% 75.00% | 9 16.07% 91.07% | 5 8.93% 100.00%
-system.ruby.TCP_Controller.O.PrbInvData::total 56
-system.ruby.TCP_Controller.O.PrbShrData | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00%
-system.ruby.TCP_Controller.O.PrbShrData::total 3
-system.ruby.TCP_Controller.M.Load | 0 0.00% 0.00% | 1 14.29% 14.29% | 2 28.57% 42.86% | 0 0.00% 42.86% | 1 14.29% 57.14% | 0 0.00% 57.14% | 1 14.29% 71.43% | 2 28.57% 100.00%
-system.ruby.TCP_Controller.M.Load::total 7
-system.ruby.TCP_Controller.M.Store | 9 14.06% 14.06% | 11 17.19% 31.25% | 9 14.06% 45.31% | 7 10.94% 56.25% | 9 14.06% 70.31% | 8 12.50% 82.81% | 4 6.25% 89.06% | 7 10.94% 100.00%
-system.ruby.TCP_Controller.M.Store::total 64
-system.ruby.TCP_Controller.M.PrbInvData | 69 12.02% 12.02% | 73 12.72% 24.74% | 68 11.85% 36.59% | 62 10.80% 47.39% | 79 13.76% 61.15% | 75 13.07% 74.22% | 82 14.29% 88.50% | 66 11.50% 100.00%
-system.ruby.TCP_Controller.M.PrbInvData::total 574
-system.ruby.TCP_Controller.M.PrbShrData | 14 16.47% 16.47% | 10 11.76% 28.24% | 9 10.59% 38.82% | 8 9.41% 48.24% | 14 16.47% 64.71% | 6 7.06% 71.76% | 14 16.47% 88.24% | 10 11.76% 100.00%
-system.ruby.TCP_Controller.M.PrbShrData::total 85
-system.ruby.TCP_Controller.I_M.TCC_AckM | 93 13.06% 13.06% | 89 12.50% 25.56% | 86 12.08% 37.64% | 76 10.67% 48.31% | 92 12.92% 61.24% | 89 12.50% 73.74% | 104 14.61% 88.34% | 83 11.66% 100.00%
-system.ruby.TCP_Controller.I_M.TCC_AckM::total 712
-system.ruby.TCP_Controller.I_ES.TCC_AckS | 9 14.52% 14.52% | 8 12.90% 27.42% | 8 12.90% 40.32% | 12 19.35% 59.68% | 5 8.06% 67.74% | 3 4.84% 72.58% | 8 12.90% 85.48% | 9 14.52% 100.00%
-system.ruby.TCP_Controller.I_ES.TCC_AckS::total 62
-system.ruby.TCP_Controller.I_ES.TCC_AckE | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00%
-system.ruby.TCP_Controller.I_ES.TCC_AckE::total 3
-system.ruby.TCP_Controller.S_M.TCC_AckM | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00%
-system.ruby.TCP_Controller.S_M.TCC_AckM::total 2
-system.ruby.TCP_Controller.O_M.TCC_AckM | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 12.50% 12.50% | 0 0.00% 12.50% | 5 62.50% 75.00% | 0 0.00% 75.00% | 1 12.50% 87.50% | 1 12.50% 100.00%
-system.ruby.TCP_Controller.O_M.TCC_AckM::total 8
-system.ruby.TCP_Controller.O_M.PrbShrData | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.TCP_Controller.O_M.PrbShrData::total 2
-
----------- End Simulation Statistics ----------
+++ /dev/null
-#
-# Copyright (c) 2010-2015 Advanced Micro Devices, Inc.
-# All rights reserved.
-#
-# For use for simulation and test purposes only
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#
-# 1. Redistributions of source code must retain the above copyright notice,
-# this list of conditions and the following disclaimer.
-#
-# 2. Redistributions in binary form must reproduce the above copyright notice,
-# this list of conditions and the following disclaimer in the documentation
-# and/or other materials provided with the distribution.
-#
-# 3. Neither the name of the copyright holder nor the names of its contributors
-# may be used to endorse or promote products derived from this software
-# without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-# POSSIBILITY OF SUCH DAMAGE.
-#
-# Author: Brad Beckmann
-#
-
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
-
-[system]
-type=System
-children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:268435455:0:0:0:0
-memories=system.mem_ctrls
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.sys_port_proxy.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=RubyTester
-check_flush=false
-checks_to_complete=100
-clk_domain=system.clk_domain
-deadlock_threshold=50000
-default_p_state=UNDEFINED
-eventq_index=0
-num_cpus=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-system=system
-wakeup_frequency=10
-cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000
-
-[system.mem_ctrls]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-page_policy=open_adaptive
-power_model=Null
-range=0:268435455:5:19:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10
-static_frontend_latency=10
-tBURST=5
-tCCD_L=0
-tCK=1
-tCL=14
-tCS=3
-tRAS=35
-tRCD=14
-tREFI=7800
-tRFC=260
-tRP=14
-tRRD=6
-tRRD_L=0
-tRTP=8
-tRTW=3
-tWR=15
-tWTR=8
-tXAW=30
-tXP=6
-tXPDLL=0
-tXS=270
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.ruby.dir_cntrl0.memory
-
-[system.ruby]
-type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
-access_backing_store=false
-all_instructions=false
-block_size_bytes=64
-clk_domain=system.ruby.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hot_lines=false
-memory_size_bits=48
-num_of_sequencers=1
-number_of_virtual_networks=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-phys_mem=Null
-power_model=Null
-randomization=true
-
-[system.ruby.clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.ruby.dir_cntrl0]
-type=Directory_Controller
-children=directory requestToDir responseFromDir responseFromMemory responseToDir
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-default_p_state=UNDEFINED
-directory=system.ruby.dir_cntrl0.directory
-directory_latency=6
-eventq_index=0
-number_of_TBEs=256
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-recycle_latency=10
-requestToDir=system.ruby.dir_cntrl0.requestToDir
-responseFromDir=system.ruby.dir_cntrl0.responseFromDir
-responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory
-responseToDir=system.ruby.dir_cntrl0.responseToDir
-ruby_system=system.ruby
-system=system
-to_mem_ctrl_latency=1
-transitions_per_cycle=32
-version=0
-memory=system.mem_ctrls.port
-
-[system.ruby.dir_cntrl0.directory]
-type=RubyDirectoryMemory
-eventq_index=0
-numa_high_bit=5
-size=268435456
-version=0
-
-[system.ruby.dir_cntrl0.requestToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[5]
-
-[system.ruby.dir_cntrl0.responseFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[6]
-
-[system.ruby.dir_cntrl0.responseFromMemory]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.dir_cntrl0.responseToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[6]
-
-[system.ruby.l1_cntrl0]
-type=L1Cache_Controller
-children=L1Dcache L1Icache mandatoryQueue optionalQueue prefetcher requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer unblockFromL1Cache
-L1Dcache=system.ruby.l1_cntrl0.L1Dcache
-L1Icache=system.ruby.l1_cntrl0.L1Icache
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-default_p_state=UNDEFINED
-enable_prefetch=false
-eventq_index=0
-l1_request_latency=2
-l1_response_latency=2
-l2_select_num_bits=0
-mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
-number_of_TBEs=256
-optionalQueue=system.ruby.l1_cntrl0.optionalQueue
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-prefetcher=system.ruby.l1_cntrl0.prefetcher
-recycle_latency=10
-requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache
-requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache
-responseFromL1Cache=system.ruby.l1_cntrl0.responseFromL1Cache
-responseToL1Cache=system.ruby.l1_cntrl0.responseToL1Cache
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl0.sequencer
-system=system
-to_l2_latency=1
-transitions_per_cycle=32
-unblockFromL1Cache=system.ruby.l1_cntrl0.unblockFromL1Cache
-version=0
-
-[system.ruby.l1_cntrl0.L1Dcache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l1_cntrl0.L1Dcache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.L1Dcache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl0.L1Icache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=true
-replacement_policy=system.ruby.l1_cntrl0.L1Icache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.L1Icache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl0.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl0.optionalQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl0.prefetcher]
-type=Prefetcher
-cross_page=false
-eventq_index=0
-nonunit_filter=8
-num_startup_pfs=1
-num_streams=4
-pf_per_stream=1
-sys=system
-train_misses=4
-unit_filter=8
-
-[system.ruby.l1_cntrl0.requestFromL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[0]
-
-[system.ruby.l1_cntrl0.requestToL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[0]
-
-[system.ruby.l1_cntrl0.responseFromL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[1]
-
-[system.ruby.l1_cntrl0.responseToL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[1]
-
-[system.ruby.l1_cntrl0.sequencer]
-type=RubySequencer
-clk_domain=system.ruby.clk_domain
-coreid=99
-dcache=system.ruby.l1_cntrl0.L1Dcache
-dcache_hit_latency=1
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.ruby.l1_cntrl0.L1Icache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=true
-version=0
-slave=system.cpu.cpuInstDataPort[0]
-
-[system.ruby.l1_cntrl0.unblockFromL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[2]
-
-[system.ruby.l2_cntrl0]
-type=L2Cache_Controller
-children=DirRequestFromL2Cache L1RequestFromL2Cache L1RequestToL2Cache L2cache responseFromL2Cache responseToL2Cache unblockToL2Cache
-DirRequestFromL2Cache=system.ruby.l2_cntrl0.DirRequestFromL2Cache
-L1RequestFromL2Cache=system.ruby.l2_cntrl0.L1RequestFromL2Cache
-L1RequestToL2Cache=system.ruby.l2_cntrl0.L1RequestToL2Cache
-L2cache=system.ruby.l2_cntrl0.L2cache
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-default_p_state=UNDEFINED
-eventq_index=0
-l2_request_latency=2
-l2_response_latency=2
-number_of_TBEs=256
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-recycle_latency=10
-responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache
-responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache
-ruby_system=system.ruby
-system=system
-to_l1_latency=1
-transitions_per_cycle=32
-unblockToL2Cache=system.ruby.l2_cntrl0.unblockToL2Cache
-version=0
-
-[system.ruby.l2_cntrl0.DirRequestFromL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[3]
-
-[system.ruby.l2_cntrl0.L1RequestFromL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[4]
-
-[system.ruby.l2_cntrl0.L1RequestToL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[3]
-
-[system.ruby.l2_cntrl0.L2cache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l2_cntrl0.L2cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=512
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l2_cntrl0.L2cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=512
-
-[system.ruby.l2_cntrl0.responseFromL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[5]
-
-[system.ruby.l2_cntrl0.responseToL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[4]
-
-[system.ruby.l2_cntrl0.unblockToL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[2]
-
-[system.ruby.memctrl_clk_domain]
-type=DerivedClockDomain
-clk_divider=3
-clk_domain=system.ruby.clk_domain
-eventq_index=0
-
-[system.ruby.network]
-type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3
-adaptive_routing=false
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-control_msg_size=8
-default_p_state=UNDEFINED
-endpoint_bandwidth=1000
-eventq_index=0
-ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35
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-[system.ruby.network.routers3.port_buffers07]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers3.port_buffers08]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers3.port_buffers09]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers3.port_buffers10]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers3.port_buffers11]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers3.port_buffers12]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers3.port_buffers13]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers3.port_buffers14]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers3.port_buffers15]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers3.port_buffers16]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers3.port_buffers17]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.sys_port_proxy]
-type=RubyPortProxy
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_cpu_sequencer=true
-no_retry_on_stall=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=0
-slave=system.system_port
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
+++ /dev/null
-Redirecting stdout to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level/simout
-Redirecting stderr to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 13 2016 20:28:06
-gem5 started Oct 13 2016 20:28:31
-gem5 executing on e108600-lin, pid 8234
-command line: /work/curdun01/gem5-external.hg/build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level
-
-Global frequency set at 1000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 44021 because Ruby Tester completed
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000044 # Number of seconds simulated
-sim_ticks 44021 # Number of ticks simulated
-final_tick 44021 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 749300 # Simulator tick rate (ticks/s)
-host_mem_usage 393900 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 55424 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 55424 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 49920 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 49920 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 866 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 866 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 780 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 780 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 1259035460 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 1259035460 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 1134004225 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 1134004225 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 2393039686 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 2393039686 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 866 # Number of read requests accepted
-system.mem_ctrls.writeReqs 780 # Number of write requests accepted
-system.mem_ctrls.readBursts 866 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 780 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 45760 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 9664 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 40640 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 55424 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 49920 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 151 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 116 # Number of DRAM write bursts merged with an existing one
-system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 210 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 228 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 223 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 54 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 184 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 198 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 203 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 50 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
-system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
-system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 44002 # Total gap between requests
-system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 866 # Read request sizes (log2)
-system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 780 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 430 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 284 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
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-system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
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-system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
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-system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 7 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 29 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 41 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 41 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 48 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 41 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 39 # What write queue length does an incoming req see
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-system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
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-system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 93 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 915.268817 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 819.587468 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 267.362608 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 2 2.15% 2.15% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 5 5.38% 7.53% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 1 1.08% 8.60% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 3 3.23% 11.83% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 3 3.23% 15.05% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 4 4.30% 19.35% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 75 80.65% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 93 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 39 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 17.897436 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 17.675839 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 3.385689 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15 5 12.82% 12.82% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17 14 35.90% 48.72% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19 15 38.46% 87.18% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-21 3 7.69% 94.87% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::22-23 1 2.56% 97.44% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::36-37 1 2.56% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 39 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 39 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.282051 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.268709 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 0.686284 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 33 84.62% 84.62% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 1 2.56% 87.18% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 5 12.82% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 39 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 12989 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 26574 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 3575 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 18.17 # Average queueing delay per DRAM burst
-system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 37.17 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 1039.50 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 923.20 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 1259.04 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 1134.00 # Average system write bandwidth in MiByte/s
-system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 15.33 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 8.12 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 7.21 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 1.66 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 25.56 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 627 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 627 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 87.69 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 94.43 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 26.73 # Average gap between requests
-system.mem_ctrls.pageHitRate 90.94 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 685440 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 359352 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 8168160 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 5303520 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 8952648 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 72576 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.actPowerDownEnergy 11032464 # Energy for active power-down per rank (pJ)
-system.mem_ctrls_0.prePowerDownEnergy 1920 # Energy for precharge power-down per rank (pJ)
-system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
-system.mem_ctrls_0.totalEnergy 37649280 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 855.257264 # Core power per rank (mW)
-system.mem_ctrls_0.totalIdleTime 24199 # Total Idle time Per DRAM Rank
-system.mem_ctrls_0.memoryStateTime::IDLE 49 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 5 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 18473 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 24194 # Time in different power states
-system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 224352 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 3002880 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ)
-system.mem_ctrls_1.prePowerDownEnergy 2889984 # Energy for precharge power-down per rank (pJ)
-system.mem_ctrls_1.selfRefreshEnergy 6763920 # Energy for self refresh per rank (pJ)
-system.mem_ctrls_1.totalEnergy 14110416 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 320.538289 # Core power per rank (mW)
-system.mem_ctrls_1.totalIdleTime 7526 # Total Idle time Per DRAM Rank
-system.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 526 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::SREF 28183 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 7526 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states
-system.ruby.clk_domain.clock 1 # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states
-system.ruby.delayHist::bucket_size 4 # delay histogram for all message
-system.ruby.delayHist::max_bucket 39 # delay histogram for all message
-system.ruby.delayHist::samples 6525 # delay histogram for all message
-system.ruby.delayHist::mean 2.632031 # delay histogram for all message
-system.ruby.delayHist::stdev 5.481611 # delay histogram for all message
-system.ruby.delayHist | 5040 77.24% 77.24% | 61 0.93% 78.18% | 1056 16.18% 94.36% | 7 0.11% 94.47% | 285 4.37% 98.84% | 1 0.02% 98.85% | 1 0.02% 98.87% | 70 1.07% 99.94% | 0 0.00% 99.94% | 4 0.06% 100.00% # delay histogram for all message
-system.ruby.delayHist::total 6525 # delay histogram for all message
-system.ruby.outstanding_req_hist_seqr::bucket_size 2
-system.ruby.outstanding_req_hist_seqr::max_bucket 19
-system.ruby.outstanding_req_hist_seqr::samples 1019
-system.ruby.outstanding_req_hist_seqr::mean 15.664377
-system.ruby.outstanding_req_hist_seqr::gmean 15.560778
-system.ruby.outstanding_req_hist_seqr::stdev 1.199712
-system.ruby.outstanding_req_hist_seqr | 1 0.10% 0.10% | 2 0.20% 0.29% | 2 0.20% 0.49% | 2 0.20% 0.69% | 4 0.39% 1.08% | 2 0.20% 1.28% | 5 0.49% 1.77% | 199 19.53% 21.30% | 802 78.70% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist_seqr::total 1019
-system.ruby.latency_hist_seqr::bucket_size 128
-system.ruby.latency_hist_seqr::max_bucket 1279
-system.ruby.latency_hist_seqr::samples 1004
-system.ruby.latency_hist_seqr::mean 684.454183
-system.ruby.latency_hist_seqr::gmean 346.202279
-system.ruby.latency_hist_seqr::stdev 321.934539
-system.ruby.latency_hist_seqr | 155 15.44% 15.44% | 28 2.79% 18.23% | 4 0.40% 18.63% | 3 0.30% 18.92% | 6 0.60% 19.52% | 263 26.20% 45.72% | 367 36.55% 82.27% | 113 11.25% 93.53% | 53 5.28% 98.80% | 12 1.20% 100.00%
-system.ruby.latency_hist_seqr::total 1004
-system.ruby.hit_latency_hist_seqr::bucket_size 1
-system.ruby.hit_latency_hist_seqr::max_bucket 9
-system.ruby.hit_latency_hist_seqr::samples 101
-system.ruby.hit_latency_hist_seqr::mean 1
-system.ruby.hit_latency_hist_seqr::gmean 1
-system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 101 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist_seqr::total 101
-system.ruby.miss_latency_hist_seqr::bucket_size 128
-system.ruby.miss_latency_hist_seqr::max_bucket 1279
-system.ruby.miss_latency_hist_seqr::samples 903
-system.ruby.miss_latency_hist_seqr::mean 760.898117
-system.ruby.miss_latency_hist_seqr::gmean 665.813242
-system.ruby.miss_latency_hist_seqr::stdev 238.941361
-system.ruby.miss_latency_hist_seqr | 54 5.98% 5.98% | 28 3.10% 9.08% | 4 0.44% 9.52% | 3 0.33% 9.86% | 6 0.66% 10.52% | 263 29.13% 39.65% | 367 40.64% 80.29% | 113 12.51% 92.80% | 53 5.87% 98.67% | 12 1.33% 100.00%
-system.ruby.miss_latency_hist_seqr::total 903
-system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.019672 # Average number of messages in buffer
-system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.800736 # Average number of cycles messages are stalled in this MB
-system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.039208 # Average number of messages in buffer
-system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.998319 # Average number of cycles messages are stalled in this MB
-system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.037345 # Average number of messages in buffer
-system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.998342 # Average number of cycles messages are stalled in this MB
-system.ruby.dir_cntrl0.responseToDir.avg_buf_msgs 0.019581 # Average number of messages in buffer
-system.ruby.dir_cntrl0.responseToDir.avg_stall_time 8.079642 # Average number of cycles messages are stalled in this MB
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 101 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 855 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 956 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 50 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 50 # Number of cache demand accesses
-system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 13.866976 # Average number of messages in buffer
-system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 7.367248 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.mandatoryQueue.num_msg_stalls 11024 # Number of times messages were stalled
-system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
-system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
-system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
-system.ruby.l1_cntrl0.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
-system.ruby.l1_cntrl0.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
-system.ruby.l1_cntrl0.prefetcher.hits 0 # number of prefetched blocks accessed
-system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
-system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
-system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl0.requestFromL1Cache.avg_buf_msgs 0.077552 # Average number of messages in buffer
-system.ruby.l1_cntrl0.requestFromL1Cache.avg_stall_time 1.999818 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.requestToL1Cache.avg_buf_msgs 0.006088 # Average number of messages in buffer
-system.ruby.l1_cntrl0.requestToL1Cache.avg_stall_time 6.577348 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.responseFromL1Cache.avg_buf_msgs 0.012176 # Average number of messages in buffer
-system.ruby.l1_cntrl0.responseFromL1Cache.avg_stall_time 1.879151 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.responseToL1Cache.avg_buf_msgs 0.038731 # Average number of messages in buffer
-system.ruby.l1_cntrl0.responseToL1Cache.avg_stall_time 8.395552 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 4 # Number of times a store aliased with a pending load
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 86 # Number of times a store aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 8 # Number of times a load aliased with a pending store
-system.ruby.l1_cntrl0.unblockFromL1Cache.avg_buf_msgs 0.019354 # Average number of messages in buffer
-system.ruby.l1_cntrl0.unblockFromL1Cache.avg_stall_time 0.998001 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states
-system.ruby.l2_cntrl0.DirRequestFromL2Cache.avg_buf_msgs 0.039344 # Average number of messages in buffer
-system.ruby.l2_cntrl0.DirRequestFromL2Cache.avg_stall_time 1.999455 # Average number of cycles messages are stalled in this MB
-system.ruby.l2_cntrl0.L1RequestFromL2Cache.avg_buf_msgs 0.006201 # Average number of messages in buffer
-system.ruby.l2_cntrl0.L1RequestFromL2Cache.avg_stall_time 0.939757 # Average number of cycles messages are stalled in this MB
-system.ruby.l2_cntrl0.L1RequestToL2Cache.avg_buf_msgs 0.394962 # Average number of messages in buffer
-system.ruby.l2_cntrl0.L1RequestToL2Cache.avg_stall_time 24.096134 # Average number of cycles messages are stalled in this MB
-system.ruby.l2_cntrl0.L1RequestToL2Cache.num_msg_stalls 396 # Number of times messages were stalled
-system.ruby.l2_cntrl0.L2cache.demand_hits 39 # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses 866 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 905 # Number of cache demand accesses
-system.ruby.l2_cntrl0.responseFromL2Cache.avg_buf_msgs 0.078756 # Average number of messages in buffer
-system.ruby.l2_cntrl0.responseFromL2Cache.avg_stall_time 1.598428 # Average number of cycles messages are stalled in this MB
-system.ruby.l2_cntrl0.responseToL2Cache.avg_buf_msgs 0.045273 # Average number of messages in buffer
-system.ruby.l2_cntrl0.responseToL2Cache.avg_stall_time 7.165917 # Average number of cycles messages are stalled in this MB
-system.ruby.l2_cntrl0.unblockToL2Cache.avg_buf_msgs 0.019354 # Average number of messages in buffer
-system.ruby.l2_cntrl0.unblockToL2Cache.avg_stall_time 6.985053 # Average number of cycles messages are stalled in this MB
-system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states
-system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.port_buffers01.avg_buf_msgs 0.038731 # Average number of messages in buffer
-system.ruby.network.routers0.port_buffers01.avg_stall_time 7.397778 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers0.port_buffers02.avg_buf_msgs 0.006088 # Average number of messages in buffer
-system.ruby.network.routers0.port_buffers02.avg_stall_time 5.637863 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.204034 # Average number of messages in buffer
-system.ruby.network.routers0.port_buffers03.avg_stall_time 11.022807 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.006542 # Average number of messages in buffer
-system.ruby.network.routers0.port_buffers04.avg_stall_time 2.850416 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers0.port_buffers05.avg_buf_msgs 0.019354 # Average number of messages in buffer
-system.ruby.network.routers0.port_buffers05.avg_stall_time 1.995957 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized 11.308239
-system.ruby.network.routers0.msg_count.Control::0 905
-system.ruby.network.routers0.msg_count.Request_Control::2 268
-system.ruby.network.routers0.msg_count.Response_Data::1 902
-system.ruby.network.routers0.msg_count.Response_Control::1 853
-system.ruby.network.routers0.msg_count.Response_Control::2 852
-system.ruby.network.routers0.msg_count.Writeback_Data::0 769
-system.ruby.network.routers0.msg_count.Writeback_Data::1 218
-system.ruby.network.routers0.msg_count.Writeback_Control::0 33
-system.ruby.network.routers0.msg_bytes.Control::0 7240
-system.ruby.network.routers0.msg_bytes.Request_Control::2 2144
-system.ruby.network.routers0.msg_bytes.Response_Data::1 64944
-system.ruby.network.routers0.msg_bytes.Response_Control::1 6824
-system.ruby.network.routers0.msg_bytes.Response_Control::2 6816
-system.ruby.network.routers0.msg_bytes.Writeback_Data::0 55368
-system.ruby.network.routers0.msg_bytes.Writeback_Data::1 15696
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0 264
-system.ruby.network.routers1.port_buffers00.avg_buf_msgs 0.038776 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers00.avg_stall_time 15.044228 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.port_buffers01.avg_buf_msgs 0.045273 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers01.avg_stall_time 6.167871 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.019354 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers02.avg_stall_time 5.987325 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.port_buffers03.avg_buf_msgs 0.099337 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers03.avg_stall_time 6.730339 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.port_buffers04.avg_buf_msgs 0.085185 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers04.avg_stall_time 2.717936 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.port_buffers05.avg_buf_msgs 0.006088 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers05.avg_stall_time 1.879469 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized 20.738398
-system.ruby.network.routers1.msg_count.Control::0 1771
-system.ruby.network.routers1.msg_count.Request_Control::2 268
-system.ruby.network.routers1.msg_count.Response_Data::1 2546
-system.ruby.network.routers1.msg_count.Response_Control::1 1796
-system.ruby.network.routers1.msg_count.Response_Control::2 852
-system.ruby.network.routers1.msg_count.Writeback_Data::0 769
-system.ruby.network.routers1.msg_count.Writeback_Data::1 218
-system.ruby.network.routers1.msg_count.Writeback_Control::0 33
-system.ruby.network.routers1.msg_bytes.Control::0 14168
-system.ruby.network.routers1.msg_bytes.Request_Control::2 2144
-system.ruby.network.routers1.msg_bytes.Response_Data::1 183312
-system.ruby.network.routers1.msg_bytes.Response_Control::1 14368
-system.ruby.network.routers1.msg_bytes.Response_Control::2 6816
-system.ruby.network.routers1.msg_bytes.Writeback_Data::0 55368
-system.ruby.network.routers1.msg_bytes.Writeback_Data::1 15696
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0 264
-system.ruby.network.routers2.port_buffers00.avg_buf_msgs 0.019672 # Average number of messages in buffer
-system.ruby.network.routers2.port_buffers00.avg_stall_time 10.801508 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.port_buffers01.avg_buf_msgs 0.019581 # Average number of messages in buffer
-system.ruby.network.routers2.port_buffers01.avg_stall_time 7.082459 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.041570 # Average number of messages in buffer
-system.ruby.network.routers2.port_buffers03.avg_stall_time 2.061628 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized 9.432430
-system.ruby.network.routers2.msg_count.Control::0 866
-system.ruby.network.routers2.msg_count.Response_Data::1 1645
-system.ruby.network.routers2.msg_count.Response_Control::1 943
-system.ruby.network.routers2.msg_bytes.Control::0 6928
-system.ruby.network.routers2.msg_bytes.Response_Data::1 118440
-system.ruby.network.routers2.msg_bytes.Response_Control::1 7544
-system.ruby.network.int_link_buffers00.avg_buf_msgs 0.038776 # Average number of messages in buffer
-system.ruby.network.int_link_buffers00.avg_stall_time 12.022534 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers01.avg_buf_msgs 0.006088 # Average number of messages in buffer
-system.ruby.network.int_link_buffers01.avg_stall_time 3.789878 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers02.avg_buf_msgs 0.019354 # Average number of messages in buffer
-system.ruby.network.int_link_buffers02.avg_stall_time 2.993867 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers03.avg_buf_msgs 0.019672 # Average number of messages in buffer
-system.ruby.network.int_link_buffers03.avg_stall_time 7.729749 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers04.avg_buf_msgs 0.058312 # Average number of messages in buffer
-system.ruby.network.int_link_buffers04.avg_stall_time 3.715892 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers05.avg_buf_msgs 0.006088 # Average number of messages in buffer
-system.ruby.network.int_link_buffers05.avg_stall_time 2.819136 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers07.avg_buf_msgs 0.039208 # Average number of messages in buffer
-system.ruby.network.int_link_buffers07.avg_stall_time 3.059856 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers10.avg_buf_msgs 0.038731 # Average number of messages in buffer
-system.ruby.network.int_link_buffers10.avg_stall_time 6.399959 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers11.avg_buf_msgs 0.006088 # Average number of messages in buffer
-system.ruby.network.int_link_buffers11.avg_stall_time 4.698333 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers12.avg_buf_msgs 0.038776 # Average number of messages in buffer
-system.ruby.network.int_link_buffers12.avg_stall_time 14.044637 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers13.avg_buf_msgs 0.045273 # Average number of messages in buffer
-system.ruby.network.int_link_buffers13.avg_stall_time 5.169779 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers14.avg_buf_msgs 0.019354 # Average number of messages in buffer
-system.ruby.network.int_link_buffers14.avg_stall_time 4.989551 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers15.avg_buf_msgs 0.019672 # Average number of messages in buffer
-system.ruby.network.int_link_buffers15.avg_stall_time 9.802235 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers16.avg_buf_msgs 0.019581 # Average number of messages in buffer
-system.ruby.network.int_link_buffers16.avg_stall_time 6.085230 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers3.port_buffers01.avg_buf_msgs 0.038731 # Average number of messages in buffer
-system.ruby.network.routers3.port_buffers01.avg_stall_time 5.402094 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers3.port_buffers02.avg_buf_msgs 0.006088 # Average number of messages in buffer
-system.ruby.network.routers3.port_buffers02.avg_stall_time 3.758757 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers3.port_buffers03.avg_buf_msgs 0.039094 # Average number of messages in buffer
-system.ruby.network.routers3.port_buffers03.avg_stall_time 13.045000 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers3.port_buffers04.avg_buf_msgs 0.046045 # Average number of messages in buffer
-system.ruby.network.routers3.port_buffers04.avg_stall_time 4.171641 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers3.port_buffers05.avg_buf_msgs 0.019354 # Average number of messages in buffer
-system.ruby.network.routers3.port_buffers05.avg_stall_time 3.991731 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers3.port_buffers06.avg_buf_msgs 0.021171 # Average number of messages in buffer
-system.ruby.network.routers3.port_buffers06.avg_stall_time 8.802917 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers3.port_buffers07.avg_buf_msgs 0.019581 # Average number of messages in buffer
-system.ruby.network.routers3.port_buffers07.avg_stall_time 5.087956 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers3.percent_links_utilized 13.825598
-system.ruby.network.routers3.msg_count.Control::0 1771
-system.ruby.network.routers3.msg_count.Request_Control::2 268
-system.ruby.network.routers3.msg_count.Response_Data::1 2546
-system.ruby.network.routers3.msg_count.Response_Control::1 1796
-system.ruby.network.routers3.msg_count.Response_Control::2 852
-system.ruby.network.routers3.msg_count.Writeback_Data::0 769
-system.ruby.network.routers3.msg_count.Writeback_Data::1 218
-system.ruby.network.routers3.msg_count.Writeback_Control::0 33
-system.ruby.network.routers3.msg_bytes.Control::0 14168
-system.ruby.network.routers3.msg_bytes.Request_Control::2 2144
-system.ruby.network.routers3.msg_bytes.Response_Data::1 183312
-system.ruby.network.routers3.msg_bytes.Response_Control::1 14368
-system.ruby.network.routers3.msg_bytes.Response_Control::2 6816
-system.ruby.network.routers3.msg_bytes.Writeback_Data::0 55368
-system.ruby.network.routers3.msg_bytes.Writeback_Data::1 15696
-system.ruby.network.routers3.msg_bytes.Writeback_Control::0 264
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states
-system.ruby.network.msg_count.Control 5313
-system.ruby.network.msg_count.Request_Control 804
-system.ruby.network.msg_count.Response_Data 7639
-system.ruby.network.msg_count.Response_Control 7944
-system.ruby.network.msg_count.Writeback_Data 2961
-system.ruby.network.msg_count.Writeback_Control 99
-system.ruby.network.msg_byte.Control 42504
-system.ruby.network.msg_byte.Request_Control 6432
-system.ruby.network.msg_byte.Response_Data 550008
-system.ruby.network.msg_byte.Response_Control 63552
-system.ruby.network.msg_byte.Writeback_Data 213192
-system.ruby.network.msg_byte.Writeback_Control 792
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization 10.437064
-system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 268
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 902
-system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 803
-system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 2144
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 64944
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 6424
-system.ruby.network.routers0.throttle1.link_utilization 12.179414
-system.ruby.network.routers0.throttle1.msg_count.Control::0 905
-system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 50
-system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 852
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 769
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 218
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 33
-system.ruby.network.routers0.throttle1.msg_bytes.Control::0 7240
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 400
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 6816
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 55368
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 15696
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 264
-system.ruby.network.routers1.throttle0.link_utilization 21.989505
-system.ruby.network.routers1.throttle0.msg_count.Control::0 905
-system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 864
-system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 911
-system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 852
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0 769
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1 218
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 33
-system.ruby.network.routers1.throttle0.msg_bytes.Control::0 7240
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 62208
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 7288
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 6816
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 55368
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 15696
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 264
-system.ruby.network.routers1.throttle1.link_utilization 19.487290
-system.ruby.network.routers1.throttle1.msg_count.Control::0 866
-system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 268
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1682
-system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 885
-system.ruby.network.routers1.throttle1.msg_bytes.Control::0 6928
-system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 2144
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 121104
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 7080
-system.ruby.network.routers2.throttle0.link_utilization 9.050226
-system.ruby.network.routers2.throttle0.msg_count.Control::0 866
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 780
-system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 82
-system.ruby.network.routers2.throttle0.msg_bytes.Control::0 6928
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 56160
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 656
-system.ruby.network.routers2.throttle1.link_utilization 9.814634
-system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 865
-system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 861
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 62280
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 6888
-system.ruby.network.routers3.throttle0.link_utilization 10.437064
-system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 268
-system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 902
-system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 803
-system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 2144
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 64944
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 6424
-system.ruby.network.routers3.throttle1.link_utilization 21.989505
-system.ruby.network.routers3.throttle1.msg_count.Control::0 905
-system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 864
-system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 911
-system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 852
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0 769
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1 218
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 33
-system.ruby.network.routers3.throttle1.msg_bytes.Control::0 7240
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 62208
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 7288
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 6816
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 55368
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 15696
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 264
-system.ruby.network.routers3.throttle2.link_utilization 9.050226
-system.ruby.network.routers3.throttle2.msg_count.Control::0 866
-system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 780
-system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 82
-system.ruby.network.routers3.throttle2.msg_bytes.Control::0 6928
-system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1 56160
-system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 656
-system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::samples 2559 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::mean 5.696757 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::stdev 7.319490 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0 | 1396 54.55% 54.55% | 8 0.31% 54.87% | 792 30.95% 85.81% | 2 0.08% 85.89% | 285 11.14% 97.03% | 1 0.04% 97.07% | 1 0.04% 97.11% | 70 2.74% 99.84% | 0 0.00% 99.84% | 4 0.16% 100.00% # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::total 2559 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples 3698 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::mean 0.702001 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev 2.286109 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1 | 3361 90.89% 90.89% | 15 0.41% 91.29% | 10 0.27% 91.56% | 43 1.16% 92.73% | 218 5.90% 98.62% | 46 1.24% 99.86% | 3 0.08% 99.95% | 2 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total 3698 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples 268 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2 | 268 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total 268 # delay histogram for vnet_2
-system.ruby.LD.latency_hist_seqr::bucket_size 128
-system.ruby.LD.latency_hist_seqr::max_bucket 1279
-system.ruby.LD.latency_hist_seqr::samples 50
-system.ruby.LD.latency_hist_seqr::mean 631.160000
-system.ruby.LD.latency_hist_seqr::gmean 197.121649
-system.ruby.LD.latency_hist_seqr::stdev 346.030868
-system.ruby.LD.latency_hist_seqr | 11 22.00% 22.00% | 0 0.00% 22.00% | 0 0.00% 22.00% | 0 0.00% 22.00% | 1 2.00% 24.00% | 12 24.00% 48.00% | 21 42.00% 90.00% | 5 10.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.latency_hist_seqr::total 50
-system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
-system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
-system.ruby.LD.hit_latency_hist_seqr::samples 10
-system.ruby.LD.hit_latency_hist_seqr::mean 1
-system.ruby.LD.hit_latency_hist_seqr::gmean 1
-system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.hit_latency_hist_seqr::total 10
-system.ruby.LD.miss_latency_hist_seqr::bucket_size 128
-system.ruby.LD.miss_latency_hist_seqr::max_bucket 1279
-system.ruby.LD.miss_latency_hist_seqr::samples 40
-system.ruby.LD.miss_latency_hist_seqr::mean 788.700000
-system.ruby.LD.miss_latency_hist_seqr::gmean 738.614626
-system.ruby.LD.miss_latency_hist_seqr::stdev 152.194242
-system.ruby.LD.miss_latency_hist_seqr | 1 2.50% 2.50% | 0 0.00% 2.50% | 0 0.00% 2.50% | 0 0.00% 2.50% | 1 2.50% 5.00% | 12 30.00% 35.00% | 21 52.50% 87.50% | 5 12.50% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.miss_latency_hist_seqr::total 40
-system.ruby.ST.latency_hist_seqr::bucket_size 128
-system.ruby.ST.latency_hist_seqr::max_bucket 1279
-system.ruby.ST.latency_hist_seqr::samples 904
-system.ruby.ST.latency_hist_seqr::mean 719.136062
-system.ruby.ST.latency_hist_seqr::gmean 383.374715
-system.ruby.ST.latency_hist_seqr::stdev 298.133155
-system.ruby.ST.latency_hist_seqr | 114 12.61% 12.61% | 8 0.88% 13.50% | 4 0.44% 13.94% | 3 0.33% 14.27% | 5 0.55% 14.82% | 251 27.77% 42.59% | 346 38.27% 80.86% | 108 11.95% 92.81% | 53 5.86% 98.67% | 12 1.33% 100.00%
-system.ruby.ST.latency_hist_seqr::total 904
-system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
-system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
-system.ruby.ST.hit_latency_hist_seqr::samples 91
-system.ruby.ST.hit_latency_hist_seqr::mean 1
-system.ruby.ST.hit_latency_hist_seqr::gmean 1
-system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 91 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.hit_latency_hist_seqr::total 91
-system.ruby.ST.miss_latency_hist_seqr::bucket_size 128
-system.ruby.ST.miss_latency_hist_seqr::max_bucket 1279
-system.ruby.ST.miss_latency_hist_seqr::samples 813
-system.ruby.ST.miss_latency_hist_seqr::mean 799.517835
-system.ruby.ST.miss_latency_hist_seqr::gmean 746.124556
-system.ruby.ST.miss_latency_hist_seqr::stdev 185.954617
-system.ruby.ST.miss_latency_hist_seqr | 23 2.83% 2.83% | 8 0.98% 3.81% | 4 0.49% 4.31% | 3 0.37% 4.67% | 5 0.62% 5.29% | 251 30.87% 36.16% | 346 42.56% 78.72% | 108 13.28% 92.00% | 53 6.52% 98.52% | 12 1.48% 100.00%
-system.ruby.ST.miss_latency_hist_seqr::total 813
-system.ruby.IFETCH.latency_hist_seqr::bucket_size 32
-system.ruby.IFETCH.latency_hist_seqr::max_bucket 319
-system.ruby.IFETCH.latency_hist_seqr::samples 50
-system.ruby.IFETCH.latency_hist_seqr::mean 110.700000
-system.ruby.IFETCH.latency_hist_seqr::gmean 96.182985
-system.ruby.IFETCH.latency_hist_seqr::stdev 52.466607
-system.ruby.IFETCH.latency_hist_seqr | 1 2.00% 2.00% | 9 18.00% 20.00% | 11 22.00% 42.00% | 9 18.00% 60.00% | 13 26.00% 86.00% | 5 10.00% 96.00% | 0 0.00% 96.00% | 2 4.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.latency_hist_seqr::total 50
-system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32
-system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319
-system.ruby.IFETCH.miss_latency_hist_seqr::samples 50
-system.ruby.IFETCH.miss_latency_hist_seqr::mean 110.700000
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean 96.182985
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev 52.466607
-system.ruby.IFETCH.miss_latency_hist_seqr | 1 2.00% 2.00% | 9 18.00% 20.00% | 11 22.00% 42.00% | 9 18.00% 60.00% | 13 26.00% 86.00% | 5 10.00% 96.00% | 0 0.00% 96.00% | 2 4.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.miss_latency_hist_seqr::total 50
-system.ruby.Directory_Controller.Fetch 866 0.00% 0.00%
-system.ruby.Directory_Controller.Data 780 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 865 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 779 0.00% 0.00%
-system.ruby.Directory_Controller.CleanReplacement 82 0.00% 0.00%
-system.ruby.Directory_Controller.I.Fetch 866 0.00% 0.00%
-system.ruby.Directory_Controller.M.Data 780 0.00% 0.00%
-system.ruby.Directory_Controller.M.CleanReplacement 82 0.00% 0.00%
-system.ruby.Directory_Controller.IM.Memory_Data 865 0.00% 0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack 779 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load 51 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ifetch 55 0.00% 0.00%
-system.ruby.L1Cache_Controller.Store 905 0.00% 0.00%
-system.ruby.L1Cache_Controller.Inv 268 0.00% 0.00%
-system.ruby.L1Cache_Controller.L1_Replacement 11918 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data_Exclusive 39 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data_all_Acks 863 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ack_all 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.WB_Ack 802 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Load 41 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Ifetch 50 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Store 813 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement 92 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.Store 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.Inv 37 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement 5 0.00% 0.00%
-system.ruby.L1Cache_Controller.E.Inv 6 0.00% 0.00%
-system.ruby.L1Cache_Controller.E.L1_Replacement 33 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Load 10 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Store 91 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Inv 43 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement 769 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Inv 7 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.L1_Replacement 452 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data_Exclusive 39 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data_all_Acks 44 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement 10567 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.Data_all_Acks 812 0.00% 0.00%
-system.ruby.L1Cache_Controller.SM.Ack_all 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS_I.Data_all_Acks 7 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_I.Ifetch 5 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_I.Inv 175 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_I.WB_Ack 627 0.00% 0.00%
-system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack 175 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GET_INSTR 50 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETS 41 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETX 813 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_UPGRADE 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTX 627 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTX_old 314 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement 568 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement_clean 551 0.00% 0.00%
-system.ruby.L2Cache_Controller.Mem_Data 864 0.00% 0.00%
-system.ruby.L2Cache_Controller.Mem_Ack 861 0.00% 0.00%
-system.ruby.L2Cache_Controller.WB_Data 212 0.00% 0.00%
-system.ruby.L2Cache_Controller.WB_Data_clean 6 0.00% 0.00%
-system.ruby.L2Cache_Controller.Ack_all 50 0.00% 0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock 852 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 44 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS 39 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX 783 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_PUTX_old 163 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETS 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETX 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_UPGRADE 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 44 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GET_INSTR 6 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX 26 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 568 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement_clean 26 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_PUTX 627 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 224 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 12 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.Mem_Ack 861 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 139 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data 212 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 6 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.Ack_all 6 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_I.Ack_all 44 0.00% 0.00%
-system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 3 0.00% 0.00%
-system.ruby.L2Cache_Controller.ISS.Mem_Data 38 0.00% 0.00%
-system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 96 0.00% 0.00%
-system.ruby.L2Cache_Controller.IS.Mem_Data 44 0.00% 0.00%
-system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 132 0.00% 0.00%
-system.ruby.L2Cache_Controller.IM.Mem_Data 782 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 5 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 26 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 847 0.00% 0.00%
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
-
-[system]
-type=System
-children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:268435455:0:0:0:0
-memories=system.mem_ctrls
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.sys_port_proxy.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=RubyTester
-check_flush=false
-checks_to_complete=100
-clk_domain=system.clk_domain
-deadlock_threshold=50000
-default_p_state=UNDEFINED
-eventq_index=0
-num_cpus=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-system=system
-wakeup_frequency=10
-cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000
-
-[system.mem_ctrls]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-page_policy=open_adaptive
-power_model=Null
-range=0:268435455:5:19:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10
-static_frontend_latency=10
-tBURST=5
-tCCD_L=0
-tCK=1
-tCL=14
-tCS=3
-tRAS=35
-tRCD=14
-tREFI=7800
-tRFC=260
-tRP=14
-tRRD=6
-tRRD_L=0
-tRTP=8
-tRTW=3
-tWR=15
-tWTR=8
-tXAW=30
-tXP=6
-tXPDLL=0
-tXS=270
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.ruby.dir_cntrl0.memory
-
-[system.ruby]
-type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
-access_backing_store=false
-all_instructions=false
-block_size_bytes=64
-clk_domain=system.ruby.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hot_lines=false
-memory_size_bits=48
-num_of_sequencers=1
-number_of_virtual_networks=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-phys_mem=Null
-power_model=Null
-randomization=true
-
-[system.ruby.clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.ruby.dir_cntrl0]
-type=Directory_Controller
-children=directory forwardFromDir requestToDir responseFromDir responseFromMemory responseToDir
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-default_p_state=UNDEFINED
-directory=system.ruby.dir_cntrl0.directory
-directory_latency=6
-eventq_index=0
-forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir
-number_of_TBEs=256
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-recycle_latency=10
-requestToDir=system.ruby.dir_cntrl0.requestToDir
-responseFromDir=system.ruby.dir_cntrl0.responseFromDir
-responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory
-responseToDir=system.ruby.dir_cntrl0.responseToDir
-ruby_system=system.ruby
-system=system
-to_memory_controller_latency=1
-transitions_per_cycle=32
-version=0
-memory=system.mem_ctrls.port
-
-[system.ruby.dir_cntrl0.directory]
-type=RubyDirectoryMemory
-eventq_index=0
-numa_high_bit=5
-size=268435456
-version=0
-
-[system.ruby.dir_cntrl0.forwardFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[6]
-
-[system.ruby.dir_cntrl0.requestToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[5]
-
-[system.ruby.dir_cntrl0.responseFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[5]
-
-[system.ruby.dir_cntrl0.responseFromMemory]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.dir_cntrl0.responseToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[6]
-
-[system.ruby.l1_cntrl0]
-type=L1Cache_Controller
-children=L1Dcache L1Icache mandatoryQueue requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer triggerQueue
-L1Dcache=system.ruby.l1_cntrl0.L1Dcache
-L1Icache=system.ruby.l1_cntrl0.L1Icache
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-default_p_state=UNDEFINED
-eventq_index=0
-l2_select_num_bits=0
-mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
-number_of_TBEs=256
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-recycle_latency=10
-requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache
-requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache
-request_latency=2
-responseFromL1Cache=system.ruby.l1_cntrl0.responseFromL1Cache
-responseToL1Cache=system.ruby.l1_cntrl0.responseToL1Cache
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl0.sequencer
-system=system
-transitions_per_cycle=32
-triggerQueue=system.ruby.l1_cntrl0.triggerQueue
-use_timeout_latency=50
-version=0
-
-[system.ruby.l1_cntrl0.L1Dcache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l1_cntrl0.L1Dcache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.L1Dcache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl0.L1Icache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=true
-replacement_policy=system.ruby.l1_cntrl0.L1Icache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.L1Icache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl0.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl0.requestFromL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[0]
-
-[system.ruby.l1_cntrl0.requestToL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[0]
-
-[system.ruby.l1_cntrl0.responseFromL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[1]
-
-[system.ruby.l1_cntrl0.responseToL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[1]
-
-[system.ruby.l1_cntrl0.sequencer]
-type=RubySequencer
-clk_domain=system.ruby.clk_domain
-coreid=99
-dcache=system.ruby.l1_cntrl0.L1Dcache
-dcache_hit_latency=1
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.ruby.l1_cntrl0.L1Icache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=true
-version=0
-slave=system.cpu.cpuInstDataPort[0]
-
-[system.ruby.l1_cntrl0.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.l2_cntrl0]
-type=L2Cache_Controller
-children=GlobalRequestFromL2Cache GlobalRequestToL2Cache L1RequestFromL2Cache L1RequestToL2Cache L2cache responseFromL2Cache responseToL2Cache triggerQueue
-GlobalRequestFromL2Cache=system.ruby.l2_cntrl0.GlobalRequestFromL2Cache
-GlobalRequestToL2Cache=system.ruby.l2_cntrl0.GlobalRequestToL2Cache
-L1RequestFromL2Cache=system.ruby.l2_cntrl0.L1RequestFromL2Cache
-L1RequestToL2Cache=system.ruby.l2_cntrl0.L1RequestToL2Cache
-L2cache=system.ruby.l2_cntrl0.L2cache
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-default_p_state=UNDEFINED
-eventq_index=0
-number_of_TBEs=256
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-recycle_latency=10
-request_latency=2
-responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache
-responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache
-response_latency=2
-ruby_system=system.ruby
-system=system
-transitions_per_cycle=32
-triggerQueue=system.ruby.l2_cntrl0.triggerQueue
-version=0
-
-[system.ruby.l2_cntrl0.GlobalRequestFromL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[2]
-
-[system.ruby.l2_cntrl0.GlobalRequestToL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[2]
-
-[system.ruby.l2_cntrl0.L1RequestFromL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[3]
-
-[system.ruby.l2_cntrl0.L1RequestToL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[3]
-
-[system.ruby.l2_cntrl0.L2cache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l2_cntrl0.L2cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=512
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l2_cntrl0.L2cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=512
-
-[system.ruby.l2_cntrl0.responseFromL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[4]
-
-[system.ruby.l2_cntrl0.responseToL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[4]
-
-[system.ruby.l2_cntrl0.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.memctrl_clk_domain]
-type=DerivedClockDomain
-clk_divider=3
-clk_domain=system.ruby.clk_domain
-eventq_index=0
-
-[system.ruby.network]
-type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3
-adaptive_routing=false
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-control_msg_size=8
-default_p_state=UNDEFINED
-endpoint_bandwidth=1000
-eventq_index=0
-ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5
-netifs=
-number_of_virtual_networks=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3
-ruby_system=system.ruby
-topology=Crossbar
-master=system.ruby.l1_cntrl0.requestToL1Cache.slave system.ruby.l1_cntrl0.responseToL1Cache.slave system.ruby.l2_cntrl0.GlobalRequestToL2Cache.slave system.ruby.l2_cntrl0.L1RequestToL2Cache.slave system.ruby.l2_cntrl0.responseToL2Cache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.responseToDir.slave
-slave=system.ruby.l1_cntrl0.requestFromL1Cache.master system.ruby.l1_cntrl0.responseFromL1Cache.master system.ruby.l2_cntrl0.GlobalRequestFromL2Cache.master system.ruby.l2_cntrl0.L1RequestFromL2Cache.master system.ruby.l2_cntrl0.responseFromL2Cache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master
-
-[system.ruby.network.ext_links0]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.l1_cntrl0
-int_node=system.ruby.network.routers0
-latency=1
-link_id=0
-weight=1
-
-[system.ruby.network.ext_links1]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.l2_cntrl0
-int_node=system.ruby.network.routers1
-latency=1
-link_id=1
-weight=1
-
-[system.ruby.network.ext_links2]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.dir_cntrl0
-int_node=system.ruby.network.routers2
-latency=1
-link_id=2
-weight=1
-
-[system.ruby.network.int_link_buffers00]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers01]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers02]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
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-type=MessageBuffer
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-[system.ruby.network.int_link_buffers27]
-type=MessageBuffer
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-
-[system.ruby.network.int_link_buffers28]
-type=MessageBuffer
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-[system.ruby.network.int_link_buffers29]
-type=MessageBuffer
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-[system.ruby.network.int_link_buffers30]
-type=MessageBuffer
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-
-[system.ruby.network.int_link_buffers31]
-type=MessageBuffer
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-
-[system.ruby.network.int_link_buffers32]
-type=MessageBuffer
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-
-[system.ruby.network.int_link_buffers33]
-type=MessageBuffer
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-
-[system.ruby.network.int_link_buffers34]
-type=MessageBuffer
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-
-[system.ruby.network.int_link_buffers35]
-type=MessageBuffer
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-
-[system.ruby.network.int_links0]
-type=SimpleIntLink
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-dst_inport=
-dst_node=system.ruby.network.routers3
-eventq_index=0
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-weight=1
-
-[system.ruby.network.int_links1]
-type=SimpleIntLink
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-dst_inport=
-dst_node=system.ruby.network.routers3
-eventq_index=0
-latency=1
-link_id=4
-src_node=system.ruby.network.routers1
-src_outport=
-weight=1
-
-[system.ruby.network.int_links2]
-type=SimpleIntLink
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-dst_inport=
-dst_node=system.ruby.network.routers3
-eventq_index=0
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-link_id=5
-src_node=system.ruby.network.routers2
-src_outport=
-weight=1
-
-[system.ruby.network.int_links3]
-type=SimpleIntLink
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-dst_node=system.ruby.network.routers0
-eventq_index=0
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-
-[system.ruby.network.int_links4]
-type=SimpleIntLink
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-weight=1
-
-[system.ruby.network.int_links5]
-type=SimpleIntLink
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-
-[system.ruby.network.routers0]
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-
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-
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-
-[system.ruby.network.routers0.port_buffers06]
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-
-[system.ruby.network.routers0.port_buffers07]
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-[system.ruby.network.routers1]
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-power_model=Null
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-
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-[system.ruby.network.routers1.port_buffers07]
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-[system.ruby.network.routers2]
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-
-[system.ruby.network.routers2.port_buffers00]
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-[system.ruby.network.routers2.port_buffers03]
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-[system.ruby.network.routers2.port_buffers07]
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-[system.ruby.network.routers2.port_buffers09]
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-[system.ruby.network.routers2.port_buffers10]
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-[system.ruby.network.routers2.port_buffers11]
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-[system.ruby.network.routers3]
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-[system.ruby.network.routers3.port_buffers00]
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-[system.ruby.network.routers3.port_buffers03]
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-[system.ruby.network.routers3.port_buffers04]
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-[system.ruby.network.routers3.port_buffers05]
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-[system.ruby.network.routers3.port_buffers06]
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-
-[system.ruby.network.routers3.port_buffers07]
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-
-[system.ruby.network.routers3.port_buffers08]
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-
-[system.ruby.network.routers3.port_buffers09]
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-
-[system.ruby.network.routers3.port_buffers10]
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-
-[system.ruby.network.routers3.port_buffers11]
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-
-[system.ruby.network.routers3.port_buffers12]
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-
-[system.ruby.network.routers3.port_buffers13]
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-
-[system.ruby.network.routers3.port_buffers14]
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-[system.ruby.network.routers3.port_buffers15]
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-[system.ruby.network.routers3.port_buffers16]
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-
-[system.ruby.network.routers3.port_buffers17]
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-
-[system.sys_port_proxy]
-type=RubyPortProxy
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-default_p_state=UNDEFINED
-eventq_index=0
-is_cpu_sequencer=true
-no_retry_on_stall=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=0
-slave=system.system_port
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
+++ /dev/null
-Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
-Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 13 2016 20:30:58
-gem5 started Oct 13 2016 20:31:25
-gem5 executing on e108600-lin, pid 17788
-command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
-
-Global frequency set at 1000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 57351 because Ruby Tester completed
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000057 # Number of seconds simulated
-sim_ticks 57351 # Number of ticks simulated
-final_tick 57351 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 566783 # Simulator tick rate (ticks/s)
-host_mem_usage 396800 # Number of bytes of host memory used
-host_seconds 0.10 # Real time elapsed on the host
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 56384 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 56384 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 50624 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 50624 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 881 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 881 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 791 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 791 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 983138916 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 983138916 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 882704748 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 882704748 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 1865843664 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 1865843664 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 881 # Number of read requests accepted
-system.mem_ctrls.writeReqs 791 # Number of write requests accepted
-system.mem_ctrls.readBursts 881 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 791 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 48256 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 8128 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 42816 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 56384 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 50624 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 127 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 95 # Number of DRAM write bursts merged with an existing one
-system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 222 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 247 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 228 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 57 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 195 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 221 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 201 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 52 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
-system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
-system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 57270 # Total gap between requests
-system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 881 # Read request sizes (log2)
-system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 791 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 553 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 198 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2 3 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 25 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 26 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 31 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 45 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 43 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 42 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 38 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 38 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 38 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 38 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33 2 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 103 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 877.359223 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 782.793653 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 281.638652 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 2 1.94% 1.94% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 4 3.88% 5.83% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 6 5.83% 11.65% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 6 5.83% 17.48% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 4 3.88% 21.36% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 3 2.91% 24.27% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 2 1.94% 26.21% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 76 73.79% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 103 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 38 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 19.447368 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 19.196443 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 3.599530 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15 1 2.63% 2.63% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17 9 23.68% 26.32% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19 10 26.32% 52.63% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-21 13 34.21% 86.84% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::22-23 3 7.89% 94.74% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::24-25 1 2.63% 97.37% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::36-37 1 2.63% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 38 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 38 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 17.605263 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 17.559134 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 1.284828 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 13 34.21% 34.21% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 1 2.63% 36.84% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 13 34.21% 71.05% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19 10 26.32% 97.37% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20 1 2.63% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 38 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 10814 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 25140 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 3770 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 14.34 # Average queueing delay per DRAM burst
-system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 33.34 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 841.42 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 746.56 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 983.14 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 882.70 # Average system write bandwidth in MiByte/s
-system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 12.41 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 6.57 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 5.83 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 1.47 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 24.63 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 656 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 661 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 87.00 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 94.97 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 34.25 # Average gap between requests
-system.mem_ctrls.pageHitRate 90.83 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 756840 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 397992 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 8613696 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 5587488 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 11006472 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 91776 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.actPowerDownEnergy 15034776 # Energy for active power-down per rank (pJ)
-system.mem_ctrls_0.prePowerDownEnergy 1536 # Energy for precharge power-down per rank (pJ)
-system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
-system.mem_ctrls_0.totalEnergy 45793056 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 798.470053 # Core power per rank (mW)
-system.mem_ctrls_0.totalIdleTime 32938 # Total Idle time Per DRAM Rank
-system.mem_ctrls_0.memoryStateTime::IDLE 43 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 1820 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 4 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 22513 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 32971 # Time in different power states
-system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 224352 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 3002880 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ)
-system.mem_ctrls_1.prePowerDownEnergy 2889984 # Energy for precharge power-down per rank (pJ)
-system.mem_ctrls_1.selfRefreshEnergy 9963120 # Energy for self refresh per rank (pJ)
-system.mem_ctrls_1.totalEnergy 17309616 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 301.818905 # Core power per rank (mW)
-system.mem_ctrls_1.totalIdleTime 7526 # Total Idle time Per DRAM Rank
-system.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 526 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::SREF 41513 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 7526 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states
-system.ruby.clk_domain.clock 1 # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states
-system.ruby.outstanding_req_hist_seqr::bucket_size 2
-system.ruby.outstanding_req_hist_seqr::max_bucket 19
-system.ruby.outstanding_req_hist_seqr::samples 1014
-system.ruby.outstanding_req_hist_seqr::mean 15.673570
-system.ruby.outstanding_req_hist_seqr::gmean 15.569970
-system.ruby.outstanding_req_hist_seqr::stdev 1.195975
-system.ruby.outstanding_req_hist_seqr | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.49% | 2 0.20% 0.69% | 4 0.39% 1.08% | 2 0.20% 1.28% | 3 0.30% 1.58% | 194 19.13% 20.71% | 804 79.29% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist_seqr::total 1014
-system.ruby.latency_hist_seqr::bucket_size 256
-system.ruby.latency_hist_seqr::max_bucket 2559
-system.ruby.latency_hist_seqr::samples 999
-system.ruby.latency_hist_seqr::mean 900.097097
-system.ruby.latency_hist_seqr::gmean 478.512857
-system.ruby.latency_hist_seqr::stdev 377.349343
-system.ruby.latency_hist_seqr | 145 14.51% 14.51% | 9 0.90% 15.42% | 4 0.40% 15.82% | 380 38.04% 53.85% | 412 41.24% 95.10% | 49 4.90% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist_seqr::total 999
-system.ruby.hit_latency_hist_seqr::bucket_size 1
-system.ruby.hit_latency_hist_seqr::max_bucket 9
-system.ruby.hit_latency_hist_seqr::samples 90
-system.ruby.hit_latency_hist_seqr::mean 1
-system.ruby.hit_latency_hist_seqr::gmean 1
-system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 90 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist_seqr::total 90
-system.ruby.miss_latency_hist_seqr::bucket_size 256
-system.ruby.miss_latency_hist_seqr::max_bucket 2559
-system.ruby.miss_latency_hist_seqr::samples 909
-system.ruby.miss_latency_hist_seqr::mean 989.116612
-system.ruby.miss_latency_hist_seqr::gmean 881.514808
-system.ruby.miss_latency_hist_seqr::stdev 261.625282
-system.ruby.miss_latency_hist_seqr | 55 6.05% 6.05% | 9 0.99% 7.04% | 4 0.44% 7.48% | 380 41.80% 49.28% | 412 45.32% 94.61% | 49 5.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.miss_latency_hist_seqr::total 909
-system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.082752 # Average number of messages in buffer
-system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 5.967569 # Average number of cycles messages are stalled in this MB
-system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.029153 # Average number of messages in buffer
-system.ruby.dir_cntrl0.requestToDir.avg_stall_time 8.096701 # Average number of cycles messages are stalled in this MB
-system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.015361 # Average number of messages in buffer
-system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.998710 # Average number of cycles messages are stalled in this MB
-system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029153 # Average number of messages in buffer
-system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.998727 # Average number of cycles messages are stalled in this MB
-system.ruby.dir_cntrl0.responseToDir.avg_buf_msgs 0.029136 # Average number of messages in buffer
-system.ruby.dir_cntrl0.responseToDir.avg_stall_time 8.057888 # Average number of cycles messages are stalled in this MB
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 88 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 859 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 947 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 2 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 50 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 52 # Number of cache demand accesses
-system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 14.523364 # Average number of messages in buffer
-system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 864.375262 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.requestFromL1Cache.avg_buf_msgs 0.063224 # Average number of messages in buffer
-system.ruby.l1_cntrl0.requestFromL1Cache.avg_stall_time 1.999861 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.requestToL1Cache.avg_buf_msgs 0.015762 # Average number of messages in buffer
-system.ruby.l1_cntrl0.requestToL1Cache.avg_stall_time 8.191536 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.responseFromL1Cache.avg_buf_msgs 0.063224 # Average number of messages in buffer
-system.ruby.l1_cntrl0.responseFromL1Cache.avg_stall_time 1.996792 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.responseToL1Cache.avg_buf_msgs 0.015849 # Average number of messages in buffer
-system.ruby.l1_cntrl0.responseToL1Cache.avg_stall_time 8.002040 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 2 # Number of times a store aliased with a pending load
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 89 # Number of times a store aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 5 # Number of times a load aliased with a pending store
-system.ruby.l1_cntrl0.triggerQueue.avg_buf_msgs 0.014263 # Average number of messages in buffer
-system.ruby.l1_cntrl0.triggerQueue.avg_stall_time 0.998431 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states
-system.ruby.l2_cntrl0.GlobalRequestFromL2Cache.avg_buf_msgs 0.058307 # Average number of messages in buffer
-system.ruby.l2_cntrl0.GlobalRequestFromL2Cache.avg_stall_time 1.999582 # Average number of cycles messages are stalled in this MB
-system.ruby.l2_cntrl0.GlobalRequestToL2Cache.avg_buf_msgs 0.013792 # Average number of messages in buffer
-system.ruby.l2_cntrl0.GlobalRequestToL2Cache.avg_stall_time 12.105995 # Average number of cycles messages are stalled in this MB
-system.ruby.l2_cntrl0.L1RequestFromL2Cache.avg_buf_msgs 0.031525 # Average number of messages in buffer
-system.ruby.l2_cntrl0.L1RequestFromL2Cache.avg_stall_time 1.994699 # Average number of cycles messages are stalled in this MB
-system.ruby.l2_cntrl0.L1RequestToL2Cache.avg_buf_msgs 0.031612 # Average number of messages in buffer
-system.ruby.l2_cntrl0.L1RequestToL2Cache.avg_stall_time 8.273016 # Average number of cycles messages are stalled in this MB
-system.ruby.l2_cntrl0.L2cache.demand_hits 28 # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses 881 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 909 # Number of cache demand accesses
-system.ruby.l2_cntrl0.responseFromL2Cache.avg_buf_msgs 0.089971 # Average number of messages in buffer
-system.ruby.l2_cntrl0.responseFromL2Cache.avg_stall_time 1.997106 # Average number of cycles messages are stalled in this MB
-system.ruby.l2_cntrl0.responseToL2Cache.avg_buf_msgs 0.046956 # Average number of messages in buffer
-system.ruby.l2_cntrl0.responseToL2Cache.avg_stall_time 7.981239 # Average number of cycles messages are stalled in this MB
-system.ruby.l2_cntrl0.triggerQueue.avg_buf_msgs 0.013879 # Average number of messages in buffer
-system.ruby.l2_cntrl0.triggerQueue.avg_stall_time 0.998588 # Average number of cycles messages are stalled in this MB
-system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states
-system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.port_buffers00.avg_buf_msgs 0.015762 # Average number of messages in buffer
-system.ruby.network.routers0.port_buffers00.avg_stall_time 7.194431 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers0.port_buffers02.avg_buf_msgs 0.015849 # Average number of messages in buffer
-system.ruby.network.routers0.port_buffers02.avg_stall_time 7.003714 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.035622 # Average number of messages in buffer
-system.ruby.network.routers0.port_buffers03.avg_stall_time 3.255039 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers0.port_buffers05.avg_buf_msgs 0.034628 # Average number of messages in buffer
-system.ruby.network.routers0.port_buffers05.avg_stall_time 3.156385 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized 8.691653
-system.ruby.network.routers0.msg_count.Request_Control::0 909
-system.ruby.network.routers0.msg_count.Response_Data::2 881
-system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 28
-system.ruby.network.routers0.msg_count.Writeback_Data::2 904
-system.ruby.network.routers0.msg_count.Writeback_Control::0 1808
-system.ruby.network.routers0.msg_count.Unblock_Control::2 908
-system.ruby.network.routers0.msg_bytes.Request_Control::0 7272
-system.ruby.network.routers0.msg_bytes.Response_Data::2 63432
-system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 2016
-system.ruby.network.routers0.msg_bytes.Writeback_Data::2 65088
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0 14464
-system.ruby.network.routers0.msg_bytes.Unblock_Control::2 7264
-system.ruby.network.routers1.port_buffers00.avg_buf_msgs 0.031612 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers00.avg_stall_time 7.273312 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.port_buffers01.avg_buf_msgs 0.013792 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers01.avg_stall_time 11.111696 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.046956 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers02.avg_stall_time 6.982738 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.port_buffers03.avg_buf_msgs 0.019127 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers03.avg_stall_time 3.205660 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.port_buffers04.avg_buf_msgs 0.030740 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers04.avg_stall_time 3.098532 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.port_buffers05.avg_buf_msgs 0.048542 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers05.avg_stall_time 3.049118 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized 16.709822
-system.ruby.network.routers1.msg_count.Request_Control::0 909
-system.ruby.network.routers1.msg_count.Request_Control::1 881
-system.ruby.network.routers1.msg_count.Response_Data::2 1762
-system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2 28
-system.ruby.network.routers1.msg_count.Writeback_Data::2 1695
-system.ruby.network.routers1.msg_count.Writeback_Control::0 1808
-system.ruby.network.routers1.msg_count.Writeback_Control::1 1582
-system.ruby.network.routers1.msg_count.Unblock_Control::2 1788
-system.ruby.network.routers1.msg_bytes.Request_Control::0 7272
-system.ruby.network.routers1.msg_bytes.Request_Control::1 7048
-system.ruby.network.routers1.msg_bytes.Response_Data::2 126864
-system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2 2016
-system.ruby.network.routers1.msg_bytes.Writeback_Data::2 122040
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0 14464
-system.ruby.network.routers1.msg_bytes.Writeback_Control::1 12656
-system.ruby.network.routers1.msg_bytes.Unblock_Control::2 14304
-system.ruby.network.routers2.port_buffers01.avg_buf_msgs 0.029153 # Average number of messages in buffer
-system.ruby.network.routers2.port_buffers01.avg_stall_time 7.097137 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.port_buffers02.avg_buf_msgs 0.029136 # Average number of messages in buffer
-system.ruby.network.routers2.port_buffers02.avg_stall_time 7.059858 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.014891 # Average number of messages in buffer
-system.ruby.network.routers2.port_buffers04.avg_stall_time 7.047653 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.port_buffers05.avg_buf_msgs 0.016006 # Average number of messages in buffer
-system.ruby.network.routers2.port_buffers05.avg_stall_time 2.063241 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized 8.016861
-system.ruby.network.routers2.msg_count.Request_Control::1 881
-system.ruby.network.routers2.msg_count.Response_Data::2 881
-system.ruby.network.routers2.msg_count.Writeback_Data::2 791
-system.ruby.network.routers2.msg_count.Writeback_Control::1 1582
-system.ruby.network.routers2.msg_count.Unblock_Control::2 880
-system.ruby.network.routers2.msg_bytes.Request_Control::1 7048
-system.ruby.network.routers2.msg_bytes.Response_Data::2 63432
-system.ruby.network.routers2.msg_bytes.Writeback_Data::2 56952
-system.ruby.network.routers2.msg_bytes.Writeback_Control::1 12656
-system.ruby.network.routers2.msg_bytes.Unblock_Control::2 7040
-system.ruby.network.int_link_buffers00.avg_buf_msgs 0.031612 # Average number of messages in buffer
-system.ruby.network.int_link_buffers00.avg_stall_time 4.254882 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers02.avg_buf_msgs 0.031594 # Average number of messages in buffer
-system.ruby.network.int_link_buffers02.avg_stall_time 4.154694 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers03.avg_buf_msgs 0.015762 # Average number of messages in buffer
-system.ruby.network.int_link_buffers03.avg_stall_time 4.202905 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers04.avg_buf_msgs 0.029153 # Average number of messages in buffer
-system.ruby.network.int_link_buffers04.avg_stall_time 4.098235 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers05.avg_buf_msgs 0.044985 # Average number of messages in buffer
-system.ruby.network.int_link_buffers05.avg_stall_time 4.047583 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers07.avg_buf_msgs 0.013792 # Average number of messages in buffer
-system.ruby.network.int_link_buffers07.avg_stall_time 8.042091 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers08.avg_buf_msgs 0.015361 # Average number of messages in buffer
-system.ruby.network.int_link_buffers08.avg_stall_time 3.061881 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers09.avg_buf_msgs 0.015762 # Average number of messages in buffer
-system.ruby.network.int_link_buffers09.avg_stall_time 6.197290 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers11.avg_buf_msgs 0.015849 # Average number of messages in buffer
-system.ruby.network.int_link_buffers11.avg_stall_time 6.005353 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers12.avg_buf_msgs 0.031612 # Average number of messages in buffer
-system.ruby.network.int_link_buffers12.avg_stall_time 6.273574 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers13.avg_buf_msgs 0.013792 # Average number of messages in buffer
-system.ruby.network.int_link_buffers13.avg_stall_time 10.117363 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers14.avg_buf_msgs 0.046956 # Average number of messages in buffer
-system.ruby.network.int_link_buffers14.avg_stall_time 5.984203 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers16.avg_buf_msgs 0.029153 # Average number of messages in buffer
-system.ruby.network.int_link_buffers16.avg_stall_time 6.097538 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers17.avg_buf_msgs 0.029136 # Average number of messages in buffer
-system.ruby.network.int_link_buffers17.avg_stall_time 6.061794 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers3.port_buffers00.avg_buf_msgs 0.015762 # Average number of messages in buffer
-system.ruby.network.routers3.port_buffers00.avg_stall_time 5.200115 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers3.port_buffers02.avg_buf_msgs 0.015849 # Average number of messages in buffer
-system.ruby.network.routers3.port_buffers02.avg_stall_time 5.006957 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers3.port_buffers03.avg_buf_msgs 0.032030 # Average number of messages in buffer
-system.ruby.network.routers3.port_buffers03.avg_stall_time 5.273800 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers3.port_buffers04.avg_buf_msgs 0.017140 # Average number of messages in buffer
-system.ruby.network.routers3.port_buffers04.avg_stall_time 9.122995 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers3.port_buffers05.avg_buf_msgs 0.050792 # Average number of messages in buffer
-system.ruby.network.routers3.port_buffers05.avg_stall_time 4.985633 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers3.port_buffers07.avg_buf_msgs 0.029153 # Average number of messages in buffer
-system.ruby.network.routers3.port_buffers07.avg_stall_time 5.097904 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers3.port_buffers08.avg_buf_msgs 0.029136 # Average number of messages in buffer
-system.ruby.network.routers3.port_buffers08.avg_stall_time 5.063694 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers3.percent_links_utilized 11.139881
-system.ruby.network.routers3.msg_count.Request_Control::0 909
-system.ruby.network.routers3.msg_count.Request_Control::1 881
-system.ruby.network.routers3.msg_count.Response_Data::2 1762
-system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2 28
-system.ruby.network.routers3.msg_count.Writeback_Data::2 1695
-system.ruby.network.routers3.msg_count.Writeback_Control::0 1808
-system.ruby.network.routers3.msg_count.Writeback_Control::1 1582
-system.ruby.network.routers3.msg_count.Unblock_Control::2 1788
-system.ruby.network.routers3.msg_bytes.Request_Control::0 7272
-system.ruby.network.routers3.msg_bytes.Request_Control::1 7048
-system.ruby.network.routers3.msg_bytes.Response_Data::2 126864
-system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2 2016
-system.ruby.network.routers3.msg_bytes.Writeback_Data::2 122040
-system.ruby.network.routers3.msg_bytes.Writeback_Control::0 14464
-system.ruby.network.routers3.msg_bytes.Writeback_Control::1 12656
-system.ruby.network.routers3.msg_bytes.Unblock_Control::2 14304
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states
-system.ruby.network.msg_count.Request_Control 5370
-system.ruby.network.msg_count.Response_Data 5286
-system.ruby.network.msg_count.ResponseL2hit_Data 84
-system.ruby.network.msg_count.Writeback_Data 5085
-system.ruby.network.msg_count.Writeback_Control 10170
-system.ruby.network.msg_count.Unblock_Control 5364
-system.ruby.network.msg_byte.Request_Control 42960
-system.ruby.network.msg_byte.Response_Data 380592
-system.ruby.network.msg_byte.ResponseL2hit_Data 6048
-system.ruby.network.msg_byte.Writeback_Data 366120
-system.ruby.network.msg_byte.Writeback_Control 81360
-system.ruby.network.msg_byte.Unblock_Control 42912
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization 7.917909
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 881
-system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 28
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 904
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 63432
-system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 2016
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 7232
-system.ruby.network.routers0.throttle1.link_utilization 9.465397
-system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 909
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 904
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 904
-system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2 908
-system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 7272
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 65088
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 7232
-system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 7264
-system.ruby.network.routers1.throttle0.link_utilization 17.067706
-system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 909
-system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 881
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 904
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 904
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1 791
-system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2 908
-system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 7272
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 63432
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 65088
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 7232
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 6328
-system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 7264
-system.ruby.network.routers1.throttle1.link_utilization 16.351938
-system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 881
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 881
-system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 28
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2 791
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 904
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1 791
-system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 880
-system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 7048
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 63432
-system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2 2016
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 56952
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 7232
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 6328
-system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 7040
-system.ruby.network.routers2.throttle0.link_utilization 8.431414
-system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 881
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 791
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 791
-system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2 880
-system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 7048
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 56952
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 6328
-system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 7040
-system.ruby.network.routers2.throttle1.link_utilization 7.602309
-system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 881
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 791
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 63432
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 6328
-system.ruby.network.routers3.throttle0.link_utilization 7.920524
-system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 881
-system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 28
-system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 904
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 63432
-system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 2016
-system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 7232
-system.ruby.network.routers3.throttle1.link_utilization 17.067706
-system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 909
-system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 881
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 904
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 904
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 791
-system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2 908
-system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0 7272
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2 63432
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 65088
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 7232
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 6328
-system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 7264
-system.ruby.network.routers3.throttle2.link_utilization 8.431414
-system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 881
-system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 791
-system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 791
-system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 880
-system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 7048
-system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 56952
-system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 6328
-system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 7040
-system.ruby.LD.latency_hist_seqr::bucket_size 256
-system.ruby.LD.latency_hist_seqr::max_bucket 2559
-system.ruby.LD.latency_hist_seqr::samples 48
-system.ruby.LD.latency_hist_seqr::mean 885.875000
-system.ruby.LD.latency_hist_seqr::gmean 375.211617
-system.ruby.LD.latency_hist_seqr::stdev 381.714030
-system.ruby.LD.latency_hist_seqr | 7 14.58% 14.58% | 0 0.00% 14.58% | 0 0.00% 14.58% | 21 43.75% 58.33% | 18 37.50% 95.83% | 2 4.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.latency_hist_seqr::total 48
-system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
-system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
-system.ruby.LD.hit_latency_hist_seqr::samples 7
-system.ruby.LD.hit_latency_hist_seqr::mean 1
-system.ruby.LD.hit_latency_hist_seqr::gmean 1
-system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.hit_latency_hist_seqr::total 7
-system.ruby.LD.miss_latency_hist_seqr::bucket_size 256
-system.ruby.LD.miss_latency_hist_seqr::max_bucket 2559
-system.ruby.LD.miss_latency_hist_seqr::samples 41
-system.ruby.LD.miss_latency_hist_seqr::mean 1036.951220
-system.ruby.LD.miss_latency_hist_seqr::gmean 1032.254678
-system.ruby.LD.miss_latency_hist_seqr::stdev 103.845065
-system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 21 51.22% 51.22% | 18 43.90% 95.12% | 2 4.88% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.miss_latency_hist_seqr::total 41
-system.ruby.ST.latency_hist_seqr::bucket_size 256
-system.ruby.ST.latency_hist_seqr::max_bucket 2559
-system.ruby.ST.latency_hist_seqr::samples 899
-system.ruby.ST.latency_hist_seqr::mean 947.919911
-system.ruby.ST.latency_hist_seqr::gmean 545.272647
-system.ruby.ST.latency_hist_seqr::stdev 331.026961
-system.ruby.ST.latency_hist_seqr | 89 9.90% 9.90% | 6 0.67% 10.57% | 4 0.44% 11.01% | 359 39.93% 50.95% | 394 43.83% 94.77% | 47 5.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.latency_hist_seqr::total 899
-system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
-system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
-system.ruby.ST.hit_latency_hist_seqr::samples 81
-system.ruby.ST.hit_latency_hist_seqr::mean 1
-system.ruby.ST.hit_latency_hist_seqr::gmean 1
-system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 81 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.hit_latency_hist_seqr::total 81
-system.ruby.ST.miss_latency_hist_seqr::bucket_size 256
-system.ruby.ST.miss_latency_hist_seqr::max_bucket 2559
-system.ruby.ST.miss_latency_hist_seqr::samples 818
-system.ruby.ST.miss_latency_hist_seqr::mean 1041.685819
-system.ruby.ST.miss_latency_hist_seqr::gmean 1017.650590
-system.ruby.ST.miss_latency_hist_seqr::stdev 150.806361
-system.ruby.ST.miss_latency_hist_seqr | 8 0.98% 0.98% | 6 0.73% 1.71% | 4 0.49% 2.20% | 359 43.89% 46.09% | 394 48.17% 94.25% | 47 5.75% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.miss_latency_hist_seqr::total 818
-system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
-system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
-system.ruby.IFETCH.latency_hist_seqr::samples 52
-system.ruby.IFETCH.latency_hist_seqr::mean 86.442308
-system.ruby.IFETCH.latency_hist_seqr::gmean 62.630120
-system.ruby.IFETCH.latency_hist_seqr::stdev 84.743769
-system.ruby.IFETCH.latency_hist_seqr | 17 32.69% 32.69% | 31 59.62% 92.31% | 1 1.92% 94.23% | 0 0.00% 94.23% | 0 0.00% 94.23% | 2 3.85% 98.08% | 0 0.00% 98.08% | 1 1.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.latency_hist_seqr::total 52
-system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
-system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
-system.ruby.IFETCH.hit_latency_hist_seqr::samples 2
-system.ruby.IFETCH.hit_latency_hist_seqr::mean 1
-system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1
-system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.hit_latency_hist_seqr::total 2
-system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
-system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
-system.ruby.IFETCH.miss_latency_hist_seqr::samples 50
-system.ruby.IFETCH.miss_latency_hist_seqr::mean 89.860000
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean 73.901725
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev 84.644758
-system.ruby.IFETCH.miss_latency_hist_seqr | 15 30.00% 30.00% | 31 62.00% 92.00% | 1 2.00% 94.00% | 0 0.00% 94.00% | 0 0.00% 94.00% | 2 4.00% 98.00% | 0 0.00% 98.00% | 1 2.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.miss_latency_hist_seqr::total 50
-system.ruby.Directory_Controller.GETX 796 0.00% 0.00%
-system.ruby.Directory_Controller.GETS 85 0.00% 0.00%
-system.ruby.Directory_Controller.PUTX 791 0.00% 0.00%
-system.ruby.Directory_Controller.Unblock 81 0.00% 0.00%
-system.ruby.Directory_Controller.Last_Unblock 3 0.00% 0.00%
-system.ruby.Directory_Controller.Exclusive_Unblock 796 0.00% 0.00%
-system.ruby.Directory_Controller.Dirty_Writeback 791 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 881 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 791 0.00% 0.00%
-system.ruby.Directory_Controller.I.GETX 735 0.00% 0.00%
-system.ruby.Directory_Controller.I.GETS 82 0.00% 0.00%
-system.ruby.Directory_Controller.I.Memory_Ack 791 0.00% 0.00%
-system.ruby.Directory_Controller.S.GETX 61 0.00% 0.00%
-system.ruby.Directory_Controller.S.GETS 3 0.00% 0.00%
-system.ruby.Directory_Controller.M.PUTX 791 0.00% 0.00%
-system.ruby.Directory_Controller.IS.Unblock 81 0.00% 0.00%
-system.ruby.Directory_Controller.IS.Memory_Data 82 0.00% 0.00%
-system.ruby.Directory_Controller.SS.Last_Unblock 3 0.00% 0.00%
-system.ruby.Directory_Controller.SS.Memory_Data 3 0.00% 0.00%
-system.ruby.Directory_Controller.MM.Exclusive_Unblock 796 0.00% 0.00%
-system.ruby.Directory_Controller.MM.Memory_Data 796 0.00% 0.00%
-system.ruby.Directory_Controller.MI.Dirty_Writeback 791 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load 48 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ifetch 64 0.00% 0.00%
-system.ruby.L1Cache_Controller.Store 905 0.00% 0.00%
-system.ruby.L1Cache_Controller.L1_Replacement 84079 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data 85 0.00% 0.00%
-system.ruby.L1Cache_Controller.Exclusive_Data 824 0.00% 0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack_Data 904 0.00% 0.00%
-system.ruby.L1Cache_Controller.All_acks 818 0.00% 0.00%
-system.ruby.L1Cache_Controller.Use_Timeout 823 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Load 41 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Ifetch 50 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Store 818 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.Ifetch 2 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement 82 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement 5 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.Use_Timeout 6 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.Load 7 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.Store 70 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.L1_Replacement 817 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.Store 11 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.L1_Replacement 31468 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.Use_Timeout 817 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement 48874 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.Exclusive_Data 818 0.00% 0.00%
-system.ruby.L1Cache_Controller.OM.L1_Replacement 674 0.00% 0.00%
-system.ruby.L1Cache_Controller.OM.All_acks 818 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.L1_Replacement 2159 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data 85 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Exclusive_Data 6 0.00% 0.00%
-system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 82 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Ifetch 12 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Store 6 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 822 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETS 91 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETX 818 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTX 822 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTS_only 82 0.00% 0.00%
-system.ruby.L2Cache_Controller.All_Acks 796 0.00% 0.00%
-system.ruby.L2Cache_Controller.Data 881 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_WBCLEANDATA 82 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 822 0.00% 0.00%
-system.ruby.L2Cache_Controller.Writeback_Ack 791 0.00% 0.00%
-system.ruby.L2Cache_Controller.Unblock 84 0.00% 0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock 824 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement 873 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS 85 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX 796 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 82 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.L1_PUTX 822 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L2_Replacement 82 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS 6 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX 22 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 791 0.00% 0.00%
-system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 82 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 822 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.Data 85 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.Unblock 84 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGM.Data 796 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.All_Acks 796 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 796 0.00% 0.00%
-system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 22 0.00% 0.00%
-system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 6 0.00% 0.00%
-system.ruby.L2Cache_Controller.MI.Writeback_Ack 791 0.00% 0.00%
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
-
-[system]
-type=System
-children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:268435455:0:0:0:0
-memories=system.mem_ctrls
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.sys_port_proxy.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=RubyTester
-check_flush=false
-checks_to_complete=100
-clk_domain=system.clk_domain
-deadlock_threshold=50000
-default_p_state=UNDEFINED
-eventq_index=0
-num_cpus=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-system=system
-wakeup_frequency=10
-cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000
-
-[system.mem_ctrls]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-page_policy=open_adaptive
-power_model=Null
-range=0:268435455:5:19:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10
-static_frontend_latency=10
-tBURST=5
-tCCD_L=0
-tCK=1
-tCL=14
-tCS=3
-tRAS=35
-tRCD=14
-tREFI=7800
-tRFC=260
-tRP=14
-tRRD=6
-tRRD_L=0
-tRTP=8
-tRTW=3
-tWR=15
-tWTR=8
-tXAW=30
-tXP=6
-tXPDLL=0
-tXS=270
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.ruby.dir_cntrl0.memory
-
-[system.ruby]
-type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
-access_backing_store=false
-all_instructions=false
-block_size_bytes=64
-clk_domain=system.ruby.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hot_lines=false
-memory_size_bits=48
-num_of_sequencers=1
-number_of_virtual_networks=6
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-phys_mem=Null
-power_model=Null
-randomization=true
-
-[system.ruby.clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.ruby.dir_cntrl0]
-type=Directory_Controller
-children=directory dmaRequestToDir dmaResponseFromDir persistentFromDir persistentToDir requestFromDir requestToDir responseFromDir responseFromMemory responseToDir
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-default_p_state=UNDEFINED
-directory=system.ruby.dir_cntrl0.directory
-directory_latency=5
-distributed_persistent=true
-dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir
-dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir
-eventq_index=0
-fixed_timeout_latency=100
-l2_select_num_bits=0
-number_of_TBEs=256
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-persistentFromDir=system.ruby.dir_cntrl0.persistentFromDir
-persistentToDir=system.ruby.dir_cntrl0.persistentToDir
-power_model=Null
-recycle_latency=10
-reissue_wakeup_latency=10
-requestFromDir=system.ruby.dir_cntrl0.requestFromDir
-requestToDir=system.ruby.dir_cntrl0.requestToDir
-responseFromDir=system.ruby.dir_cntrl0.responseFromDir
-responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory
-responseToDir=system.ruby.dir_cntrl0.responseToDir
-ruby_system=system.ruby
-system=system
-to_memory_controller_latency=1
-transitions_per_cycle=32
-version=0
-memory=system.mem_ctrls.port
-
-[system.ruby.dir_cntrl0.directory]
-type=RubyDirectoryMemory
-eventq_index=0
-numa_high_bit=5
-size=268435456
-version=0
-
-[system.ruby.dir_cntrl0.dmaRequestToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[10]
-
-[system.ruby.dir_cntrl0.dmaResponseFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[9]
-
-[system.ruby.dir_cntrl0.persistentFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[8]
-
-[system.ruby.dir_cntrl0.persistentToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[9]
-
-[system.ruby.dir_cntrl0.requestFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[6]
-
-[system.ruby.dir_cntrl0.requestToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[7]
-
-[system.ruby.dir_cntrl0.responseFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[7]
-
-[system.ruby.dir_cntrl0.responseFromMemory]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.dir_cntrl0.responseToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[8]
-
-[system.ruby.l1_cntrl0]
-type=L1Cache_Controller
-children=L1Dcache L1Icache mandatoryQueue persistentFromL1Cache persistentToL1Cache requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer
-L1Dcache=system.ruby.l1_cntrl0.L1Dcache
-L1Icache=system.ruby.l1_cntrl0.L1Icache
-N_tokens=2
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-default_p_state=UNDEFINED
-dynamic_timeout_enabled=true
-eventq_index=0
-fixed_timeout_latency=300
-l1_request_latency=2
-l1_response_latency=2
-l2_select_num_bits=0
-mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
-no_mig_atomic=true
-number_of_TBEs=256
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-persistentFromL1Cache=system.ruby.l1_cntrl0.persistentFromL1Cache
-persistentToL1Cache=system.ruby.l1_cntrl0.persistentToL1Cache
-power_model=Null
-recycle_latency=10
-reissue_wakeup_latency=10
-requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache
-requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache
-responseFromL1Cache=system.ruby.l1_cntrl0.responseFromL1Cache
-responseToL1Cache=system.ruby.l1_cntrl0.responseToL1Cache
-retry_threshold=1
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl0.sequencer
-system=system
-transitions_per_cycle=32
-use_timeout_latency=50
-version=0
-
-[system.ruby.l1_cntrl0.L1Dcache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l1_cntrl0.L1Dcache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.L1Dcache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl0.L1Icache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l1_cntrl0.L1Icache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.L1Icache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl0.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl0.persistentFromL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[2]
-
-[system.ruby.l1_cntrl0.persistentToL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[2]
-
-[system.ruby.l1_cntrl0.requestFromL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[0]
-
-[system.ruby.l1_cntrl0.requestToL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[0]
-
-[system.ruby.l1_cntrl0.responseFromL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[1]
-
-[system.ruby.l1_cntrl0.responseToL1Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[1]
-
-[system.ruby.l1_cntrl0.sequencer]
-type=RubySequencer
-clk_domain=system.ruby.clk_domain
-coreid=99
-dcache=system.ruby.l1_cntrl0.L1Dcache
-dcache_hit_latency=1
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.ruby.l1_cntrl0.L1Icache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=true
-version=0
-slave=system.cpu.cpuInstDataPort[0]
-
-[system.ruby.l2_cntrl0]
-type=L2Cache_Controller
-children=GlobalRequestFromL2Cache GlobalRequestToL2Cache L1RequestFromL2Cache L1RequestToL2Cache L2cache persistentToL2Cache responseFromL2Cache responseToL2Cache
-GlobalRequestFromL2Cache=system.ruby.l2_cntrl0.GlobalRequestFromL2Cache
-GlobalRequestToL2Cache=system.ruby.l2_cntrl0.GlobalRequestToL2Cache
-L1RequestFromL2Cache=system.ruby.l2_cntrl0.L1RequestFromL2Cache
-L1RequestToL2Cache=system.ruby.l2_cntrl0.L1RequestToL2Cache
-L2cache=system.ruby.l2_cntrl0.L2cache
-N_tokens=2
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-default_p_state=UNDEFINED
-eventq_index=0
-filtering_enabled=true
-l2_request_latency=5
-l2_response_latency=5
-number_of_TBEs=256
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-persistentToL2Cache=system.ruby.l2_cntrl0.persistentToL2Cache
-power_model=Null
-recycle_latency=10
-responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache
-responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache
-ruby_system=system.ruby
-system=system
-transitions_per_cycle=32
-version=0
-
-[system.ruby.l2_cntrl0.GlobalRequestFromL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[3]
-
-[system.ruby.l2_cntrl0.GlobalRequestToL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[3]
-
-[system.ruby.l2_cntrl0.L1RequestFromL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[4]
-
-[system.ruby.l2_cntrl0.L1RequestToL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[4]
-
-[system.ruby.l2_cntrl0.L2cache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l2_cntrl0.L2cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=512
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l2_cntrl0.L2cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=512
-
-[system.ruby.l2_cntrl0.persistentToL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[6]
-
-[system.ruby.l2_cntrl0.responseFromL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[5]
-
-[system.ruby.l2_cntrl0.responseToL2Cache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[5]
-
-[system.ruby.memctrl_clk_domain]
-type=DerivedClockDomain
-clk_divider=3
-clk_domain=system.ruby.clk_domain
-eventq_index=0
-
-[system.ruby.network]
-type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_link_buffers48 int_link_buffers49 int_link_buffers50 int_link_buffers51 int_link_buffers52 int_link_buffers53 int_link_buffers54 int_link_buffers55 int_link_buffers56 int_link_buffers57 int_link_buffers58 int_link_buffers59 int_link_buffers60 int_link_buffers61 int_link_buffers62 int_link_buffers63 int_link_buffers64 int_link_buffers65 int_link_buffers66 int_link_buffers67 int_link_buffers68 int_link_buffers69 int_link_buffers70 int_link_buffers71 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3
-adaptive_routing=false
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-control_msg_size=8
-default_p_state=UNDEFINED
-endpoint_bandwidth=1000
-eventq_index=0
-ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 system.ruby.network.int_link_buffers48 system.ruby.network.int_link_buffers49 system.ruby.network.int_link_buffers50 system.ruby.network.int_link_buffers51 system.ruby.network.int_link_buffers52 system.ruby.network.int_link_buffers53 system.ruby.network.int_link_buffers54 system.ruby.network.int_link_buffers55 system.ruby.network.int_link_buffers56 system.ruby.network.int_link_buffers57 system.ruby.network.int_link_buffers58 system.ruby.network.int_link_buffers59 system.ruby.network.int_link_buffers60 system.ruby.network.int_link_buffers61 system.ruby.network.int_link_buffers62 system.ruby.network.int_link_buffers63 system.ruby.network.int_link_buffers64 system.ruby.network.int_link_buffers65 system.ruby.network.int_link_buffers66 system.ruby.network.int_link_buffers67 system.ruby.network.int_link_buffers68 system.ruby.network.int_link_buffers69 system.ruby.network.int_link_buffers70 system.ruby.network.int_link_buffers71
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5
-netifs=
-number_of_virtual_networks=6
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3
-ruby_system=system.ruby
-topology=Crossbar
-master=system.ruby.l1_cntrl0.requestToL1Cache.slave system.ruby.l1_cntrl0.responseToL1Cache.slave system.ruby.l1_cntrl0.persistentToL1Cache.slave system.ruby.l2_cntrl0.GlobalRequestToL2Cache.slave system.ruby.l2_cntrl0.L1RequestToL2Cache.slave system.ruby.l2_cntrl0.responseToL2Cache.slave system.ruby.l2_cntrl0.persistentToL2Cache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.responseToDir.slave system.ruby.dir_cntrl0.persistentToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave
-slave=system.ruby.l1_cntrl0.requestFromL1Cache.master system.ruby.l1_cntrl0.responseFromL1Cache.master system.ruby.l1_cntrl0.persistentFromL1Cache.master system.ruby.l2_cntrl0.GlobalRequestFromL2Cache.master system.ruby.l2_cntrl0.L1RequestFromL2Cache.master system.ruby.l2_cntrl0.responseFromL2Cache.master system.ruby.dir_cntrl0.requestFromDir.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.persistentFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master
-
-[system.ruby.network.ext_links0]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.l1_cntrl0
-int_node=system.ruby.network.routers0
-latency=1
-link_id=0
-weight=1
-
-[system.ruby.network.ext_links1]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.l2_cntrl0
-int_node=system.ruby.network.routers1
-latency=1
-link_id=1
-weight=1
-
-[system.ruby.network.ext_links2]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.dir_cntrl0
-int_node=system.ruby.network.routers2
-latency=1
-link_id=2
-weight=1
-
-[system.ruby.network.int_link_buffers00]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers01]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers02]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers03]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers04]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers05]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers06]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers07]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers08]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers09]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers10]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers11]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers12]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers13]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
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-children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23
-clk_domain=system.ruby.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 system.ruby.network.routers2.port_buffers20 system.ruby.network.routers2.port_buffers21 system.ruby.network.routers2.port_buffers22 system.ruby.network.routers2.port_buffers23
-power_model=Null
-router_id=2
-virt_nets=6
-
-[system.ruby.network.routers2.port_buffers00]
-type=MessageBuffer
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-
-[system.ruby.network.routers2.port_buffers01]
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-
-[system.ruby.network.routers2.port_buffers02]
-type=MessageBuffer
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-
-[system.ruby.network.routers2.port_buffers03]
-type=MessageBuffer
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-
-[system.ruby.network.routers2.port_buffers04]
-type=MessageBuffer
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-
-[system.ruby.network.routers2.port_buffers05]
-type=MessageBuffer
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-
-[system.ruby.network.routers2.port_buffers06]
-type=MessageBuffer
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-
-[system.ruby.network.routers2.port_buffers07]
-type=MessageBuffer
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-
-[system.ruby.network.routers2.port_buffers08]
-type=MessageBuffer
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-
-[system.ruby.network.routers2.port_buffers09]
-type=MessageBuffer
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-
-[system.ruby.network.routers2.port_buffers10]
-type=MessageBuffer
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-
-[system.ruby.network.routers2.port_buffers11]
-type=MessageBuffer
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-
-[system.ruby.network.routers2.port_buffers12]
-type=MessageBuffer
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-ordered=true
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-
-[system.ruby.network.routers2.port_buffers13]
-type=MessageBuffer
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-
-[system.ruby.network.routers2.port_buffers14]
-type=MessageBuffer
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-
-[system.ruby.network.routers2.port_buffers15]
-type=MessageBuffer
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-[system.ruby.network.routers2.port_buffers16]
-type=MessageBuffer
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-
-[system.ruby.network.routers2.port_buffers17]
-type=MessageBuffer
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-
-[system.ruby.network.routers2.port_buffers18]
-type=MessageBuffer
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-
-[system.ruby.network.routers2.port_buffers19]
-type=MessageBuffer
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-
-[system.ruby.network.routers2.port_buffers20]
-type=MessageBuffer
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-[system.ruby.network.routers2.port_buffers21]
-type=MessageBuffer
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-[system.ruby.network.routers2.port_buffers22]
-type=MessageBuffer
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-ordered=true
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-
-[system.ruby.network.routers2.port_buffers23]
-type=MessageBuffer
-buffer_size=0
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-
-[system.ruby.network.routers3]
-type=Switch
-children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 port_buffers24 port_buffers25 port_buffers26 port_buffers27 port_buffers28 port_buffers29 port_buffers30 port_buffers31 port_buffers32 port_buffers33 port_buffers34 port_buffers35
-clk_domain=system.ruby.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 system.ruby.network.routers3.port_buffers18 system.ruby.network.routers3.port_buffers19 system.ruby.network.routers3.port_buffers20 system.ruby.network.routers3.port_buffers21 system.ruby.network.routers3.port_buffers22 system.ruby.network.routers3.port_buffers23 system.ruby.network.routers3.port_buffers24 system.ruby.network.routers3.port_buffers25 system.ruby.network.routers3.port_buffers26 system.ruby.network.routers3.port_buffers27 system.ruby.network.routers3.port_buffers28 system.ruby.network.routers3.port_buffers29 system.ruby.network.routers3.port_buffers30 system.ruby.network.routers3.port_buffers31 system.ruby.network.routers3.port_buffers32 system.ruby.network.routers3.port_buffers33 system.ruby.network.routers3.port_buffers34 system.ruby.network.routers3.port_buffers35
-power_model=Null
-router_id=3
-virt_nets=6
-
-[system.ruby.network.routers3.port_buffers00]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers3.port_buffers01]
-type=MessageBuffer
-buffer_size=0
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-ordered=true
-randomization=false
-
-[system.ruby.network.routers3.port_buffers02]
-type=MessageBuffer
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-ordered=true
-randomization=false
-
-[system.ruby.network.routers3.port_buffers03]
-type=MessageBuffer
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-
-[system.ruby.network.routers3.port_buffers04]
-type=MessageBuffer
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-
-[system.ruby.network.routers3.port_buffers05]
-type=MessageBuffer
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-
-[system.ruby.network.routers3.port_buffers06]
-type=MessageBuffer
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-
-[system.ruby.network.routers3.port_buffers07]
-type=MessageBuffer
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-
-[system.ruby.network.routers3.port_buffers08]
-type=MessageBuffer
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-
-[system.ruby.network.routers3.port_buffers09]
-type=MessageBuffer
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-
-[system.ruby.network.routers3.port_buffers10]
-type=MessageBuffer
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-
-[system.ruby.network.routers3.port_buffers11]
-type=MessageBuffer
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-
-[system.ruby.network.routers3.port_buffers12]
-type=MessageBuffer
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-
-[system.ruby.network.routers3.port_buffers13]
-type=MessageBuffer
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-
-[system.ruby.network.routers3.port_buffers14]
-type=MessageBuffer
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-
-[system.ruby.network.routers3.port_buffers15]
-type=MessageBuffer
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-
-[system.ruby.network.routers3.port_buffers16]
-type=MessageBuffer
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-
-[system.ruby.network.routers3.port_buffers17]
-type=MessageBuffer
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-
-[system.ruby.network.routers3.port_buffers18]
-type=MessageBuffer
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-
-[system.ruby.network.routers3.port_buffers19]
-type=MessageBuffer
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-
-[system.ruby.network.routers3.port_buffers20]
-type=MessageBuffer
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-
-[system.ruby.network.routers3.port_buffers21]
-type=MessageBuffer
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-
-[system.ruby.network.routers3.port_buffers22]
-type=MessageBuffer
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-
-[system.ruby.network.routers3.port_buffers23]
-type=MessageBuffer
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-
-[system.ruby.network.routers3.port_buffers24]
-type=MessageBuffer
-buffer_size=0
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-randomization=false
-
-[system.ruby.network.routers3.port_buffers25]
-type=MessageBuffer
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-randomization=false
-
-[system.ruby.network.routers3.port_buffers26]
-type=MessageBuffer
-buffer_size=0
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-randomization=false
-
-[system.ruby.network.routers3.port_buffers27]
-type=MessageBuffer
-buffer_size=0
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-ordered=true
-randomization=false
-
-[system.ruby.network.routers3.port_buffers28]
-type=MessageBuffer
-buffer_size=0
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-ordered=true
-randomization=false
-
-[system.ruby.network.routers3.port_buffers29]
-type=MessageBuffer
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-ordered=true
-randomization=false
-
-[system.ruby.network.routers3.port_buffers30]
-type=MessageBuffer
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-ordered=true
-randomization=false
-
-[system.ruby.network.routers3.port_buffers31]
-type=MessageBuffer
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-ordered=true
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-
-[system.ruby.network.routers3.port_buffers32]
-type=MessageBuffer
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-ordered=true
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-
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-type=MessageBuffer
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-
-[system.ruby.network.routers3.port_buffers34]
-type=MessageBuffer
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-
-[system.ruby.network.routers3.port_buffers35]
-type=MessageBuffer
-buffer_size=0
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-ordered=true
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-
-[system.sys_port_proxy]
-type=RubyPortProxy
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_cpu_sequencer=true
-no_retry_on_stall=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=0
-slave=system.system_port
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
+++ /dev/null
-Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
-Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 13 2016 20:33:48
-gem5 started Oct 13 2016 20:34:17
-gem5 executing on e108600-lin, pid 27528
-command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
-
-Global frequency set at 1000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 53801 because Ruby Tester completed
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000054 # Number of seconds simulated
-sim_ticks 53801 # Number of ticks simulated
-final_tick 53801 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 1148907 # Simulator tick rate (ticks/s)
-host_mem_usage 394184 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 52672 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 52672 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 47552 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 47552 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 823 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 823 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 743 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 743 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 979015260 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 979015260 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 883849743 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 883849743 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 1862865003 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 1862865003 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 824 # Number of read requests accepted
-system.mem_ctrls.writeReqs 743 # Number of write requests accepted
-system.mem_ctrls.readBursts 824 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 743 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 43776 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 8960 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 40320 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 52736 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 47552 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 140 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 90 # Number of DRAM write bursts merged with an existing one
-system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 217 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 193 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 224 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 50 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 196 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 186 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 201 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 47 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
-system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
-system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 53772 # Total gap between requests
-system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 824 # Read request sizes (log2)
-system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 743 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 527 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 156 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
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-system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 4 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 4 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 20 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 43 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 44 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 41 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 41 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 41 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 41 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 45 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 39 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 39 # What write queue length does an incoming req see
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-system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 90 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 916.622222 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 830.573922 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 254.887972 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 1 1.11% 1.11% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 5 5.56% 6.67% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 1 1.11% 7.78% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 2 2.22% 10.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 3 3.33% 13.33% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 4 4.44% 17.78% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 4 4.44% 22.22% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 70 77.78% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 90 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 39 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 17.282051 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 16.989006 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 3.886202 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::12-13 1 2.56% 2.56% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15 8 20.51% 23.08% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17 18 46.15% 69.23% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19 8 20.51% 89.74% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-21 2 5.13% 94.87% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::22-23 1 2.56% 97.44% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::38-39 1 2.56% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 39 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 39 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.153846 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.145622 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 0.539906 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 36 92.31% 92.31% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 3 7.69% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 39 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 11889 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 24885 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 3420 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 17.38 # Average queueing delay per DRAM burst
-system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 36.38 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 813.67 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 749.43 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 980.20 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 883.85 # Average system write bandwidth in MiByte/s
-system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 12.21 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 6.36 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 5.85 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 1.38 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 25.30 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 599 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 622 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 87.57 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 95.25 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 34.32 # Average gap between requests
-system.mem_ctrls.pageHitRate 91.32 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 664020 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 347760 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 7814016 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 5261760 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 10048872 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 77568 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.actPowerDownEnergy 14391360 # Energy for active power-down per rank (pJ)
-system.mem_ctrls_0.prePowerDownEnergy 768 # Energy for precharge power-down per rank (pJ)
-system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
-system.mem_ctrls_0.totalEnergy 42293964 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 786.118548 # Core power per rank (mW)
-system.mem_ctrls_0.totalIdleTime 31562 # Total Idle time Per DRAM Rank
-system.mem_ctrls_0.memoryStateTime::IDLE 34 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 2 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 20645 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 31560 # Time in different power states
-system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 224352 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 3002880 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ)
-system.mem_ctrls_1.prePowerDownEnergy 2889984 # Energy for precharge power-down per rank (pJ)
-system.mem_ctrls_1.selfRefreshEnergy 9111120 # Energy for self refresh per rank (pJ)
-system.mem_ctrls_1.totalEnergy 16457616 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 305.897957 # Core power per rank (mW)
-system.mem_ctrls_1.totalIdleTime 7526 # Total Idle time Per DRAM Rank
-system.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 526 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::SREF 37963 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 7526 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states
-system.ruby.clk_domain.clock 1 # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states
-system.ruby.outstanding_req_hist_seqr::bucket_size 2
-system.ruby.outstanding_req_hist_seqr::max_bucket 19
-system.ruby.outstanding_req_hist_seqr::samples 973
-system.ruby.outstanding_req_hist_seqr::mean 15.744090
-system.ruby.outstanding_req_hist_seqr::gmean 15.636746
-system.ruby.outstanding_req_hist_seqr::stdev 1.206668
-system.ruby.outstanding_req_hist_seqr | 1 0.10% 0.10% | 2 0.21% 0.31% | 2 0.21% 0.51% | 2 0.21% 0.72% | 4 0.41% 1.13% | 2 0.21% 1.34% | 3 0.31% 1.64% | 112 11.51% 13.16% | 845 86.84% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist_seqr::total 973
-system.ruby.latency_hist_seqr::bucket_size 256
-system.ruby.latency_hist_seqr::max_bucket 2559
-system.ruby.latency_hist_seqr::samples 958
-system.ruby.latency_hist_seqr::mean 879.328810
-system.ruby.latency_hist_seqr::gmean 422.320646
-system.ruby.latency_hist_seqr::stdev 422.809847
-system.ruby.latency_hist_seqr | 182 19.00% 19.00% | 6 0.63% 19.62% | 4 0.42% 20.04% | 214 22.34% 42.38% | 516 53.86% 96.24% | 36 3.76% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist_seqr::total 958
-system.ruby.hit_latency_hist_seqr::bucket_size 256
-system.ruby.hit_latency_hist_seqr::max_bucket 2559
-system.ruby.hit_latency_hist_seqr::samples 136
-system.ruby.hit_latency_hist_seqr::mean 190.117647
-system.ruby.hit_latency_hist_seqr::gmean 5.669159
-system.ruby.hit_latency_hist_seqr::stdev 399.173351
-system.ruby.hit_latency_hist_seqr | 112 82.35% 82.35% | 0 0.00% 82.35% | 0 0.00% 82.35% | 10 7.35% 89.71% | 13 9.56% 99.26% | 1 0.74% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist_seqr::total 136
-system.ruby.miss_latency_hist_seqr::bucket_size 256
-system.ruby.miss_latency_hist_seqr::max_bucket 2559
-system.ruby.miss_latency_hist_seqr::samples 822
-system.ruby.miss_latency_hist_seqr::mean 993.358881
-system.ruby.miss_latency_hist_seqr::gmean 861.758158
-system.ruby.miss_latency_hist_seqr::stdev 300.791358
-system.ruby.miss_latency_hist_seqr | 70 8.52% 8.52% | 6 0.73% 9.25% | 4 0.49% 9.73% | 204 24.82% 34.55% | 503 61.19% 95.74% | 35 4.26% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.miss_latency_hist_seqr::total 822
-system.ruby.Directory.incomplete_times_seqr 822
-system.ruby.dir_cntrl0.persistentToDir.avg_buf_msgs 0.000706 # Average number of messages in buffer
-system.ruby.dir_cntrl0.persistentToDir.avg_stall_time 7.203896 # Average number of cycles messages are stalled in this MB
-system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.015334 # Average number of messages in buffer
-system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.130237 # Average number of cycles messages are stalled in this MB
-system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.015297 # Average number of messages in buffer
-system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.998569 # Average number of cycles messages are stalled in this MB
-system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029107 # Average number of messages in buffer
-system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.998587 # Average number of cycles messages are stalled in this MB
-system.ruby.dir_cntrl0.responseToDir.avg_buf_msgs 0.015204 # Average number of messages in buffer
-system.ruby.dir_cntrl0.responseToDir.avg_stall_time 10.935597 # Average number of cycles messages are stalled in this MB
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 92 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 820 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 912 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 48 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 48 # Number of cache demand accesses
-system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 14.571763 # Average number of messages in buffer
-system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 24.837199 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.mandatoryQueue.num_msg_stalls 22280 # Number of times messages were stalled
-system.ruby.l1_cntrl0.persistentFromL1Cache.avg_buf_msgs 0.001413 # Average number of messages in buffer
-system.ruby.l1_cntrl0.persistentFromL1Cache.avg_stall_time 1.410728 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.persistentToL1Cache.avg_buf_msgs 0.000706 # Average number of messages in buffer
-system.ruby.l1_cntrl0.persistentToL1Cache.avg_stall_time 2.822237 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.requestFromL1Cache.avg_buf_msgs 0.064533 # Average number of messages in buffer
-system.ruby.l1_cntrl0.requestFromL1Cache.avg_stall_time 1.999851 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.responseFromL1Cache.avg_buf_msgs 0.032285 # Average number of messages in buffer
-system.ruby.l1_cntrl0.responseFromL1Cache.avg_stall_time 1.976135 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.responseToL1Cache.avg_buf_msgs 0.016356 # Average number of messages in buffer
-system.ruby.l1_cntrl0.responseToL1Cache.avg_stall_time 7.201145 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 4 # Number of times a store aliased with a pending load
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 91 # Number of times a store aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 7 # Number of times a load aliased with a pending store
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states
-system.ruby.l2_cntrl0.GlobalRequestFromL2Cache.avg_buf_msgs 0.076670 # Average number of messages in buffer
-system.ruby.l2_cntrl0.GlobalRequestFromL2Cache.avg_stall_time 4.998606 # Average number of cycles messages are stalled in this MB
-system.ruby.l2_cntrl0.L1RequestToL2Cache.avg_buf_msgs 0.016133 # Average number of messages in buffer
-system.ruby.l2_cntrl0.L1RequestToL2Cache.avg_stall_time 12.070443 # Average number of cycles messages are stalled in this MB
-system.ruby.l2_cntrl0.L2cache.demand_hits 43 # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses 825 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 868 # Number of cache demand accesses
-system.ruby.l2_cntrl0.persistentToL2Cache.avg_buf_msgs 0.000706 # Average number of messages in buffer
-system.ruby.l2_cntrl0.persistentToL2Cache.avg_stall_time 7.203896 # Average number of cycles messages are stalled in this MB
-system.ruby.l2_cntrl0.responseFromL2Cache.avg_buf_msgs 0.079142 # Average number of messages in buffer
-system.ruby.l2_cntrl0.responseFromL2Cache.avg_stall_time 4.970763 # Average number of cycles messages are stalled in this MB
-system.ruby.l2_cntrl0.responseToL2Cache.avg_buf_msgs 0.016022 # Average number of messages in buffer
-system.ruby.l2_cntrl0.responseToL2Cache.avg_stall_time 8.050407 # Average number of cycles messages are stalled in this MB
-system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states
-system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.000725 # Average number of messages in buffer
-system.ruby.network.routers0.port_buffers03.avg_stall_time 2.116966 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.016356 # Average number of messages in buffer
-system.ruby.network.routers0.port_buffers04.avg_stall_time 6.202799 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers0.port_buffers06.avg_buf_msgs 0.081800 # Average number of messages in buffer
-system.ruby.network.routers0.port_buffers06.avg_stall_time 7.012881 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers0.port_buffers08.avg_buf_msgs 0.001673 # Average number of messages in buffer
-system.ruby.network.routers0.port_buffers08.avg_stall_time 3.678283 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers0.port_buffers09.avg_buf_msgs 0.016932 # Average number of messages in buffer
-system.ruby.network.routers0.port_buffers09.avg_stall_time 3.044943 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized 7.774948
-system.ruby.network.routers0.msg_count.Request_Control::1 868
-system.ruby.network.routers0.msg_count.Response_Data::4 823
-system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4 44
-system.ruby.network.routers0.msg_count.Writeback_Data::4 888
-system.ruby.network.routers0.msg_count.Persistent_Control::3 76
-system.ruby.network.routers0.msg_bytes.Request_Control::1 6944
-system.ruby.network.routers0.msg_bytes.Response_Data::4 59256
-system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 3168
-system.ruby.network.routers0.msg_bytes.Writeback_Data::4 63936
-system.ruby.network.routers0.msg_bytes.Persistent_Control::3 608
-system.ruby.network.routers1.port_buffers01.avg_buf_msgs 0.016133 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers01.avg_stall_time 11.070834 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.port_buffers03.avg_buf_msgs 0.000706 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers03.avg_stall_time 6.498848 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.port_buffers04.avg_buf_msgs 0.016022 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers04.avg_stall_time 7.053158 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.016747 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers07.avg_stall_time 6.087710 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.port_buffers09.avg_buf_msgs 0.016672 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers09.avg_stall_time 6.054478 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized 7.735451
-system.ruby.network.routers1.msg_count.Request_Control::1 868
-system.ruby.network.routers1.msg_count.Request_Control::2 825
-system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4 44
-system.ruby.network.routers1.msg_count.Writeback_Data::4 1605
-system.ruby.network.routers1.msg_count.Writeback_Control::4 75
-system.ruby.network.routers1.msg_count.Persistent_Control::3 38
-system.ruby.network.routers1.msg_bytes.Request_Control::1 6944
-system.ruby.network.routers1.msg_bytes.Request_Control::2 6600
-system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4 3168
-system.ruby.network.routers1.msg_bytes.Writeback_Data::4 115560
-system.ruby.network.routers1.msg_bytes.Writeback_Control::4 600
-system.ruby.network.routers1.msg_bytes.Persistent_Control::3 304
-system.ruby.network.routers2.port_buffers02.avg_buf_msgs 0.015334 # Average number of messages in buffer
-system.ruby.network.routers2.port_buffers02.avg_stall_time 10.130813 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.000706 # Average number of messages in buffer
-system.ruby.network.routers2.port_buffers03.avg_stall_time 6.498848 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.015204 # Average number of messages in buffer
-system.ruby.network.routers2.port_buffers04.avg_stall_time 9.940969 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.port_buffers09.avg_buf_msgs 0.015576 # Average number of messages in buffer
-system.ruby.network.routers2.port_buffers09.avg_stall_time 2.034924 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized 6.985000
-system.ruby.network.routers2.msg_count.Request_Control::2 825
-system.ruby.network.routers2.msg_count.Response_Data::4 823
-system.ruby.network.routers2.msg_count.Writeback_Data::4 743
-system.ruby.network.routers2.msg_count.Writeback_Control::4 75
-system.ruby.network.routers2.msg_count.Persistent_Control::3 38
-system.ruby.network.routers2.msg_bytes.Request_Control::2 6600
-system.ruby.network.routers2.msg_bytes.Response_Data::4 59256
-system.ruby.network.routers2.msg_bytes.Writeback_Data::4 53496
-system.ruby.network.routers2.msg_bytes.Writeback_Control::4 600
-system.ruby.network.routers2.msg_bytes.Persistent_Control::3 304
-system.ruby.network.int_link_buffers01.avg_buf_msgs 0.016133 # Average number of messages in buffer
-system.ruby.network.int_link_buffers01.avg_stall_time 8.012639 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers03.avg_buf_msgs 0.000706 # Average number of messages in buffer
-system.ruby.network.int_link_buffers03.avg_stall_time 4.383480 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers04.avg_buf_msgs 0.016263 # Average number of messages in buffer
-system.ruby.network.int_link_buffers04.avg_stall_time 4.042340 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers08.avg_buf_msgs 0.015334 # Average number of messages in buffer
-system.ruby.network.int_link_buffers08.avg_stall_time 7.087283 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers10.avg_buf_msgs 0.016022 # Average number of messages in buffer
-system.ruby.network.int_link_buffers10.avg_stall_time 7.049255 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers16.avg_buf_msgs 0.015297 # Average number of messages in buffer
-system.ruby.network.int_link_buffers16.avg_stall_time 3.033419 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers22.avg_buf_msgs 0.016356 # Average number of messages in buffer
-system.ruby.network.int_link_buffers22.avg_stall_time 5.204416 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers25.avg_buf_msgs 0.016133 # Average number of messages in buffer
-system.ruby.network.int_link_buffers25.avg_stall_time 10.071187 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers27.avg_buf_msgs 0.000706 # Average number of messages in buffer
-system.ruby.network.int_link_buffers27.avg_stall_time 5.793762 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers28.avg_buf_msgs 0.016022 # Average number of messages in buffer
-system.ruby.network.int_link_buffers28.avg_stall_time 6.055872 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers32.avg_buf_msgs 0.015334 # Average number of messages in buffer
-system.ruby.network.int_link_buffers32.avg_stall_time 9.131352 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers33.avg_buf_msgs 0.000706 # Average number of messages in buffer
-system.ruby.network.int_link_buffers33.avg_stall_time 5.793762 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers34.avg_buf_msgs 0.015204 # Average number of messages in buffer
-system.ruby.network.int_link_buffers34.avg_stall_time 8.946303 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers3.port_buffers04.avg_buf_msgs 0.016449 # Average number of messages in buffer
-system.ruby.network.routers3.port_buffers04.avg_stall_time 4.205996 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers3.port_buffers07.avg_buf_msgs 0.017063 # Average number of messages in buffer
-system.ruby.network.routers3.port_buffers07.avg_stall_time 9.071503 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers3.port_buffers09.avg_buf_msgs 0.000706 # Average number of messages in buffer
-system.ruby.network.routers3.port_buffers09.avg_stall_time 5.088640 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers3.port_buffers10.avg_buf_msgs 0.016022 # Average number of messages in buffer
-system.ruby.network.routers3.port_buffers10.avg_stall_time 5.058548 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers3.port_buffers14.avg_buf_msgs 0.015947 # Average number of messages in buffer
-system.ruby.network.routers3.port_buffers14.avg_stall_time 8.131854 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers3.port_buffers15.avg_buf_msgs 0.000706 # Average number of messages in buffer
-system.ruby.network.routers3.port_buffers15.avg_stall_time 5.088640 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers3.port_buffers16.avg_buf_msgs 0.015464 # Average number of messages in buffer
-system.ruby.network.routers3.port_buffers16.avg_stall_time 7.951600 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers3.percent_links_utilized 7.498621
-system.ruby.network.routers3.msg_count.Request_Control::1 868
-system.ruby.network.routers3.msg_count.Request_Control::2 825
-system.ruby.network.routers3.msg_count.Response_Data::4 823
-system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4 44
-system.ruby.network.routers3.msg_count.Writeback_Data::4 1618
-system.ruby.network.routers3.msg_count.Writeback_Control::4 75
-system.ruby.network.routers3.msg_count.Persistent_Control::3 76
-system.ruby.network.routers3.msg_bytes.Request_Control::1 6944
-system.ruby.network.routers3.msg_bytes.Request_Control::2 6600
-system.ruby.network.routers3.msg_bytes.Response_Data::4 59256
-system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4 3168
-system.ruby.network.routers3.msg_bytes.Writeback_Data::4 116496
-system.ruby.network.routers3.msg_bytes.Writeback_Control::4 600
-system.ruby.network.routers3.msg_bytes.Persistent_Control::3 608
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states
-system.ruby.network.msg_count.Request_Control 5079
-system.ruby.network.msg_count.Response_Data 2469
-system.ruby.network.msg_count.ResponseL2hit_Data 132
-system.ruby.network.msg_count.Writeback_Data 4854
-system.ruby.network.msg_count.Writeback_Control 225
-system.ruby.network.msg_count.Persistent_Control 228
-system.ruby.network.msg_byte.Request_Control 40632
-system.ruby.network.msg_byte.Response_Data 177768
-system.ruby.network.msg_byte.ResponseL2hit_Data 9504
-system.ruby.network.msg_byte.Writeback_Data 349488
-system.ruby.network.msg_byte.Writeback_Control 1800
-system.ruby.network.msg_byte.Persistent_Control 1824
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization 7.389268
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 823
-system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 44
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Data::4 13
-system.ruby.network.routers0.throttle0.msg_count.Persistent_Control::3 38
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 59256
-system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4 3168
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Data::4 936
-system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3 304
-system.ruby.network.routers0.throttle1.link_utilization 8.160629
-system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 868
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 875
-system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 38
-system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 6944
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 63000
-system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 304
-system.ruby.network.routers1.throttle0.link_utilization 8.051895
-system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 868
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 862
-system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 38
-system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 6944
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 62064
-system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 304
-system.ruby.network.routers1.throttle1.link_utilization 7.419007
-system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 825
-system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4 44
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::4 743
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::4 75
-system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 6600
-system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4 3168
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4 53496
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 600
-system.ruby.network.routers2.throttle0.link_utilization 7.086300
-system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 825
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4 743
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 75
-system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3 38
-system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 6600
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4 53496
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 600
-system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 304
-system.ruby.network.routers2.throttle1.link_utilization 6.883701
-system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 823
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 59256
-system.ruby.network.routers3.throttle0.link_utilization 7.357670
-system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 823
-system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4 44
-system.ruby.network.routers3.throttle0.msg_count.Writeback_Data::4 13
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 59256
-system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4 3168
-system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Data::4 936
-system.ruby.network.routers3.throttle1.link_utilization 8.051895
-system.ruby.network.routers3.throttle1.msg_count.Request_Control::1 868
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4 862
-system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3 38
-system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1 6944
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4 62064
-system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3 304
-system.ruby.network.routers3.throttle2.link_utilization 7.086300
-system.ruby.network.routers3.throttle2.msg_count.Request_Control::2 825
-system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4 743
-system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4 75
-system.ruby.network.routers3.throttle2.msg_count.Persistent_Control::3 38
-system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 6600
-system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4 53496
-system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 600
-system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 304
-system.ruby.LD.latency_hist_seqr::bucket_size 256
-system.ruby.LD.latency_hist_seqr::max_bucket 2559
-system.ruby.LD.latency_hist_seqr::samples 53
-system.ruby.LD.latency_hist_seqr::mean 911.113208
-system.ruby.LD.latency_hist_seqr::gmean 398.266031
-system.ruby.LD.latency_hist_seqr::stdev 447.197842
-system.ruby.LD.latency_hist_seqr | 10 18.87% 18.87% | 0 0.00% 18.87% | 0 0.00% 18.87% | 10 18.87% 37.74% | 28 52.83% 90.57% | 5 9.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.latency_hist_seqr::total 53
-system.ruby.LD.hit_latency_hist_seqr::bucket_size 256
-system.ruby.LD.hit_latency_hist_seqr::max_bucket 2559
-system.ruby.LD.hit_latency_hist_seqr::samples 9
-system.ruby.LD.hit_latency_hist_seqr::mean 152
-system.ruby.LD.hit_latency_hist_seqr::gmean 4.500121
-system.ruby.LD.hit_latency_hist_seqr::stdev 435.863798
-system.ruby.LD.hit_latency_hist_seqr | 8 88.89% 88.89% | 0 0.00% 88.89% | 0 0.00% 88.89% | 0 0.00% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.hit_latency_hist_seqr::total 9
-system.ruby.LD.miss_latency_hist_seqr::bucket_size 256
-system.ruby.LD.miss_latency_hist_seqr::max_bucket 2559
-system.ruby.LD.miss_latency_hist_seqr::samples 44
-system.ruby.LD.miss_latency_hist_seqr::mean 1066.386364
-system.ruby.LD.miss_latency_hist_seqr::gmean 996.352114
-system.ruby.LD.miss_latency_hist_seqr::stdev 247.421326
-system.ruby.LD.miss_latency_hist_seqr | 2 4.55% 4.55% | 0 0.00% 4.55% | 0 0.00% 4.55% | 10 22.73% 27.27% | 28 63.64% 90.91% | 4 9.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.miss_latency_hist_seqr::total 44
-system.ruby.ST.latency_hist_seqr::bucket_size 256
-system.ruby.ST.latency_hist_seqr::max_bucket 2559
-system.ruby.ST.latency_hist_seqr::samples 858
-system.ruby.ST.latency_hist_seqr::mean 921.592075
-system.ruby.ST.latency_hist_seqr::gmean 471.652464
-system.ruby.ST.latency_hist_seqr::stdev 386.984382
-system.ruby.ST.latency_hist_seqr | 126 14.69% 14.69% | 5 0.58% 15.27% | 4 0.47% 15.73% | 204 23.78% 39.51% | 488 56.88% 96.39% | 31 3.61% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.latency_hist_seqr::total 858
-system.ruby.ST.hit_latency_hist_seqr::bucket_size 128
-system.ruby.ST.hit_latency_hist_seqr::max_bucket 1279
-system.ruby.ST.hit_latency_hist_seqr::samples 120
-system.ruby.ST.hit_latency_hist_seqr::mean 202.641667
-system.ruby.ST.hit_latency_hist_seqr::gmean 5.297334
-system.ruby.ST.hit_latency_hist_seqr::stdev 407.564189
-system.ruby.ST.hit_latency_hist_seqr | 97 80.83% 80.83% | 0 0.00% 80.83% | 0 0.00% 80.83% | 0 0.00% 80.83% | 0 0.00% 80.83% | 0 0.00% 80.83% | 0 0.00% 80.83% | 10 8.33% 89.17% | 12 10.00% 99.17% | 1 0.83% 100.00%
-system.ruby.ST.hit_latency_hist_seqr::total 120
-system.ruby.ST.miss_latency_hist_seqr::bucket_size 256
-system.ruby.ST.miss_latency_hist_seqr::max_bucket 2559
-system.ruby.ST.miss_latency_hist_seqr::samples 738
-system.ruby.ST.miss_latency_hist_seqr::mean 1038.494580
-system.ruby.ST.miss_latency_hist_seqr::gmean 978.643470
-system.ruby.ST.miss_latency_hist_seqr::stdev 222.427518
-system.ruby.ST.miss_latency_hist_seqr | 29 3.93% 3.93% | 5 0.68% 4.61% | 4 0.54% 5.15% | 194 26.29% 31.44% | 475 64.36% 95.80% | 31 4.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.miss_latency_hist_seqr::total 738
-system.ruby.IFETCH.latency_hist_seqr::bucket_size 32
-system.ruby.IFETCH.latency_hist_seqr::max_bucket 319
-system.ruby.IFETCH.latency_hist_seqr::samples 47
-system.ruby.IFETCH.latency_hist_seqr::mean 71.957447
-system.ruby.IFETCH.latency_hist_seqr::gmean 60.044920
-system.ruby.IFETCH.latency_hist_seqr::stdev 50.481575
-system.ruby.IFETCH.latency_hist_seqr | 7 14.89% 14.89% | 14 29.79% 44.68% | 21 44.68% 89.36% | 0 0.00% 89.36% | 1 2.13% 91.49% | 2 4.26% 95.74% | 1 2.13% 97.87% | 0 0.00% 97.87% | 1 2.13% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.latency_hist_seqr::total 47
-system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 4
-system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 39
-system.ruby.IFETCH.hit_latency_hist_seqr::samples 7
-system.ruby.IFETCH.hit_latency_hist_seqr::mean 24.428571
-system.ruby.IFETCH.hit_latency_hist_seqr::gmean 24.407244
-system.ruby.IFETCH.hit_latency_hist_seqr::stdev 1.133893
-system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.hit_latency_hist_seqr::total 7
-system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32
-system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319
-system.ruby.IFETCH.miss_latency_hist_seqr::samples 40
-system.ruby.IFETCH.miss_latency_hist_seqr::mean 80.275000
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean 70.290048
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev 50.290942
-system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 14 35.00% 35.00% | 21 52.50% 87.50% | 0 0.00% 87.50% | 1 2.50% 90.00% | 2 5.00% 95.00% | 1 2.50% 97.50% | 0 0.00% 97.50% | 1 2.50% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.miss_latency_hist_seqr::total 40
-system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1
-system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9
-system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 92
-system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean 1
-system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean 1
-system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 92 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 92
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 256
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 2559
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 44
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 585.545455
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 213.332787
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 513.546966
-system.ruby.L2Cache.hit_mach_latency_hist_seqr | 20 45.45% 45.45% | 0 0.00% 45.45% | 0 0.00% 45.45% | 10 22.73% 68.18% | 13 29.55% 97.73% | 1 2.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 44
-system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 256
-system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 2559
-system.ruby.Directory.miss_mach_latency_hist_seqr::samples 822
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean 993.358881
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 861.758158
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 300.791358
-system.ruby.Directory.miss_mach_latency_hist_seqr | 70 8.52% 8.52% | 6 0.73% 9.25% | 4 0.49% 9.73% | 204 24.82% 34.55% | 503 61.19% 95.74% | 35 4.26% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory.miss_mach_latency_hist_seqr::total 822
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 6
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 6 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 6
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 256
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 2559
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 3
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 454
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 91.132360
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev 744.781847
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 2 66.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 3
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 256
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 2559
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 44
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 1066.386364
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 996.352114
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 247.421326
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 2 4.55% 4.55% | 0 0.00% 4.55% | 0 0.00% 4.55% | 10 22.73% 27.27% | 28 63.64% 90.91% | 4 9.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 44
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 86
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::mean 1
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 86 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 86
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 128
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 1279
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 34
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 712.676471
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 359.332613
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 474.361052
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 11 32.35% 32.35% | 0 0.00% 32.35% | 0 0.00% 32.35% | 0 0.00% 32.35% | 0 0.00% 32.35% | 0 0.00% 32.35% | 0 0.00% 32.35% | 10 29.41% 61.76% | 12 35.29% 97.06% | 1 2.94% 100.00%
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 34
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 256
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 2559
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 738
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 1038.494580
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 978.643470
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 222.427518
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 29 3.93% 3.93% | 5 0.68% 4.61% | 4 0.54% 5.15% | 194 26.29% 31.44% | 475 64.36% 95.80% | 31 4.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 738
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 7
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 24.428571
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 24.407244
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::stdev 1.133893
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 7
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 40
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 80.275000
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 70.290048
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 50.290942
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 14 35.00% 35.00% | 21 52.50% 87.50% | 0 0.00% 87.50% | 1 2.50% 90.00% | 2 5.00% 95.00% | 1 2.50% 97.50% | 0 0.00% 97.50% | 1 2.50% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 40
-system.ruby.Directory_Controller.GETX 740 0.00% 0.00%
-system.ruby.Directory_Controller.GETS 85 0.00% 0.00%
-system.ruby.Directory_Controller.Lockdown 19 0.00% 0.00%
-system.ruby.Directory_Controller.Unlockdown 19 0.00% 0.00%
-system.ruby.Directory_Controller.Data_Owner 2 0.00% 0.00%
-system.ruby.Directory_Controller.Data_All_Tokens 741 0.00% 0.00%
-system.ruby.Directory_Controller.Ack_Owner_All_Tokens 73 0.00% 0.00%
-system.ruby.Directory_Controller.Ack_All_Tokens 2 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 823 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 743 0.00% 0.00%
-system.ruby.Directory_Controller.O.GETX 739 0.00% 0.00%
-system.ruby.Directory_Controller.O.GETS 85 0.00% 0.00%
-system.ruby.Directory_Controller.O.Ack_All_Tokens 2 0.00% 0.00%
-system.ruby.Directory_Controller.NO.GETX 1 0.00% 0.00%
-system.ruby.Directory_Controller.NO.Lockdown 4 0.00% 0.00%
-system.ruby.Directory_Controller.NO.Data_Owner 2 0.00% 0.00%
-system.ruby.Directory_Controller.NO.Data_All_Tokens 741 0.00% 0.00%
-system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 73 0.00% 0.00%
-system.ruby.Directory_Controller.L.Unlockdown 19 0.00% 0.00%
-system.ruby.Directory_Controller.O_W.Memory_Ack 743 0.00% 0.00%
-system.ruby.Directory_Controller.L_NO_W.Memory_Data 15 0.00% 0.00%
-system.ruby.Directory_Controller.NO_W.Lockdown 15 0.00% 0.00%
-system.ruby.Directory_Controller.NO_W.Memory_Data 808 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load 53 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ifetch 48 0.00% 0.00%
-system.ruby.L1Cache_Controller.Store 859 0.00% 0.00%
-system.ruby.L1Cache_Controller.L1_Replacement 23142 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data_Shared 10 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data_All_Tokens 869 0.00% 0.00%
-system.ruby.L1Cache_Controller.Own_Lock_or_Unlock 38 0.00% 0.00%
-system.ruby.L1Cache_Controller.Request_Timeout 35 0.00% 0.00%
-system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers 855 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Load 47 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Ifetch 48 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Store 772 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Data_All_Tokens 13 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock 14 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.Load 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.Store 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement 9 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement 82 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock 3 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.Load 4 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.Store 69 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.L1_Replacement 771 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock 2 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.L1_Replacement 624 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 83 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.Load 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.Store 17 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.L1_Replacement 10842 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers 772 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement 10272 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.Data_All_Tokens 771 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock 12 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.Request_Timeout 25 0.00% 0.00%
-system.ruby.L1Cache_Controller.SM.Data_All_Tokens 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.L1_Replacement 542 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data_Shared 10 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data_All_Tokens 84 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock 5 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Request_Timeout 10 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETS 95 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETX 773 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement 805 0.00% 0.00%
-system.ruby.L2Cache_Controller.Writeback_Shared_Data 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.Writeback_All_Tokens 860 0.00% 0.00%
-system.ruby.L2Cache_Controller.Persistent_GETX 13 0.00% 0.00%
-system.ruby.L2Cache_Controller.Persistent_GETS 6 0.00% 0.00%
-system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 19 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS 85 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX 739 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 807 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 19 0.00% 0.00%
-system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 33 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L2_Replacement 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.O.L1_GETX 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.O.L2_Replacement 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 7 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS 10 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX 33 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 801 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 13 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.Persistent_GETX 13 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.Persistent_GETS 6 0.00% 0.00%
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
-
-[system]
-type=System
-children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:268435455:0:0:0:0
-memories=system.mem_ctrls
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.sys_port_proxy.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=RubyTester
-check_flush=true
-checks_to_complete=100
-clk_domain=system.clk_domain
-deadlock_threshold=50000
-default_p_state=UNDEFINED
-eventq_index=0
-num_cpus=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-system=system
-wakeup_frequency=10
-cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000
-
-[system.mem_ctrls]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-page_policy=open_adaptive
-power_model=Null
-range=0:268435455:5:19:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10
-static_frontend_latency=10
-tBURST=5
-tCCD_L=0
-tCK=1
-tCL=14
-tCS=3
-tRAS=35
-tRCD=14
-tREFI=7800
-tRFC=260
-tRP=14
-tRRD=6
-tRRD_L=0
-tRTP=8
-tRTW=3
-tWR=15
-tWTR=8
-tXAW=30
-tXP=6
-tXPDLL=0
-tXS=270
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.ruby.dir_cntrl0.memory
-
-[system.ruby]
-type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
-access_backing_store=false
-all_instructions=false
-block_size_bytes=64
-clk_domain=system.ruby.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hot_lines=false
-memory_size_bits=48
-num_of_sequencers=1
-number_of_virtual_networks=6
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-phys_mem=Null
-power_model=Null
-randomization=true
-
-[system.ruby.clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.ruby.dir_cntrl0]
-type=Directory_Controller
-children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir probeFilter requestToDir responseFromDir responseFromMemory responseToDir triggerQueue unblockToDir
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-default_p_state=UNDEFINED
-directory=system.ruby.dir_cntrl0.directory
-dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir
-dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir
-eventq_index=0
-forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir
-from_memory_controller_latency=2
-full_bit_dir_enabled=false
-number_of_TBEs=256
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-probeFilter=system.ruby.dir_cntrl0.probeFilter
-probe_filter_enabled=false
-recycle_latency=10
-requestToDir=system.ruby.dir_cntrl0.requestToDir
-responseFromDir=system.ruby.dir_cntrl0.responseFromDir
-responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory
-responseToDir=system.ruby.dir_cntrl0.responseToDir
-ruby_system=system.ruby
-system=system
-to_memory_controller_latency=1
-transitions_per_cycle=32
-triggerQueue=system.ruby.dir_cntrl0.triggerQueue
-unblockToDir=system.ruby.dir_cntrl0.unblockToDir
-version=0
-memory=system.mem_ctrls.port
-
-[system.ruby.dir_cntrl0.directory]
-type=RubyDirectoryMemory
-eventq_index=0
-numa_high_bit=5
-size=268435456
-version=0
-
-[system.ruby.dir_cntrl0.dmaRequestToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[5]
-
-[system.ruby.dir_cntrl0.dmaResponseFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[5]
-
-[system.ruby.dir_cntrl0.forwardFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[3]
-
-[system.ruby.dir_cntrl0.probeFilter]
-type=RubyCache
-children=replacement_policy
-assoc=4
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.dir_cntrl0.probeFilter.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=1024
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.dir_cntrl0.probeFilter.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=4
-block_size=64
-eventq_index=0
-size=1024
-
-[system.ruby.dir_cntrl0.requestToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[4]
-
-[system.ruby.dir_cntrl0.responseFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[4]
-
-[system.ruby.dir_cntrl0.responseFromMemory]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.dir_cntrl0.responseToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[3]
-
-[system.ruby.dir_cntrl0.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.dir_cntrl0.unblockToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[2]
-
-[system.ruby.l1_cntrl0]
-type=L1Cache_Controller
-children=L1Dcache L1Icache L2cache forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer triggerQueue unblockFromCache
-L1Dcache=system.ruby.l1_cntrl0.L1Dcache
-L1Icache=system.ruby.l1_cntrl0.L1Icache
-L2cache=system.ruby.l1_cntrl0.L2cache
-buffer_size=0
-cache_response_latency=10
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-default_p_state=UNDEFINED
-eventq_index=0
-forwardToCache=system.ruby.l1_cntrl0.forwardToCache
-issue_latency=2
-l2_cache_hit_latency=10
-mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
-no_mig_atomic=true
-number_of_TBEs=256
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-recycle_latency=10
-requestFromCache=system.ruby.l1_cntrl0.requestFromCache
-responseFromCache=system.ruby.l1_cntrl0.responseFromCache
-responseToCache=system.ruby.l1_cntrl0.responseToCache
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl0.sequencer
-system=system
-transitions_per_cycle=32
-triggerQueue=system.ruby.l1_cntrl0.triggerQueue
-unblockFromCache=system.ruby.l1_cntrl0.unblockFromCache
-version=0
-
-[system.ruby.l1_cntrl0.L1Dcache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l1_cntrl0.L1Dcache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.L1Dcache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl0.L1Icache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=true
-replacement_policy=system.ruby.l1_cntrl0.L1Icache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.L1Icache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl0.L2cache]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l1_cntrl0.L2cache.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=512
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.L2cache.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=512
-
-[system.ruby.l1_cntrl0.forwardToCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[0]
-
-[system.ruby.l1_cntrl0.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl0.requestFromCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[0]
-
-[system.ruby.l1_cntrl0.responseFromCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[1]
-
-[system.ruby.l1_cntrl0.responseToCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-slave=system.ruby.network.master[1]
-
-[system.ruby.l1_cntrl0.sequencer]
-type=RubySequencer
-clk_domain=system.ruby.clk_domain
-coreid=99
-dcache=system.ruby.l1_cntrl0.L1Dcache
-dcache_hit_latency=1
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.ruby.l1_cntrl0.L1Icache
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=true
-version=0
-slave=system.cpu.cpuInstDataPort[0]
-
-[system.ruby.l1_cntrl0.triggerQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl0.unblockFromCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[2]
-
-[system.ruby.memctrl_clk_domain]
-type=DerivedClockDomain
-clk_divider=3
-clk_domain=system.ruby.clk_domain
-eventq_index=0
-
-[system.ruby.network]
-type=SimpleNetwork
-children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2
-adaptive_routing=false
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-control_msg_size=8
-default_p_state=UNDEFINED
-endpoint_bandwidth=1000
-eventq_index=0
-ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3
-netifs=
-number_of_virtual_networks=6
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2
-ruby_system=system.ruby
-topology=Crossbar
-master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.dir_cntrl0.unblockToDir.slave system.ruby.dir_cntrl0.responseToDir.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave
-slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.l1_cntrl0.unblockFromCache.master system.ruby.dir_cntrl0.forwardFromDir.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master
-
-[system.ruby.network.ext_links0]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.l1_cntrl0
-int_node=system.ruby.network.routers0
-latency=1
-link_id=0
-weight=1
-
-[system.ruby.network.ext_links1]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.dir_cntrl0
-int_node=system.ruby.network.routers1
-latency=1
-link_id=1
-weight=1
-
-[system.ruby.network.int_link_buffers00]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers01]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers02]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers03]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers04]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers05]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers06]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers07]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers08]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers09]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers10]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers11]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers12]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers13]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers14]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers15]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers16]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers17]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers18]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers19]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers20]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers21]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers22]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers23]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers24]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers25]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers26]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers27]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers28]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers29]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers30]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers31]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers32]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers33]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers34]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers35]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers36]
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-[system.ruby.network.int_link_buffers37]
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-[system.ruby.network.int_link_buffers38]
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-[system.ruby.network.int_link_buffers39]
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-[system.ruby.network.int_link_buffers40]
-type=MessageBuffer
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-[system.ruby.network.int_link_buffers41]
-type=MessageBuffer
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-[system.ruby.network.int_link_buffers42]
-type=MessageBuffer
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-[system.ruby.network.int_link_buffers43]
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-[system.ruby.network.int_link_buffers44]
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-[system.ruby.network.int_link_buffers45]
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-[system.ruby.network.int_link_buffers46]
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-[system.ruby.network.int_link_buffers47]
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-[system.ruby.network.int_links0]
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-dst_inport=
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-
-[system.ruby.network.int_links1]
-type=SimpleIntLink
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-
-[system.ruby.network.int_links2]
-type=SimpleIntLink
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-weight=1
-
-[system.ruby.network.int_links3]
-type=SimpleIntLink
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-weight=1
-
-[system.ruby.network.routers0]
-type=Switch
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-
-[system.ruby.network.routers0.port_buffers00]
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-[system.ruby.network.routers0.port_buffers10]
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-[system.ruby.network.routers0.port_buffers17]
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-[system.ruby.network.routers1]
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-power_model=Null
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-[system.ruby.network.routers1.port_buffers00]
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-[system.ruby.network.routers2]
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-clk_domain=system.ruby.clk_domain
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-port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 system.ruby.network.routers2.port_buffers20 system.ruby.network.routers2.port_buffers21 system.ruby.network.routers2.port_buffers22 system.ruby.network.routers2.port_buffers23
-power_model=Null
-router_id=2
-virt_nets=6
-
-[system.ruby.network.routers2.port_buffers00]
-type=MessageBuffer
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-[system.ruby.network.routers2.port_buffers01]
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-[system.ruby.network.routers2.port_buffers13]
-type=MessageBuffer
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-[system.ruby.network.routers2.port_buffers14]
-type=MessageBuffer
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-
-[system.sys_port_proxy]
-type=RubyPortProxy
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-no_retry_on_stall=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=0
-slave=system.system_port
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
+++ /dev/null
-Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer/simout
-Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 13 2016 20:24:36
-gem5 started Oct 13 2016 20:24:58
-gem5 executing on e108600-lin, pid 38873
-command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
-
-Global frequency set at 1000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 31071 because Ruby Tester completed
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000031 # Number of seconds simulated
-sim_ticks 31071 # Number of ticks simulated
-final_tick 31071 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 718641 # Simulator tick rate (ticks/s)
-host_mem_usage 392596 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 55104 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 55104 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 50048 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 50048 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 861 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 861 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 782 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 782 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 1773486531 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 1773486531 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 1610762447 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 1610762447 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 3384248978 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 3384248978 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 862 # Number of read requests accepted
-system.mem_ctrls.writeReqs 782 # Number of write requests accepted
-system.mem_ctrls.readBursts 862 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 782 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 45632 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 9536 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 41024 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 55168 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 50048 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 111 # Number of DRAM write bursts merged with an existing one
-system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 191 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 231 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 240 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 51 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 172 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 202 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 220 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 47 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
-system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
-system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 31040 # Total gap between requests
-system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 862 # Read request sizes (log2)
-system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 782 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 405 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 288 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2 19 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3 1 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 2 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 22 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 41 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 41 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 42 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 41 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 44 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 42 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 41 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 53 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 44 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 41 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 41 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 40 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 90 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 943.644444 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 882.472849 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 228.764454 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 5 5.56% 5.56% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 1 1.11% 6.67% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 1 1.11% 7.78% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 3 3.33% 11.11% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 2 2.22% 13.33% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 78 86.67% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 90 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 40 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 17.425000 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 17.142863 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 3.754570 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::12-13 1 2.50% 2.50% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15 10 25.00% 27.50% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17 16 40.00% 67.50% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19 6 15.00% 82.50% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-21 5 12.50% 95.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::22-23 1 2.50% 97.50% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::36-37 1 2.50% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 40 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 40 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.025000 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.024268 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 0.158114 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 39 97.50% 97.50% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 1 2.50% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 40 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 12133 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 25680 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 3565 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 17.02 # Average queueing delay per DRAM burst
-system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 36.02 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 1468.64 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 1320.33 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 1775.55 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 1610.76 # Average system write bandwidth in MiByte/s
-system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 21.79 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 11.47 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 10.32 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 1.76 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 25.13 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 625 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 635 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 87.66 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 94.63 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 18.88 # Average gap between requests
-system.mem_ctrls.pageHitRate 91.04 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 671160 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 347760 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 8145312 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 5353632 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 8199792 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 36480 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.actPowerDownEnergy 5925264 # Energy for active power-down per rank (pJ)
-system.mem_ctrls_0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ)
-system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
-system.mem_ctrls_0.totalEnergy 30523320 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 982.373274 # Core power per rank (mW)
-system.mem_ctrls_0.totalIdleTime 12994 # Total Idle time Per DRAM Rank
-system.mem_ctrls_0.memoryStateTime::IDLE 11 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 780 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 17286 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 12994 # Time in different power states
-system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 224352 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 3002880 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ)
-system.mem_ctrls_1.prePowerDownEnergy 2889984 # Energy for precharge power-down per rank (pJ)
-system.mem_ctrls_1.selfRefreshEnergy 3655920 # Energy for self refresh per rank (pJ)
-system.mem_ctrls_1.totalEnergy 11002416 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 354.105629 # Core power per rank (mW)
-system.mem_ctrls_1.totalIdleTime 7526 # Total Idle time Per DRAM Rank
-system.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 526 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::SREF 15233 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 7526 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states
-system.ruby.clk_domain.clock 1 # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states
-system.ruby.outstanding_req_hist_seqr::bucket_size 2
-system.ruby.outstanding_req_hist_seqr::max_bucket 19
-system.ruby.outstanding_req_hist_seqr::samples 1010
-system.ruby.outstanding_req_hist_seqr::mean 15.556436
-system.ruby.outstanding_req_hist_seqr::gmean 15.445317
-system.ruby.outstanding_req_hist_seqr::stdev 1.273066
-system.ruby.outstanding_req_hist_seqr | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.50% | 3 0.30% 0.79% | 3 0.30% 1.09% | 6 0.59% 1.68% | 3 0.30% 1.98% | 272 26.93% 28.91% | 718 71.09% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist_seqr::total 1010
-system.ruby.latency_hist_seqr::bucket_size 128
-system.ruby.latency_hist_seqr::max_bucket 1279
-system.ruby.latency_hist_seqr::samples 995
-system.ruby.latency_hist_seqr::mean 482.717588
-system.ruby.latency_hist_seqr::gmean 245.065735
-system.ruby.latency_hist_seqr::stdev 262.743362
-system.ruby.latency_hist_seqr | 233 23.42% 23.42% | 9 0.90% 24.32% | 5 0.50% 24.82% | 58 5.83% 30.65% | 397 39.90% 70.55% | 236 23.72% 94.27% | 55 5.53% 99.80% | 2 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist_seqr::total 995
-system.ruby.hit_latency_hist_seqr::bucket_size 128
-system.ruby.hit_latency_hist_seqr::max_bucket 1279
-system.ruby.hit_latency_hist_seqr::samples 135
-system.ruby.hit_latency_hist_seqr::mean 110.851852
-system.ruby.hit_latency_hist_seqr::gmean 6.261385
-system.ruby.hit_latency_hist_seqr::stdev 224.829770
-system.ruby.hit_latency_hist_seqr | 111 82.22% 82.22% | 0 0.00% 82.22% | 0 0.00% 82.22% | 3 2.22% 84.44% | 17 12.59% 97.04% | 3 2.22% 99.26% | 0 0.00% 99.26% | 1 0.74% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist_seqr::total 135
-system.ruby.miss_latency_hist_seqr::bucket_size 128
-system.ruby.miss_latency_hist_seqr::max_bucket 1279
-system.ruby.miss_latency_hist_seqr::samples 860
-system.ruby.miss_latency_hist_seqr::mean 541.091860
-system.ruby.miss_latency_hist_seqr::gmean 435.798434
-system.ruby.miss_latency_hist_seqr::stdev 216.457686
-system.ruby.miss_latency_hist_seqr | 122 14.19% 14.19% | 9 1.05% 15.23% | 5 0.58% 15.81% | 55 6.40% 22.21% | 380 44.19% 66.40% | 233 27.09% 93.49% | 55 6.40% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.miss_latency_hist_seqr::total 860
-system.ruby.Directory.incomplete_times_seqr 860
-system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.055098 # Average number of messages in buffer
-system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 1.993950 # Average number of cycles messages are stalled in this MB
-system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits
-system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses
-system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses
-system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.079332 # Average number of messages in buffer
-system.ruby.dir_cntrl0.requestToDir.avg_stall_time 9.743402 # Average number of cycles messages are stalled in this MB
-system.ruby.dir_cntrl0.requestToDir.num_msg_stalls 247 # Number of times messages were stalled
-system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.027710 # Average number of messages in buffer
-system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.997779 # Average number of cycles messages are stalled in this MB
-system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.052877 # Average number of messages in buffer
-system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.997812 # Average number of cycles messages are stalled in this MB
-system.ruby.dir_cntrl0.unblockToDir.avg_buf_msgs 0.055098 # Average number of messages in buffer
-system.ruby.dir_cntrl0.unblockToDir.avg_stall_time 16.445417 # Average number of cycles messages are stalled in this MB
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 79 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 852 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 931 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 63 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 63 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L2cache.demand_hits 54 # Number of cache demand hits
-system.ruby.l1_cntrl0.L2cache.demand_misses 861 # Number of cache demand misses
-system.ruby.l1_cntrl0.L2cache.demand_accesses 915 # Number of cache demand accesses
-system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.027549 # Average number of messages in buffer
-system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 7.992179 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 13.810859 # Average number of messages in buffer
-system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 11.674884 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.mandatoryQueue.num_msg_stalls 17591 # Number of times messages were stalled
-system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.110582 # Average number of messages in buffer
-system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999743 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.027710 # Average number of messages in buffer
-system.ruby.l1_cntrl0.responseToCache.avg_stall_time 7.080072 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 3 # Number of times a store aliased with a pending load
-system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 84 # Number of times a store aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 7 # Number of times a load aliased with a pending store
-system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 1 # Number of times a load aliased with a pending load
-system.ruby.l1_cntrl0.triggerQueue.avg_buf_msgs 0.045411 # Average number of messages in buffer
-system.ruby.l1_cntrl0.triggerQueue.avg_stall_time 1.709803 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.unblockFromCache.avg_buf_msgs 0.551686 # Average number of messages in buffer
-system.ruby.l1_cntrl0.unblockFromCache.avg_stall_time 9.972322 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states
-system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.027549 # Average number of messages in buffer
-system.ruby.network.routers0.port_buffers03.avg_stall_time 6.995623 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.027710 # Average number of messages in buffer
-system.ruby.network.routers0.port_buffers04.avg_stall_time 6.082679 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.063755 # Average number of messages in buffer
-system.ruby.network.routers0.port_buffers07.avg_stall_time 3.199504 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers0.port_buffers10.avg_buf_msgs 0.069355 # Average number of messages in buffer
-system.ruby.network.routers0.port_buffers10.avg_stall_time 11.461992 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized 14.722732
-system.ruby.network.routers0.msg_count.Request_Control::2 863
-system.ruby.network.routers0.msg_count.Response_Data::4 861
-system.ruby.network.routers0.msg_count.Writeback_Data::5 783
-system.ruby.network.routers0.msg_count.Writeback_Control::2 855
-system.ruby.network.routers0.msg_count.Writeback_Control::3 856
-system.ruby.network.routers0.msg_count.Writeback_Control::5 71
-system.ruby.network.routers0.msg_count.Unblock_Control::5 859
-system.ruby.network.routers0.msg_bytes.Request_Control::2 6904
-system.ruby.network.routers0.msg_bytes.Response_Data::4 61992
-system.ruby.network.routers0.msg_bytes.Writeback_Data::5 56376
-system.ruby.network.routers0.msg_bytes.Writeback_Control::2 6840
-system.ruby.network.routers0.msg_bytes.Writeback_Control::3 6848
-system.ruby.network.routers0.msg_bytes.Writeback_Control::5 568
-system.ruby.network.routers0.msg_bytes.Unblock_Control::5 6872
-system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.055291 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers02.avg_stall_time 7.197960 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.port_buffers05.avg_buf_msgs 0.055130 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers05.avg_stall_time 15.448861 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.port_buffers09.avg_buf_msgs 0.027871 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers09.avg_stall_time 3.008754 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.port_buffers10.avg_buf_msgs 0.029480 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers10.avg_stall_time 2.092463 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized 14.717100
-system.ruby.network.routers1.msg_count.Request_Control::2 863
-system.ruby.network.routers1.msg_count.Response_Data::4 861
-system.ruby.network.routers1.msg_count.Writeback_Data::5 782
-system.ruby.network.routers1.msg_count.Writeback_Control::2 855
-system.ruby.network.routers1.msg_count.Writeback_Control::3 856
-system.ruby.network.routers1.msg_count.Writeback_Control::5 71
-system.ruby.network.routers1.msg_count.Unblock_Control::5 859
-system.ruby.network.routers1.msg_bytes.Request_Control::2 6904
-system.ruby.network.routers1.msg_bytes.Response_Data::4 61992
-system.ruby.network.routers1.msg_bytes.Writeback_Data::5 56304
-system.ruby.network.routers1.msg_bytes.Writeback_Control::2 6840
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3 6848
-system.ruby.network.routers1.msg_bytes.Writeback_Control::5 568
-system.ruby.network.routers1.msg_bytes.Unblock_Control::5 6872
-system.ruby.network.int_link_buffers02.avg_buf_msgs 0.055291 # Average number of messages in buffer
-system.ruby.network.int_link_buffers02.avg_stall_time 4.199215 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers05.avg_buf_msgs 0.055130 # Average number of messages in buffer
-system.ruby.network.int_link_buffers05.avg_stall_time 12.458805 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers09.avg_buf_msgs 0.027549 # Average number of messages in buffer
-system.ruby.network.int_link_buffers09.avg_stall_time 4.005568 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers10.avg_buf_msgs 0.027710 # Average number of messages in buffer
-system.ruby.network.int_link_buffers10.avg_stall_time 3.090113 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers15.avg_buf_msgs 0.027549 # Average number of messages in buffer
-system.ruby.network.int_link_buffers15.avg_stall_time 5.999002 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers16.avg_buf_msgs 0.027710 # Average number of messages in buffer
-system.ruby.network.int_link_buffers16.avg_stall_time 5.085221 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers20.avg_buf_msgs 0.055291 # Average number of messages in buffer
-system.ruby.network.int_link_buffers20.avg_stall_time 6.198442 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers23.avg_buf_msgs 0.055130 # Average number of messages in buffer
-system.ruby.network.int_link_buffers23.avg_stall_time 14.452240 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.027549 # Average number of messages in buffer
-system.ruby.network.routers2.port_buffers03.avg_stall_time 5.002317 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.027710 # Average number of messages in buffer
-system.ruby.network.routers2.port_buffers04.avg_stall_time 4.087700 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.port_buffers08.avg_buf_msgs 0.055291 # Average number of messages in buffer
-system.ruby.network.routers2.port_buffers08.avg_stall_time 5.198861 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.port_buffers11.avg_buf_msgs 0.055130 # Average number of messages in buffer
-system.ruby.network.routers2.port_buffers11.avg_stall_time 13.455555 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized 14.720318
-system.ruby.network.routers2.msg_count.Request_Control::2 863
-system.ruby.network.routers2.msg_count.Response_Data::4 861
-system.ruby.network.routers2.msg_count.Writeback_Data::5 783
-system.ruby.network.routers2.msg_count.Writeback_Control::2 855
-system.ruby.network.routers2.msg_count.Writeback_Control::3 856
-system.ruby.network.routers2.msg_count.Writeback_Control::5 71
-system.ruby.network.routers2.msg_count.Unblock_Control::5 859
-system.ruby.network.routers2.msg_bytes.Request_Control::2 6904
-system.ruby.network.routers2.msg_bytes.Response_Data::4 61992
-system.ruby.network.routers2.msg_bytes.Writeback_Data::5 56376
-system.ruby.network.routers2.msg_bytes.Writeback_Control::2 6840
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3 6848
-system.ruby.network.routers2.msg_bytes.Writeback_Control::5 568
-system.ruby.network.routers2.msg_bytes.Unblock_Control::5 6872
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states
-system.ruby.network.msg_count.Request_Control 2589
-system.ruby.network.msg_count.Response_Data 2583
-system.ruby.network.msg_count.Writeback_Data 2348
-system.ruby.network.msg_count.Writeback_Control 5346
-system.ruby.network.msg_count.Unblock_Control 2577
-system.ruby.network.msg_byte.Request_Control 20712
-system.ruby.network.msg_byte.Response_Data 185976
-system.ruby.network.msg_byte.Writeback_Data 169056
-system.ruby.network.msg_byte.Writeback_Control 42768
-system.ruby.network.msg_byte.Unblock_Control 20616
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization 13.845708
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 861
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 856
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 61992
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 6848
-system.ruby.network.routers0.throttle1.link_utilization 15.599755
-system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 863
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 783
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 855
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5 71
-system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5 859
-system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2 6904
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 56376
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 6840
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 568
-system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 6872
-system.ruby.network.routers1.throttle0.link_utilization 15.586882
-system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 863
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5 782
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 855
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::5 71
-system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::5 859
-system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2 6904
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5 56304
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 6840
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 568
-system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 6872
-system.ruby.network.routers1.throttle1.link_utilization 13.847317
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 861
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 856
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 61992
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 6848
-system.ruby.network.routers2.throttle0.link_utilization 13.847317
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 861
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 856
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 61992
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 6848
-system.ruby.network.routers2.throttle1.link_utilization 15.593319
-system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 863
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 783
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 855
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5 71
-system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5 859
-system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 6904
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 56376
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 6840
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 568
-system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 6872
-system.ruby.LD.latency_hist_seqr::bucket_size 128
-system.ruby.LD.latency_hist_seqr::max_bucket 1279
-system.ruby.LD.latency_hist_seqr::samples 37
-system.ruby.LD.latency_hist_seqr::mean 484.027027
-system.ruby.LD.latency_hist_seqr::gmean 206.042037
-system.ruby.LD.latency_hist_seqr::stdev 286.676016
-system.ruby.LD.latency_hist_seqr | 10 27.03% 27.03% | 0 0.00% 27.03% | 0 0.00% 27.03% | 0 0.00% 27.03% | 12 32.43% 59.46% | 13 35.14% 94.59% | 2 5.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.latency_hist_seqr::total 37
-system.ruby.LD.hit_latency_hist_seqr::bucket_size 64
-system.ruby.LD.hit_latency_hist_seqr::max_bucket 639
-system.ruby.LD.hit_latency_hist_seqr::samples 6
-system.ruby.LD.hit_latency_hist_seqr::mean 104
-system.ruby.LD.hit_latency_hist_seqr::gmean 4.461922
-system.ruby.LD.hit_latency_hist_seqr::stdev 246.465413
-system.ruby.LD.hit_latency_hist_seqr | 5 83.33% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 1 16.67% 100.00%
-system.ruby.LD.hit_latency_hist_seqr::total 6
-system.ruby.LD.miss_latency_hist_seqr::bucket_size 128
-system.ruby.LD.miss_latency_hist_seqr::max_bucket 1279
-system.ruby.LD.miss_latency_hist_seqr::samples 31
-system.ruby.LD.miss_latency_hist_seqr::mean 557.580645
-system.ruby.LD.miss_latency_hist_seqr::gmean 432.617733
-system.ruby.LD.miss_latency_hist_seqr::stdev 232.424149
-system.ruby.LD.miss_latency_hist_seqr | 5 16.13% 16.13% | 0 0.00% 16.13% | 0 0.00% 16.13% | 0 0.00% 16.13% | 11 35.48% 51.61% | 13 41.94% 93.55% | 2 6.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.miss_latency_hist_seqr::total 31
-system.ruby.ST.latency_hist_seqr::bucket_size 128
-system.ruby.ST.latency_hist_seqr::max_bucket 1279
-system.ruby.ST.latency_hist_seqr::samples 893
-system.ruby.ST.latency_hist_seqr::mean 513.324748
-system.ruby.ST.latency_hist_seqr::gmean 281.060775
-system.ruby.ST.latency_hist_seqr::stdev 242.626948
-system.ruby.ST.latency_hist_seqr | 160 17.92% 17.92% | 8 0.90% 18.81% | 5 0.56% 19.37% | 58 6.49% 25.87% | 385 43.11% 68.98% | 223 24.97% 93.95% | 53 5.94% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.latency_hist_seqr::total 893
-system.ruby.ST.hit_latency_hist_seqr::bucket_size 128
-system.ruby.ST.hit_latency_hist_seqr::max_bucket 1279
-system.ruby.ST.hit_latency_hist_seqr::samples 116
-system.ruby.ST.hit_latency_hist_seqr::mean 114.353448
-system.ruby.ST.hit_latency_hist_seqr::gmean 5.688161
-system.ruby.ST.hit_latency_hist_seqr::stdev 222.966921
-system.ruby.ST.hit_latency_hist_seqr | 94 81.03% 81.03% | 0 0.00% 81.03% | 0 0.00% 81.03% | 3 2.59% 83.62% | 16 13.79% 97.41% | 3 2.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.hit_latency_hist_seqr::total 116
-system.ruby.ST.miss_latency_hist_seqr::bucket_size 128
-system.ruby.ST.miss_latency_hist_seqr::max_bucket 1279
-system.ruby.ST.miss_latency_hist_seqr::samples 777
-system.ruby.ST.miss_latency_hist_seqr::mean 572.888031
-system.ruby.ST.miss_latency_hist_seqr::gmean 503.124564
-system.ruby.ST.miss_latency_hist_seqr::stdev 181.530163
-system.ruby.ST.miss_latency_hist_seqr | 66 8.49% 8.49% | 8 1.03% 9.52% | 5 0.64% 10.17% | 55 7.08% 17.25% | 369 47.49% 64.74% | 220 28.31% 93.05% | 53 6.82% 99.87% | 1 0.13% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.miss_latency_hist_seqr::total 777
-system.ruby.IFETCH.latency_hist_seqr::bucket_size 32
-system.ruby.IFETCH.latency_hist_seqr::max_bucket 319
-system.ruby.IFETCH.latency_hist_seqr::samples 63
-system.ruby.IFETCH.latency_hist_seqr::mean 48.269841
-system.ruby.IFETCH.latency_hist_seqr::gmean 39.118214
-system.ruby.IFETCH.latency_hist_seqr::stdev 28.730790
-system.ruby.IFETCH.latency_hist_seqr | 25 39.68% 39.68% | 19 30.16% 69.84% | 18 28.57% 98.41% | 0 0.00% 98.41% | 0 0.00% 98.41% | 1 1.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.latency_hist_seqr::total 63
-system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 2
-system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 19
-system.ruby.IFETCH.hit_latency_hist_seqr::samples 11
-system.ruby.IFETCH.hit_latency_hist_seqr::mean 11
-system.ruby.IFETCH.hit_latency_hist_seqr::gmean 11.000000
-system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.hit_latency_hist_seqr::total 11
-system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32
-system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319
-system.ruby.IFETCH.miss_latency_hist_seqr::samples 52
-system.ruby.IFETCH.miss_latency_hist_seqr::mean 56.153846
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean 51.160387
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev 25.308593
-system.ruby.IFETCH.miss_latency_hist_seqr | 14 26.92% 26.92% | 19 36.54% 63.46% | 18 34.62% 98.08% | 0 0.00% 98.08% | 0 0.00% 98.08% | 1 1.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.miss_latency_hist_seqr::total 52
-system.ruby.FLUSH.latency_hist_seqr::bucket_size 128
-system.ruby.FLUSH.latency_hist_seqr::max_bucket 1279
-system.ruby.FLUSH.latency_hist_seqr::samples 2
-system.ruby.FLUSH.latency_hist_seqr::mean 477.500000
-system.ruby.FLUSH.latency_hist_seqr::gmean 204.484718
-system.ruby.FLUSH.latency_hist_seqr::stdev 610.233152
-system.ruby.FLUSH.latency_hist_seqr | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.FLUSH.latency_hist_seqr::total 2
-system.ruby.FLUSH.hit_latency_hist_seqr::bucket_size 128
-system.ruby.FLUSH.hit_latency_hist_seqr::max_bucket 1279
-system.ruby.FLUSH.hit_latency_hist_seqr::samples 2
-system.ruby.FLUSH.hit_latency_hist_seqr::mean 477.500000
-system.ruby.FLUSH.hit_latency_hist_seqr::gmean 204.484718
-system.ruby.FLUSH.hit_latency_hist_seqr::stdev 610.233152
-system.ruby.FLUSH.hit_latency_hist_seqr | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.FLUSH.hit_latency_hist_seqr::total 2
-system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 128
-system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 1279
-system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 81
-system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean 12.765432
-system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean 1.140390
-system.ruby.L1Cache.hit_mach_latency_hist_seqr::stdev 100.950269
-system.ruby.L1Cache.hit_mach_latency_hist_seqr | 80 98.77% 98.77% | 0 0.00% 98.77% | 0 0.00% 98.77% | 0 0.00% 98.77% | 0 0.00% 98.77% | 0 0.00% 98.77% | 0 0.00% 98.77% | 1 1.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 81
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 128
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 1279
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 54
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 257.981481
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 80.555654
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 275.063320
-system.ruby.L2Cache.hit_mach_latency_hist_seqr | 31 57.41% 57.41% | 0 0.00% 57.41% | 0 0.00% 57.41% | 3 5.56% 62.96% | 17 31.48% 94.44% | 3 5.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 54
-system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 128
-system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 1279
-system.ruby.Directory.miss_mach_latency_hist_seqr::samples 860
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean 541.091860
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 435.798434
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 216.457686
-system.ruby.Directory.miss_mach_latency_hist_seqr | 122 14.19% 14.19% | 9 1.05% 15.23% | 5 0.58% 15.81% | 55 6.40% 22.21% | 380 44.19% 66.40% | 233 27.09% 93.49% | 55 6.40% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory.miss_mach_latency_hist_seqr::total 860
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 4
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 4
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 64
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 639
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 2
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 310
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 88.831301
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev 420.021428
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00%
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 2
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 128
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 1279
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 31
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 557.580645
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 432.617733
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 232.424149
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 5 16.13% 16.13% | 0 0.00% 16.13% | 0 0.00% 16.13% | 0 0.00% 16.13% | 11 35.48% 51.61% | 13 41.94% 93.55% | 2 6.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 31
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 75
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::mean 1
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 75 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 75
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 128
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 1279
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 41
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 321.707317
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 136.778519
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 273.433835
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 19 46.34% 46.34% | 0 0.00% 46.34% | 0 0.00% 46.34% | 3 7.32% 53.66% | 16 39.02% 92.68% | 3 7.32% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 41
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 128
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 1279
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 777
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 572.888031
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 503.124564
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 181.530163
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 66 8.49% 8.49% | 8 1.03% 9.52% | 5 0.64% 10.17% | 55 7.08% 17.25% | 369 47.49% 64.74% | 220 28.31% 93.05% | 53 6.82% 99.87% | 1 0.13% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 777
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 11
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 11
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 11
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 52
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 56.153846
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 51.160387
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 25.308593
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 14 26.92% 26.92% | 19 36.54% 63.46% | 18 34.62% 98.08% | 0 0.00% 98.08% | 0 0.00% 98.08% | 1 1.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 52
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 128
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 1279
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::samples 2
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::mean 477.500000
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 204.484718
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::stdev 610.233152
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::total 2
-system.ruby.Directory_Controller.GETX 778 0.00% 0.00%
-system.ruby.Directory_Controller.GETS 84 0.00% 0.00%
-system.ruby.Directory_Controller.PUT 1099 0.00% 0.00%
-system.ruby.Directory_Controller.UnblockM 859 0.00% 0.00%
-system.ruby.Directory_Controller.Writeback_Exclusive_Clean 71 0.00% 0.00%
-system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 782 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 861 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 782 0.00% 0.00%
-system.ruby.Directory_Controller.GETF 2 0.00% 0.00%
-system.ruby.Directory_Controller.PUTF 2 0.00% 0.00%
-system.ruby.Directory_Controller.NO.PUT 853 0.00% 0.00%
-system.ruby.Directory_Controller.NO.GETF 1 0.00% 0.00%
-system.ruby.Directory_Controller.E.GETX 778 0.00% 0.00%
-system.ruby.Directory_Controller.E.GETS 83 0.00% 0.00%
-system.ruby.Directory_Controller.E.GETF 1 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B.PUT 246 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B.UnblockM 859 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B_W.Memory_Data 860 0.00% 0.00%
-system.ruby.Directory_Controller.WB.GETS 1 0.00% 0.00%
-system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 71 0.00% 0.00%
-system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 782 0.00% 0.00%
-system.ruby.Directory_Controller.WB_E_W.Memory_Ack 782 0.00% 0.00%
-system.ruby.Directory_Controller.NO_F.PUTF 2 0.00% 0.00%
-system.ruby.Directory_Controller.NO_F_W.Memory_Data 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load 39 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ifetch 64 0.00% 0.00%
-system.ruby.L1Cache_Controller.Store 934 0.00% 0.00%
-system.ruby.L1Cache_Controller.L2_Replacement 853 0.00% 0.00%
-system.ruby.L1Cache_Controller.L1_to_L2 18403 0.00% 0.00%
-system.ruby.L1Cache_Controller.Trigger_L2_to_L1D 44 0.00% 0.00%
-system.ruby.L1Cache_Controller.Trigger_L2_to_L1I 11 0.00% 0.00%
-system.ruby.L1Cache_Controller.Complete_L2_to_L1 55 0.00% 0.00%
-system.ruby.L1Cache_Controller.Exclusive_Data 861 0.00% 0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack 855 0.00% 0.00%
-system.ruby.L1Cache_Controller.All_acks_no_sharers 861 0.00% 0.00%
-system.ruby.L1Cache_Controller.Flush_line 2 0.00% 0.00%
-system.ruby.L1Cache_Controller.Block_Ack 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Load 31 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Ifetch 52 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Store 778 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Flush_line 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.L2_Replacement 71 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.L1_to_L2 81 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D 10 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.Load 4 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.Store 75 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.L2_Replacement 782 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.L1_to_L2 829 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D 34 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1I 11 0.00% 0.00%
-system.ruby.L1Cache_Controller.MR.Store 10 0.00% 0.00%
-system.ruby.L1Cache_Controller.MR.L1_to_L2 114 0.00% 0.00%
-system.ruby.L1Cache_Controller.MMR.Load 2 0.00% 0.00%
-system.ruby.L1Cache_Controller.MMR.Ifetch 11 0.00% 0.00%
-system.ruby.L1Cache_Controller.MMR.Store 31 0.00% 0.00%
-system.ruby.L1Cache_Controller.MMR.L1_to_L2 14 0.00% 0.00%
-system.ruby.L1Cache_Controller.MMR.Flush_line 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.L1_to_L2 10904 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.Exclusive_Data 777 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.L1_to_L2 223 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers 83 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.L1_to_L2 5430 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers 777 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.L1_to_L2 455 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Exclusive_Data 83 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Ifetch 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Store 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack 853 0.00% 0.00%
-system.ruby.L1Cache_Controller.MT.Store 9 0.00% 0.00%
-system.ruby.L1Cache_Controller.MT.L1_to_L2 130 0.00% 0.00%
-system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 10 0.00% 0.00%
-system.ruby.L1Cache_Controller.MMT.Load 2 0.00% 0.00%
-system.ruby.L1Cache_Controller.MMT.Store 30 0.00% 0.00%
-system.ruby.L1Cache_Controller.MMT.L1_to_L2 223 0.00% 0.00%
-system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 45 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI_F.Writeback_Ack 2 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_F.Block_Ack 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM_F.Exclusive_Data 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.MM_WF.All_acks_no_sharers 1 0.00% 0.00%
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
-
-[system]
-type=System
-children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=0:268435455:0:0:0:0
-memories=system.mem_ctrls
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.sys_port_proxy.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=RubyTester
-check_flush=false
-checks_to_complete=100
-clk_domain=system.clk_domain
-deadlock_threshold=50000
-default_p_state=UNDEFINED
-eventq_index=0
-num_cpus=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-system=system
-wakeup_frequency=10
-cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000
-
-[system.mem_ctrls]
-type=DRAMCtrl
-IDD0=0.055
-IDD02=0.0
-IDD2N=0.032
-IDD2N2=0.0
-IDD2P0=0.0
-IDD2P02=0.0
-IDD2P1=0.032
-IDD2P12=0.0
-IDD3N=0.038
-IDD3N2=0.0
-IDD3P0=0.0
-IDD3P02=0.0
-IDD3P1=0.038
-IDD3P12=0.0
-IDD4R=0.157
-IDD4R2=0.0
-IDD4W=0.125
-IDD4W2=0.0
-IDD5=0.235
-IDD52=0.0
-IDD6=0.02
-IDD62=0.0
-VDD=1.5
-VDD2=0.0
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-page_policy=open_adaptive
-power_model=Null
-range=0:268435455:5:19:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10
-static_frontend_latency=10
-tBURST=5
-tCCD_L=0
-tCK=1
-tCL=14
-tCS=3
-tRAS=35
-tRCD=14
-tREFI=7800
-tRFC=260
-tRP=14
-tRRD=6
-tRRD_L=0
-tRTP=8
-tRTW=3
-tWR=15
-tWTR=8
-tXAW=30
-tXP=6
-tXPDLL=0
-tXS=270
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.ruby.dir_cntrl0.memory
-
-[system.ruby]
-type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
-access_backing_store=false
-all_instructions=false
-block_size_bytes=64
-clk_domain=system.ruby.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hot_lines=false
-memory_size_bits=48
-num_of_sequencers=1
-number_of_virtual_networks=5
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-phys_mem=Null
-power_model=Null
-randomization=true
-
-[system.ruby.clk_domain]
-type=SrcClockDomain
-clock=1
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.ruby.dir_cntrl0]
-type=Directory_Controller
-children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory
-addr_ranges=0:268435455:5:0:0:0
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-default_p_state=UNDEFINED
-directory=system.ruby.dir_cntrl0.directory
-directory_latency=12
-dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir
-dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir
-eventq_index=0
-forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir
-number_of_TBEs=256
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-recycle_latency=10
-requestToDir=system.ruby.dir_cntrl0.requestToDir
-responseFromDir=system.ruby.dir_cntrl0.responseFromDir
-responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory
-ruby_system=system.ruby
-system=system
-to_memory_controller_latency=1
-transitions_per_cycle=32
-version=0
-memory=system.mem_ctrls.port
-
-[system.ruby.dir_cntrl0.directory]
-type=RubyDirectoryMemory
-addr_ranges=0:268435455:5:0:0:0
-eventq_index=0
-
-[system.ruby.dir_cntrl0.dmaRequestToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[3]
-
-[system.ruby.dir_cntrl0.dmaResponseFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[3]
-
-[system.ruby.dir_cntrl0.forwardFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[4]
-
-[system.ruby.dir_cntrl0.requestToDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[2]
-
-[system.ruby.dir_cntrl0.responseFromDir]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-master=system.ruby.network.slave[2]
-
-[system.ruby.dir_cntrl0.responseFromMemory]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl0]
-type=L1Cache_Controller
-children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer
-addr_ranges=0:18446744073709551615:0:0:0:0
-buffer_size=0
-cacheMemory=system.ruby.l1_cntrl0.cacheMemory
-cache_response_latency=12
-clk_domain=system.ruby.clk_domain
-cluster_id=0
-default_p_state=UNDEFINED
-eventq_index=0
-forwardToCache=system.ruby.l1_cntrl0.forwardToCache
-issue_latency=2
-mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
-number_of_TBEs=256
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-recycle_latency=10
-requestFromCache=system.ruby.l1_cntrl0.requestFromCache
-responseFromCache=system.ruby.l1_cntrl0.responseFromCache
-responseToCache=system.ruby.l1_cntrl0.responseToCache
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl0.sequencer
-system=system
-transitions_per_cycle=32
-version=0
-
-[system.ruby.l1_cntrl0.cacheMemory]
-type=RubyCache
-children=replacement_policy
-assoc=2
-block_size=0
-dataAccessLatency=1
-dataArrayBanks=1
-eventq_index=0
-is_icache=false
-replacement_policy=system.ruby.l1_cntrl0.cacheMemory.replacement_policy
-resourceStalls=false
-ruby_system=system.ruby
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.cacheMemory.replacement_policy]
-type=PseudoLRUReplacementPolicy
-assoc=2
-block_size=64
-eventq_index=0
-size=256
-
-[system.ruby.l1_cntrl0.forwardToCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[0]
-
-[system.ruby.l1_cntrl0.mandatoryQueue]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=false
-randomization=false
-
-[system.ruby.l1_cntrl0.requestFromCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[0]
-
-[system.ruby.l1_cntrl0.responseFromCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-master=system.ruby.network.slave[1]
-
-[system.ruby.l1_cntrl0.responseToCache]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-slave=system.ruby.network.master[1]
-
-[system.ruby.l1_cntrl0.sequencer]
-type=RubySequencer
-clk_domain=system.ruby.clk_domain
-coreid=99
-dcache=system.ruby.l1_cntrl0.cacheMemory
-dcache_hit_latency=1
-deadlock_threshold=500000
-default_p_state=UNDEFINED
-eventq_index=0
-garnet_standalone=false
-icache=system.ruby.l1_cntrl0.cacheMemory
-icache_hit_latency=1
-is_cpu_sequencer=true
-max_outstanding_requests=16
-no_retry_on_stall=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=true
-version=0
-slave=system.cpu.cpuInstDataPort[0]
-
-[system.ruby.memctrl_clk_domain]
-type=DerivedClockDomain
-clk_divider=3
-clk_domain=system.ruby.clk_domain
-eventq_index=0
-
-[system.ruby.network]
-type=SimpleNetwork
-children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2
-adaptive_routing=false
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-control_msg_size=8
-default_p_state=UNDEFINED
-endpoint_bandwidth=1000
-eventq_index=0
-ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3
-netifs=
-number_of_virtual_networks=5
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2
-ruby_system=system.ruby
-topology=Crossbar
-master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave
-slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master
-
-[system.ruby.network.ext_links0]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.l1_cntrl0
-int_node=system.ruby.network.routers0
-latency=1
-link_id=0
-weight=1
-
-[system.ruby.network.ext_links1]
-type=SimpleExtLink
-bandwidth_factor=16
-eventq_index=0
-ext_node=system.ruby.dir_cntrl0
-int_node=system.ruby.network.routers1
-latency=1
-link_id=1
-weight=1
-
-[system.ruby.network.int_link_buffers00]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers01]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers02]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers03]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers04]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers05]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers06]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers07]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers08]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers09]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers10]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers11]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers12]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers13]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers14]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers15]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers16]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers17]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers18]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers19]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers20]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers21]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers22]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers23]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers24]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers25]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers26]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers27]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers28]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers29]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers30]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers31]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers32]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers33]
-type=MessageBuffer
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-ordered=true
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-
-[system.ruby.network.int_link_buffers34]
-type=MessageBuffer
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-ordered=true
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-
-[system.ruby.network.int_link_buffers35]
-type=MessageBuffer
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-
-[system.ruby.network.int_link_buffers36]
-type=MessageBuffer
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-
-[system.ruby.network.int_link_buffers37]
-type=MessageBuffer
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-
-[system.ruby.network.int_link_buffers38]
-type=MessageBuffer
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-ordered=true
-randomization=false
-
-[system.ruby.network.int_link_buffers39]
-type=MessageBuffer
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-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.int_links0]
-type=SimpleIntLink
-bandwidth_factor=16
-dst_inport=
-dst_node=system.ruby.network.routers2
-eventq_index=0
-latency=1
-link_id=2
-src_node=system.ruby.network.routers0
-src_outport=
-weight=1
-
-[system.ruby.network.int_links1]
-type=SimpleIntLink
-bandwidth_factor=16
-dst_inport=
-dst_node=system.ruby.network.routers2
-eventq_index=0
-latency=1
-link_id=3
-src_node=system.ruby.network.routers1
-src_outport=
-weight=1
-
-[system.ruby.network.int_links2]
-type=SimpleIntLink
-bandwidth_factor=16
-dst_inport=
-dst_node=system.ruby.network.routers0
-eventq_index=0
-latency=1
-link_id=4
-src_node=system.ruby.network.routers2
-src_outport=
-weight=1
-
-[system.ruby.network.int_links3]
-type=SimpleIntLink
-bandwidth_factor=16
-dst_inport=
-dst_node=system.ruby.network.routers1
-eventq_index=0
-latency=1
-link_id=5
-src_node=system.ruby.network.routers2
-src_outport=
-weight=1
-
-[system.ruby.network.routers0]
-type=Switch
-children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14
-clk_domain=system.ruby.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14
-power_model=Null
-router_id=0
-virt_nets=5
-
-[system.ruby.network.routers0.port_buffers00]
-type=MessageBuffer
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-
-[system.ruby.network.routers0.port_buffers01]
-type=MessageBuffer
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-
-[system.ruby.network.routers0.port_buffers02]
-type=MessageBuffer
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-ordered=true
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-
-[system.ruby.network.routers0.port_buffers03]
-type=MessageBuffer
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-
-[system.ruby.network.routers0.port_buffers04]
-type=MessageBuffer
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-
-[system.ruby.network.routers0.port_buffers05]
-type=MessageBuffer
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-
-[system.ruby.network.routers0.port_buffers06]
-type=MessageBuffer
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-
-[system.ruby.network.routers0.port_buffers07]
-type=MessageBuffer
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-
-[system.ruby.network.routers0.port_buffers08]
-type=MessageBuffer
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-
-[system.ruby.network.routers0.port_buffers09]
-type=MessageBuffer
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-
-[system.ruby.network.routers0.port_buffers10]
-type=MessageBuffer
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-
-[system.ruby.network.routers0.port_buffers11]
-type=MessageBuffer
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-
-[system.ruby.network.routers0.port_buffers12]
-type=MessageBuffer
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-
-[system.ruby.network.routers0.port_buffers13]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers0.port_buffers14]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1]
-type=Switch
-children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14
-clk_domain=system.ruby.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14
-power_model=Null
-router_id=1
-virt_nets=5
-
-[system.ruby.network.routers1.port_buffers00]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers01]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers02]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers03]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers04]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers05]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers06]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers07]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers08]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers09]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers10]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers11]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers12]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers13]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers1.port_buffers14]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2]
-type=Switch
-children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19
-clk_domain=system.ruby.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19
-power_model=Null
-router_id=2
-virt_nets=5
-
-[system.ruby.network.routers2.port_buffers00]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers01]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers02]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers03]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers04]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers05]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers06]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers07]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers08]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers09]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers10]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers11]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers12]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers13]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers14]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers15]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers16]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers17]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers18]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.ruby.network.routers2.port_buffers19]
-type=MessageBuffer
-buffer_size=0
-eventq_index=0
-ordered=true
-randomization=false
-
-[system.sys_port_proxy]
-type=RubyPortProxy
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_cpu_sequencer=true
-no_retry_on_stall=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000
-p_state_clk_gate_min=1
-power_model=Null
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_ruby_tester=false
-version=0
-slave=system.system_port
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.0
-
+++ /dev/null
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-info: Entering event queue @ 0. Starting simulation...
-warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
+++ /dev/null
-Redirecting stdout to build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby/simout
-Redirecting stderr to build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Nov 15 2017 18:28:23
-gem5 started Nov 15 2017 18:28:28
-gem5 executing on e108600-lin, pid 19889
-command line: /work/andsan01/outgoing/gem5/build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby --stats-file 'text://stats.txt?desc=False' -re /work/andsan01/outgoing/gem5/tests/testing/../run.py quick/se/60.rubytest/null/none/rubytest-ruby
-
-Global frequency set at 1000000000 ticks per second
-Exiting @ tick 39431 because Ruby Tester completed
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000039
-sim_ticks 39431
-final_tick 39431
-sim_freq 1000000000
-host_tick_rate 701018
-host_mem_usage 390584
-host_seconds 0.06
-system.voltage_domain.voltage 1
-system.clk_domain.clock 1
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 39431
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 60224
-system.mem_ctrls.bytes_read::total 60224
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 60032
-system.mem_ctrls.bytes_written::total 60032
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 941
-system.mem_ctrls.num_reads::total 941
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 938
-system.mem_ctrls.num_writes::total 938
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 1527326215
-system.mem_ctrls.bw_read::total 1527326215
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 1522456950
-system.mem_ctrls.bw_write::total 1522456950
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 3049783166
-system.mem_ctrls.bw_total::total 3049783166
-system.mem_ctrls.readReqs 941
-system.mem_ctrls.writeReqs 938
-system.mem_ctrls.readBursts 941
-system.mem_ctrls.writeBursts 938
-system.mem_ctrls.bytesReadDRAM 50560
-system.mem_ctrls.bytesReadWrQ 9664
-system.mem_ctrls.bytesWritten 49728
-system.mem_ctrls.bytesReadSys 60224
-system.mem_ctrls.bytesWrittenSys 60032
-system.mem_ctrls.servicedByWrQ 151
-system.mem_ctrls.mergedWrBursts 134
-system.mem_ctrls.neitherReadNorWriteReqs 0
-system.mem_ctrls.perBankRdBursts::0 259
-system.mem_ctrls.perBankRdBursts::1 247
-system.mem_ctrls.perBankRdBursts::2 238
-system.mem_ctrls.perBankRdBursts::3 46
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-system.mem_ctrls.perBankRdBursts::6 0
-system.mem_ctrls.perBankRdBursts::7 0
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-system.mem_ctrls.perBankRdBursts::15 0
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-system.mem_ctrls.perBankWrBursts::2 232
-system.mem_ctrls.perBankWrBursts::3 44
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-system.mem_ctrls.numRdRetry 0
-system.mem_ctrls.numWrRetry 0
-system.mem_ctrls.totGap 39357
-system.mem_ctrls.readPktSize::0 0
-system.mem_ctrls.readPktSize::1 0
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-system.mem_ctrls.readPktSize::5 0
-system.mem_ctrls.readPktSize::6 941
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-system.mem_ctrls.writePktSize::6 938
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-system.mem_ctrls.rdQLenPdf::2 1
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-system.mem_ctrls.bytesPerActivate::samples 108
-system.mem_ctrls.bytesPerActivate::mean 925.629630
-system.mem_ctrls.bytesPerActivate::gmean 827.187599
-system.mem_ctrls.bytesPerActivate::stdev 260.509945
-system.mem_ctrls.bytesPerActivate::0-127 4 3.70% 3.70%
-system.mem_ctrls.bytesPerActivate::128-255 3 2.78% 6.48%
-system.mem_ctrls.bytesPerActivate::256-383 2 1.85% 8.33%
-system.mem_ctrls.bytesPerActivate::384-511 2 1.85% 10.19%
-system.mem_ctrls.bytesPerActivate::512-639 1 0.93% 11.11%
-system.mem_ctrls.bytesPerActivate::640-767 1 0.93% 12.04%
-system.mem_ctrls.bytesPerActivate::768-895 1 0.93% 12.96%
-system.mem_ctrls.bytesPerActivate::896-1023 3 2.78% 15.74%
-system.mem_ctrls.bytesPerActivate::1024-1151 91 84.26% 100.00%
-system.mem_ctrls.bytesPerActivate::total 108
-system.mem_ctrls.rdPerTurnAround::samples 48
-system.mem_ctrls.rdPerTurnAround::mean 16.229167
-system.mem_ctrls.rdPerTurnAround::gmean 16.080832
-system.mem_ctrls.rdPerTurnAround::stdev 2.837736
-system.mem_ctrls.rdPerTurnAround::14-15 10 20.83% 20.83%
-system.mem_ctrls.rdPerTurnAround::16-17 37 77.08% 97.92%
-system.mem_ctrls.rdPerTurnAround::34-35 1 2.08% 100.00%
-system.mem_ctrls.rdPerTurnAround::total 48
-system.mem_ctrls.wrPerTurnAround::samples 48
-system.mem_ctrls.wrPerTurnAround::mean 16.187500
-system.mem_ctrls.wrPerTurnAround::gmean 16.181743
-system.mem_ctrls.wrPerTurnAround::stdev 0.445127
-system.mem_ctrls.wrPerTurnAround::16 40 83.33% 83.33%
-system.mem_ctrls.wrPerTurnAround::17 7 14.58% 97.92%
-system.mem_ctrls.wrPerTurnAround::18 1 2.08% 100.00%
-system.mem_ctrls.wrPerTurnAround::total 48
-system.mem_ctrls.totQLat 14435
-system.mem_ctrls.totMemAccLat 29445
-system.mem_ctrls.totBusLat 3950
-system.mem_ctrls.avgQLat 18.27
-system.mem_ctrls.avgBusLat 5.00
-system.mem_ctrls.avgMemAccLat 37.27
-system.mem_ctrls.avgRdBW 1282.24
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-system.ruby.ST.miss_latency_hist_seqr | 2 0.24% 0.24% | 7 0.83% 1.07% | 6 0.71% 1.78% | 61 7.23% 9.00% | 394 46.68% 55.69% | 317 37.56% 93.25% | 29 3.44% 96.68% | 28 3.32% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.IFETCH.hit_latency_hist_seqr::gmean 604.216848
-system.ruby.IFETCH.hit_latency_hist_seqr::stdev 26.162951
-system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00%
-system.ruby.IFETCH.hit_latency_hist_seqr::total 2
-system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 128
-system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 1279
-system.ruby.IFETCH.miss_latency_hist_seqr::samples 47
-system.ruby.IFETCH.miss_latency_hist_seqr::mean 644.234043
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean 635.873481
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev 108.241922
-system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 8.51% 8.51% | 22 46.81% 55.32% | 16 34.04% 89.36% | 2 4.26% 93.62% | 3 6.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.miss_latency_hist_seqr::total 47
-system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 128
-system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 1279
-system.ruby.Directory.miss_mach_latency_hist_seqr::samples 940
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean 627.082979
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 616.094261
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 106.107284
-system.ruby.Directory.miss_mach_latency_hist_seqr | 2 0.21% 0.21% | 7 0.74% 0.96% | 6 0.64% 1.60% | 71 7.55% 9.15% | 434 46.17% 55.32% | 354 37.66% 92.98% | 33 3.51% 96.49% | 33 3.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory.miss_mach_latency_hist_seqr::total 940
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 128
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 1279
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 49
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 634.816327
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 627.246231
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 101.240159
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6 12.24% 12.24% | 18 36.73% 48.98% | 21 42.86% 91.84% | 2 4.08% 95.92% | 2 4.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 49
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 128
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 1279
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 844
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 625.678910
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 614.370879
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 106.283167
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 2 0.24% 0.24% | 7 0.83% 1.07% | 6 0.71% 1.78% | 61 7.23% 9.00% | 394 46.68% 55.69% | 317 37.56% 93.25% | 29 3.44% 96.68% | 28 3.32% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 844
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 128
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 1279
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 47
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 644.234043
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 635.873481
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 108.241922
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 8.51% 8.51% | 22 46.81% 55.32% | 16 34.04% 89.36% | 2 4.26% 93.62% | 3 6.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 47
-system.ruby.Directory_Controller.GETX 941 0.00% 0.00%
-system.ruby.Directory_Controller.PUTX 938 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 941 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 938 0.00% 0.00%
-system.ruby.Directory_Controller.I.GETX 941 0.00% 0.00%
-system.ruby.Directory_Controller.M.PUTX 938 0.00% 0.00%
-system.ruby.Directory_Controller.IM.Memory_Data 941 0.00% 0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack 938 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load 51 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ifetch 49 0.00% 0.00%
-system.ruby.L1Cache_Controller.Store 883 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data 940 0.00% 0.00%
-system.ruby.L1Cache_Controller.Replacement 938 0.00% 0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack 938 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Load 49 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Ifetch 47 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Store 845 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Load 2 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Ifetch 2 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Store 38 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Replacement 938 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack 938 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data 96 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.Data 844 0.00% 0.00%
-
----------- End Simulation Statistics ----------
+++ /dev/null
-# Copyright (c) 2010 Advanced Micro Devices, Inc.
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu dvfs_handler membus monitor physmem
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.clk_domain.voltage_domain
-
-[system.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.0
-
-[system.cpu]
-type=TrafficGen
-clk_domain=system.clk_domain
-config_file=/work/andsan01/outgoing/gem5/tests/testing/../../tests/quick/se/70.tgen/tgen-dram-ctrl.cfg
-default_p_state=UNDEFINED
-elastic_req=false
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-progress_check=1000000000
-system=system
-port=system.monitor.slave
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.monitor.master system.system_port
-
-[system.monitor]
-type=CommMonitor
-bandwidth_bins=20
-burst_length_bins=20
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-disable_addr_dists=true
-disable_bandwidth_hists=false
-disable_burst_length_hists=false
-disable_itt_dists=false
-disable_latency_hists=false
-disable_outstanding_hists=false
-disable_transaction_hists=false
-eventq_index=0
-itt_bins=20
-itt_max_bin=100000
-latency_bins=20
-outstanding_bins=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-read_addr_mask=18446744073709551615
-sample_period=1000000000
-system=system
-transaction_bins=20
-write_addr_mask=18446744073709551615
-master=system.membus.slave[0]
-slave=system.cpu.port
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055
-IDD02=0.0
-IDD2N=0.032
-IDD2N2=0.0
-IDD2P0=0.0
-IDD2P02=0.0
-IDD2P1=0.032
-IDD2P12=0.0
-IDD3N=0.038
-IDD3N2=0.0
-IDD3P0=0.0
-IDD3P02=0.0
-IDD3P1=0.038
-IDD3P12=0.0
-IDD4R=0.157
-IDD4R2=0.0
-IDD4W=0.125
-IDD4W2=0.0
-IDD5=0.235
-IDD52=0.0
-IDD6=0.02
-IDD62=0.0
-VDD=1.5
-VDD2=0.0
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:134217727:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-info: Entering event queue @ 0. Starting simulation...
+++ /dev/null
-Redirecting stdout to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl/simout
-Redirecting stderr to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Nov 15 2017 18:28:23
-gem5 started Nov 15 2017 18:28:28
-gem5 executing on e108600-lin, pid 19888
-command line: /work/andsan01/outgoing/gem5/build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl --stats-file 'text://stats.txt?desc=False' -re /work/andsan01/outgoing/gem5/tests/testing/../run.py quick/se/70.tgen/null/none/tgen-dram-ctrl
-
-Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 100000000000 because simulate() limit reached
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.100000
-sim_ticks 100000000000
-final_tick 100000000000
-sim_freq 1000000000000
-host_tick_rate 7892072988
-host_mem_usage 221112
-host_seconds 12.67
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 1000
-system.physmem.pwrStateResidencyTicks::UNDEFINED 100000000000
-system.physmem.bytes_read::cpu 106649408
-system.physmem.bytes_read::total 106649408
-system.physmem.bytes_written::cpu 106680256
-system.physmem.bytes_written::total 106680256
-system.physmem.num_reads::cpu 1666397
-system.physmem.num_reads::total 1666397
-system.physmem.num_writes::cpu 1666879
-system.physmem.num_writes::total 1666879
-system.physmem.bw_read::cpu 1066494080
-system.physmem.bw_read::total 1066494080
-system.physmem.bw_write::cpu 1066802560
-system.physmem.bw_write::total 1066802560
-system.physmem.bw_total::cpu 2133296640
-system.physmem.bw_total::total 2133296640
-system.physmem.readReqs 1666397
-system.physmem.writeReqs 1666879
-system.physmem.readBursts 1666397
-system.physmem.writeBursts 1666879
-system.physmem.bytesReadDRAM 106647808
-system.physmem.bytesReadWrQ 1600
-system.physmem.bytesWritten 106676416
-system.physmem.bytesReadSys 106649408
-system.physmem.bytesWrittenSys 106680256
-system.physmem.servicedByWrQ 25
-system.physmem.mergedWrBursts 31
-system.physmem.neitherReadNorWriteReqs 0
-system.physmem.perBankRdBursts::0 104029
-system.physmem.perBankRdBursts::1 103995
-system.physmem.perBankRdBursts::2 104918
-system.physmem.perBankRdBursts::3 104597
-system.physmem.perBankRdBursts::4 103869
-system.physmem.perBankRdBursts::5 103933
-system.physmem.perBankRdBursts::6 103649
-system.physmem.perBankRdBursts::7 104313
-system.physmem.perBankRdBursts::8 103869
-system.physmem.perBankRdBursts::9 104354
-system.physmem.perBankRdBursts::10 103834
-system.physmem.perBankRdBursts::11 104271
-system.physmem.perBankRdBursts::12 104077
-system.physmem.perBankRdBursts::13 104035
-system.physmem.perBankRdBursts::14 104583
-system.physmem.perBankRdBursts::15 104046
-system.physmem.perBankWrBursts::0 104356
-system.physmem.perBankWrBursts::1 104090
-system.physmem.perBankWrBursts::2 104175
-system.physmem.perBankWrBursts::3 103885
-system.physmem.perBankWrBursts::4 104730
-system.physmem.perBankWrBursts::5 104507
-system.physmem.perBankWrBursts::6 104083
-system.physmem.perBankWrBursts::7 104224
-system.physmem.perBankWrBursts::8 104317
-system.physmem.perBankWrBursts::9 104219
-system.physmem.perBankWrBursts::10 104226
-system.physmem.perBankWrBursts::11 103701
-system.physmem.perBankWrBursts::12 104104
-system.physmem.perBankWrBursts::13 103984
-system.physmem.perBankWrBursts::14 104295
-system.physmem.perBankWrBursts::15 103923
-system.physmem.numRdRetry 0
-system.physmem.numWrRetry 0
-system.physmem.totGap 99999956143
-system.physmem.readPktSize::0 0
-system.physmem.readPktSize::1 0
-system.physmem.readPktSize::2 0
-system.physmem.readPktSize::3 0
-system.physmem.readPktSize::4 0
-system.physmem.readPktSize::5 0
-system.physmem.readPktSize::6 1666397
-system.physmem.writePktSize::0 0
-system.physmem.writePktSize::1 0
-system.physmem.writePktSize::2 0
-system.physmem.writePktSize::3 0
-system.physmem.writePktSize::4 0
-system.physmem.writePktSize::5 0
-system.physmem.writePktSize::6 1666879
-system.physmem.rdQLenPdf::0 733345
-system.physmem.rdQLenPdf::1 766437
-system.physmem.rdQLenPdf::2 105881
-system.physmem.rdQLenPdf::3 41900
-system.physmem.rdQLenPdf::4 12740
-system.physmem.rdQLenPdf::5 3643
-system.physmem.rdQLenPdf::6 1163
-system.physmem.rdQLenPdf::7 473
-system.physmem.rdQLenPdf::8 265
-system.physmem.rdQLenPdf::9 141
-system.physmem.rdQLenPdf::10 64
-system.physmem.rdQLenPdf::11 32
-system.physmem.rdQLenPdf::12 64
-system.physmem.rdQLenPdf::13 32
-system.physmem.rdQLenPdf::14 32
-system.physmem.rdQLenPdf::15 32
-system.physmem.rdQLenPdf::16 32
-system.physmem.rdQLenPdf::17 64
-system.physmem.rdQLenPdf::18 32
-system.physmem.rdQLenPdf::19 0
-system.physmem.rdQLenPdf::20 0
-system.physmem.rdQLenPdf::21 0
-system.physmem.rdQLenPdf::22 0
-system.physmem.rdQLenPdf::23 0
-system.physmem.rdQLenPdf::24 0
-system.physmem.rdQLenPdf::25 0
-system.physmem.rdQLenPdf::26 0
-system.physmem.rdQLenPdf::27 0
-system.physmem.rdQLenPdf::28 0
-system.physmem.rdQLenPdf::29 0
-system.physmem.rdQLenPdf::30 0
-system.physmem.rdQLenPdf::31 0
-system.physmem.wrQLenPdf::0 1
-system.physmem.wrQLenPdf::1 1
-system.physmem.wrQLenPdf::2 1
-system.physmem.wrQLenPdf::3 1
-system.physmem.wrQLenPdf::4 1
-system.physmem.wrQLenPdf::5 1
-system.physmem.wrQLenPdf::6 1
-system.physmem.wrQLenPdf::7 1
-system.physmem.wrQLenPdf::8 1
-system.physmem.wrQLenPdf::9 1
-system.physmem.wrQLenPdf::10 1
-system.physmem.wrQLenPdf::11 1
-system.physmem.wrQLenPdf::12 1
-system.physmem.wrQLenPdf::13 1
-system.physmem.wrQLenPdf::14 1
-system.physmem.wrQLenPdf::15 10965
-system.physmem.wrQLenPdf::16 13956
-system.physmem.wrQLenPdf::17 32108
-system.physmem.wrQLenPdf::18 80984
-system.physmem.wrQLenPdf::19 108644
-system.physmem.wrQLenPdf::20 106582
-system.physmem.wrQLenPdf::21 109181
-system.physmem.wrQLenPdf::22 116667
-system.physmem.wrQLenPdf::23 116376
-system.physmem.wrQLenPdf::24 107705
-system.physmem.wrQLenPdf::25 108162
-system.physmem.wrQLenPdf::26 128453
-system.physmem.wrQLenPdf::27 112926
-system.physmem.wrQLenPdf::28 102716
-system.physmem.wrQLenPdf::29 100795
-system.physmem.wrQLenPdf::30 100305
-system.physmem.wrQLenPdf::31 100289
-system.physmem.wrQLenPdf::32 100289
-system.physmem.wrQLenPdf::33 4132
-system.physmem.wrQLenPdf::34 2753
-system.physmem.wrQLenPdf::35 1624
-system.physmem.wrQLenPdf::36 822
-system.physmem.wrQLenPdf::37 299
-system.physmem.wrQLenPdf::38 87
-system.physmem.wrQLenPdf::39 13
-system.physmem.wrQLenPdf::40 0
-system.physmem.wrQLenPdf::41 0
-system.physmem.wrQLenPdf::42 0
-system.physmem.wrQLenPdf::43 0
-system.physmem.wrQLenPdf::44 0
-system.physmem.wrQLenPdf::45 0
-system.physmem.wrQLenPdf::46 0
-system.physmem.wrQLenPdf::47 0
-system.physmem.wrQLenPdf::48 0
-system.physmem.wrQLenPdf::49 0
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-system.monitor.ittReqReq::30001-35000 1648324 49.45% 100.00%
-system.monitor.ittReqReq::35001-40000 18 0.00% 100.00%
-system.monitor.ittReqReq::40001-45000 13 0.00% 100.00%
-system.monitor.ittReqReq::45001-50000 13 0.00% 100.00%
-system.monitor.ittReqReq::50001-55000 16 0.00% 100.00%
-system.monitor.ittReqReq::55001-60000 16 0.00% 100.00%
-system.monitor.ittReqReq::60001-65000 8 0.00% 100.00%
-system.monitor.ittReqReq::65001-70000 0 0.00% 100.00%
-system.monitor.ittReqReq::70001-75000 0 0.00% 100.00%
-system.monitor.ittReqReq::75001-80000 0 0.00% 100.00%
-system.monitor.ittReqReq::80001-85000 0 0.00% 100.00%
-system.monitor.ittReqReq::85001-90000 0 0.00% 100.00%
-system.monitor.ittReqReq::90001-95000 0 0.00% 100.00%
-system.monitor.ittReqReq::95001-100000 0 0.00% 100.00%
-system.monitor.ittReqReq::overflows 1 0.00% 100.00%
-system.monitor.ittReqReq::min_value 28000
-system.monitor.ittReqReq::max_value 1041309
-system.monitor.ittReqReq::total 3333275
-system.monitor.outstandingReadsHist::samples 100
-system.monitor.outstandingReadsHist::mean 1.310000
-system.monitor.outstandingReadsHist::gmean 0
-system.monitor.outstandingReadsHist::stdev 0.991835
-system.monitor.outstandingReadsHist::0 20 20.00% 20.00%
-system.monitor.outstandingReadsHist::1 44 44.00% 64.00%
-system.monitor.outstandingReadsHist::2 24 24.00% 88.00%
-system.monitor.outstandingReadsHist::3 9 9.00% 97.00%
-system.monitor.outstandingReadsHist::4 3 3.00% 100.00%
-system.monitor.outstandingReadsHist::5 0 0.00% 100.00%
-system.monitor.outstandingReadsHist::6 0 0.00% 100.00%
-system.monitor.outstandingReadsHist::7 0 0.00% 100.00%
-system.monitor.outstandingReadsHist::8 0 0.00% 100.00%
-system.monitor.outstandingReadsHist::9 0 0.00% 100.00%
-system.monitor.outstandingReadsHist::10 0 0.00% 100.00%
-system.monitor.outstandingReadsHist::11 0 0.00% 100.00%
-system.monitor.outstandingReadsHist::12 0 0.00% 100.00%
-system.monitor.outstandingReadsHist::13 0 0.00% 100.00%
-system.monitor.outstandingReadsHist::14 0 0.00% 100.00%
-system.monitor.outstandingReadsHist::15 0 0.00% 100.00%
-system.monitor.outstandingReadsHist::16 0 0.00% 100.00%
-system.monitor.outstandingReadsHist::17 0 0.00% 100.00%
-system.monitor.outstandingReadsHist::18 0 0.00% 100.00%
-system.monitor.outstandingReadsHist::19 0 0.00% 100.00%
-system.monitor.outstandingReadsHist::total 100
-system.monitor.outstandingWritesHist::samples 100
-system.monitor.outstandingWritesHist::mean 0.380000
-system.monitor.outstandingWritesHist::gmean 0
-system.monitor.outstandingWritesHist::stdev 0.487832
-system.monitor.outstandingWritesHist::0 62 62.00% 62.00%
-system.monitor.outstandingWritesHist::1 38 38.00% 100.00%
-system.monitor.outstandingWritesHist::2 0 0.00% 100.00%
-system.monitor.outstandingWritesHist::3 0 0.00% 100.00%
-system.monitor.outstandingWritesHist::4 0 0.00% 100.00%
-system.monitor.outstandingWritesHist::5 0 0.00% 100.00%
-system.monitor.outstandingWritesHist::6 0 0.00% 100.00%
-system.monitor.outstandingWritesHist::7 0 0.00% 100.00%
-system.monitor.outstandingWritesHist::8 0 0.00% 100.00%
-system.monitor.outstandingWritesHist::9 0 0.00% 100.00%
-system.monitor.outstandingWritesHist::10 0 0.00% 100.00%
-system.monitor.outstandingWritesHist::11 0 0.00% 100.00%
-system.monitor.outstandingWritesHist::12 0 0.00% 100.00%
-system.monitor.outstandingWritesHist::13 0 0.00% 100.00%
-system.monitor.outstandingWritesHist::14 0 0.00% 100.00%
-system.monitor.outstandingWritesHist::15 0 0.00% 100.00%
-system.monitor.outstandingWritesHist::16 0 0.00% 100.00%
-system.monitor.outstandingWritesHist::17 0 0.00% 100.00%
-system.monitor.outstandingWritesHist::18 0 0.00% 100.00%
-system.monitor.outstandingWritesHist::19 0 0.00% 100.00%
-system.monitor.outstandingWritesHist::total 100
-system.monitor.readTransHist::samples 100
-system.monitor.readTransHist::mean 16663.970000
-system.monitor.readTransHist::gmean 16611.784927
-system.monitor.readTransHist::stdev 1686.281945
-system.monitor.readTransHist::0-2047 0 0.00% 0.00%
-system.monitor.readTransHist::2048-4095 0 0.00% 0.00%
-system.monitor.readTransHist::4096-6143 0 0.00% 0.00%
-system.monitor.readTransHist::6144-8191 0 0.00% 0.00%
-system.monitor.readTransHist::8192-10239 0 0.00% 0.00%
-system.monitor.readTransHist::10240-12287 0 0.00% 0.00%
-system.monitor.readTransHist::12288-14335 0 0.00% 0.00%
-system.monitor.readTransHist::14336-16383 12 12.00% 12.00%
-system.monitor.readTransHist::16384-18431 87 87.00% 99.00%
-system.monitor.readTransHist::18432-20479 0 0.00% 99.00%
-system.monitor.readTransHist::20480-22527 0 0.00% 99.00%
-system.monitor.readTransHist::22528-24575 0 0.00% 99.00%
-system.monitor.readTransHist::24576-26623 0 0.00% 99.00%
-system.monitor.readTransHist::26624-28671 0 0.00% 99.00%
-system.monitor.readTransHist::28672-30719 0 0.00% 99.00%
-system.monitor.readTransHist::30720-32767 0 0.00% 99.00%
-system.monitor.readTransHist::32768-34815 1 1.00% 100.00%
-system.monitor.readTransHist::34816-36863 0 0.00% 100.00%
-system.monitor.readTransHist::36864-38911 0 0.00% 100.00%
-system.monitor.readTransHist::38912-40959 0 0.00% 100.00%
-system.monitor.readTransHist::total 100
-system.monitor.writeTransHist::samples 100
-system.monitor.writeTransHist::mean 16668.790000
-system.monitor.writeTransHist::gmean 0
-system.monitor.writeTransHist::stdev 1686.323754
-system.monitor.writeTransHist::0-1023 1 1.00% 1.00%
-system.monitor.writeTransHist::1024-2047 0 0.00% 1.00%
-system.monitor.writeTransHist::2048-3071 0 0.00% 1.00%
-system.monitor.writeTransHist::3072-4095 0 0.00% 1.00%
-system.monitor.writeTransHist::4096-5119 0 0.00% 1.00%
-system.monitor.writeTransHist::5120-6143 0 0.00% 1.00%
-system.monitor.writeTransHist::6144-7167 0 0.00% 1.00%
-system.monitor.writeTransHist::7168-8191 0 0.00% 1.00%
-system.monitor.writeTransHist::8192-9215 0 0.00% 1.00%
-system.monitor.writeTransHist::9216-10239 0 0.00% 1.00%
-system.monitor.writeTransHist::10240-11263 0 0.00% 1.00%
-system.monitor.writeTransHist::11264-12287 0 0.00% 1.00%
-system.monitor.writeTransHist::12288-13311 0 0.00% 1.00%
-system.monitor.writeTransHist::13312-14335 0 0.00% 1.00%
-system.monitor.writeTransHist::14336-15359 0 0.00% 1.00%
-system.monitor.writeTransHist::15360-16383 0 0.00% 1.00%
-system.monitor.writeTransHist::16384-17407 99 99.00% 100.00%
-system.monitor.writeTransHist::17408-18431 0 0.00% 100.00%
-system.monitor.writeTransHist::18432-19455 0 0.00% 100.00%
-system.monitor.writeTransHist::19456-20479 0 0.00% 100.00%
-system.monitor.writeTransHist::total 100
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu dvfs_handler membus monitor physmem
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.clk_domain]
-type=SrcClockDomain
-children=voltage_domain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.clk_domain.voltage_domain
-
-[system.clk_domain.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
-[system.cpu]
-type=TrafficGen
-clk_domain=system.clk_domain
-config_file=tests/quick/se/70.tgen/tgen-simple-mem.cfg
-elastic_req=false
-eventq_index=0
-system=system
-port=system.monitor.slave
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-response_latency=2
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.monitor.master system.system_port
-
-[system.monitor]
-type=CommMonitor
-children=stackdist trace
-bandwidth_bins=20
-burst_length_bins=20
-clk_domain=system.clk_domain
-disable_addr_dists=true
-disable_bandwidth_hists=false
-disable_burst_length_hists=false
-disable_itt_dists=false
-disable_latency_hists=false
-disable_outstanding_hists=false
-disable_transaction_hists=false
-eventq_index=0
-itt_bins=20
-itt_max_bin=100000
-latency_bins=20
-outstanding_bins=20
-read_addr_mask=18446744073709551615
-sample_period=1000000000
-system=system
-transaction_bins=20
-write_addr_mask=18446744073709551615
-master=system.membus.slave[0]
-slave=system.cpu.port
-
-[system.monitor.stackdist]
-type=StackDistProbe
-disable_linear_hists=false
-disable_log_hists=false
-eventq_index=0
-line_size=64
-linear_hist_bins=16
-log_hist_bins=32
-manager=system.monitor
-probe_name=PktRequest
-system=system
-verify=true
-
-[system.monitor.trace]
-type=MemTraceProbe
-eventq_index=0
-manager=system.monitor
-probe_name=PktRequest
-trace_compress=true
-trace_file=monitor.ptrc.gz
-with_pc=false
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-port=system.membus.master[0]
-
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 21 2016 14:20:17
-gem5 started Jan 21 2016 14:20:32
-gem5 executing on zizzer, pid 63119
-command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem -re /z/atgutier/gem5/gem5-commit/tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem
-
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 100000000000 because simulate() limit reached
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.100000 # Number of seconds simulated
-sim_ticks 100000000000 # Number of ticks simulated
-final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 18414287723 # Simulator tick rate (ticks/s)
-host_mem_usage 264992 # Number of bytes of host memory used
-host_seconds 5.43 # Real time elapsed on the host
-system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory
-system.physmem.bytes_read::total 64 # Number of bytes read from this memory
-system.physmem.bytes_written::cpu 853312 # Number of bytes written to this memory
-system.physmem.bytes_written::total 853312 # Number of bytes written to this memory
-system.physmem.num_reads::cpu 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu 13333 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 13333 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu 640 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 640 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu 8533120 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 8533120 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu 8533760 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 8533760 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states
-system.cpu.numPackets 13334 # Number of packets generated
-system.cpu.numRetries 1 # Number of retries
-system.cpu.retryTicks 1672 # Time spent waiting due to back-pressure (ticks)
-system.membus.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 1 # Transaction distribution
-system.membus.trans_dist::ReadResp 1 # Transaction distribution
-system.membus.trans_dist::WriteReq 13333 # Transaction distribution
-system.membus.trans_dist::WriteResp 13333 # Transaction distribution
-system.membus.pkt_count_system.monitor-master::system.physmem.port 26668 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 26668 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.monitor-master::system.physmem.port 853376 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 853376 # Cumulative packet size per connected master and slave (bytes)
-system.membus.reqLayer0.occupancy 66667328 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer0.occupancy 13338000 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.monitor.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states
-system.monitor.readBurstLengthHist::samples 1 # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::stdev nan # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::0-3 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::4-7 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::8-11 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::12-15 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::16-19 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::20-23 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::24-27 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::28-31 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::32-35 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::36-39 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::40-43 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::44-47 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::48-51 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::52-55 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::56-59 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::60-63 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::64-67 1 100.00% 100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::68-71 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::72-75 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::76-79 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::total 1 # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::samples 13333 # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::stdev 0 # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::0-3 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::4-7 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::8-11 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::12-15 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::16-19 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::20-23 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::24-27 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::28-31 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::32-35 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::36-39 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::40-43 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::44-47 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::48-51 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::52-55 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::56-59 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::60-63 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::64-67 13333 100.00% 100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::68-71 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::72-75 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::76-79 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::total 13333 # Histogram of burst lengths of transmitted packets
-system.monitor.readBandwidthHist::samples 100 # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::mean 640 # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::gmean 0 # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::stdev 6400 # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::0-4095 99 99.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::4096-8191 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::8192-12287 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::12288-16383 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::16384-20479 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::20480-24575 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::24576-28671 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::28672-32767 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::32768-36863 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::36864-40959 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::40960-45055 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::45056-49151 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::49152-53247 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::53248-57343 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::57344-61439 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::61440-65535 1 1.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::65536-69631 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::69632-73727 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::73728-77823 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::77824-81919 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::total 100 # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.averageReadBandwidth 640 0.00% 0.00% # Average read bandwidth (bytes/s)
-system.monitor.totalReadBytes 64 # Number of bytes read
-system.monitor.writeBandwidthHist::samples 100 # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::mean 8533120 # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::gmean 0 # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::stdev 42014178.909506 # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::0-1.67772e+07 96 96.00% 96.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::1.67772e+07-3.35544e+07 0 0.00% 96.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::3.35544e+07-5.03316e+07 0 0.00% 96.00% # Histogram of write bandwidth (bytes/s)
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-system.monitor.writeBandwidthHist::3.18767e+08-3.35544e+08 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
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-system.monitor.writeLatencyHist::38912-40959 13333 100.00% 100.00% # Write request-response latency
-system.monitor.writeLatencyHist::total 13333 # Write request-response latency
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-system.monitor.ittReqReq::25001-30000 13328 99.96% 99.97% # Request-to-request inter transaction time
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-system.monitor.stackdist.readLinearHist::12 0 # Reads linear distribution
-system.monitor.stackdist.readLinearHist::13 0 # Reads linear distribution
-system.monitor.stackdist.readLinearHist::14 0 # Reads linear distribution
-system.monitor.stackdist.readLinearHist::15 0 # Reads linear distribution
-system.monitor.stackdist.readLinearHist::total 0 # Reads linear distribution
-system.monitor.stackdist.readLogHist::samples 0 # Reads logarithmic distribution
-system.monitor.stackdist.writeLinearHist::samples 6677 # Writes linear distribution
-system.monitor.stackdist.writeLinearHist::mean 3330.175827 # Writes linear distribution
-system.monitor.stackdist.writeLinearHist::gmean 3328.329174 # Writes linear distribution
-system.monitor.stackdist.writeLinearHist::stdev 69.301570 # Writes linear distribution
-system.monitor.stackdist.writeLinearHist::0-255 1 0.01% 0.01% # Writes linear distribution
-system.monitor.stackdist.writeLinearHist::256-511 0 0.00% 0.01% # Writes linear distribution
-system.monitor.stackdist.writeLinearHist::512-767 1 0.01% 0.03% # Writes linear distribution
-system.monitor.stackdist.writeLinearHist::768-1023 1 0.01% 0.04% # Writes linear distribution
-system.monitor.stackdist.writeLinearHist::1024-1279 0 0.00% 0.04% # Writes linear distribution
-system.monitor.stackdist.writeLinearHist::1280-1535 0 0.00% 0.04% # Writes linear distribution
-system.monitor.stackdist.writeLinearHist::1536-1791 2 0.03% 0.07% # Writes linear distribution
-system.monitor.stackdist.writeLinearHist::1792-2047 1 0.01% 0.09% # Writes linear distribution
-system.monitor.stackdist.writeLinearHist::2048-2303 0 0.00% 0.09% # Writes linear distribution
-system.monitor.stackdist.writeLinearHist::2304-2559 0 0.00% 0.09% # Writes linear distribution
-system.monitor.stackdist.writeLinearHist::2560-2815 0 0.00% 0.09% # Writes linear distribution
-system.monitor.stackdist.writeLinearHist::2816-3071 1 0.01% 0.10% # Writes linear distribution
-system.monitor.stackdist.writeLinearHist::3072-3327 1 0.01% 0.12% # Writes linear distribution
-system.monitor.stackdist.writeLinearHist::3328-3583 6666 99.84% 99.96% # Writes linear distribution
-system.monitor.stackdist.writeLinearHist::3584-3839 2 0.03% 99.99% # Writes linear distribution
-system.monitor.stackdist.writeLinearHist::3840-4095 1 0.01% 100.00% # Writes linear distribution
-system.monitor.stackdist.writeLinearHist::total 6677 # Writes linear distribution
-system.monitor.stackdist.writeLogHist::samples 6677 # Writes logarithmic distribution
-system.monitor.stackdist.writeLogHist::7 1 # Writes logarithmic distribution
-system.monitor.stackdist.writeLogHist::9 2 # Writes logarithmic distribution
-system.monitor.stackdist.writeLogHist::10 3 # Writes logarithmic distribution
-system.monitor.stackdist.writeLogHist::11 6671 # Writes logarithmic distribution
-system.monitor.stackdist.infinity 6657 # Number of requests with infinite stack distance
-
----------- End Simulation Statistics ----------
+++ /dev/null
-# Copyright (c) 2012 ARM Limited
-# All rights reserved.
-#
-# The license below extends only to copyright in the software and shall
-# not be construed as granting a license to any other intellectual
-# property including but not limited to intellectual property relating
-# to a hardware implementation of the functionality of the software
-# licensed hereunder. You may use the software subject to the license
-# terms below provided that you ensure that this notice is replicated
-# unmodified and in its entirety in all distributions of the software,
-# modified or unmodified, in source code or in binary form.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-maxtick = 100000000000
+++ /dev/null
-# This format supports comments using the '#' symbol as the leading
-# character of the line
-#
-# The file format contains [STATE]+ [INIT] [TRANSITION]+ in any order,
-# where the states are the nodes in the graph, init describes what
-# state to start in, and transition describes the edges of the graph.
-#
-# STATE <id> <duration (ticks)> <type>
-#
-# State IDLE idles
-#
-# States LINEAR and RANDOM have additional <percent reads> <start addr>
-# <end addr> <access size (bytes)> <min period (ticks)> <max period (ticks)>
-# <data limit (bytes)>
-#
-# State TRACE plays back a pre-recorded trace once
-#
-# Addresses are expressed as decimal numbers, both in the
-# configuration and the trace file. The period in the linear and
-# random state is from a uniform random distribution over the
-# interval. If a specific value is desired, then the min and max can
-# be set to the same value.
-STATE 0 100 IDLE
-STATE 1 1000000000 LINEAR 100 0 134217728 64 30000 30000 0
-STATE 2 1000000 IDLE
-STATE 3 1000000000 RANDOM 50 0 134217728 64 28000 32000 0
-INIT 0
-TRANSITION 0 1 1
-TRANSITION 1 2 1
-TRANSITION 2 3 1
-TRANSITION 3 3 1
+++ /dev/null
-# This format supports comments using the '#' symbol as the leading
-# character of the line
-#
-# The file format contains [STATE]+ [INIT] [TRANSITION]+ in any order,
-# where the states are the nodes in the graph, init describes what
-# state to start in, and transition describes the edges of the graph.
-#
-# STATE <id> <duration (ticks)> <type>
-#
-# State IDLE idles
-#
-# States LINEAR and RANDOM have additional <percent reads> <start addr>
-# <end addr> <access size (bytes)> <min period (ticks)> <max period (ticks)>
-# <data limit (bytes)>
-#
-# State TRACE plays back a pre-recorded trace once
-#
-# Addresses are expressed as decimal numbers. The period in the linear
-# and random state is from a uniform random distribution over the
-# interval. If a specific value is desired, then the min and max can
-# be set to the same value.
-STATE 0 1000000 TRACE tgen-simple-mem.trc 100
-STATE 1 100000000 RANDOM 0 0 134217728 64 30000 30000 0
-STATE 2 1000000000 IDLE
-STATE 3 100000000 LINEAR 0 0 134217728 64 30000 30000 0
-STATE 4 1000000 IDLE
-INIT 0
-TRANSITION 0 1 1
-TRANSITION 1 2 1
-TRANSITION 2 3 0.5
-TRANSITION 2 4 0.5
-TRANSITION 3 2 1
-TRANSITION 4 4 1
+++ /dev/null
-gem5)
- Converted ASCII trace output.txt\18\80 \94¥\8d\1d\f\bè\a\10\ 1\18ç\8a\8d @\v\b \1f\10\ 4\18ïý\ 2 @
\ No newline at end of file
+++ /dev/null
-STATE 0 10000 RANDOM 100 0 134217727 256 1000 1000 0
-STATE 1 1000000 TRACE tests/quick/se/70.tgen/tgen-simple-mem.trc 100
-STATE 2 1000 IDLE
-INIT 0
-TRANSITION 0 1 1
-TRANSITION 1 2 1
-TRANSITION 2 0 1
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 250000000
-sim_freq 1000000000000
-host_tick_rate 4330044439
-host_mem_usage 91320
-host_seconds 0.06
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
-system.mem_ctrls.bytes_read::tgen 631936
-system.mem_ctrls.bytes_read::total 631936
-system.mem_ctrls.num_reads::tgen 9874
-system.mem_ctrls.num_reads::total 9874
-system.mem_ctrls.bw_read::tgen 2527744000
-system.mem_ctrls.bw_read::total 2527744000
-system.mem_ctrls.bw_total::tgen 2527744000
-system.mem_ctrls.bw_total::total 2527744000
-system.mem_ctrls.readReqs 9899
-system.mem_ctrls.writeReqs 0
-system.mem_ctrls.readBursts 9899
-system.mem_ctrls.writeBursts 0
-system.mem_ctrls.bytesReadDRAM 632064
-system.mem_ctrls.bytesReadWrQ 0
-system.mem_ctrls.bytesWritten 0
-system.mem_ctrls.bytesReadSys 633536
-system.mem_ctrls.bytesWrittenSys 0
-system.mem_ctrls.servicedByWrQ 0
-system.mem_ctrls.mergedWrBursts 0
-system.mem_ctrls.neitherReadNorWriteReqs 0
-system.mem_ctrls.perBankRdBursts::0 4843
-system.mem_ctrls.perBankRdBursts::1 0
-system.mem_ctrls.perBankRdBursts::2 0
-system.mem_ctrls.perBankRdBursts::3 0
-system.mem_ctrls.perBankRdBursts::4 0
-system.mem_ctrls.perBankRdBursts::5 0
-system.mem_ctrls.perBankRdBursts::6 0
-system.mem_ctrls.perBankRdBursts::7 0
-system.mem_ctrls.perBankRdBursts::8 0
-system.mem_ctrls.perBankRdBursts::9 0
-system.mem_ctrls.perBankRdBursts::10 0
-system.mem_ctrls.perBankRdBursts::11 0
-system.mem_ctrls.perBankRdBursts::12 0
-system.mem_ctrls.perBankRdBursts::13 0
-system.mem_ctrls.perBankRdBursts::14 0
-system.mem_ctrls.perBankRdBursts::15 0
-system.mem_ctrls.perBankRdBursts::16 5033
-system.mem_ctrls.perBankRdBursts::17 0
-system.mem_ctrls.perBankRdBursts::18 0
-system.mem_ctrls.perBankRdBursts::19 0
-system.mem_ctrls.perBankRdBursts::20 0
-system.mem_ctrls.perBankRdBursts::21 0
-system.mem_ctrls.perBankRdBursts::22 0
-system.mem_ctrls.perBankRdBursts::23 0
-system.mem_ctrls.perBankRdBursts::24 0
-system.mem_ctrls.perBankRdBursts::25 0
-system.mem_ctrls.perBankRdBursts::26 0
-system.mem_ctrls.perBankRdBursts::27 0
-system.mem_ctrls.perBankRdBursts::28 0
-system.mem_ctrls.perBankRdBursts::29 0
-system.mem_ctrls.perBankRdBursts::30 0
-system.mem_ctrls.perBankRdBursts::31 0
-system.mem_ctrls.perBankWrBursts::0 0
-system.mem_ctrls.perBankWrBursts::1 0
-system.mem_ctrls.perBankWrBursts::2 0
-system.mem_ctrls.perBankWrBursts::3 0
-system.mem_ctrls.perBankWrBursts::4 0
-system.mem_ctrls.perBankWrBursts::5 0
-system.mem_ctrls.perBankWrBursts::6 0
-system.mem_ctrls.perBankWrBursts::7 0
-system.mem_ctrls.perBankWrBursts::8 0
-system.mem_ctrls.perBankWrBursts::9 0
-system.mem_ctrls.perBankWrBursts::10 0
-system.mem_ctrls.perBankWrBursts::11 0
-system.mem_ctrls.perBankWrBursts::12 0
-system.mem_ctrls.perBankWrBursts::13 0
-system.mem_ctrls.perBankWrBursts::14 0
-system.mem_ctrls.perBankWrBursts::15 0
-system.mem_ctrls.perBankWrBursts::16 0
-system.mem_ctrls.perBankWrBursts::17 0
-system.mem_ctrls.perBankWrBursts::18 0
-system.mem_ctrls.perBankWrBursts::19 0
-system.mem_ctrls.perBankWrBursts::20 0
-system.mem_ctrls.perBankWrBursts::21 0
-system.mem_ctrls.perBankWrBursts::22 0
-system.mem_ctrls.perBankWrBursts::23 0
-system.mem_ctrls.perBankWrBursts::24 0
-system.mem_ctrls.perBankWrBursts::25 0
-system.mem_ctrls.perBankWrBursts::26 0
-system.mem_ctrls.perBankWrBursts::27 0
-system.mem_ctrls.perBankWrBursts::28 0
-system.mem_ctrls.perBankWrBursts::29 0
-system.mem_ctrls.perBankWrBursts::30 0
-system.mem_ctrls.perBankWrBursts::31 0
-system.mem_ctrls.numRdRetry 0
-system.mem_ctrls.numWrRetry 0
-system.mem_ctrls.totGap 249939941
-system.mem_ctrls.readPktSize::0 0
-system.mem_ctrls.readPktSize::1 0
-system.mem_ctrls.readPktSize::2 0
-system.mem_ctrls.readPktSize::3 0
-system.mem_ctrls.readPktSize::4 0
-system.mem_ctrls.readPktSize::5 0
-system.mem_ctrls.readPktSize::6 9899
-system.mem_ctrls.writePktSize::0 0
-system.mem_ctrls.writePktSize::1 0
-system.mem_ctrls.writePktSize::2 0
-system.mem_ctrls.writePktSize::3 0
-system.mem_ctrls.writePktSize::4 0
-system.mem_ctrls.writePktSize::5 0
-system.mem_ctrls.writePktSize::6 0
-system.mem_ctrls.rdQLenPdf::0 3
-system.mem_ctrls.rdQLenPdf::1 29
-system.mem_ctrls.rdQLenPdf::2 83
-system.mem_ctrls.rdQLenPdf::3 214
-system.mem_ctrls.rdQLenPdf::4 397
-system.mem_ctrls.rdQLenPdf::5 488
-system.mem_ctrls.rdQLenPdf::6 503
-system.mem_ctrls.rdQLenPdf::7 470
-system.mem_ctrls.rdQLenPdf::8 500
-system.mem_ctrls.rdQLenPdf::9 481
-system.mem_ctrls.rdQLenPdf::10 513
-system.mem_ctrls.rdQLenPdf::11 547
-system.mem_ctrls.rdQLenPdf::12 544
-system.mem_ctrls.rdQLenPdf::13 556
-system.mem_ctrls.rdQLenPdf::14 509
-system.mem_ctrls.rdQLenPdf::15 487
-system.mem_ctrls.rdQLenPdf::16 517
-system.mem_ctrls.rdQLenPdf::17 492
-system.mem_ctrls.rdQLenPdf::18 431
-system.mem_ctrls.rdQLenPdf::19 338
-system.mem_ctrls.rdQLenPdf::20 325
-system.mem_ctrls.rdQLenPdf::21 333
-system.mem_ctrls.rdQLenPdf::22 277
-system.mem_ctrls.rdQLenPdf::23 228
-system.mem_ctrls.rdQLenPdf::24 178
-system.mem_ctrls.rdQLenPdf::25 149
-system.mem_ctrls.rdQLenPdf::26 111
-system.mem_ctrls.rdQLenPdf::27 66
-system.mem_ctrls.rdQLenPdf::28 40
-system.mem_ctrls.rdQLenPdf::29 31
-system.mem_ctrls.rdQLenPdf::30 22
-system.mem_ctrls.rdQLenPdf::31 13
-system.mem_ctrls.rdQLenPdf::32 3
-system.mem_ctrls.rdQLenPdf::33 10
-system.mem_ctrls.rdQLenPdf::34 10
-system.mem_ctrls.rdQLenPdf::35 1
-system.mem_ctrls.rdQLenPdf::36 0
-system.mem_ctrls.rdQLenPdf::37 0
-system.mem_ctrls.rdQLenPdf::38 0
-system.mem_ctrls.rdQLenPdf::39 0
-system.mem_ctrls.rdQLenPdf::40 0
-system.mem_ctrls.rdQLenPdf::41 0
-system.mem_ctrls.rdQLenPdf::42 0
-system.mem_ctrls.rdQLenPdf::43 0
-system.mem_ctrls.rdQLenPdf::44 0
-system.mem_ctrls.rdQLenPdf::45 0
-system.mem_ctrls.rdQLenPdf::46 0
-system.mem_ctrls.rdQLenPdf::47 0
-system.mem_ctrls.rdQLenPdf::48 0
-system.mem_ctrls.rdQLenPdf::49 0
-system.mem_ctrls.rdQLenPdf::50 0
-system.mem_ctrls.rdQLenPdf::51 0
-system.mem_ctrls.rdQLenPdf::52 0
-system.mem_ctrls.rdQLenPdf::53 0
-system.mem_ctrls.rdQLenPdf::54 0
-system.mem_ctrls.rdQLenPdf::55 0
-system.mem_ctrls.rdQLenPdf::56 0
-system.mem_ctrls.rdQLenPdf::57 0
-system.mem_ctrls.rdQLenPdf::58 0
-system.mem_ctrls.rdQLenPdf::59 0
-system.mem_ctrls.rdQLenPdf::60 0
-system.mem_ctrls.rdQLenPdf::61 0
-system.mem_ctrls.rdQLenPdf::62 0
-system.mem_ctrls.rdQLenPdf::63 0
-system.mem_ctrls.wrQLenPdf::0 0
-system.mem_ctrls.wrQLenPdf::1 0
-system.mem_ctrls.wrQLenPdf::2 0
-system.mem_ctrls.wrQLenPdf::3 0
-system.mem_ctrls.wrQLenPdf::4 0
-system.mem_ctrls.wrQLenPdf::5 0
-system.mem_ctrls.wrQLenPdf::6 0
-system.mem_ctrls.wrQLenPdf::7 0
-system.mem_ctrls.wrQLenPdf::8 0
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-system.mem_ctrls.wrQLenPdf::15 0
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-system.mem_ctrls.wrQLenPdf::22 0
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-system.mem_ctrls.wrQLenPdf::24 0
-system.mem_ctrls.wrQLenPdf::25 0
-system.mem_ctrls.wrQLenPdf::26 0
-system.mem_ctrls.wrQLenPdf::27 0
-system.mem_ctrls.wrQLenPdf::28 0
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-system.mem_ctrls.wrQLenPdf::30 0
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-system.mem_ctrls.wrQLenPdf::32 0
-system.mem_ctrls.wrQLenPdf::33 0
-system.mem_ctrls.wrQLenPdf::34 0
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-system.mem_ctrls.wrQLenPdf::38 0
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-system.mem_ctrls.wrQLenPdf::62 0
-system.mem_ctrls.wrQLenPdf::63 0
-system.mem_ctrls.wrQLenPdf::64 0
-system.mem_ctrls.wrQLenPdf::65 0
-system.mem_ctrls.wrQLenPdf::66 0
-system.mem_ctrls.wrQLenPdf::67 0
-system.mem_ctrls.wrQLenPdf::68 0
-system.mem_ctrls.wrQLenPdf::69 0
-system.mem_ctrls.wrQLenPdf::70 0
-system.mem_ctrls.wrQLenPdf::71 0
-system.mem_ctrls.wrQLenPdf::72 0
-system.mem_ctrls.wrQLenPdf::73 0
-system.mem_ctrls.wrQLenPdf::74 0
-system.mem_ctrls.wrQLenPdf::75 0
-system.mem_ctrls.wrQLenPdf::76 0
-system.mem_ctrls.wrQLenPdf::77 0
-system.mem_ctrls.wrQLenPdf::78 0
-system.mem_ctrls.wrQLenPdf::79 0
-system.mem_ctrls.wrQLenPdf::80 0
-system.mem_ctrls.wrQLenPdf::81 0
-system.mem_ctrls.wrQLenPdf::82 0
-system.mem_ctrls.wrQLenPdf::83 0
-system.mem_ctrls.wrQLenPdf::84 0
-system.mem_ctrls.wrQLenPdf::85 0
-system.mem_ctrls.wrQLenPdf::86 0
-system.mem_ctrls.wrQLenPdf::87 0
-system.mem_ctrls.wrQLenPdf::88 0
-system.mem_ctrls.wrQLenPdf::89 0
-system.mem_ctrls.wrQLenPdf::90 0
-system.mem_ctrls.wrQLenPdf::91 0
-system.mem_ctrls.wrQLenPdf::92 0
-system.mem_ctrls.wrQLenPdf::93 0
-system.mem_ctrls.wrQLenPdf::94 0
-system.mem_ctrls.wrQLenPdf::95 0
-system.mem_ctrls.wrQLenPdf::96 0
-system.mem_ctrls.wrQLenPdf::97 0
-system.mem_ctrls.wrQLenPdf::98 0
-system.mem_ctrls.wrQLenPdf::99 0
-system.mem_ctrls.wrQLenPdf::100 0
-system.mem_ctrls.wrQLenPdf::101 0
-system.mem_ctrls.wrQLenPdf::102 0
-system.mem_ctrls.wrQLenPdf::103 0
-system.mem_ctrls.wrQLenPdf::104 0
-system.mem_ctrls.wrQLenPdf::105 0
-system.mem_ctrls.wrQLenPdf::106 0
-system.mem_ctrls.wrQLenPdf::107 0
-system.mem_ctrls.wrQLenPdf::108 0
-system.mem_ctrls.wrQLenPdf::109 0
-system.mem_ctrls.wrQLenPdf::110 0
-system.mem_ctrls.wrQLenPdf::111 0
-system.mem_ctrls.wrQLenPdf::112 0
-system.mem_ctrls.wrQLenPdf::113 0
-system.mem_ctrls.wrQLenPdf::114 0
-system.mem_ctrls.wrQLenPdf::115 0
-system.mem_ctrls.wrQLenPdf::116 0
-system.mem_ctrls.wrQLenPdf::117 0
-system.mem_ctrls.wrQLenPdf::118 0
-system.mem_ctrls.wrQLenPdf::119 0
-system.mem_ctrls.wrQLenPdf::120 0
-system.mem_ctrls.wrQLenPdf::121 0
-system.mem_ctrls.wrQLenPdf::122 0
-system.mem_ctrls.wrQLenPdf::123 0
-system.mem_ctrls.wrQLenPdf::124 0
-system.mem_ctrls.wrQLenPdf::125 0
-system.mem_ctrls.wrQLenPdf::126 0
-system.mem_ctrls.wrQLenPdf::127 0
-system.mem_ctrls.bytesPerActivate::samples 9829
-system.mem_ctrls.bytesPerActivate::mean 64.306033
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 500000000
-sim_freq 1000000000000
-host_tick_rate 6701298261
-host_mem_usage 91320
-host_seconds 0.04
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
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-system.mem_ctrls.bytes_read::total 636096
-system.mem_ctrls.num_reads::tgen 9939
-system.mem_ctrls.num_reads::total 9939
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-system.mem_ctrls.bw_read::total 2544384000
-system.mem_ctrls.bw_total::tgen 2544384000
-system.mem_ctrls.bw_total::total 2544384000
-system.mem_ctrls.readReqs 9916
-system.mem_ctrls.writeReqs 0
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-system.mem_ctrls.writeBursts 0
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
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-final_tick 750000000
-sim_freq 1000000000000
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-system.monitor.ittReqReq::35001-40000 1089 10.94% 83.88%
-system.monitor.ittReqReq::40001-45000 1122 11.27% 95.15%
-system.monitor.ittReqReq::45001-50000 483 4.85% 100.00%
-system.monitor.ittReqReq::50001-55000 0 0.00% 100.00%
-system.monitor.ittReqReq::55001-60000 0 0.00% 100.00%
-system.monitor.ittReqReq::60001-65000 0 0.00% 100.00%
-system.monitor.ittReqReq::65001-70000 0 0.00% 100.00%
-system.monitor.ittReqReq::70001-75000 0 0.00% 100.00%
-system.monitor.ittReqReq::75001-80000 0 0.00% 100.00%
-system.monitor.ittReqReq::80001-85000 0 0.00% 100.00%
-system.monitor.ittReqReq::85001-90000 0 0.00% 100.00%
-system.monitor.ittReqReq::90001-95000 0 0.00% 100.00%
-system.monitor.ittReqReq::95001-100000 0 0.00% 100.00%
-system.monitor.ittReqReq::overflows 0 0.00% 100.00%
-system.monitor.ittReqReq::min_value 3332
-system.monitor.ittReqReq::max_value 47612
-system.monitor.ittReqReq::total 9958
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-system.tgen.pwrStateResidencyTicks::UNDEFINED 250000000
-system.tgen.numPackets 9958
-system.tgen.numRetries 0
-system.tgen.retryTicks 0
-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 1000000000
-sim_freq 1000000000000
-host_tick_rate 6017522496
-host_mem_usage 91320
-host_seconds 0.04
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
-system.mem_ctrls.bytes_read::tgen 636992
-system.mem_ctrls.bytes_read::total 636992
-system.mem_ctrls.num_reads::tgen 9953
-system.mem_ctrls.num_reads::total 9953
-system.mem_ctrls.bw_read::tgen 2547968000
-system.mem_ctrls.bw_read::total 2547968000
-system.mem_ctrls.bw_total::tgen 2547968000
-system.mem_ctrls.bw_total::total 2547968000
-system.mem_ctrls.readReqs 9952
-system.mem_ctrls.writeReqs 0
-system.mem_ctrls.readBursts 9952
-system.mem_ctrls.writeBursts 0
-system.mem_ctrls.bytesReadDRAM 636928
-system.mem_ctrls.bytesReadWrQ 0
-system.mem_ctrls.bytesWritten 0
-system.mem_ctrls.bytesReadSys 636928
-system.mem_ctrls.bytesWrittenSys 0
-system.mem_ctrls.servicedByWrQ 0
-system.mem_ctrls.mergedWrBursts 0
-system.mem_ctrls.neitherReadNorWriteReqs 0
-system.mem_ctrls.perBankRdBursts::0 597
-system.mem_ctrls.perBankRdBursts::1 657
-system.mem_ctrls.perBankRdBursts::2 608
-system.mem_ctrls.perBankRdBursts::3 642
-system.mem_ctrls.perBankRdBursts::4 640
-system.mem_ctrls.perBankRdBursts::5 603
-system.mem_ctrls.perBankRdBursts::6 597
-system.mem_ctrls.perBankRdBursts::7 642
-system.mem_ctrls.perBankRdBursts::8 0
-system.mem_ctrls.perBankRdBursts::9 0
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-system.mem_ctrls.perBankRdBursts::15 0
-system.mem_ctrls.perBankRdBursts::16 574
-system.mem_ctrls.perBankRdBursts::17 639
-system.mem_ctrls.perBankRdBursts::18 599
-system.mem_ctrls.perBankRdBursts::19 616
-system.mem_ctrls.perBankRdBursts::20 585
-system.mem_ctrls.perBankRdBursts::21 636
-system.mem_ctrls.perBankRdBursts::22 647
-system.mem_ctrls.perBankRdBursts::23 670
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-system.mem_ctrls.rdQLenPdf::0 2273
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-system.mem_ctrls.totQLat 302707121
-system.mem_ctrls.totMemAccLat 476787505
-system.mem_ctrls.totBusLat 33160064
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-system.mem_ctrls.avgBusLat 3332.00
-system.mem_ctrls.avgMemAccLat 47908.71
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-system.mem_ctrls.avgRdBWSys 2547.71
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-system.mem_ctrls.peakBW 19207.00
-system.mem_ctrls.busUtil 13.26
-system.mem_ctrls.busUtilRead 13.26
-system.mem_ctrls.busUtilWrite 0.00
-system.mem_ctrls.avgRdQLen 2.50
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-system.mem_ctrls.pageHitRate 0.00
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 1250000000
-sim_freq 1000000000000
-host_tick_rate 7152164766
-host_mem_usage 91320
-host_seconds 0.04
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
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-system.mem_ctrls.num_reads::total 9877
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
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-final_tick 1500000000
-sim_freq 1000000000000
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-host_seconds 0.03
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-system.tgen.pwrStateResidencyTicks::UNDEFINED 250000000
-system.tgen.numPackets 9984
-system.tgen.numRetries 0
-system.tgen.retryTicks 0
-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 1750000000
-sim_freq 1000000000000
-host_tick_rate 6096135521
-host_mem_usage 91320
-host_seconds 0.04
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
-system.mem_ctrls.bytes_read::tgen 630336
-system.mem_ctrls.bytes_read::total 630336
-system.mem_ctrls.num_reads::tgen 9849
-system.mem_ctrls.num_reads::total 9849
-system.mem_ctrls.bw_read::tgen 2521344000
-system.mem_ctrls.bw_read::total 2521344000
-system.mem_ctrls.bw_total::tgen 2521344000
-system.mem_ctrls.bw_total::total 2521344000
-system.mem_ctrls.readReqs 9848
-system.mem_ctrls.writeReqs 0
-system.mem_ctrls.readBursts 9848
-system.mem_ctrls.writeBursts 0
-system.mem_ctrls.bytesReadDRAM 630400
-system.mem_ctrls.bytesReadWrQ 0
-system.mem_ctrls.bytesWritten 0
-system.mem_ctrls.bytesReadSys 630272
-system.mem_ctrls.bytesWrittenSys 0
-system.mem_ctrls.servicedByWrQ 0
-system.mem_ctrls.mergedWrBursts 0
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-system.mem_ctrls.perBankRdBursts::0 320
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-system.mem_ctrls.perBankRdBursts::4 309
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-system.mem_ctrls.perBankRdBursts::6 300
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-system.mem_ctrls.totQLat 278304455
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-system.mem_ctrls.avgBusLat 3332.68
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-system.mem_ctrls.busUtil 13.13
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-system.mem_ctrls.avgRdQLen 2.38
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-system.mem_ctrls_0.averagePower 1115.329562
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 2000000000
-sim_freq 1000000000000
-host_tick_rate 7143372486
-host_mem_usage 91320
-host_seconds 0.04
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
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-system.mem_ctrls.num_reads::tgen 9925
-system.mem_ctrls.num_reads::total 9925
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-system.mem_ctrls.bw_read::total 2540800000
-system.mem_ctrls.bw_total::tgen 2540800000
-system.mem_ctrls.bw_total::total 2540800000
-system.mem_ctrls.readReqs 9924
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 2250000000
-sim_freq 1000000000000
-host_tick_rate 7830382636
-host_mem_usage 91320
-host_seconds 0.03
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
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-system.mem_ctrls.bw_total::total 2531328000
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-system.monitor.writeTransHist::total 0
-system.tgen.pwrStateResidencyTicks::UNDEFINED 250000000
-system.tgen.numPackets 9890
-system.tgen.numRetries 0
-system.tgen.retryTicks 0
-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 2500000000
-sim_freq 1000000000000
-host_tick_rate 66020493289
-host_mem_usage 91320
-host_seconds 0.00
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
-system.mem_ctrls.bytes_read::tgen 33344
-system.mem_ctrls.bytes_read::total 33344
-system.mem_ctrls.num_reads::tgen 521
-system.mem_ctrls.num_reads::total 521
-system.mem_ctrls.bw_read::tgen 133376000
-system.mem_ctrls.bw_read::total 133376000
-system.mem_ctrls.bw_total::tgen 133376000
-system.mem_ctrls.bw_total::total 133376000
-system.mem_ctrls.readReqs 517
-system.mem_ctrls.writeReqs 0
-system.mem_ctrls.readBursts 517
-system.mem_ctrls.writeBursts 0
-system.mem_ctrls.bytesReadDRAM 33152
-system.mem_ctrls.bytesReadWrQ 0
-system.mem_ctrls.bytesWritten 0
-system.mem_ctrls.bytesReadSys 33088
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-system.mem_ctrls.servicedByWrQ 0
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 2750000000
-sim_freq 1000000000000
-host_tick_rate 69292194096
-host_mem_usage 91320
-host_seconds 0.00
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-system.mem_ctrls.bytes_read::total 33984
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-system.mem_ctrls.bw_total::tgen 135936000
-system.mem_ctrls.bw_total::total 135936000
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-system.monitor.ittReadRead::85001-90000 2 0.38% 10.73%
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-system.monitor.ittReadRead::95001-100000 1 0.19% 11.30%
-system.monitor.ittReadRead::overflows 471 88.70% 100.00%
-system.monitor.ittReadRead::min_value 4925
-system.monitor.ittReadRead::max_value 936922
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-system.tgen.pwrStateResidencyTicks::UNDEFINED 250000000
-system.tgen.numPackets 531
-system.tgen.numRetries 0
-system.tgen.retryTicks 0
-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 3000000000
-sim_freq 1000000000000
-host_tick_rate 72324674141
-host_mem_usage 91320
-host_seconds 0.00
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
-system.mem_ctrls.bytes_read::tgen 34432
-system.mem_ctrls.bytes_read::total 34432
-system.mem_ctrls.num_reads::tgen 538
-system.mem_ctrls.num_reads::total 538
-system.mem_ctrls.bw_read::tgen 137728000
-system.mem_ctrls.bw_read::total 137728000
-system.mem_ctrls.bw_total::tgen 137728000
-system.mem_ctrls.bw_total::total 137728000
-system.mem_ctrls.readReqs 538
-system.mem_ctrls.writeReqs 0
-system.mem_ctrls.readBursts 538
-system.mem_ctrls.writeBursts 0
-system.mem_ctrls.bytesReadDRAM 34432
-system.mem_ctrls.bytesReadWrQ 0
-system.mem_ctrls.bytesWritten 0
-system.mem_ctrls.bytesReadSys 34432
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-system.tgen.pwrStateResidencyTicks::UNDEFINED 250000000
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-system.tgen.retryTicks 0
-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 3250000000
-sim_freq 1000000000000
-host_tick_rate 65111406919
-host_mem_usage 91320
-host_seconds 0.00
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
-system.mem_ctrls.bytes_read::tgen 34112
-system.mem_ctrls.bytes_read::total 34112
-system.mem_ctrls.num_reads::tgen 533
-system.mem_ctrls.num_reads::total 533
-system.mem_ctrls.bw_read::tgen 136448000
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 3500000000
-sim_freq 1000000000000
-host_tick_rate 68941211898
-host_mem_usage 91320
-host_seconds 0.00
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-system.clk_domain.clock 500
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-system.mem_ctrls.bw_read::tgen 136704000
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-system.mem_ctrls.bw_total::tgen 136704000
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-system.monitor.ittReqReq::45001-50000 0 0.00% 2.43%
-system.monitor.ittReqReq::50001-55000 1 0.19% 2.62%
-system.monitor.ittReqReq::55001-60000 4 0.75% 3.37%
-system.monitor.ittReqReq::60001-65000 6 1.12% 4.49%
-system.monitor.ittReqReq::65001-70000 2 0.37% 4.87%
-system.monitor.ittReqReq::70001-75000 1 0.19% 5.06%
-system.monitor.ittReqReq::75001-80000 4 0.75% 5.81%
-system.monitor.ittReqReq::80001-85000 3 0.56% 6.37%
-system.monitor.ittReqReq::85001-90000 5 0.94% 7.30%
-system.monitor.ittReqReq::90001-95000 5 0.94% 8.24%
-system.monitor.ittReqReq::95001-100000 5 0.94% 9.18%
-system.monitor.ittReqReq::overflows 485 90.82% 100.00%
-system.monitor.ittReqReq::min_value 6829
-system.monitor.ittReqReq::max_value 1009247
-system.monitor.ittReqReq::total 534
-system.monitor.outstandingReadsHist::samples 0
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-system.monitor.writeTransHist::samples 0
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-system.monitor.writeTransHist::19 0
-system.monitor.writeTransHist::total 0
-system.tgen.pwrStateResidencyTicks::UNDEFINED 250000000
-system.tgen.numPackets 534
-system.tgen.numRetries 0
-system.tgen.retryTicks 0
-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 3750000000
-sim_freq 1000000000000
-host_tick_rate 75668332984
-host_mem_usage 91320
-host_seconds 0.00
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
-system.mem_ctrls.bytes_read::tgen 34176
-system.mem_ctrls.bytes_read::total 34176
-system.mem_ctrls.num_reads::tgen 534
-system.mem_ctrls.num_reads::total 534
-system.mem_ctrls.bw_read::tgen 136704000
-system.mem_ctrls.bw_read::total 136704000
-system.mem_ctrls.bw_total::tgen 136704000
-system.mem_ctrls.bw_total::total 136704000
-system.mem_ctrls.readReqs 534
-system.mem_ctrls.writeReqs 0
-system.mem_ctrls.readBursts 534
-system.mem_ctrls.writeBursts 0
-system.mem_ctrls.bytesReadDRAM 34176
-system.mem_ctrls.bytesReadWrQ 0
-system.mem_ctrls.bytesWritten 0
-system.mem_ctrls.bytesReadSys 34176
-system.mem_ctrls.bytesWrittenSys 0
-system.mem_ctrls.servicedByWrQ 0
-system.mem_ctrls.mergedWrBursts 0
-system.mem_ctrls.neitherReadNorWriteReqs 0
-system.mem_ctrls.perBankRdBursts::0 24
-system.mem_ctrls.perBankRdBursts::1 40
-system.mem_ctrls.perBankRdBursts::2 40
-system.mem_ctrls.perBankRdBursts::3 16
-system.mem_ctrls.perBankRdBursts::4 24
-system.mem_ctrls.perBankRdBursts::5 48
-system.mem_ctrls.perBankRdBursts::6 32
-system.mem_ctrls.perBankRdBursts::7 48
-system.mem_ctrls.perBankRdBursts::8 0
-system.mem_ctrls.perBankRdBursts::9 0
-system.mem_ctrls.perBankRdBursts::10 0
-system.mem_ctrls.perBankRdBursts::11 0
-system.mem_ctrls.perBankRdBursts::12 0
-system.mem_ctrls.perBankRdBursts::13 0
-system.mem_ctrls.perBankRdBursts::14 0
-system.mem_ctrls.perBankRdBursts::15 0
-system.mem_ctrls.perBankRdBursts::16 24
-system.mem_ctrls.perBankRdBursts::17 48
-system.mem_ctrls.perBankRdBursts::18 16
-system.mem_ctrls.perBankRdBursts::19 32
-system.mem_ctrls.perBankRdBursts::20 32
-system.mem_ctrls.perBankRdBursts::21 40
-system.mem_ctrls.perBankRdBursts::22 62
-system.mem_ctrls.perBankRdBursts::23 8
-system.mem_ctrls.perBankRdBursts::24 0
-system.mem_ctrls.perBankRdBursts::25 0
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-system.mem_ctrls.perBankRdBursts::27 0
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-system.mem_ctrls.perBankRdBursts::31 0
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-system.mem_ctrls.numRdRetry 0
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-system.mem_ctrls.totGap 249956131
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-system.mem_ctrls.bytesPerActivate::samples 512
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-system.mem_ctrls.bytesPerActivate::gmean 65.786802
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-system.mem_ctrls.bytesPerActivate::64-79 494 96.48% 96.48%
-system.mem_ctrls.bytesPerActivate::128-143 14 2.73% 99.22%
-system.mem_ctrls.bytesPerActivate::192-207 4 0.78% 100.00%
-system.mem_ctrls.bytesPerActivate::total 512
-system.mem_ctrls.totQLat 36140785
-system.mem_ctrls.totMemAccLat 45481513
-system.mem_ctrls.totBusLat 1779288
-system.mem_ctrls.avgQLat 67679.37
-system.mem_ctrls.avgBusLat 3332.00
-system.mem_ctrls.avgMemAccLat 85171.37
-system.mem_ctrls.avgRdBW 136.70
-system.mem_ctrls.avgWrBW 0.00
-system.mem_ctrls.avgRdBWSys 136.70
-system.mem_ctrls.avgWrBWSys 0.00
-system.mem_ctrls.peakBW 19207.00
-system.mem_ctrls.busUtil 0.71
-system.mem_ctrls.busUtilRead 0.71
-system.mem_ctrls.busUtilWrite 0.00
-system.mem_ctrls.avgRdQLen 1.08
-system.mem_ctrls.avgWrQLen 0.00
-system.mem_ctrls.readRowHits 22
-system.mem_ctrls.writeRowHits 0
-system.mem_ctrls.readRowHitRate 4.12
-system.mem_ctrls.writeRowHitRate nan
-system.mem_ctrls.avgGap 468082.64
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 4000000000
-sim_freq 1000000000000
-host_tick_rate 65400495631
-host_mem_usage 91320
-host_seconds 0.00
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
-system.mem_ctrls.bytes_read::tgen 33984
-system.mem_ctrls.bytes_read::total 33984
-system.mem_ctrls.num_reads::tgen 531
-system.mem_ctrls.num_reads::total 531
-system.mem_ctrls.bw_read::tgen 135936000
-system.mem_ctrls.bw_read::total 135936000
-system.mem_ctrls.bw_total::tgen 135936000
-system.mem_ctrls.bw_total::total 135936000
-system.mem_ctrls.readReqs 533
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 4250000000
-sim_freq 1000000000000
-host_tick_rate 71769311615
-host_mem_usage 91320
-host_seconds 0.00
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
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-system.mem_ctrls.bw_total::tgen 134656000
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-system.mem_ctrls.readReqs 524
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-system.monitor.writeTransHist::total 0
-system.tgen.pwrStateResidencyTicks::UNDEFINED 250000000
-system.tgen.numPackets 524
-system.tgen.numRetries 0
-system.tgen.retryTicks 0
-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 4500000000
-sim_freq 1000000000000
-host_tick_rate 72933289379
-host_mem_usage 91320
-host_seconds 0.00
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
-system.mem_ctrls.bytes_read::tgen 33152
-system.mem_ctrls.bytes_read::total 33152
-system.mem_ctrls.num_reads::tgen 518
-system.mem_ctrls.num_reads::total 518
-system.mem_ctrls.bw_read::tgen 132608000
-system.mem_ctrls.bw_read::total 132608000
-system.mem_ctrls.bw_total::tgen 132608000
-system.mem_ctrls.bw_total::total 132608000
-system.mem_ctrls.readReqs 518
-system.mem_ctrls.writeReqs 0
-system.mem_ctrls.readBursts 518
-system.mem_ctrls.writeBursts 0
-system.mem_ctrls.bytesReadDRAM 33152
-system.mem_ctrls.bytesReadWrQ 0
-system.mem_ctrls.bytesWritten 0
-system.mem_ctrls.bytesReadSys 33152
-system.mem_ctrls.bytesWrittenSys 0
-system.mem_ctrls.servicedByWrQ 0
-system.mem_ctrls.mergedWrBursts 0
-system.mem_ctrls.neitherReadNorWriteReqs 0
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-system.mem_ctrls.perBankRdBursts::1 8
-system.mem_ctrls.perBankRdBursts::2 8
-system.mem_ctrls.perBankRdBursts::3 22
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-system.mem_ctrls.perBankRdBursts::5 8
-system.mem_ctrls.perBankRdBursts::6 24
-system.mem_ctrls.perBankRdBursts::7 16
-system.mem_ctrls.perBankRdBursts::8 32
-system.mem_ctrls.perBankRdBursts::9 16
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-system.mem_ctrls.perBankRdBursts::13 24
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-system.mem_ctrls.perBankRdBursts::20 32
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-system.mem_ctrls.perBankRdBursts::25 32
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-system.mem_ctrls.numRdRetry 0
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-system.mem_ctrls.totGap 250499522
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-system.mem_ctrls.bytesPerActivate::256-287 1 0.21% 100.00%
-system.mem_ctrls.bytesPerActivate::total 473
-system.mem_ctrls.totQLat 46867594
-system.mem_ctrls.totMemAccLat 55928450
-system.mem_ctrls.totBusLat 1725976
-system.mem_ctrls.avgQLat 90477.98
-system.mem_ctrls.avgBusLat 3332.00
-system.mem_ctrls.avgMemAccLat 107969.98
-system.mem_ctrls.avgRdBW 132.61
-system.mem_ctrls.avgWrBW 0.00
-system.mem_ctrls.avgRdBWSys 132.61
-system.mem_ctrls.avgWrBWSys 0.00
-system.mem_ctrls.peakBW 19207.00
-system.mem_ctrls.busUtil 0.69
-system.mem_ctrls.busUtilRead 0.69
-system.mem_ctrls.busUtilWrite 0.00
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-system.mem_ctrls.avgWrQLen 0.00
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-system.mem_ctrls.readRowHitRate 8.69
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-system.mem_ctrls.pageHitRate 8.69
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-system.mem_ctrls_0.readEnergy 1203006.604800
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-system.mem_ctrls_0.preBackEnergy 7153457.472000
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-system.mem_ctrls_0.averagePower 856.841494
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-system.mem_ctrls_1.memoryStateTime::ACT 9693600
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 0
-system.pwrStateResidencyTicks::UNDEFINED 250000000
-system.membus.pwrStateResidencyTicks::UNDEFINED 250000000
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 4750000000
-sim_freq 1000000000000
-host_tick_rate 132881606741
-host_mem_usage 91320
-host_seconds 0.00
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
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-system.mem_ctrls.bytes_read::total 6976
-system.mem_ctrls.num_reads::tgen 109
-system.mem_ctrls.num_reads::total 109
-system.mem_ctrls.bw_read::tgen 27904000
-system.mem_ctrls.bw_read::total 27904000
-system.mem_ctrls.bw_total::tgen 27904000
-system.mem_ctrls.bw_total::total 27904000
-system.mem_ctrls.readReqs 109
-system.mem_ctrls.writeReqs 0
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-system.mem_ctrls.bytesReadDRAM 6976
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-system.mem_ctrls.bytesReadSys 6976
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 5000000000
-sim_freq 1000000000000
-host_tick_rate 168672406476
-host_mem_usage 91320
-host_seconds 0.00
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
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-system.mem_ctrls.bytes_read::total 6464
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-system.mem_ctrls.bw_total::tgen 25856000
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 5250000000
-sim_freq 1000000000000
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
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-sim_ticks 250000000
-final_tick 5500000000
-sim_freq 1000000000000
-host_tick_rate 139152737941
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-system.monitor.ittReqReq::25001-30000 1 0.93% 0.93%
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-system.monitor.ittReqReq::min_value 28010
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-system.tgen.pwrStateResidencyTicks::UNDEFINED 250000000
-system.tgen.numPackets 107
-system.tgen.numRetries 0
-system.tgen.retryTicks 0
-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 5750000000
-sim_freq 1000000000000
-host_tick_rate 161132828236
-host_mem_usage 91320
-host_seconds 0.00
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
-system.mem_ctrls.bytes_read::tgen 6784
-system.mem_ctrls.bytes_read::total 6784
-system.mem_ctrls.num_reads::tgen 106
-system.mem_ctrls.num_reads::total 106
-system.mem_ctrls.bw_read::tgen 27136000
-system.mem_ctrls.bw_read::total 27136000
-system.mem_ctrls.bw_total::tgen 27136000
-system.mem_ctrls.bw_total::total 27136000
-system.mem_ctrls.readReqs 106
-system.mem_ctrls.writeReqs 0
-system.mem_ctrls.readBursts 106
-system.mem_ctrls.writeBursts 0
-system.mem_ctrls.bytesReadDRAM 6784
-system.mem_ctrls.bytesReadWrQ 0
-system.mem_ctrls.bytesWritten 0
-system.mem_ctrls.bytesReadSys 6784
-system.mem_ctrls.bytesWrittenSys 0
-system.mem_ctrls.servicedByWrQ 0
-system.mem_ctrls.mergedWrBursts 0
-system.mem_ctrls.neitherReadNorWriteReqs 0
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-system.mem_ctrls.perBankRdBursts::5 12
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-system.mem_ctrls.perBankRdBursts::7 2
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-system.mem_ctrls.totQLat 22242055
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-system.mem_ctrls.avgQLat 209830.71
-system.mem_ctrls.avgBusLat 3332.00
-system.mem_ctrls.avgMemAccLat 227322.71
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-system.mem_ctrls.avgRdBWSys 27.14
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 6000000000
-sim_freq 1000000000000
-host_tick_rate 176603061308
-host_mem_usage 91320
-host_seconds 0.00
-system.clk_domain.voltage_domain.voltage 1
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-system.mem_ctrls.num_reads::total 98
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-system.mem_ctrls.bw_total::tgen 25088000
-system.mem_ctrls.bw_total::total 25088000
-system.mem_ctrls.readReqs 98
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
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-final_tick 6250000000
-sim_freq 1000000000000
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-system.monitor.writeTransHist::total 0
-system.tgen.pwrStateResidencyTicks::UNDEFINED 250000000
-system.tgen.numPackets 103
-system.tgen.numRetries 0
-system.tgen.retryTicks 0
-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 6500000000
-sim_freq 1000000000000
-host_tick_rate 157766530777
-host_mem_usage 91320
-host_seconds 0.00
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
-system.mem_ctrls.bytes_read::tgen 7424
-system.mem_ctrls.bytes_read::total 7424
-system.mem_ctrls.num_reads::tgen 116
-system.mem_ctrls.num_reads::total 116
-system.mem_ctrls.bw_read::tgen 29696000
-system.mem_ctrls.bw_read::total 29696000
-system.mem_ctrls.bw_total::tgen 29696000
-system.mem_ctrls.bw_total::total 29696000
-system.mem_ctrls.readReqs 116
-system.mem_ctrls.writeReqs 0
-system.mem_ctrls.readBursts 116
-system.mem_ctrls.writeBursts 0
-system.mem_ctrls.bytesReadDRAM 7424
-system.mem_ctrls.bytesReadWrQ 0
-system.mem_ctrls.bytesWritten 0
-system.mem_ctrls.bytesReadSys 7424
-system.mem_ctrls.bytesWrittenSys 0
-system.mem_ctrls.servicedByWrQ 0
-system.mem_ctrls.mergedWrBursts 0
-system.mem_ctrls.neitherReadNorWriteReqs 0
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-system.mem_ctrls.perBankRdBursts::1 8
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-system.mem_ctrls.perBankRdBursts::7 8
-system.mem_ctrls.perBankRdBursts::8 12
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-system.mem_ctrls.perBankRdBursts::24 8
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-system.mem_ctrls.numRdRetry 0
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-system.mem_ctrls.totGap 249142190
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-system.mem_ctrls.avgMemAccLat 225659.75
-system.mem_ctrls.avgRdBW 29.70
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-system.mem_ctrls.avgWrQLen 0.00
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-system.pwrStateResidencyTicks::UNDEFINED 250000000
-system.membus.pwrStateResidencyTicks::UNDEFINED 250000000
-system.membus.trans_dist::ReadReq 116
-system.membus.trans_dist::ReadResp 116
-system.membus.pkt_count_system.monitor-master::system.mem_ctrls.port 232
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 6750000000
-sim_freq 1000000000000
-host_tick_rate 171049993808
-host_mem_usage 91320
-host_seconds 0.00
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
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-final_tick 6800000000
-sim_freq 1000000000000
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-system.mem_ctrls.busUtilWrite 0.00
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-system.mem_ctrls_0.actPowerDownEnergy 0
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-system.mem_ctrls_0.selfRefreshEnergy 29213282.011200
-system.mem_ctrls_0.totalEnergy 31368095.740800
-system.mem_ctrls_0.averagePower 627.361915
-system.mem_ctrls_0.totalIdleTime 981375
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-system.mem_ctrls_0.memoryStateTime::REF 356000
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-system.mem_ctrls_0.memoryStateTime::ACT 0
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 0
-system.mem_ctrls_1.actEnergy 0
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-system.mem_ctrls_1.selfRefreshEnergy 28799995.392000
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-system.mem_ctrls_1.averagePower 575.999908
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-system.mem_ctrls_1.memoryStateTime::SREF 50000000
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-system.pwrStateResidencyTicks::UNDEFINED 50000000
-system.membus.pwrStateResidencyTicks::UNDEFINED 50000000
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-system.tgen.pwrStateResidencyTicks::UNDEFINED 50000000
-system.tgen.numPackets 0
-system.tgen.numRetries 0
-system.tgen.retryTicks 0
-
----------- End Simulation Statistics ----------
+++ /dev/null
-# Copyright (c) 2017 ARM Limited
-# All rights reserved.
-#
-# The license below extends only to copyright in the software and shall
-# not be construed as granting a license to any other intellectual
-# property including but not limited to intellectual property relating
-# to a hardware implementation of the functionality of the software
-# licensed hereunder. You may use the software subject to the license
-# terms below provided that you ensure that this notice is replicated
-# unmodified and in its entirety in all distributions of the software,
-# modified or unmodified, in source code or in binary form.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-page_policy = 'close_adaptive'
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 250000000
-sim_freq 1000000000000
-host_tick_rate 3680764416
-host_mem_usage 91320
-host_seconds 0.07
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
-system.mem_ctrls.bytes_read::tgen 631872
-system.mem_ctrls.bytes_read::total 631872
-system.mem_ctrls.num_reads::tgen 9873
-system.mem_ctrls.num_reads::total 9873
-system.mem_ctrls.bw_read::tgen 2527488000
-system.mem_ctrls.bw_read::total 2527488000
-system.mem_ctrls.bw_total::tgen 2527488000
-system.mem_ctrls.bw_total::total 2527488000
-system.mem_ctrls.readReqs 9899
-system.mem_ctrls.writeReqs 0
-system.mem_ctrls.readBursts 9899
-system.mem_ctrls.writeBursts 0
-system.mem_ctrls.bytesReadDRAM 632064
-system.mem_ctrls.bytesReadWrQ 0
-system.mem_ctrls.bytesWritten 0
-system.mem_ctrls.bytesReadSys 633536
-system.mem_ctrls.bytesWrittenSys 0
-system.mem_ctrls.servicedByWrQ 0
-system.mem_ctrls.mergedWrBursts 0
-system.mem_ctrls.neitherReadNorWriteReqs 0
-system.mem_ctrls.perBankRdBursts::0 4843
-system.mem_ctrls.perBankRdBursts::1 0
-system.mem_ctrls.perBankRdBursts::2 0
-system.mem_ctrls.perBankRdBursts::3 0
-system.mem_ctrls.perBankRdBursts::4 0
-system.mem_ctrls.perBankRdBursts::5 0
-system.mem_ctrls.perBankRdBursts::6 0
-system.mem_ctrls.perBankRdBursts::7 0
-system.mem_ctrls.perBankRdBursts::8 0
-system.mem_ctrls.perBankRdBursts::9 0
-system.mem_ctrls.perBankRdBursts::10 0
-system.mem_ctrls.perBankRdBursts::11 0
-system.mem_ctrls.perBankRdBursts::12 0
-system.mem_ctrls.perBankRdBursts::13 0
-system.mem_ctrls.perBankRdBursts::14 0
-system.mem_ctrls.perBankRdBursts::15 0
-system.mem_ctrls.perBankRdBursts::16 5033
-system.mem_ctrls.perBankRdBursts::17 0
-system.mem_ctrls.perBankRdBursts::18 0
-system.mem_ctrls.perBankRdBursts::19 0
-system.mem_ctrls.perBankRdBursts::20 0
-system.mem_ctrls.perBankRdBursts::21 0
-system.mem_ctrls.perBankRdBursts::22 0
-system.mem_ctrls.perBankRdBursts::23 0
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 500000000
-sim_freq 1000000000000
-host_tick_rate 6467216335
-host_mem_usage 91320
-host_seconds 0.04
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
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-system.tgen.pwrStateResidencyTicks::UNDEFINED 250000000
-system.tgen.numPackets 9916
-system.tgen.numRetries 0
-system.tgen.retryTicks 0
-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 750000000
-sim_freq 1000000000000
-host_tick_rate 7917062876
-host_mem_usage 91320
-host_seconds 0.03
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
-system.mem_ctrls.bytes_read::tgen 637376
-system.mem_ctrls.bytes_read::total 637376
-system.mem_ctrls.num_reads::tgen 9959
-system.mem_ctrls.num_reads::total 9959
-system.mem_ctrls.bw_read::tgen 2549504000
-system.mem_ctrls.bw_read::total 2549504000
-system.mem_ctrls.bw_total::tgen 2549504000
-system.mem_ctrls.bw_total::total 2549504000
-system.mem_ctrls.readReqs 9958
-system.mem_ctrls.writeReqs 0
-system.mem_ctrls.readBursts 9958
-system.mem_ctrls.writeBursts 0
-system.mem_ctrls.bytesReadDRAM 637312
-system.mem_ctrls.bytesReadWrQ 0
-system.mem_ctrls.bytesWritten 0
-system.mem_ctrls.bytesReadSys 637312
-system.mem_ctrls.bytesWrittenSys 0
-system.mem_ctrls.servicedByWrQ 0
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-system.mem_ctrls.perBankRdBursts::0 4920
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-system.mem_ctrls.bytesPerActivate::512-575 1211 94.83% 100.00%
-system.mem_ctrls.bytesPerActivate::total 1277
-system.mem_ctrls.totQLat 226783560
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-system.mem_ctrls.totBusLat 33180056
-system.mem_ctrls.avgQLat 22774.01
-system.mem_ctrls.avgBusLat 3332.00
-system.mem_ctrls.avgMemAccLat 40266.01
-system.mem_ctrls.avgRdBW 2549.25
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-system.mem_ctrls.avgRdBWSys 2549.25
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-system.mem_ctrls.busUtil 13.27
-system.mem_ctrls.busUtilRead 13.27
-system.mem_ctrls.busUtilWrite 0.00
-system.mem_ctrls.avgRdQLen 2.24
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-system.mem_ctrls.readRowHits 8681
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-system.mem_ctrls_0.actEnergy 1967932.512000
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-system.mem_ctrls_0.actPowerDownEnergy 88169518.080000
-system.mem_ctrls_0.prePowerDownEnergy 907636.800000
-system.mem_ctrls_0.selfRefreshEnergy 0
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-system.mem_ctrls_0.averagePower 982.758547
-system.mem_ctrls_0.totalIdleTime 145094735
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 1000000000
-sim_freq 1000000000000
-host_tick_rate 5954737469
-host_mem_usage 91320
-host_seconds 0.04
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
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-final_tick 1250000000
-sim_freq 1000000000000
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-system.monitor.outstandingWritesHist::18 0
-system.monitor.outstandingWritesHist::19 0
-system.monitor.outstandingWritesHist::total 0
-system.monitor.readTransHist::samples 0
-system.monitor.readTransHist::mean nan
-system.monitor.readTransHist::gmean nan
-system.monitor.readTransHist::stdev nan
-system.monitor.readTransHist::0 0
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-system.monitor.readTransHist::19 0
-system.monitor.readTransHist::total 0
-system.monitor.writeTransHist::samples 0
-system.monitor.writeTransHist::mean nan
-system.monitor.writeTransHist::gmean nan
-system.monitor.writeTransHist::stdev nan
-system.monitor.writeTransHist::0 0
-system.monitor.writeTransHist::1 0
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-system.monitor.writeTransHist::5 0
-system.monitor.writeTransHist::6 0
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-system.monitor.writeTransHist::9 0
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-system.monitor.writeTransHist::11 0
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-system.monitor.writeTransHist::17 0
-system.monitor.writeTransHist::18 0
-system.monitor.writeTransHist::19 0
-system.monitor.writeTransHist::total 0
-system.tgen.pwrStateResidencyTicks::UNDEFINED 250000000
-system.tgen.numPackets 9875
-system.tgen.numRetries 0
-system.tgen.retryTicks 0
-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 1500000000
-sim_freq 1000000000000
-host_tick_rate 8456851570
-host_mem_usage 91320
-host_seconds 0.03
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
-system.mem_ctrls.bytes_read::tgen 638976
-system.mem_ctrls.bytes_read::total 638976
-system.mem_ctrls.num_reads::tgen 9984
-system.mem_ctrls.num_reads::total 9984
-system.mem_ctrls.bw_read::tgen 2555904000
-system.mem_ctrls.bw_read::total 2555904000
-system.mem_ctrls.bw_total::tgen 2555904000
-system.mem_ctrls.bw_total::total 2555904000
-system.mem_ctrls.readReqs 9984
-system.mem_ctrls.writeReqs 0
-system.mem_ctrls.readBursts 9984
-system.mem_ctrls.writeBursts 0
-system.mem_ctrls.bytesReadDRAM 638976
-system.mem_ctrls.bytesReadWrQ 0
-system.mem_ctrls.bytesWritten 0
-system.mem_ctrls.bytesReadSys 638976
-system.mem_ctrls.bytesWrittenSys 0
-system.mem_ctrls.servicedByWrQ 0
-system.mem_ctrls.mergedWrBursts 0
-system.mem_ctrls.neitherReadNorWriteReqs 0
-system.mem_ctrls.perBankRdBursts::0 568
-system.mem_ctrls.perBankRdBursts::1 728
-system.mem_ctrls.perBankRdBursts::2 608
-system.mem_ctrls.perBankRdBursts::3 664
-system.mem_ctrls.perBankRdBursts::4 576
-system.mem_ctrls.perBankRdBursts::5 528
-system.mem_ctrls.perBankRdBursts::6 544
-system.mem_ctrls.perBankRdBursts::7 696
-system.mem_ctrls.perBankRdBursts::8 0
-system.mem_ctrls.perBankRdBursts::9 0
-system.mem_ctrls.perBankRdBursts::10 0
-system.mem_ctrls.perBankRdBursts::11 0
-system.mem_ctrls.perBankRdBursts::12 0
-system.mem_ctrls.perBankRdBursts::13 0
-system.mem_ctrls.perBankRdBursts::14 0
-system.mem_ctrls.perBankRdBursts::15 0
-system.mem_ctrls.perBankRdBursts::16 592
-system.mem_ctrls.perBankRdBursts::17 584
-system.mem_ctrls.perBankRdBursts::18 704
-system.mem_ctrls.perBankRdBursts::19 536
-system.mem_ctrls.perBankRdBursts::20 784
-system.mem_ctrls.perBankRdBursts::21 544
-system.mem_ctrls.perBankRdBursts::22 624
-system.mem_ctrls.perBankRdBursts::23 704
-system.mem_ctrls.perBankRdBursts::24 0
-system.mem_ctrls.perBankRdBursts::25 0
-system.mem_ctrls.perBankRdBursts::26 0
-system.mem_ctrls.perBankRdBursts::27 0
-system.mem_ctrls.perBankRdBursts::28 0
-system.mem_ctrls.perBankRdBursts::29 0
-system.mem_ctrls.perBankRdBursts::30 0
-system.mem_ctrls.perBankRdBursts::31 0
-system.mem_ctrls.perBankWrBursts::0 0
-system.mem_ctrls.perBankWrBursts::1 0
-system.mem_ctrls.perBankWrBursts::2 0
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-system.mem_ctrls.perBankWrBursts::4 0
-system.mem_ctrls.perBankWrBursts::5 0
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-system.mem_ctrls.perBankWrBursts::7 0
-system.mem_ctrls.perBankWrBursts::8 0
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-system.mem_ctrls.perBankWrBursts::10 0
-system.mem_ctrls.perBankWrBursts::11 0
-system.mem_ctrls.perBankWrBursts::12 0
-system.mem_ctrls.perBankWrBursts::13 0
-system.mem_ctrls.perBankWrBursts::14 0
-system.mem_ctrls.perBankWrBursts::15 0
-system.mem_ctrls.perBankWrBursts::16 0
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-system.mem_ctrls.perBankWrBursts::18 0
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-system.mem_ctrls.perBankWrBursts::21 0
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-system.mem_ctrls.perBankWrBursts::30 0
-system.mem_ctrls.perBankWrBursts::31 0
-system.mem_ctrls.numRdRetry 0
-system.mem_ctrls.numWrRetry 0
-system.mem_ctrls.totGap 250014042
-system.mem_ctrls.readPktSize::0 0
-system.mem_ctrls.readPktSize::1 0
-system.mem_ctrls.readPktSize::2 0
-system.mem_ctrls.readPktSize::3 0
-system.mem_ctrls.readPktSize::4 0
-system.mem_ctrls.readPktSize::5 0
-system.mem_ctrls.readPktSize::6 9984
-system.mem_ctrls.writePktSize::0 0
-system.mem_ctrls.writePktSize::1 0
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-system.mem_ctrls.writePktSize::5 0
-system.mem_ctrls.writePktSize::6 0
-system.mem_ctrls.rdQLenPdf::0 4621
-system.mem_ctrls.rdQLenPdf::1 3660
-system.mem_ctrls.rdQLenPdf::2 991
-system.mem_ctrls.rdQLenPdf::3 207
-system.mem_ctrls.rdQLenPdf::4 70
-system.mem_ctrls.rdQLenPdf::5 36
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-system.mem_ctrls.bytesPerActivate::samples 1275
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-system.mem_ctrls.bytesPerActivate::0-127 7 0.55% 0.55%
-system.mem_ctrls.bytesPerActivate::128-255 18 1.41% 1.96%
-system.mem_ctrls.bytesPerActivate::256-383 28 2.20% 4.16%
-system.mem_ctrls.bytesPerActivate::384-511 16 1.25% 5.41%
-system.mem_ctrls.bytesPerActivate::512-639 1204 94.43% 99.84%
-system.mem_ctrls.bytesPerActivate::768-895 1 0.08% 99.92%
-system.mem_ctrls.bytesPerActivate::1024-1151 1 0.08% 100.00%
-system.mem_ctrls.bytesPerActivate::total 1275
-system.mem_ctrls.totQLat 195750132
-system.mem_ctrls.totMemAccLat 370390260
-system.mem_ctrls.totBusLat 33266688
-system.mem_ctrls.avgQLat 19606.38
-system.mem_ctrls.avgBusLat 3332.00
-system.mem_ctrls.avgMemAccLat 37098.38
-system.mem_ctrls.avgRdBW 2555.90
-system.mem_ctrls.avgWrBW 0.00
-system.mem_ctrls.avgRdBWSys 2555.90
-system.mem_ctrls.avgWrBWSys 0.00
-system.mem_ctrls.peakBW 19207.00
-system.mem_ctrls.busUtil 13.31
-system.mem_ctrls.busUtilRead 13.31
-system.mem_ctrls.busUtilWrite 0.00
-system.mem_ctrls.avgRdQLen 2.11
-system.mem_ctrls.avgWrQLen 0.00
-system.mem_ctrls.readRowHits 8711
-system.mem_ctrls.writeRowHits 0
-system.mem_ctrls.readRowHitRate 87.25
-system.mem_ctrls.writeRowHitRate nan
-system.mem_ctrls.avgGap 25041.47
-system.mem_ctrls.pageHitRate 87.25
-system.mem_ctrls_0.actEnergy 1936744.992000
-system.mem_ctrls_0.preEnergy 2574877.636800
-system.mem_ctrls_0.readEnergy 20661428.121600
-system.mem_ctrls_0.writeEnergy 0
-system.mem_ctrls_0.refreshEnergy 44332084.070400
-system.mem_ctrls_0.actBackEnergy 87461057.577600
-system.mem_ctrls_0.preBackEnergy 754769.971200
-system.mem_ctrls_0.actPowerDownEnergy 88147510.886400
-system.mem_ctrls_0.prePowerDownEnergy 1166733.120000
-system.mem_ctrls_0.selfRefreshEnergy 0
-system.mem_ctrls_0.totalEnergy 247035206.376000
-system.mem_ctrls_0.averagePower 988.140826
-system.mem_ctrls_0.totalIdleTime 145923109
-system.mem_ctrls_0.memoryStateTime::IDLE 187748
-system.mem_ctrls_0.memoryStateTime::REF 11200000
-system.mem_ctrls_0.memoryStateTime::SREF 0
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-system.mem_ctrls_0.memoryStateTime::ACT 92689143
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 143492900
-system.mem_ctrls_1.actEnergy 2033426.304000
-system.mem_ctrls_1.preEnergy 2711706.883200
-system.mem_ctrls_1.readEnergy 21334438.809600
-system.mem_ctrls_1.writeEnergy 0
-system.mem_ctrls_1.refreshEnergy 44332084.070400
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-system.mem_ctrls_1.preBackEnergy 681359.347200
-system.mem_ctrls_1.actPowerDownEnergy 88702808.678400
-system.mem_ctrls_1.prePowerDownEnergy 584166.240000
-system.mem_ctrls_1.selfRefreshEnergy 0
-system.mem_ctrls_1.totalEnergy 248199860.328000
-system.mem_ctrls_1.averagePower 992.799441
-system.mem_ctrls_1.totalIdleTime 145391575
-system.mem_ctrls_1.memoryStateTime::IDLE 117200
-system.mem_ctrls_1.memoryStateTime::REF 11200000
-system.mem_ctrls_1.memoryStateTime::SREF 0
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 1216864
-system.mem_ctrls_1.memoryStateTime::ACT 93066447
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 144399489
-system.pwrStateResidencyTicks::UNDEFINED 250000000
-system.membus.pwrStateResidencyTicks::UNDEFINED 250000000
-system.membus.trans_dist::ReadReq 9984
-system.membus.trans_dist::ReadResp 9984
-system.membus.pkt_count_system.monitor-master::system.mem_ctrls.port 19968
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 1750000000
-sim_freq 1000000000000
-host_tick_rate 5927080504
-host_mem_usage 91320
-host_seconds 0.04
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
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-system.mem_ctrls.num_reads::total 9846
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-system.mem_ctrls.bw_total::total 2520576000
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-system.monitor.ittReadRead::25001-30000 1189 12.07% 60.74%
-system.monitor.ittReadRead::30001-35000 1109 11.26% 72.00%
-system.monitor.ittReadRead::35001-40000 1139 11.57% 83.57%
-system.monitor.ittReadRead::40001-45000 1185 12.03% 95.60%
-system.monitor.ittReadRead::45001-50000 433 4.40% 100.00%
-system.monitor.ittReadRead::50001-55000 0 0.00% 100.00%
-system.monitor.ittReadRead::55001-60000 0 0.00% 100.00%
-system.monitor.ittReadRead::60001-65000 0 0.00% 100.00%
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-system.tgen.pwrStateResidencyTicks::UNDEFINED 250000000
-system.tgen.numPackets 9848
-system.tgen.numRetries 0
-system.tgen.retryTicks 0
-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 2000000000
-sim_freq 1000000000000
-host_tick_rate 8066808143
-host_mem_usage 91320
-host_seconds 0.03
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
-system.mem_ctrls.bytes_read::tgen 635264
-system.mem_ctrls.bytes_read::total 635264
-system.mem_ctrls.num_reads::tgen 9926
-system.mem_ctrls.num_reads::total 9926
-system.mem_ctrls.bw_read::tgen 2541056000
-system.mem_ctrls.bw_read::total 2541056000
-system.mem_ctrls.bw_total::tgen 2541056000
-system.mem_ctrls.bw_total::total 2541056000
-system.mem_ctrls.readReqs 9924
-system.mem_ctrls.writeReqs 0
-system.mem_ctrls.readBursts 9924
-system.mem_ctrls.writeBursts 0
-system.mem_ctrls.bytesReadDRAM 635136
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-system.mem_ctrls.bytesReadSys 635136
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-system.monitor.writeTransHist::18 0
-system.monitor.writeTransHist::19 0
-system.monitor.writeTransHist::total 0
-system.tgen.pwrStateResidencyTicks::UNDEFINED 250000000
-system.tgen.numPackets 9924
-system.tgen.numRetries 0
-system.tgen.retryTicks 0
-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 2250000000
-sim_freq 1000000000000
-host_tick_rate 8541831175
-host_mem_usage 91320
-host_seconds 0.03
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
-system.mem_ctrls.bytes_read::tgen 632896
-system.mem_ctrls.bytes_read::total 632896
-system.mem_ctrls.num_reads::tgen 9889
-system.mem_ctrls.num_reads::total 9889
-system.mem_ctrls.bw_read::tgen 2531584000
-system.mem_ctrls.bw_read::total 2531584000
-system.mem_ctrls.bw_total::tgen 2531584000
-system.mem_ctrls.bw_total::total 2531584000
-system.mem_ctrls.readReqs 9890
-system.mem_ctrls.writeReqs 0
-system.mem_ctrls.readBursts 9890
-system.mem_ctrls.writeBursts 0
-system.mem_ctrls.bytesReadDRAM 632960
-system.mem_ctrls.bytesReadWrQ 0
-system.mem_ctrls.bytesWritten 0
-system.mem_ctrls.bytesReadSys 632960
-system.mem_ctrls.bytesWrittenSys 0
-system.mem_ctrls.servicedByWrQ 0
-system.mem_ctrls.mergedWrBursts 0
-system.mem_ctrls.neitherReadNorWriteReqs 0
-system.mem_ctrls.perBankRdBursts::0 344
-system.mem_ctrls.perBankRdBursts::1 296
-system.mem_ctrls.perBankRdBursts::2 248
-system.mem_ctrls.perBankRdBursts::3 272
-system.mem_ctrls.perBankRdBursts::4 288
-system.mem_ctrls.perBankRdBursts::5 344
-system.mem_ctrls.perBankRdBursts::6 338
-system.mem_ctrls.perBankRdBursts::7 328
-system.mem_ctrls.perBankRdBursts::8 272
-system.mem_ctrls.perBankRdBursts::9 328
-system.mem_ctrls.perBankRdBursts::10 256
-system.mem_ctrls.perBankRdBursts::11 200
-system.mem_ctrls.perBankRdBursts::12 360
-system.mem_ctrls.perBankRdBursts::13 296
-system.mem_ctrls.perBankRdBursts::14 376
-system.mem_ctrls.perBankRdBursts::15 352
-system.mem_ctrls.perBankRdBursts::16 376
-system.mem_ctrls.perBankRdBursts::17 336
-system.mem_ctrls.perBankRdBursts::18 280
-system.mem_ctrls.perBankRdBursts::19 328
-system.mem_ctrls.perBankRdBursts::20 336
-system.mem_ctrls.perBankRdBursts::21 264
-system.mem_ctrls.perBankRdBursts::22 384
-system.mem_ctrls.perBankRdBursts::23 304
-system.mem_ctrls.perBankRdBursts::24 256
-system.mem_ctrls.perBankRdBursts::25 312
-system.mem_ctrls.perBankRdBursts::26 304
-system.mem_ctrls.perBankRdBursts::27 288
-system.mem_ctrls.perBankRdBursts::28 328
-system.mem_ctrls.perBankRdBursts::29 360
-system.mem_ctrls.perBankRdBursts::30 264
-system.mem_ctrls.perBankRdBursts::31 272
-system.mem_ctrls.perBankWrBursts::0 0
-system.mem_ctrls.perBankWrBursts::1 0
-system.mem_ctrls.perBankWrBursts::2 0
-system.mem_ctrls.perBankWrBursts::3 0
-system.mem_ctrls.perBankWrBursts::4 0
-system.mem_ctrls.perBankWrBursts::5 0
-system.mem_ctrls.perBankWrBursts::6 0
-system.mem_ctrls.perBankWrBursts::7 0
-system.mem_ctrls.perBankWrBursts::8 0
-system.mem_ctrls.perBankWrBursts::9 0
-system.mem_ctrls.perBankWrBursts::10 0
-system.mem_ctrls.perBankWrBursts::11 0
-system.mem_ctrls.perBankWrBursts::12 0
-system.mem_ctrls.perBankWrBursts::13 0
-system.mem_ctrls.perBankWrBursts::14 0
-system.mem_ctrls.perBankWrBursts::15 0
-system.mem_ctrls.perBankWrBursts::16 0
-system.mem_ctrls.perBankWrBursts::17 0
-system.mem_ctrls.perBankWrBursts::18 0
-system.mem_ctrls.perBankWrBursts::19 0
-system.mem_ctrls.perBankWrBursts::20 0
-system.mem_ctrls.perBankWrBursts::21 0
-system.mem_ctrls.perBankWrBursts::22 0
-system.mem_ctrls.perBankWrBursts::23 0
-system.mem_ctrls.perBankWrBursts::24 0
-system.mem_ctrls.perBankWrBursts::25 0
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-system.mem_ctrls.perBankWrBursts::27 0
-system.mem_ctrls.perBankWrBursts::28 0
-system.mem_ctrls.perBankWrBursts::29 0
-system.mem_ctrls.perBankWrBursts::30 0
-system.mem_ctrls.perBankWrBursts::31 0
-system.mem_ctrls.numRdRetry 0
-system.mem_ctrls.numWrRetry 0
-system.mem_ctrls.totGap 249997651
-system.mem_ctrls.readPktSize::0 0
-system.mem_ctrls.readPktSize::1 0
-system.mem_ctrls.readPktSize::2 0
-system.mem_ctrls.readPktSize::3 0
-system.mem_ctrls.readPktSize::4 0
-system.mem_ctrls.readPktSize::5 0
-system.mem_ctrls.readPktSize::6 9890
-system.mem_ctrls.writePktSize::0 0
-system.mem_ctrls.writePktSize::1 0
-system.mem_ctrls.writePktSize::2 0
-system.mem_ctrls.writePktSize::3 0
-system.mem_ctrls.writePktSize::4 0
-system.mem_ctrls.writePktSize::5 0
-system.mem_ctrls.writePktSize::6 0
-system.mem_ctrls.rdQLenPdf::0 4775
-system.mem_ctrls.rdQLenPdf::1 3588
-system.mem_ctrls.rdQLenPdf::2 869
-system.mem_ctrls.rdQLenPdf::3 172
-system.mem_ctrls.rdQLenPdf::4 52
-system.mem_ctrls.rdQLenPdf::5 39
-system.mem_ctrls.rdQLenPdf::6 40
-system.mem_ctrls.rdQLenPdf::7 41
-system.mem_ctrls.rdQLenPdf::8 37
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-system.mem_ctrls.rdQLenPdf::10 39
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-system.mem_ctrls.rdQLenPdf::63 0
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-system.mem_ctrls.bytesPerActivate::samples 1270
-system.mem_ctrls.bytesPerActivate::mean 495.319685
-system.mem_ctrls.bytesPerActivate::gmean 485.291385
-system.mem_ctrls.bytesPerActivate::stdev 69.226619
-system.mem_ctrls.bytesPerActivate::64-127 10 0.79% 0.79%
-system.mem_ctrls.bytesPerActivate::128-191 7 0.55% 1.34%
-system.mem_ctrls.bytesPerActivate::192-255 7 0.55% 1.89%
-system.mem_ctrls.bytesPerActivate::256-319 34 2.68% 4.57%
-system.mem_ctrls.bytesPerActivate::320-383 8 0.63% 5.20%
-system.mem_ctrls.bytesPerActivate::384-447 7 0.55% 5.75%
-system.mem_ctrls.bytesPerActivate::448-511 10 0.79% 6.54%
-system.mem_ctrls.bytesPerActivate::512-575 1187 93.46% 100.00%
-system.mem_ctrls.bytesPerActivate::total 1270
-system.mem_ctrls.totQLat 188570688
-system.mem_ctrls.totMemAccLat 361566568
-system.mem_ctrls.totBusLat 32953480
-system.mem_ctrls.avgQLat 19066.80
-system.mem_ctrls.avgBusLat 3332.00
-system.mem_ctrls.avgMemAccLat 36558.80
-system.mem_ctrls.avgRdBW 2531.84
-system.mem_ctrls.avgWrBW 0.00
-system.mem_ctrls.avgRdBWSys 2531.84
-system.mem_ctrls.avgWrBWSys 0.00
-system.mem_ctrls.peakBW 19207.00
-system.mem_ctrls.busUtil 13.18
-system.mem_ctrls.busUtilRead 13.18
-system.mem_ctrls.busUtilWrite 0.00
-system.mem_ctrls.avgRdQLen 2.07
-system.mem_ctrls.avgWrQLen 0.00
-system.mem_ctrls.readRowHits 8624
-system.mem_ctrls.writeRowHits 0
-system.mem_ctrls.readRowHitRate 87.20
-system.mem_ctrls.writeRowHitRate nan
-system.mem_ctrls.avgGap 25277.82
-system.mem_ctrls.pageHitRate 87.20
-system.mem_ctrls_0.actEnergy 1971051.264000
-system.mem_ctrls_0.preEnergy 2637072.748800
-system.mem_ctrls_0.readEnergy 20594127.052800
-system.mem_ctrls_0.writeEnergy 0
-system.mem_ctrls_0.refreshEnergy 44332084.070400
-system.mem_ctrls_0.actBackEnergy 86325879.830400
-system.mem_ctrls_0.preBackEnergy 665589.657600
-system.mem_ctrls_0.actPowerDownEnergy 89835923.251200
-system.mem_ctrls_0.prePowerDownEnergy 554578.080000
-system.mem_ctrls_0.selfRefreshEnergy 0
-system.mem_ctrls_0.totalEnergy 246916305.955200
-system.mem_ctrls_0.averagePower 987.665224
-system.mem_ctrls_0.totalIdleTime 147385375
-system.mem_ctrls_0.memoryStateTime::IDLE 106175
-system.mem_ctrls_0.memoryStateTime::REF 11200000
-system.mem_ctrls_0.memoryStateTime::SREF 0
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 1155878
-system.mem_ctrls_0.memoryStateTime::ACT 91308450
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 146229497
-system.mem_ctrls_1.actEnergy 1977288.768000
-system.mem_ctrls_1.preEnergy 2628780.067200
-system.mem_ctrls_1.readEnergy 20997933.465600
-system.mem_ctrls_1.writeEnergy 0
-system.mem_ctrls_1.refreshEnergy 44332084.070400
-system.mem_ctrls_1.actBackEnergy 87528998.390400
-system.mem_ctrls_1.preBackEnergy 697672.819200
-system.mem_ctrls_1.actPowerDownEnergy 89064136.089600
-system.mem_ctrls_1.prePowerDownEnergy 454218.240000
-system.mem_ctrls_1.selfRefreshEnergy 0
-system.mem_ctrls_1.totalEnergy 247681111.910400
-system.mem_ctrls_1.averagePower 990.724448
-system.mem_ctrls_1.totalIdleTime 145899823
-system.mem_ctrls_1.memoryStateTime::IDLE 160327
-system.mem_ctrls_1.memoryStateTime::REF 11200000
-system.mem_ctrls_1.memoryStateTime::SREF 0
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 946407
-system.mem_ctrls_1.memoryStateTime::ACT 92710174
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 144983092
-system.pwrStateResidencyTicks::UNDEFINED 250000000
-system.membus.pwrStateResidencyTicks::UNDEFINED 250000000
-system.membus.trans_dist::ReadReq 9890
-system.membus.trans_dist::ReadResp 9890
-system.membus.pkt_count_system.monitor-master::system.mem_ctrls.port 19780
-system.membus.pkt_count::total 19780
-system.membus.pkt_size_system.monitor-master::system.mem_ctrls.port 632960
-system.membus.pkt_size::total 632960
-system.membus.reqLayer0.occupancy 7423146
-system.membus.reqLayer0.utilization 3.0
-system.membus.respLayer0.occupancy 15844808
-system.membus.respLayer0.utilization 6.3
-system.monitor.pwrStateResidencyTicks::UNDEFINED 250000000
-system.monitor.readBurstLengthHist::samples 9890
-system.monitor.readBurstLengthHist::mean 64
-system.monitor.readBurstLengthHist::gmean 64.000000
-system.monitor.readBurstLengthHist::stdev 0
-system.monitor.readBurstLengthHist::0-3 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::4-7 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::8-11 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::12-15 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::16-19 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::20-23 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::24-27 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::28-31 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::32-35 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::36-39 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::40-43 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::44-47 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::48-51 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::52-55 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::56-59 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::60-63 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::64-67 9890 100.00% 100.00%
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
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-sim_ticks 250000000
-final_tick 2500000000
-sim_freq 1000000000000
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-system.tgen.pwrStateResidencyTicks::UNDEFINED 250000000
-system.tgen.numPackets 517
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-system.tgen.retryTicks 0
-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 2750000000
-sim_freq 1000000000000
-host_tick_rate 80680817006
-host_mem_usage 91320
-host_seconds 0.00
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
-system.mem_ctrls.bytes_read::tgen 33984
-system.mem_ctrls.bytes_read::total 33984
-system.mem_ctrls.num_reads::tgen 531
-system.mem_ctrls.num_reads::total 531
-system.mem_ctrls.bw_read::tgen 135936000
-system.mem_ctrls.bw_read::total 135936000
-system.mem_ctrls.bw_total::tgen 135936000
-system.mem_ctrls.bw_total::total 135936000
-system.mem_ctrls.readReqs 531
-system.mem_ctrls.writeReqs 0
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-system.tgen.pwrStateResidencyTicks::UNDEFINED 250000000
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-system.tgen.retryTicks 0
-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 3000000000
-sim_freq 1000000000000
-host_tick_rate 83903288371
-host_mem_usage 91320
-host_seconds 0.00
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
-system.mem_ctrls.bytes_read::tgen 34432
-system.mem_ctrls.bytes_read::total 34432
-system.mem_ctrls.num_reads::tgen 538
-system.mem_ctrls.num_reads::total 538
-system.mem_ctrls.bw_read::tgen 137728000
-system.mem_ctrls.bw_read::total 137728000
-system.mem_ctrls.bw_total::tgen 137728000
-system.mem_ctrls.bw_total::total 137728000
-system.mem_ctrls.readReqs 538
-system.mem_ctrls.writeReqs 0
-system.mem_ctrls.readBursts 538
-system.mem_ctrls.writeBursts 0
-system.mem_ctrls.bytesReadDRAM 34432
-system.mem_ctrls.bytesReadWrQ 0
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-system.mem_ctrls.bytesReadSys 34432
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 3250000000
-sim_freq 1000000000000
-host_tick_rate 69164998637
-host_mem_usage 91320
-host_seconds 0.00
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-system.monitor.ittReqReq::80001-85000 5 0.94% 9.94%
-system.monitor.ittReqReq::85001-90000 0 0.00% 9.94%
-system.monitor.ittReqReq::90001-95000 1 0.19% 10.13%
-system.monitor.ittReqReq::95001-100000 2 0.38% 10.51%
-system.monitor.ittReqReq::overflows 477 89.49% 100.00%
-system.monitor.ittReqReq::min_value 4983
-system.monitor.ittReqReq::max_value 1009748
-system.monitor.ittReqReq::total 533
-system.monitor.outstandingReadsHist::samples 0
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-system.tgen.pwrStateResidencyTicks::UNDEFINED 250000000
-system.tgen.numPackets 533
-system.tgen.numRetries 0
-system.tgen.retryTicks 0
-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 3500000000
-sim_freq 1000000000000
-host_tick_rate 80217936089
-host_mem_usage 91320
-host_seconds 0.00
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
-system.mem_ctrls.bytes_read::tgen 34176
-system.mem_ctrls.bytes_read::total 34176
-system.mem_ctrls.num_reads::tgen 534
-system.mem_ctrls.num_reads::total 534
-system.mem_ctrls.bw_read::tgen 136704000
-system.mem_ctrls.bw_read::total 136704000
-system.mem_ctrls.bw_total::tgen 136704000
-system.mem_ctrls.bw_total::total 136704000
-system.mem_ctrls.readReqs 534
-system.mem_ctrls.writeReqs 0
-system.mem_ctrls.readBursts 534
-system.mem_ctrls.writeBursts 0
-system.mem_ctrls.bytesReadDRAM 34176
-system.mem_ctrls.bytesReadWrQ 0
-system.mem_ctrls.bytesWritten 0
-system.mem_ctrls.bytesReadSys 34176
-system.mem_ctrls.bytesWrittenSys 0
-system.mem_ctrls.servicedByWrQ 0
-system.mem_ctrls.mergedWrBursts 0
-system.mem_ctrls.neitherReadNorWriteReqs 0
-system.mem_ctrls.perBankRdBursts::0 24
-system.mem_ctrls.perBankRdBursts::1 20
-system.mem_ctrls.perBankRdBursts::2 40
-system.mem_ctrls.perBankRdBursts::3 36
-system.mem_ctrls.perBankRdBursts::4 36
-system.mem_ctrls.perBankRdBursts::5 24
-system.mem_ctrls.perBankRdBursts::6 36
-system.mem_ctrls.perBankRdBursts::7 44
-system.mem_ctrls.perBankRdBursts::8 0
-system.mem_ctrls.perBankRdBursts::9 0
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-system.mem_ctrls.perBankRdBursts::17 28
-system.mem_ctrls.perBankRdBursts::18 44
-system.mem_ctrls.perBankRdBursts::19 32
-system.mem_ctrls.perBankRdBursts::20 56
-system.mem_ctrls.perBankRdBursts::21 46
-system.mem_ctrls.perBankRdBursts::22 28
-system.mem_ctrls.perBankRdBursts::23 16
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-system.mem_ctrls.numRdRetry 0
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-system.mem_ctrls.totGap 250563495
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-system.mem_ctrls.bytesPerActivate::64-95 21 12.88% 12.88%
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-system.mem_ctrls.bytesPerActivate::192-223 19 11.66% 36.81%
-system.mem_ctrls.bytesPerActivate::256-287 103 63.19% 100.00%
-system.mem_ctrls.bytesPerActivate::total 163
-system.mem_ctrls.totQLat 12460859
-system.mem_ctrls.totMemAccLat 21801587
-system.mem_ctrls.totBusLat 1779288
-system.mem_ctrls.avgQLat 23334.94
-system.mem_ctrls.avgBusLat 3332.00
-system.mem_ctrls.avgMemAccLat 40826.94
-system.mem_ctrls.avgRdBW 136.70
-system.mem_ctrls.avgWrBW 0.00
-system.mem_ctrls.avgRdBWSys 136.70
-system.mem_ctrls.avgWrBWSys 0.00
-system.mem_ctrls.peakBW 19207.00
-system.mem_ctrls.busUtil 0.71
-system.mem_ctrls.busUtilRead 0.71
-system.mem_ctrls.busUtilWrite 0.00
-system.mem_ctrls.avgRdQLen 1.03
-system.mem_ctrls.avgWrQLen 0.00
-system.mem_ctrls.readRowHits 371
-system.mem_ctrls.writeRowHits 0
-system.mem_ctrls.readRowHitRate 69.48
-system.mem_ctrls.writeRowHitRate nan
-system.mem_ctrls.avgGap 469220.03
-system.mem_ctrls.pageHitRate 69.48
-system.mem_ctrls_0.actEnergy 252618.912000
-system.mem_ctrls_0.preEnergy 331707.264000
-system.mem_ctrls_0.readEnergy 1093642.368000
-system.mem_ctrls_0.writeEnergy 0
-system.mem_ctrls_0.refreshEnergy 45717461.697600
-system.mem_ctrls_0.actBackEnergy 15479181.849600
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 3750000000
-sim_freq 1000000000000
-host_tick_rate 84181489905
-host_mem_usage 91320
-host_seconds 0.00
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
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-system.mem_ctrls.bytes_read::total 34176
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-system.mem_ctrls.num_reads::total 534
-system.mem_ctrls.bw_read::tgen 136704000
-system.mem_ctrls.bw_read::total 136704000
-system.mem_ctrls.bw_total::tgen 136704000
-system.mem_ctrls.bw_total::total 136704000
-system.mem_ctrls.readReqs 534
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 4000000000
-sim_freq 1000000000000
-host_tick_rate 70488874177
-host_mem_usage 91320
-host_seconds 0.00
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
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-system.mem_ctrls.bytes_read::total 34112
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-system.mem_ctrls.num_reads::total 533
-system.mem_ctrls.bw_read::tgen 136448000
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-system.mem_ctrls.bw_total::tgen 136448000
-system.mem_ctrls.bw_total::total 136448000
-system.mem_ctrls.readReqs 533
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-system.monitor.writeTransHist::total 0
-system.tgen.pwrStateResidencyTicks::UNDEFINED 250000000
-system.tgen.numPackets 533
-system.tgen.numRetries 0
-system.tgen.retryTicks 0
-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 4250000000
-sim_freq 1000000000000
-host_tick_rate 81372261823
-host_mem_usage 91320
-host_seconds 0.00
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
-system.mem_ctrls.bytes_read::tgen 33536
-system.mem_ctrls.bytes_read::total 33536
-system.mem_ctrls.num_reads::tgen 524
-system.mem_ctrls.num_reads::total 524
-system.mem_ctrls.bw_read::tgen 134144000
-system.mem_ctrls.bw_read::total 134144000
-system.mem_ctrls.bw_total::tgen 134144000
-system.mem_ctrls.bw_total::total 134144000
-system.mem_ctrls.readReqs 524
-system.mem_ctrls.writeReqs 0
-system.mem_ctrls.readBursts 524
-system.mem_ctrls.writeBursts 0
-system.mem_ctrls.bytesReadDRAM 33536
-system.mem_ctrls.bytesReadWrQ 0
-system.mem_ctrls.bytesWritten 0
-system.mem_ctrls.bytesReadSys 33536
-system.mem_ctrls.bytesWrittenSys 0
-system.mem_ctrls.servicedByWrQ 0
-system.mem_ctrls.mergedWrBursts 0
-system.mem_ctrls.neitherReadNorWriteReqs 0
-system.mem_ctrls.perBankRdBursts::0 8
-system.mem_ctrls.perBankRdBursts::1 4
-system.mem_ctrls.perBankRdBursts::2 16
-system.mem_ctrls.perBankRdBursts::3 28
-system.mem_ctrls.perBankRdBursts::4 16
-system.mem_ctrls.perBankRdBursts::5 12
-system.mem_ctrls.perBankRdBursts::6 20
-system.mem_ctrls.perBankRdBursts::7 28
-system.mem_ctrls.perBankRdBursts::8 24
-system.mem_ctrls.perBankRdBursts::9 20
-system.mem_ctrls.perBankRdBursts::10 16
-system.mem_ctrls.perBankRdBursts::11 28
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-system.mem_ctrls.perBankRdBursts::19 24
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-system.mem_ctrls.perBankRdBursts::21 36
-system.mem_ctrls.perBankRdBursts::22 20
-system.mem_ctrls.perBankRdBursts::23 20
-system.mem_ctrls.perBankRdBursts::24 32
-system.mem_ctrls.perBankRdBursts::25 28
-system.mem_ctrls.perBankRdBursts::26 12
-system.mem_ctrls.perBankRdBursts::27 4
-system.mem_ctrls.perBankRdBursts::28 16
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-system.mem_ctrls.perBankRdBursts::30 8
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-system.mem_ctrls.numRdRetry 0
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-system.mem_ctrls.bytesPerActivate::512-575 1 0.62% 100.00%
-system.mem_ctrls.bytesPerActivate::total 160
-system.mem_ctrls.totQLat 10373089
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-system.mem_ctrls.avgMemAccLat 37287.97
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-system.mem_ctrls.avgRdBWSys 134.14
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-system.mem_ctrls.peakBW 19207.00
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-system.tgen.pwrStateResidencyTicks::UNDEFINED 250000000
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-system.tgen.retryTicks 0
-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 4500000000
-sim_freq 1000000000000
-host_tick_rate 83492302678
-host_mem_usage 91320
-host_seconds 0.00
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
-system.mem_ctrls.bytes_read::tgen 33152
-system.mem_ctrls.bytes_read::total 33152
-system.mem_ctrls.num_reads::tgen 518
-system.mem_ctrls.num_reads::total 518
-system.mem_ctrls.bw_read::tgen 132608000
-system.mem_ctrls.bw_read::total 132608000
-system.mem_ctrls.bw_total::tgen 132608000
-system.mem_ctrls.bw_total::total 132608000
-system.mem_ctrls.readReqs 518
-system.mem_ctrls.writeReqs 0
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-system.mem_ctrls.writeBursts 0
-system.mem_ctrls.bytesReadDRAM 33152
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-system.mem_ctrls.bytesReadSys 33152
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-system.mem_ctrls.perBankRdBursts::3 22
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-system.tgen.pwrStateResidencyTicks::UNDEFINED 250000000
-system.tgen.numPackets 518
-system.tgen.numRetries 0
-system.tgen.retryTicks 0
-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 4750000000
-sim_freq 1000000000000
-host_tick_rate 140739377133
-host_mem_usage 91320
-host_seconds 0.00
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
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-system.mem_ctrls.bytes_read::total 6976
-system.mem_ctrls.num_reads::tgen 109
-system.mem_ctrls.num_reads::total 109
-system.mem_ctrls.bw_read::tgen 27904000
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-system.mem_ctrls.bw_total::tgen 27904000
-system.mem_ctrls.bw_total::total 27904000
-system.mem_ctrls.readReqs 109
-system.mem_ctrls.writeReqs 0
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-system.monitor.writeTransHist::5 0
-system.monitor.writeTransHist::6 0
-system.monitor.writeTransHist::7 0
-system.monitor.writeTransHist::8 0
-system.monitor.writeTransHist::9 0
-system.monitor.writeTransHist::10 0
-system.monitor.writeTransHist::11 0
-system.monitor.writeTransHist::12 0
-system.monitor.writeTransHist::13 0
-system.monitor.writeTransHist::14 0
-system.monitor.writeTransHist::15 0
-system.monitor.writeTransHist::16 0
-system.monitor.writeTransHist::17 0
-system.monitor.writeTransHist::18 0
-system.monitor.writeTransHist::19 0
-system.monitor.writeTransHist::total 0
-system.tgen.pwrStateResidencyTicks::UNDEFINED 250000000
-system.tgen.numPackets 109
-system.tgen.numRetries 0
-system.tgen.retryTicks 0
-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 5000000000
-sim_freq 1000000000000
-host_tick_rate 162611462027
-host_mem_usage 91320
-host_seconds 0.00
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
-system.mem_ctrls.bytes_read::tgen 6464
-system.mem_ctrls.bytes_read::total 6464
-system.mem_ctrls.num_reads::tgen 101
-system.mem_ctrls.num_reads::total 101
-system.mem_ctrls.bw_read::tgen 25856000
-system.mem_ctrls.bw_read::total 25856000
-system.mem_ctrls.bw_total::tgen 25856000
-system.mem_ctrls.bw_total::total 25856000
-system.mem_ctrls.readReqs 101
-system.mem_ctrls.writeReqs 0
-system.mem_ctrls.readBursts 101
-system.mem_ctrls.writeBursts 0
-system.mem_ctrls.bytesReadDRAM 6464
-system.mem_ctrls.bytesReadWrQ 0
-system.mem_ctrls.bytesWritten 0
-system.mem_ctrls.bytesReadSys 6464
-system.mem_ctrls.bytesWrittenSys 0
-system.mem_ctrls.servicedByWrQ 0
-system.mem_ctrls.mergedWrBursts 0
-system.mem_ctrls.neitherReadNorWriteReqs 0
-system.mem_ctrls.perBankRdBursts::0 40
-system.mem_ctrls.perBankRdBursts::1 0
-system.mem_ctrls.perBankRdBursts::2 0
-system.mem_ctrls.perBankRdBursts::3 0
-system.mem_ctrls.perBankRdBursts::4 0
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-system.mem_ctrls.perBankRdBursts::6 0
-system.mem_ctrls.perBankRdBursts::7 0
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-system.mem_ctrls.perBankRdBursts::16 61
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-system.mem_ctrls.perBankRdBursts::24 0
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-system.mem_ctrls.perBankRdBursts::27 0
-system.mem_ctrls.perBankRdBursts::28 0
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-system.mem_ctrls.perBankRdBursts::30 0
-system.mem_ctrls.perBankRdBursts::31 0
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-system.mem_ctrls.perBankWrBursts::20 0
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-system.mem_ctrls.perBankWrBursts::22 0
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-system.mem_ctrls.perBankWrBursts::30 0
-system.mem_ctrls.perBankWrBursts::31 0
-system.mem_ctrls.numRdRetry 0
-system.mem_ctrls.numWrRetry 0
-system.mem_ctrls.totGap 249897204
-system.mem_ctrls.readPktSize::0 0
-system.mem_ctrls.readPktSize::1 0
-system.mem_ctrls.readPktSize::2 0
-system.mem_ctrls.readPktSize::3 0
-system.mem_ctrls.readPktSize::4 0
-system.mem_ctrls.readPktSize::5 0
-system.mem_ctrls.readPktSize::6 101
-system.mem_ctrls.writePktSize::0 0
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-system.mem_ctrls.writePktSize::2 0
-system.mem_ctrls.writePktSize::3 0
-system.mem_ctrls.writePktSize::4 0
-system.mem_ctrls.writePktSize::5 0
-system.mem_ctrls.writePktSize::6 0
-system.mem_ctrls.rdQLenPdf::0 101
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-system.mem_ctrls.bytesPerActivate::samples 41
-system.mem_ctrls.bytesPerActivate::mean 157.658537
-system.mem_ctrls.bytesPerActivate::gmean 138.538104
-system.mem_ctrls.bytesPerActivate::stdev 74.495506
-system.mem_ctrls.bytesPerActivate::64-95 11 26.83% 26.83%
-system.mem_ctrls.bytesPerActivate::128-159 11 26.83% 53.66%
-system.mem_ctrls.bytesPerActivate::192-223 8 19.51% 73.17%
-system.mem_ctrls.bytesPerActivate::256-287 11 26.83% 100.00%
-system.mem_ctrls.bytesPerActivate::total 41
-system.mem_ctrls.totQLat 10177680
-system.mem_ctrls.totMemAccLat 11944372
-system.mem_ctrls.totBusLat 336532
-system.mem_ctrls.avgQLat 100769.11
-system.mem_ctrls.avgBusLat 3332.00
-system.mem_ctrls.avgMemAccLat 118261.11
-system.mem_ctrls.avgRdBW 25.86
-system.mem_ctrls.avgWrBW 0.00
-system.mem_ctrls.avgRdBWSys 25.86
-system.mem_ctrls.avgWrBWSys 0.00
-system.mem_ctrls.peakBW 19207.00
-system.mem_ctrls.busUtil 0.13
-system.mem_ctrls.busUtilRead 0.13
-system.mem_ctrls.busUtilWrite 0.00
-system.mem_ctrls.avgRdQLen 1.00
-system.mem_ctrls.avgWrQLen 0.00
-system.mem_ctrls.readRowHits 60
-system.mem_ctrls.writeRowHits 0
-system.mem_ctrls.readRowHitRate 59.41
-system.mem_ctrls.writeRowHitRate nan
-system.mem_ctrls.avgGap 2474229.74
-system.mem_ctrls.pageHitRate 59.41
-system.mem_ctrls_0.actEnergy 43662.528000
-system.mem_ctrls_0.preEnergy 62195.112000
-system.mem_ctrls_0.readEnergy 168252.672000
-system.mem_ctrls_0.writeEnergy 0
-system.mem_ctrls_0.refreshEnergy 40175951.188800
-system.mem_ctrls_0.actBackEnergy 9263305.195200
-system.mem_ctrls_0.preBackEnergy 2003838.144000
-system.mem_ctrls_0.actPowerDownEnergy 56756040.499200
-system.mem_ctrls_0.prePowerDownEnergy 32466608.160000
-system.mem_ctrls_0.selfRefreshEnergy 53249987.481600
-system.mem_ctrls_0.totalEnergy 194189840.980800
-system.mem_ctrls_0.averagePower 776.759364
-system.mem_ctrls_0.totalIdleTime 232636363
-system.mem_ctrls_0.memoryStateTime::IDLE 2416000
-system.mem_ctrls_0.memoryStateTime::REF 10198000
-system.mem_ctrls_0.memoryStateTime::SREF 76011298
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 67641094
-system.mem_ctrls_0.memoryStateTime::ACT 1356320
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 92377288
-system.mem_ctrls_1.actEnergy 84206.304000
-system.mem_ctrls_1.preEnergy 107804.860800
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-system.mem_ctrls_1.writeEnergy 0
-system.mem_ctrls_1.refreshEnergy 44332084.070400
-system.mem_ctrls_1.actBackEnergy 10680861.945600
-system.mem_ctrls_1.preBackEnergy 1826565.081600
-system.mem_ctrls_1.actPowerDownEnergy 79552422.297600
-system.mem_ctrls_1.prePowerDownEnergy 31820466.720000
-system.mem_ctrls_1.selfRefreshEnergy 29482354.339200
-system.mem_ctrls_1.totalEnergy 198282107.419200
-system.mem_ctrls_1.averagePower 793.128430
-system.mem_ctrls_1.totalIdleTime 233331987
-system.mem_ctrls_1.memoryStateTime::IDLE 2130000
-system.mem_ctrls_1.memoryStateTime::REF 11236000
-system.mem_ctrls_1.memoryStateTime::SREF 38691980
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 66293879
-system.mem_ctrls_1.memoryStateTime::ACT 2171840
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 129476301
-system.pwrStateResidencyTicks::UNDEFINED 250000000
-system.membus.pwrStateResidencyTicks::UNDEFINED 250000000
-system.membus.trans_dist::ReadReq 101
-system.membus.trans_dist::ReadResp 101
-system.membus.pkt_count_system.monitor-master::system.mem_ctrls.port 202
-system.membus.pkt_count::total 202
-system.membus.pkt_size_system.monitor-master::system.mem_ctrls.port 6464
-system.membus.pkt_size::total 6464
-system.membus.reqLayer0.occupancy 78051
-system.membus.reqLayer0.utilization 0.0
-system.membus.respLayer0.occupancy 165128
-system.membus.respLayer0.utilization 0.1
-system.monitor.pwrStateResidencyTicks::UNDEFINED 250000000
-system.monitor.readBurstLengthHist::samples 101
-system.monitor.readBurstLengthHist::mean 64
-system.monitor.readBurstLengthHist::gmean 64.000000
-system.monitor.readBurstLengthHist::stdev 0
-system.monitor.readBurstLengthHist::0-3 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::4-7 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::8-11 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::12-15 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::16-19 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::20-23 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::24-27 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::28-31 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::32-35 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::36-39 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::40-43 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::44-47 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::48-51 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::52-55 0 0.00% 0.00%
-system.monitor.readBurstLengthHist::56-59 0 0.00% 0.00%
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
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-final_tick 5250000000
-sim_freq 1000000000000
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-system.tgen.pwrStateResidencyTicks::UNDEFINED 250000000
-system.tgen.numPackets 113
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-system.tgen.retryTicks 0
-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 5500000000
-sim_freq 1000000000000
-host_tick_rate 149441179653
-host_mem_usage 91320
-host_seconds 0.00
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
-system.mem_ctrls.bytes_read::tgen 6848
-system.mem_ctrls.bytes_read::total 6848
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-system.mem_ctrls.num_reads::total 107
-system.mem_ctrls.bw_read::tgen 27392000
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-system.mem_ctrls.bw_total::tgen 27392000
-system.mem_ctrls.bw_total::total 27392000
-system.mem_ctrls.readReqs 107
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-system.mem_ctrls.bytesReadDRAM 6848
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-system.mem_ctrls.bytesReadSys 6848
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 5750000000
-sim_freq 1000000000000
-host_tick_rate 167175660829
-host_mem_usage 91320
-host_seconds 0.00
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
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-system.mem_ctrls.readReqs 106
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
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-final_tick 6000000000
-sim_freq 1000000000000
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-system.monitor.ittReqReq::65001-70000 0 0.00% 0.00%
-system.monitor.ittReqReq::70001-75000 0 0.00% 0.00%
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-system.monitor.ittReqReq::min_value 104827
-system.monitor.ittReqReq::max_value 5642285
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-system.tgen.pwrStateResidencyTicks::UNDEFINED 250000000
-system.tgen.numPackets 98
-system.tgen.numRetries 0
-system.tgen.retryTicks 0
-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 6250000000
-sim_freq 1000000000000
-host_tick_rate 128419489969
-host_mem_usage 91320
-host_seconds 0.00
-system.clk_domain.voltage_domain.voltage 1
-system.clk_domain.clock 500
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 250000000
-system.mem_ctrls.bytes_read::tgen 6592
-system.mem_ctrls.bytes_read::total 6592
-system.mem_ctrls.num_reads::tgen 103
-system.mem_ctrls.num_reads::total 103
-system.mem_ctrls.bw_read::tgen 26368000
-system.mem_ctrls.bw_read::total 26368000
-system.mem_ctrls.bw_total::tgen 26368000
-system.mem_ctrls.bw_total::total 26368000
-system.mem_ctrls.readReqs 103
-system.mem_ctrls.writeReqs 0
-system.mem_ctrls.readBursts 103
-system.mem_ctrls.writeBursts 0
-system.mem_ctrls.bytesReadDRAM 6592
-system.mem_ctrls.bytesReadWrQ 0
-system.mem_ctrls.bytesWritten 0
-system.mem_ctrls.bytesReadSys 6592
-system.mem_ctrls.bytesWrittenSys 0
-system.mem_ctrls.servicedByWrQ 0
-system.mem_ctrls.mergedWrBursts 0
-system.mem_ctrls.neitherReadNorWriteReqs 0
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-system.mem_ctrls.perBankRdBursts::1 1
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-system.mem_ctrls.perBankRdBursts::3 3
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-system.mem_ctrls.perBankRdBursts::5 5
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-system.mem_ctrls.perBankRdBursts::7 2
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-system.mem_ctrls.totQLat 8396379
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-system.mem_ctrls.avgBusLat 3332.00
-system.mem_ctrls.avgMemAccLat 99010.24
-system.mem_ctrls.avgRdBW 26.37
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-system.mem_ctrls.avgWrBWSys 0.00
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-system.mem_ctrls_0.actEnergy 140343.840000
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-system.mem_ctrls_0.readEnergy 189284.256000
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-system.mem_ctrls_0.refreshEnergy 47102839.324800
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250
-sim_ticks 250000000
-final_tick 6500000000
-sim_freq 1000000000000
-host_tick_rate 162670503088
-host_mem_usage 91320
-host_seconds 0.00
-system.clk_domain.voltage_domain.voltage 1
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
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-final_tick 6750000000
-sim_freq 1000000000000
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-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
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-sim_ticks 50000000
-final_tick 6800000000
-sim_freq 1000000000000
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-host_mem_usage 91320
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-
----------- End Simulation Statistics ----------
+++ /dev/null
-# Copyright (c) 2017 ARM Limited
-# All rights reserved.
-#
-# The license below extends only to copyright in the software and shall
-# not be construed as granting a license to any other intellectual
-# property including but not limited to intellectual property relating
-# to a hardware implementation of the functionality of the software
-# licensed hereunder. You may use the software subject to the license
-# terms below provided that you ensure that this notice is replicated
-# unmodified and in its entirety in all distributions of the software,
-# modified or unmodified, in source code or in binary form.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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-page_policy = 'open_adaptive'
projects / gem5.git / commitdiff