tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini

   1 [root]
   2 type=Root
   3 children=system
   4 eventq_index=0
   5 full_system=false
   6 sim_quantum=0
   7 time_sync_enable=false
   8 time_sync_period=100000000000
   9 time_sync_spin_threshold=100000000
  10
  11 [system]
  12 type=System
  13 children=clk_domain cpu dvfs_handler mem_ctrl membus
  14 boot_osflags=a
  15 cache_line_size=64
  16 clk_domain=system.clk_domain
  17 default_p_state=UNDEFINED
  18 eventq_index=0
  19 exit_on_work_items=false
  20 init_param=0
  21 kernel=
  22 kernel_addr_check=true
  23 load_addr_mask=1099511627775
  24 load_offset=0
  25 mem_mode=timing
  26 mem_ranges=0:536870911:0:0:0:0
  27 memories=system.mem_ctrl
  28 mmap_using_noreserve=false
  29 multi_thread=false
  30 num_work_ids=16
  31 p_state_clk_gate_bins=20
  32 p_state_clk_gate_max=1000000000000
  33 p_state_clk_gate_min=1000
  34 power_model=Null
  35 readfile=
  36 symbolfile=
  37 thermal_components=
  38 thermal_model=Null
  39 work_begin_ckpt_count=0
  40 work_begin_cpu_id_exit=-1
  41 work_begin_exit_count=0
  42 work_cpus_ckpt_count=0
  43 work_end_ckpt_count=0
  44 work_end_exit_count=0
  45 work_item_id=-1
  46 system_port=system.membus.slave[2]
  47
  48 [system.clk_domain]
  49 type=SrcClockDomain
  50 children=voltage_domain
  51 clock=1000
  52 domain_id=-1
  53 eventq_index=0
  54 init_perf_level=0
  55 voltage_domain=system.clk_domain.voltage_domain
  56
  57 [system.clk_domain.voltage_domain]
  58 type=VoltageDomain
  59 eventq_index=0
  60 voltage=1.000000
  61
  62 [system.cpu]
  63 type=TimingSimpleCPU
  64 children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
  65 branchPred=Null
  66 checker=Null
  67 clk_domain=system.clk_domain
  68 cpu_id=-1
  69 default_p_state=UNDEFINED
  70 do_checkpoint_insts=true
  71 do_quiesce=true
  72 do_statistics_insts=true
  73 dstage2_mmu=system.cpu.dstage2_mmu
  74 dtb=system.cpu.dtb
  75 eventq_index=0
  76 function_trace=false
  77 function_trace_start=0
  78 interrupts=system.cpu.interrupts
  79 isa=system.cpu.isa
  80 istage2_mmu=system.cpu.istage2_mmu
  81 itb=system.cpu.itb
  82 max_insts_all_threads=0
  83 max_insts_any_thread=0
  84 max_loads_all_threads=0
  85 max_loads_any_thread=0
  86 numThreads=1
  87 p_state_clk_gate_bins=20
  88 p_state_clk_gate_max=1000000000000
  89 p_state_clk_gate_min=1000
  90 power_model=Null
  91 profile=0
  92 progress_interval=0
  93 simpoint_start_insts=
  94 socket_id=0
  95 switched_out=false
  96 syscallRetryLatency=10000
  97 system=system
  98 tracer=system.cpu.tracer
  99 workload=system.cpu.workload
 100 dcache_port=system.membus.slave[1]
 101 icache_port=system.membus.slave[0]
 102
 103 [system.cpu.dstage2_mmu]
 104 type=ArmStage2MMU
 105 children=stage2_tlb
 106 eventq_index=0
 107 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
 108 sys=system
 109 tlb=system.cpu.dtb
 110
 111 [system.cpu.dstage2_mmu.stage2_tlb]
 112 type=ArmTLB
 113 children=walker
 114 eventq_index=0
 115 is_stage2=true
 116 size=32
 117 walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 118
 119 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 120 type=ArmTableWalker
 121 clk_domain=system.clk_domain
 122 default_p_state=UNDEFINED
 123 eventq_index=0
 124 is_stage2=true
 125 num_squash_per_cycle=2
 126 p_state_clk_gate_bins=20
 127 p_state_clk_gate_max=1000000000000
 128 p_state_clk_gate_min=1000
 129 power_model=Null
 130 sys=system
 131
 132 [system.cpu.dtb]
 133 type=ArmTLB
 134 children=walker
 135 eventq_index=0
 136 is_stage2=false
 137 size=64
 138 walker=system.cpu.dtb.walker
 139
 140 [system.cpu.dtb.walker]
 141 type=ArmTableWalker
 142 clk_domain=system.clk_domain
 143 default_p_state=UNDEFINED
 144 eventq_index=0
 145 is_stage2=false
 146 num_squash_per_cycle=2
 147 p_state_clk_gate_bins=20
 148 p_state_clk_gate_max=1000000000000
 149 p_state_clk_gate_min=1000
 150 power_model=Null
 151 sys=system
 152
 153 [system.cpu.interrupts]
 154 type=ArmInterrupts
 155 eventq_index=0
 156
 157 [system.cpu.isa]
 158 type=ArmISA
 159 decoderFlavour=Generic
 160 eventq_index=0
 161 fpsid=1090793632
 162 id_aa64afr0_el1=0
 163 id_aa64afr1_el1=0
 164 id_aa64dfr0_el1=1052678
 165 id_aa64dfr1_el1=0
 166 id_aa64isar0_el1=0
 167 id_aa64isar1_el1=0
 168 id_aa64mmfr0_el1=15728642
 169 id_aa64mmfr1_el1=0
 170 id_isar0=34607377
 171 id_isar1=34677009
 172 id_isar2=555950401
 173 id_isar3=17899825
 174 id_isar4=268501314
 175 id_isar5=0
 176 id_mmfr0=270536963
 177 id_mmfr1=0
 178 id_mmfr2=19070976
 179 id_mmfr3=34611729
 180 midr=1091551472
 181 pmu=Null
 182 system=system
 183
 184 [system.cpu.istage2_mmu]
 185 type=ArmStage2MMU
 186 children=stage2_tlb
 187 eventq_index=0
 188 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
 189 sys=system
 190 tlb=system.cpu.itb
 191
 192 [system.cpu.istage2_mmu.stage2_tlb]
 193 type=ArmTLB
 194 children=walker
 195 eventq_index=0
 196 is_stage2=true
 197 size=32
 198 walker=system.cpu.istage2_mmu.stage2_tlb.walker
 199
 200 [system.cpu.istage2_mmu.stage2_tlb.walker]
 201 type=ArmTableWalker
 202 clk_domain=system.clk_domain
 203 default_p_state=UNDEFINED
 204 eventq_index=0
 205 is_stage2=true
 206 num_squash_per_cycle=2
 207 p_state_clk_gate_bins=20
 208 p_state_clk_gate_max=1000000000000
 209 p_state_clk_gate_min=1000
 210 power_model=Null
 211 sys=system
 212
 213 [system.cpu.itb]
 214 type=ArmTLB
 215 children=walker
 216 eventq_index=0
 217 is_stage2=false
 218 size=64
 219 walker=system.cpu.itb.walker
 220
 221 [system.cpu.itb.walker]
 222 type=ArmTableWalker
 223 clk_domain=system.clk_domain
 224 default_p_state=UNDEFINED
 225 eventq_index=0
 226 is_stage2=false
 227 num_squash_per_cycle=2
 228 p_state_clk_gate_bins=20
 229 p_state_clk_gate_max=1000000000000
 230 p_state_clk_gate_min=1000
 231 power_model=Null
 232 sys=system
 233
 234 [system.cpu.tracer]
 235 type=ExeTracer
 236 eventq_index=0
 237
 238 [system.cpu.workload]
 239 type=Process
 240 cmd=tests/test-progs/hello/bin/arm/linux/hello
 241 cwd=
 242 drivers=
 243 egid=100
 244 env=
 245 errout=cerr
 246 euid=100
 247 eventq_index=0
 248 executable=
 249 gid=100
 250 input=cin
 251 kvmInSE=false
 252 maxStackSize=67108864
 253 output=cout
 254 pgid=100
 255 pid=100
 256 ppid=0
 257 simpoint=0
 258 system=system
 259 uid=100
 260 useArchPT=false
 261
 262 [system.dvfs_handler]
 263 type=DVFSHandler
 264 domains=
 265 enable=false
 266 eventq_index=0
 267 sys_clk_domain=system.clk_domain
 268 transition_latency=100000000
 269
 270 [system.mem_ctrl]
 271 type=DRAMCtrl
 272 IDD0=0.055000
 273 IDD02=0.000000
 274 IDD2N=0.032000
 275 IDD2N2=0.000000
 276 IDD2P0=0.000000
 277 IDD2P02=0.000000
 278 IDD2P1=0.032000
 279 IDD2P12=0.000000
 280 IDD3N=0.038000
 281 IDD3N2=0.000000
 282 IDD3P0=0.000000
 283 IDD3P02=0.000000
 284 IDD3P1=0.038000
 285 IDD3P12=0.000000
 286 IDD4R=0.157000
 287 IDD4R2=0.000000
 288 IDD4W=0.125000
 289 IDD4W2=0.000000
 290 IDD5=0.235000
 291 IDD52=0.000000
 292 IDD6=0.020000
 293 IDD62=0.000000
 294 VDD=1.500000
 295 VDD2=0.000000
 296 activation_limit=4
 297 addr_mapping=RoRaBaCoCh
 298 bank_groups_per_rank=0
 299 banks_per_rank=8
 300 burst_length=8
 301 channels=1
 302 clk_domain=system.clk_domain
 303 conf_table_reported=true
 304 default_p_state=UNDEFINED
 305 device_bus_width=8
 306 device_rowbuffer_size=1024
 307 device_size=536870912
 308 devices_per_rank=8
 309 dll=true
 310 eventq_index=0
 311 in_addr_map=true
 312 kvm_map=true
 313 max_accesses_per_row=16
 314 mem_sched_policy=frfcfs
 315 min_writes_per_switch=16
 316 null=false
 317 p_state_clk_gate_bins=20
 318 p_state_clk_gate_max=1000000000000
 319 p_state_clk_gate_min=1000
 320 page_policy=open_adaptive
 321 power_model=Null
 322 range=0:536870911:0:0:0:0
 323 ranks_per_channel=2
 324 read_buffer_size=32
 325 static_backend_latency=10000
 326 static_frontend_latency=10000
 327 tBURST=5000
 328 tCCD_L=0
 329 tCK=1250
 330 tCL=13750
 331 tCS=2500
 332 tRAS=35000
 333 tRCD=13750
 334 tREFI=7800000
 335 tRFC=260000
 336 tRP=13750
 337 tRRD=6000
 338 tRRD_L=0
 339 tRTP=7500
 340 tRTW=2500
 341 tWR=15000
 342 tWTR=7500
 343 tXAW=30000
 344 tXP=6000
 345 tXPDLL=0
 346 tXS=270000
 347 tXSDLL=0
 348 write_buffer_size=64
 349 write_high_thresh_perc=85
 350 write_low_thresh_perc=50
 351 port=system.membus.master[0]
 352
 353 [system.membus]
 354 type=CoherentXBar
 355 children=snoop_filter
 356 clk_domain=system.clk_domain
 357 default_p_state=UNDEFINED
 358 eventq_index=0
 359 forward_latency=4
 360 frontend_latency=3
 361 p_state_clk_gate_bins=20
 362 p_state_clk_gate_max=1000000000000
 363 p_state_clk_gate_min=1000
 364 point_of_coherency=true
 365 power_model=Null
 366 response_latency=2
 367 snoop_filter=system.membus.snoop_filter
 368 snoop_response_latency=4
 369 system=system
 370 use_default_range=false
 371 width=16
 372 master=system.mem_ctrl.port
 373 slave=system.cpu.icache_port system.cpu.dcache_port system.system_port
 374
 375 [system.membus.snoop_filter]
 376 type=SnoopFilter
 377 eventq_index=0
 378 lookup_latency=1
 379 max_capacity=8388608
 380 system=system
 381