Add support for OP_EXTS

diff --git a/src/soc/alu/main_stage.py b/src/soc/alu/main_stage.py
index b2851015b6eca83cb30fb437ed3751e66da073cf..1231aeae99e7cd7a27ebc381cea3dba41115a2d2 100644 (file)
--- a/src/soc/alu/main_stage.py
+++ b/src/soc/alu/main_stage.py
@@ -61,6 +61,17 @@ class ALUMainStage(PipeModBase):
             #### xor ####
             with m.Case(InternalOp.OP_XOR):
                 comb += self.o.o.eq(self.i.a ^ self.i.b)
+            with m.Case(InternalOp.OP_EXTS):
+                with m.If(self.i.ctx.op.data_len == 1):
+                    comb += self.o.o.eq(Cat(self.i.a[0:8],
+                                            Repl(self.i.a[7], 64-8)))
+                with m.If(self.i.ctx.op.data_len == 2):
+                    comb += self.o.o.eq(Cat(self.i.a[0:16],
+                                            Repl(self.i.a[15], 64-16)))
+                with m.If(self.i.ctx.op.data_len == 4):
+                    comb += self.o.o.eq(Cat(self.i.a[0:32],
+                                            Repl(self.i.a[31], 64-32)))
+                    
                 
 
         ###### sticky overflow and context, both pass-through #####

diff --git a/src/soc/alu/test/test_pipe_caller.py b/src/soc/alu/test/test_pipe_caller.py
index ad1ae63a9bcfb5dfc2f7e94951946cc2fb95e592..604b5af28e4f10467a58a86af799cbd7e1c9ca0c 100644 (file)
--- a/src/soc/alu/test/test_pipe_caller.py
+++ b/src/soc/alu/test/test_pipe_caller.py
@@ -151,6 +151,16 @@ class ALUTestCase(FHDLTestCase):
         initial_regs[7] = random.randint(0, (1<<64)-1)
         self.run_tst_program(Program(lst), initial_regs, {})
 
+    def test_extsb(self):
+        insns = ["extsb", "extsh", "extsw"]
+        for i in range(10):
+            choice = random.choice(insns)
+            lst = [f"{choice} 3, 1"]
+            print(lst)
+            initial_regs = [0] * 32
+            initial_regs[1] = random.randint(0, (1<<64)-1)
+            self.run_tst_program(Program(lst), initial_regs)
+
     def test_ilang(self):
         rec = CompALUOpSubset()