rename SPBlock_512W64B8W to lowercase
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 18 Apr 2021 20:17:34 +0000 (21:17 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 18 Apr 2021 20:17:34 +0000 (21:17 +0100)
src/soc/bus/SPBlock512W64B8W.py
src/soc/litex/florent

index b86a78b389e176510e45d6404655644e9b95f980..02836a40cc32fec62906ebb68b56b944acd3adca 100644 (file)
@@ -44,7 +44,7 @@ class SPBlock512W64B8W(Elaboratable):
 
         # create Chips4Makers 4k SRAM cell here, mark it as "black box"
         # for coriolis2 to pick up
-        sram = Instance("SPBlock_512W64B8W", i_a=a, o_q=q, i_d=d,
+        sram = Instance("spblock_512w64b8w", i_a=a, o_q=q, i_d=d,
                                              i_we=we, i_clk=ClockSignal())
         m.submodules += sram
         # has to be added to the actual module rather than the instance
index d5b08ba4b0ee2fd2d23246fd456e633d8cc2264d..f1eb3ba9e89bdb1748e6655cbe8342f4e0704cae 160000 (submodule)
@@ -1 +1 @@
-Subproject commit d5b08ba4b0ee2fd2d23246fd456e633d8cc2264d
+Subproject commit f1eb3ba9e89bdb1748e6655cbe8342f4e0704cae